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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66236FP M66236FP
STANDARD CLOCK GENERATOR STANDARD CLOCK GENERATOR
DESCRIPTION M66236 is produced using the silicon gate CMOS process. It is able to output clock input signal in sync with optional external trigger input signal. It features excellent synchronizing precision (jitter) over a wide frequency band range. FEATURES * 5V single power supply (5V 5%) * Frequency band: 12 ~ 25MHz * Synchronizing precision (jitter): 5ns * Output types (1) Output of the same frequency as input clock, and its inversion (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output * Noise in the positive direction to trigger input is removed by built-in noise killer circuit APPLICATION Clock phase control for horizontal synchronization
PIN CONFIGURATION (TOP VIEW)
CLOCK INPUT CLK IN 1 TEST OUTPUT TEST2 3
ONE-SHOT PULSE OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT
TEST INPUT TEST1 2 PULSE 4
5 CKO/2 6 CKO/2 7 8 GND
GND
16 15 14 13 12 11 10 9
VCC
TEST3
GND
TEST OUTPUT TRIGGER INPUT
Outline 16P2N-A
Note: Keep test pins (TEST 1 to 3) open.
M66236FP
TR
VCC
CKO SYNC CLOCK OUTPUT CKO SYNC CLOCK INVERTED OUTPUT CNTCK CONTINUOUS CLOCK OUTPUT
BLOCK DIAGRAM
VCC
12
VCC
16 SYNC CLOCK GENERATION CIRCUIT 11 CKO 10 CKO
SYNC CLOCK OUTPUT SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT CONTINUOUS CLOCK OUTPUT ONE-SHOT PULSE OUTPUT
SYNC CLOCK SELECTOR CIRCUIT
7 CKO/2 6 CKO/2 9 CNTCK 4 PULSE
CLOCK INPUT
CLK IN 1
DELAY CLOCK GENERATION CIRCUIT
TRIGGER TR INPUT
13
PHASE DETECTION CIRCUIT 3 TEST2 TEST OUTPUT
TEST INPUT
TEST1 2 5 GND 8 GND
14
15 TEST3 TEST OUTPUT
GND
1
MITSUBISHI DIGITAL ASSP
M66236FP
STANDARD CLOCK GENERATOR
FUNCTION M66236 standard clock generator outputs clock input signal, which is input to CLK IN, synchronously with optional trigger signal, which is input to TR. Sync clock output timing is determined by trigger input signal fall edge. Time-lag between trigger input signal fall edge and sync clock output equals the sum of clock input signal "L" pulse width and M66236 internal delay. Variation in this lag (t) is 5ns, ensuring excellent synchronizing accuracy. There are six types of outputs: synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output (PULSE) and continuous clock output (CNTCK). From synchronous clock output (CKO), sync clock of the same frequency as clock input signal is output. From synchronous clock inverted output (CKO), inverted signal of sync
clock output from CKO is output. From 1/2 divider synchronous clock output (CKO/2), 1/2 divider signal of sync clock output from CKO is output. From 1/2 divider synchronous clock inverted output (CKO/2), inverted signal of that output from CKO/2 is output. From one-shot pulse output (PULSE), one-shot pulse which is almost equal to two cycles of clock input signal is output after trigger input signal falls. From continuous clock output (CNTCK), sync clock is output when trigger input signal is on "L" level; when trigger input signal is on "H" level, clock input signal, which is input to CLK IN, is output. All these outputs but continuous clock output are suspended when trigger input signal is on "H" level: Synchronous clock output, 1/2 divider synchronous clock output and one-shot pulse output stay on "L" level, and synchronous clock inverted output and 1/2 divider synchronous clock inverted output stay on "H" level.
1/fIN CLK IN tw(TR) TR tsp(CKO) CKO tsp(CKO) CKO tsp(CKO/2) CKO/2 tsp(CKO/2) CKO/2 tss(CKO/2) t PULSE tss(PULSE) tw(PULSE) t CNTCK tCH tCL tss(CNTCK)
Note 1: tSS (CKO, CKO, CKO/2, CKO/2 and PULSE) equals the sum of input clock "L" width and . Value refers to internal delay in M66236. Under environment where temperature and VCC do not change, value and tss are kept constant. Dispersion of tss under such conditions is defined as t [synchronizing precision (jitter)]. Note 2: Outputs (CKO, CKO, CKO/2, CKO/2 PULSE and CNTCK) are unknown until trigger input TR reaches "H" level for the first time after power-on.
VCC 0V 3V 0V t tss(CKO) t tss(CKO) t tss(CKO/2) t VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL
2
MITSUBISHI DIGITAL ASSP
M66236FP
STANDARD CLOCK GENERATOR
After Power-on Procedure After power-on, M66236 status is unknown till the trigger input being set to the "H" level. To get a accurate sync clock output, please keep a following procedure.
Please hold the trigger input "H" level during more than tw(TR) after the input clock frequency being stable. Also, in case of changing the clock input frequency(fIN), please keep the same procedure.
VCC
TR
CLK IN
CKO
tsp
tw (TR)
Input clock frequency is stable
3
MITSUBISHI DIGITAL ASSP
M66236FP
STANDARD CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Conditions Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 600 -65 ~ 150 Unit V V V mW C
When mounted
RECOMMENDED OPERATING CONDITIONS (Ta = 0 ~ 70C unless otherwise noted)
Symbol VCC GND VI VO Topr Parameter Supply voltage Supply voltage Input voltage Output voltage Operating temperature Min 4.75 0 0 0 Limits Typ 5 0 Max 5.25 VCC VCC 70 Unit V V V V C
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, VCC = 5V 5%, GND = 0V)
Symbol VIH VIL VIH VIL VOH VOL ICC (s) ICC (a) IIH IIL CI "H" input voltage "L" input voltage "H" input voltage "L" input voltage "H" output voltage "L" output voltage Supply current (static) Supply current (active) "H" input current "L" input current Input capacitance Parameter TR CLK IN GND = 0V, IOH = -4mA GND = 0V, IOL = 4mA GND = 0V, VI = VCC or GND GND = 0V, fIN = 25MHz, VI = VCC or GND GND = 0V, VI = VCC GND = 0V, VI = 0V Test conditions Min 2 0.8 x VCC 0.2 x VCC VCC - 0.8 0.55 50 65 +1 -1 10 Limits Typ Max 0.8 Unit V V V V V V A mA A A pF
TIMING REQUIREMENTS (Ta = 0 ~ 70C, VCC = 5V 5%, GND = 0V)
Symbol fIN fDUTY tw(TR) tr tf Parameter Clock input frequency Clock input duty Trigger input "H" pulse width Clock input rise time Clock input fall time Test conditions Min 12 40 400 Limits Typ Max 25 60 8 8 Unit MHz % ns ns ns
4
MITSUBISHI DIGITAL ASSP
M66236FP
STANDARD CLOCK GENERATOR
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70C, VCC = 5V 5%, GND = 0V)
Symbol t tss(CKO) tss(CKO) tss(CKO/2) tss(CKO/2) tss(PULSE) tss(CNTCK) tsp(CKO) tsp(CKO) tsp(CKO/2) tsp(CKO/2) tw(PULSE) tCH tCL fODUTY(CKO) fODUTY(CKO) Parameter Synchronizing precision (jitter) Sync clock output start time Sync clock inverted output start time 1/2 divider sync clock output start time 1/2 divider sync clock inverted output start time One-shot pulse output start time Continuous clock output start time Sync clock output stop time Sync clock inverted output stop time 1/2 divider sync clock output stop time 1/2 divider sync clock inverted output stop time One-shot pulse output width Sync clock-Input clock switching time Input clock-Sync clock switching time Sync clock output duty Sync clock inverted output duty Test conditions Min Limits Typ Max 5 tLp + 50 tLp + 50 tLp + 50 tLp + 50 CL=15pF 40 40 2tp - 10 2tp + 10 40 30 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns % %
30
* tp = 1/fIN, tLp = tp x (100 - fDUTY)/100 * Switching test waveform Input pulse level CLK IN: 0 to VCC TR: 0 to 3V Input pulse rise time: 3ns Input pulse fall time : 3ns Criterial voltage Input voltage CLK IN: VCC/2 TR: 1.3V Output voltage: VCC/2 for all outputs * Capacitance: CL includes stray wiring capacitance and probe input capacitance.
TEST CIRCUIT
INPUT VCC OUTPUT
PG 50
DUT CL
TIMING DIAGRAM
3.0V TR 1.3V 0V CKO CKO/2 CKO CKO/2 PULSE CNTCK 50% VOL tss VOH 50% tCL 50% VOL CNTCK tCH 50% CKO CKO/2 VOH CKO CKO/2 tsp TR 1.3V
3.0V
0V VOH 50% VOL VOH
VOL
3.0V TR 1.3V tw(TR) 1.3V 0V PULSE 50% tw(PULSE) 50%
VOH
VOL
5

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