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NB4N507A 3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer
Description
The NB4N507A is a precision clock synthesizer which generates a very low jitter differential PECL output clock. It produces a clock output based on an integer multiple of an input reference frequency. The NB4N507A accepts a standard fundamental mode crystal, using Phase-Locked-Loop (PLL) techniques, will produce output clocks up to 200 MHz. In addition, the PLL circuitry will produce a 50% duty cycle square-wave clock output. The NB4N507A can be programmed to generate a selection of input reference frequency multiples. An exact 155.52 MHz output clock can be generated from a 19.44 MHz crystal and the x8 multiplier selection. The NB4N507A is intended for low output jitter clock generation.
Features
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MARKING DIAGRAM
16 NB4N507A AWLYWW 1 = Assembly Location = Wafer Lot = Year = Work Week
* * * * * * * * *
Input Crystal Frequency of 10 - 27 MHz Enable Usage of Common Low-Cost Crystal Differential PECL Output Clock Frequencies up to 200 MHz Duty Cycle of 48%/52% Operating Range: VCC = 3.0 V to 5.5 V Ideal for SONET Applications and Oscillator Manufacturers Available in Die Form Packaged in 16-Pin Narrow SOIC Pb-Free Packages are Available*
SOIC-16 D SUFFIX CASE 751B A WL, L Y WW, W
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
Osc

PD
CP
VCO Mult
PECL
CLKOUT CLKOUT OE
S0 S1
Figure 1. Simplified Logic Block
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
March, 2005 - Rev. 0
1
Publication Order Number: NB4N507A/D
NB4N507A
VDD
X1/CLK Crystal X2 Feedback Multiplier Select S0 S1 GND Oscillator Buffer Phase Detector Charge Pump VCO PECL Output CLKOUT
CLKOUT
OE
Figure 2. NB4N507A Logic Diagram Table 1. CLOCK MULTIPLIER SELECT TABLE
X1/CLK VDD VDD S1 GND GND NC CLKOUT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 NC S0 OE NC NC NC CLKOUT S1 L L L M M M H H H S0 L M H L M H L M H Multiplier 9.72X* 10X 12X 6.25X 8X 5X NA 3X 4X
Table 2. OE, OUTPUT ENABLE FUNCTION
OE Function Disable Enable 0 1 *Crystal = 16 MHz, fCLKOUT = 155.52 MHz L = GND H = VDD M = OPEN
Figure 3. 16-Pin SOIC (Top View)
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NB4N507A
Table 3. PIN DESCRIPTION
Pin # SOIC-16 1 2,3 4 5,6 7,10,11,12, 15 8 9 13 Name X1/CLK VDD S1 GND NC CLKOUT CLKOUT OE I/O Crystal Input Power Supply Tri-Level Input Power Supply No Connect PECL Output PECL Output (LV)CMOS/(LV)TTL Input Tri-Level Input Crystal Input Non-inverted differential PECL clock output. Inverted differential PECL clock output. Output Enable for the CLKOUT/CLKOUT Outputs. Outputs are enabled when HIGH or when left open; OE pin has internal pullup resistor. Disables both outputs when LOW. CLKOUT goes LOW, CLKOUT goes HIGH. Multiplier Select Pin; When Left Open, Defaults to VDD B 2 Crystal Input Crystal or Clock Input Positive Supply Voltage (3.0 V to 5.5 V) Multiplier Select Pin; When Left Open, Defaults to VDD B 2 Negative Supply Voltage Description
14 16
S0 X2
Table 4. ATTRIBUTES
Characteristics ESD Protection Human Body Model Machine Model Charged Device Model Oxygen Index: 28 to 34 Value > 1 kV > 150 V > 1 kV Level 1 UL 94 V-0 @ 0.125 in 1145 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol VCC VI TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input Voltage Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm (Note 2) < 3 sec @ 248C < 3 sec @ 260C SOIC-16 SOIC-16 Condition 1 GND = 0 V Condition 2 Rating 6 GND - 0.5 VI VDD + 0.5 -40 to +85 -65 to +150 100 60 33 to 36 265 265 Unit V V C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
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NB4N507A
Table 6. DC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = -40C to +85C (Note 3))
Symbol IDD VOH VOL VIH VIL Cx Cin Characteristic Power Supply Current (does not include output load resistor current) Output HIGH Voltage (Notes 5 & 6) Output LOW Voltage (Notes 5 & 6) Input HIGH Voltage, S0, S1, OE, X1 Input LOW Voltage, S0, S1, OE, X1 Internal Crystal Capacitance, X1 & X2 Input Capacitance, S0, S1, OE VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V (Note 4) (Note 4) Min 15 10 3.95 2.57 3.12 1.90 VDD - 0.5 0 0 5.0 Typ 27 23 4.05 2.67 3.20 2.00 Max 35 30 4.15 2.77 3.30 2.10 VDD 0.5 Unit mA mA V V V V pF pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. PECL output parameters vary 1:1 with VDD. 4. S0 and S1 default to VDD B 2 when left open.
Table 7. AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = -40C to +85C (Note 5))
Symbol fXtal fCLK fOUT Vout pk-pk DC PLLBW tjitter (pd) tjitter (cyc-cyc) tr/tf Crystal Input Frequency Input Clock Frequency (Note 8) Output Frequency Range Output Amplitude Clock Output Duty Cycle (Note 8) PLL Bandwidth (Note 8) Period Jitter (RMS, 1s) Cycle-to-cycle Jitter Output Rise and Fall Times (Note 8) 50 270 Characteristic Min 10 5 50 550 48 10 10 40 500 680 52 Typ Max 27 52 200 Unit MHz MHz MHz mV % kHz ps ps ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. PECL outputs loaded with external resistors for proper operation (see Figure 4). 6. VOH and VOL can be set by the external resistors, which can be modified. 7. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL is the specified crystal load capacitance: Crystal caps (pF) = (CL-5) x 2. So, for a crystal with 16 pF load capacitance, use two 22 pF caps. 8. Guaranteed by design and characterization.
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NB4N507A
VDD GND VDD
NB4N507
z = 50 W
z = 50 W D 62 W VDD 62 W
PECL Driver
PECL Receiver D
z = 50 W
z = 50 W 270 W GND
GND
GND
Figure 4. Recommended PECL Output Loading for the NB4N507A
APPLICATIONS INFORMATION High Frequency Differential PECL Oscillators: The NB4N507A, along with a low frequency fundamental mode crystal, can build a high frequency differential PECL output oscillator. For example, a 10 MHz crystal connected to the NB4N507A with the 12X output selected (S1 = 0, S0 = 1) produces a 120 MHz PECL output clock. High Frequency VCXO: The bandwidth of the PLL is guaranteed to be greater than 10 kHz. This means that the PLL will track any modulation on the input with a frequency of less than 10 kHz. By using this property, a low frequency VCXO can be built. The output can then be multiplied by the NB4N507A, thereby producing a high frequency VCXO. High Frequency TCXO: Extending the previous application, an inexpensive, low frequency TCXO can be built and the output frequency can be multiplied using the
ORDERING INFORMATION
Device NB4N507AD NB4N507ADG NB4N507ADR2 NB4N507ADR2G Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) Shipping 48 Units / Rail 48 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel
NB4N507A. Since the output of the chip is phase-locked to the input, the NB4N507A has no temperature dependence, and the temperature coefficient of the combined system is the same as that of the low frequency TCXO.
Decoupling and External Components
The NB4N507A requires a 0.01 mF decoupling capacitor to be connected between VDD and GND on pins 2 and 5. It must be connected close to the NB4N507A. Other VDD and GND connections should be connected to those pins, or to the VDD and GND planes on the board. Another four resistors are needed for the PECL outputs as shown on the block diagram in Figure 1. Suggested values of these resistors are shown in the Block Diagram, but they can be varied to change the differential pair output swing, and the DC level.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB4N507A
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB4N507A
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NB4N507A/D

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