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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Dual, 1024 Position Resolution 25K, 250K Ohm Full Scale Resistance Low Temperature Coefficient -- 35ppm/C Nonvolatile Memory1 Preset Maintains Wiper Settings Wiper Settings Read Back Linear Increment/Decrement Log taper Increment/Decrement SPI Compatible Serial Interface +3V to +5V Single Supply or 2.5V Dual Supply 26 bytes User Nonvolatile Memory for Constant Storage with Current Monitoring Configurable Function APPLICATIONS SONET, SDH, ATM, Gigabit Ethernet, DWDM Laser Diode Driver Optical Supervisory Systems
Nonvolatile Memory, Dual 1024 Position Programmable Resistors
ADN2850
FUNCTIONAL BLOCK DIAGRAM
CS CLK SDI SDO
SERIAL IN PUT REG IS TE R
ADDRESS DECODE
RDAC1 REGISTER
W1 EEMEM1 RDAC1
B1
PR
PWR ON PRESET
RDAC2 REGISTER
W2 WP RDY EEMEM CON TROL EEMEM2 RDAC1
B2
V DD V SS 26 BYTES USER EEMEM C URRENT MONITOR
I1
V1
GENERAL DESCRIPTION
The ADN2850 provides dual channel, digitally controlled programmable resistors2 with resolution of 1024 positions. These devices perform the same electronic adjustment function as a mechanical rheostat. The ADN2850's versatile programming via a standard serial interface allows sixteen mode of operations and adjustment including scratch pad programming, memory storing and retrieving, increment/decrement, log taper adjustment, wiper setting readback, and extra user defined EEMEM. In the scratch pad programming mode, a specific setting can be programmed directly to the RDAC2 register, which sets the resistance between terminals W-and-B. The RDAC register can also be loaded with a value previously stored in the EEMEM1 register. The value in the EEMEM can be changed or protected. When changes are made to the RDAC register, the value of the new setting can be saved into the EEMEM. Thereafter, such value will be transferred automatically to the RDAC register during system power ON. It is enabled by the internal preset strobe. EEMEM can also be retrieved through direct programming and external preset pin control. Other key mode of operations include linear step increment and decrement commands such that the setting in the RDAC register can be moved UP or DOWN, one step at a time. For logarithmic changes in wiper setting, a left/right bit shift command adjusts the level in 6dB steps. The ADN2850 is available in the 5mm x 5mm LFCSP-16 Lead Frame Chip Scale and thin TSSOP-16 packages. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C.
I2
V2
GND
100%
RW B(D) [% of Full Sca le RW B]
75%
50%
25%
0% 0 256 512
D - C o d e in De cim al
768
1023
Figure 1. RWB(D) vs Decimal Code
Notes: 1. The term nonvolatile memory and EEMEM are used interchangebly 2. The term programmable resistor and RDAC are used interchangebly
REV PrH, 13, AUG 2001 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 617/329-4700 Fax:617/326-8703
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
-40C < TA < +85C unless otherwise noted12.)
ADN2850
1
ELECTRICAL CHARACTERISTICS 25K , 250K OHM VERSIONS (VDD = +3V to +5.5V and,
Parameter
Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Resistance Temperature Coefficent Wiper Resistance Channel Resistance Matching Nominal Resistor tolerance RESISTOR TERMINALS Terminal Voltage Range3 Capacitance4 Bx Capacitance4 Wx Common-mode Leakage Current 5 DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO, RDY) Output Logic Low Input Current Input Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current Negative Supply Current Power Dissipation6 Power Supply Sensitivity CURRENT MONITOR Terminals Current Sink at V17 Current Sink at V2 DYNAMIC CHARACTERISTICS4, 8 eN_WB CT RWB_FS = 25K / 250K, TA = 25oC VB1 = VB2 = 0V, Measured VW1 with VW2 = 100 mV p-p @ f = 100 kHz, Code1,2 = 200H 20 / 64 -65 nVHz dB Resistor Noise Spectral Density Analog Crosstalk (CW1/CW2) NOTES: See bottom of table next page. I1 I2 0.0001 10 10 mA mA VDD VDD/VSS IDD IDD(PG) IDD(READ) ISS PDISS PSS VSS = 0V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V VIH = VDD or VIL = GND VDD = +5V 10% 3.0 2.25 2 35 3 2 6 0.002 5.5 2.75 20 V V A mA mA A W %/% VIH VIL VIH VIL VIH VIL VOH VOL IIL CIL with respect to GND, VDD = 5V with respect to GND, VDD = 5V with respect to GND, VDD = 3V with respect to GND, VDD = 3V with respect to GND, VDD = +2.5V, VSS=-2.5V with respect to GND, VDD = 5V, VSS=-2.5V RPULL-UP = 2.2K to +5V IOL = 1.6mA, VLOGIC = +5V VIN = 0V or VDD 2.4 0.8 2.1 0.6 2.0 0.5 4.9 0.4 1 5 V V V V V V V V A pF VW, B CB CW ICM f = 1 MHz, measured to GND, Code = Half-scale f = 1 MHz, measured to GND, Code = Half-scale VW = VB = VDD/2 VSS 8 80 0.01 1 VDD V pF pF A
Symbol
R-DNL R-INL RWB/T RW RWB/RWB RWB
Conditions
RWB RWB VDD = +5V, IW = 1V/RWB VDD = +3V, IW = 1V/RWB Ch 1 and 2 RWB, Dx = 3FFH Dx = 3FFH
Min
-2 -4
Typ
Max
+2 +4
Units
LSB LSB ppm/C % %
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
35 50 200 0.2 -30
100
30
20 110 0.01
REV PrH, 13, AUG 2001
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
-40C < TA < +85C unless otherwise noted12.)
ADN2850
1
ELECTRICAL CHARACTERISTICS 25K , 250K OHM VERSIONS (VDD = +3V to +5.5V and,
Parameter Clock Cycle Time (tCYC) CS Setup Time CLK Shutdown Time to CS rise Input Clock Pulse Width Data Setup Time Data Hold Time CS to SDO - SPI line acquire CS to SDO - SPI line release CLK to SDO Propagation Delay10 CLK to SDO Data Hold Time CS High Pulse Width CS High to CS High RDY Rise to CS Fall CS Rise to RDY fall time Read/Store to Nonvolatile EEMEM 11 CS Rise to Clock Edge Setup Preset Pulse Width (Asynchronous) Preset Response Time to RDY High FLASH/EE MEMORY Endurance Data Retention14 NOTES:
1. 2. Typicals represent average readings at +25C and VDD = +5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50uA for VDD= +2.7V and IW ~ 400uA for VDD=+5V. See test circuit figure xxxx Resistor terminals W,B have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. Common mode leakage current is a measure of the DC leakage from any terminal B and W to a common mode bias level of VDD / 2. PDISS is calculated from (IDD x VDD) + (ISS x VSS) Applies to Photo Diode of Optical Receiver. All dynamic characteristics use VDD = +5V and VSS = 0V See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using both VDD = +3V and +5V. Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text. RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms. Device operation at TA=-40oC & VDD<+3V extends the save time to 35ms. Parts can be operated at +2.7V single supply, except from 0oC to -40oC where minimum +3V is needed The ADN2850 contains 16,000 transistors. Die size: 100 mil x 150 mil, 10,500 sq. mil. Retention lifetime equivalent at junction temperature (TJ) = 55C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure xxx in the Flash/EE Memory description section of this data sheet.
Symbol t1 t2 t3 t 4, t 5 t6 t7 t8 t9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 tPRW tPRESP
Conditions
Min 20 10 1 10 5 5
Typ
Max
Units ns ns tCYC ns ns ns ns ns ns ns ns tCYC s ms ms ns ns us Cycles Years
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 4, 9)
Clock level high or low From Positive CLK transition From Positive CLK transition
RP = 2.2K, CL < 20pF RP = 2.2K, CL < 20pF
6 34 34 0 10 4 0
40 100 100
1 0.11 25
Applies to Command 2H, 3H, 9H Not shown in timing diagram PR pulsed low to refreshed wiper positions 10 50 70 100,000 100
RELIABILITY13
3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
Specifications Subject to Change without Notice
REV PrH, 13, AUG 2001
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
Timing Diagram
CPHA = 1
ADN2850
t12
CS
t3
CLK
CPOL=1
t2 t5 t8 t10
t1 t4 t10 t11
t13 t17 t9
SDO
*
MSB
t7 t6
LSB OUT
SDI
MSB
LSB
t14
t15
RDY
* * Note: Not defined, but normally LSB character previously transmitted. The CPOL=1 micro Note: Not defined, but normally LSB of of character previously transmitted To be fully compliant the CPHA=1, CPOL=1 mode should be used clock. controller command aligns the incoming data to the positive edge of the when shifting more
than 8-bits together as the C S line can remain low (useful for daisy chaining). Processing of a serial command will not take place until C S returns high. The CPOL = 0 micro controller command aligns the incoming data to the positive edge of the clock .
t16
Figure 2A. CPHA=1 Timing Diagram
CPHA = 0
CS
t1 t3 t5 t10 t11 t9
t12 t2 t4 t8 t13 t17 t11
CLK
CPOL=0
SDO
MSB OUT
t7 t6
LSB
*
SDI
t14
MSB IN
LSB
t15 t16
RDY
Note: Not defined, but normally MSB of character just received. * * Note: Not defined,but normally MSB of character just received The CPOL=0 micro controller CS can remain lowthe incoming data to the positive edge of the multiple bytes; command aligns for the CPHA=0, CPOL=0 mode between clock. however this is not strictly SPI compliant. The CPOL = 0 micro controller command aligns the incoming data to the positive edge of the clock .
Figure 2B. CPHA=0 Timing Diagram
REV PrH, 13, AUG 2001
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
Absolute Maximum Rating (TA = +25C, unless
otherwise noted) VDD to GND............................................................-0.3V, +7V VSS to GND ............................................................+0.3V, -7V VDD to VSS .........................................................................+7V VB, VW to GND..................................... VSS-0.3V, VDD+0.3V BX - WX ....................................................................... 20mA Intermittent2 .................................................. 20mA Continuous................................................... 1.3mA Digital Inputs & Output Voltage to GND.....-0.3V, VDD+0.3V Operating Temperature Range3........................ -40C to +85C Maximum Junction Temperature (TJ MAX) ...................+150C Storage Temperature...................................... -65C to +150C Lead Temperature, Soldering4 Vapor Phase (60 sec) .......................................+215 C Infrared (15 sec)...............................................+220 C Thermal Resistance Junction-to-Ambient JA, LFCSP-16 ........................................................ 35C/W
1
ADN2850
TSSOP-16 ..................................................... 150C/W Thermal Resistance Junction-to-Case JC, LFCSP-16............................................................. TBD TSSOP-16 ....................................................... 28C/W
Package Power Dissipation = (TJMAX - TA) / JA
NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the B, and W terminals at a given resistance. 3. Includes programming of Nonvolatile memory 4. Applicable to TSSOP-16 only. For LFCSP-16, please consult factory for detail
Ordering Guide
Model ADN2850ACP25 ADN2850ACP25-RL7 RWB (k Ohm) 25 25 RDNL (LSB) 2 2 RINL (LSB) 4 4 Temp Range -40/+85C -40/+85C Package Description LFCSP-16 LFCSP-16 1500 Pieces 7" Reel LFCSP-16 LFCSP-16 1500 Pieces 7" Reel TSSOP-16 TSSOP-16 1000 Pieces 7" Reel Package Option CP-16 CP-16 Top Mark* ACP25 ACP25
ADN2850ACP250 ADN2850ACP250-RL7
250 250
2 2
4 4
-40/+85C -40/+85C
CP-16 CP-16
ACP250 ACP250
ADN2850ARU25 ADN2850ARU25-REEL7
25 25
2 2
4 4
-40/+85C -40/+85C
RU-16 RU-16
ARU25 ARU25
* Line 1 contains ADI logo symbol and date code YYWW, line 2 contains product number ADN2850, line 3 branding containing differentiating detail by part type, line 4 contains lot number.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2850 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV PrH, 13, AUG 2001
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
ADN2850ACP PIN CONFIGURATION
SDI CLK RDY CS
ADN2850
16 RDY 15 CS 14 PR 13 WP 12 VDD 11 V2 10 W2 9 B2
ADN2850ARU PIN CONFIGURATION
CLK SDI 1 2 3 4 5 6 7 8
16
SDO GND VSS V1
15
14
13 12 PR 11 WP 10 VDD 9 V2
SDO GND VSS V1 W1 B1
1 2 3 4 5
W1
6
B1
7
B2
8
W2
ADN2850ACP PIN DESCRIPTION
# 1 Name SDO Description Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10 activate the SDO output. See Instruction operation Truth Table. Table 2. Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. Ground pin, logic ground reference Negative Supply. Connect to zero volts for single supply applications. Log Output Voltage 1 generated from internal diode configured transistor Wiper terminal of RDAC1. ADDR(RDAC1) = 0H. B terminal of RDAC1 B terminal of RDAC2. Wiper terminal of RDAC2. ADDR(RDAC2) = 1H. Log Output Voltage 2 generated from internal diode configured transistor Positive Power Supply Pin. Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and cmd 1 and 8 will refresh the RDAC register from EEMEM. Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR. Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
ADN2850ARU PIN DESCRIPTION
# 1 2 3 Name CLK SDI SDO Description Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10 activate the SDO output. See Instruction operation Truth Table. Table 2. Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages Ground pin, logic ground reference Negative Supply. Connect to zero volts for single supply applications. Log Output Voltage 1 generated from internal diode configured transistor Wiper terminal of RDAC1. ADDR(RDAC1) = 0H. B terminal of RDAC1 B terminal of RDAC2. Wiper terminal of RDAC2. ADDR(RDAC2) = 1H. Log Output Voltage 2 generated from internal diode configured transistor Positive Power Supply Pin. Write Protect Pin. When active low, WP prevents any changes to the present contents except PR and cmd 1 and 8 will refresh the RDAC register from E2MEM. Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR.
2 3 4 5 6 7 8 9 10 11
GND VSS V1 W1 B1 B2 W2 V2 VDD WP
4 5 6 7 8 9 10 11 12 13
GND VSS V1 W1 B1 B2 W2 V2 VDD WP
12
PR
13 14 15 16
CS RDY CLK SDI
14
PR
15 16
CS RDY
REV PrH, 13, AUG 2001
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
Table 1. ADN2850 24-bit Serial Data Word
MSB
ADN2850
LSB
RDAC EEMEM
C3 C3
C2 C2
C1 C1
C0 C0
0 A3
0 A2
0 A1
A0 A0
X D 15
X D 14
X D 13
X D 12
X D 11
X D 10
D9 D9
D8 D8
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
Command bits are C0 to C3. Address bits are A3-A0. Data bits D0 to D9 are applicable to RDAC whereas D0 to D15 are applicable to EEMEM. Command instruction codes are defined in table 2.
Table 2. ADN2850 Instruction/Operation Truth Tablea,b,d
Inst No. 0 1 Instruction Byte 0 B23 *************** B16 C3 C2 C1 C0 A3 A2 A1 A0 0000XXXX 0 0 0 1 0 0 0 A0 Data Byte 1 B15 **** B8 X *** D9 D8 X *** X X X *** X X Data Byte 0 B7 *** B0 D7 *** D0 X *** X X *** X Operation
NOP: Do nothing Write contents of EEMEM(A0) to RDAC(A0) Register). This command leaves device in the Read Program power state. To return part to the idle state, perform NOP instruction #0 SAVE WIPER SETTING: Write contents of RDAC(A0) to EEMEM(A0) Write contents of Serial Register Data Bytes 0 & 1 to EEMEM(ADDR) Decrement 6dB: Right Shift contents of RDAC(A0), steops at all "Zeros". Decrement All 6dB: Right Shift contents of all RDAC Registers, stops at all "Zeros". Decrement contents of RDAC(A0) by "One", stops at all "Zero". Decrement contents of all RDAC Register by "One", stops at all "Zero". RESET: Load all RDACs with their corresponding EEMEM previously-saved values Write contents of EEMEM(ADDR) to Serial Register Data Bytes 0 & 1. SDO activated. See Figure xxxx Write contents of RDAC(A0) to Serial Register Data Bytes 0 & 1. SDO activated. See Figure xxxx Write contents of Serial Register Data Bytes 0 &1 to RDAC(A0) Increment 6dB: Left Shift contents of RDAC(A0), stops at all "Ones". Increment All 6dB: Left Shift contents of all RDAC Registers, stops at all "Ones". Increment contents of RDAC(A0) by "One", stops at all "Ones". Increment contents of all RDAC Register by "One", stops at all "Ones".
2 3e 4c 5c 6c 7c 8 9 10 11 12c 13c 14c 15c
0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
0
0
A0
X *** X D15 *** X *** X X *** X X *** X X *** X X *** X X *** X X *** X
X D8 X X X X X X X
X
*** X
<< ADDR >> 0 X 0 X 0 0 X 0 X 0 0 X 0 X 0 A0 X A0 X 0
D7 *** D0 X X X X X X X *** X *** X *** X *** X *** X *** X *** X
<< ADDR >> 0 0 0 X 0 X 0 0 0 X 0 X 0 0 0 X 0 X A0 A0 A0 X A0 X
X *** D9 D8 X *** X X *** X X *** X X *** X X X X X
D7 *** D0 X X X X *** X *** X *** X *** X
NOTES: a) The SDO output shifts-out the last 24-bits of data clocked into the serial register for daisy chain operation. Exception, following Instruction #9 or #10 the selected internal register data will be present in data byte 0 & 1. Instructions following #9 & #10 must be a full 24-bit data word to completely clock out the contents of the serial register. b) The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile EEMEM register. c) The increment, decrement and shift commands ignore the contents of the shift register Data Bytes 0 and 1. d) Execution of the above Operations takes place when the CS strobe returns to logic high. e) Instruction #3 write two data bytes to EEMEM. But in the cases of addresses 0 and 1, only the last 10 bits are valid for wiper position setting. REV PrH, 13, AUG 2001 7
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
OPERATIONAL OVERVIEW The ADN2850 programmable resistor is designed to operate as a true variable resistor. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratch pad register which allows unlimited changes of resistance settings. The scratch pad register can be programmed with any position setting using the standard SPI serial interface by loading the 24-bit data word. The format of the data word is that the first 4 bits are instructions, the following 4 bits are Addresses, and the last 16 bits are data. Once a specific value is set, this value can be saved into a corresponding EEMEM register. During subsequent power up, the wiper setting will automatically be loaded at that value. Saving data to the EEMEM takes about 25ms, and consumes approximately 20mA. During this time the shift register is locked preventing any changes from taking place. The RDY pin indicates the completion of this EEMEM saving process. There are also 13, 2 bytes each of user defined data that can be stored in EEMEM. OPERATION DETAIL There are sixteen instructions which faciliates users' programming needs. Refer to Table 2, the instructions are: 0. Do Nothing 1. Restore EEMEM setting to RDAC 2. Save RDAC setting to EEMEM 3. Save RDAC setting or user data to EEMEM 4. Decrement 6dB 5. Decrement all 6dB 6. Decrement one step 7. Decrement all one step 8. Reset EEMEM setting to RDAC 9. Read EEMEM to SDO 10. Read Wiper Setting to SDO 11. Write data to RDAC 12. Increment 6dB 13. Increment all 6dB 14. Increment one step 15. Increment all one step Scratch Pad and EEMEM Programming The basic mode of setting the programmable resistor wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the instruction #11, the correponding address, and the data. When the desired wiper position is determined, the user can load the serial data input register with the instruction #2, which stores the setting into the corresponding EEMEM register. After 25ms the wiper position will be stored in the corresponding EEMEM location. If desired, this value can be changed by users in the future or users can set the write-protect to permanently protect the data. Figure 3 provides a programming example listing the sequence of serial data input (SDI) words and the corresponding serial data output (SDO) in hexadecimal format.
SDI SDO Action
ADN2850
B00100H XXXXXXH Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position 20xxxxH B00100H B10200H 20xxxxH 21xxxxH B10200H Saves copy of RDAC1 register contents into corresponding EEMEM1 register. Loads 200H data into RDAC2 register, Wiper W2 moves to 1/2 full-scale position Saves copy of RDAC2 register contents into corresponding EEMEM2 register.
Figure 3. Set and Save two channels of programmable resistors with independent datas. At system power ON, the scratch pad register is refreshed with the value previously saved in the corresponding EEMEM register. The factory preset EEMEM value is midscale. The scratch pad register can also be loaded with the contents of the EEMEM register in three different ways. Executing instruction #1 retrieves the corresponding EEMEM value, executing instruction #8 resets both channels EEMEM values, and pulsing the PR pin also refreshs both EEMEM settings. Operate the PR function however requires a complete pulse signal. When PR goes low, the internal logic sets the wiper at midscale. The EEMEM value will not be loaded until PR returns to high.
E2MEM Protection The write-protect (WP) pin provides a hardware EEMEM protection feature which disables any changes of the current content in the scratch pad register at all except commands 1, 8, and PR . Executing these three events cause the EEMEM values restored to the scratch pad registers. Linear Increment and Decrement Commands The increment and decrement commands (#14, #15, #6, #7) are useful for linear step adjustment applications. These commands simplify micro controller software coding by allowing the controller to just send an increment or decrement command to the device. The adjustment can be individual or ganged arrangement. For increment command, executing instruction #14 will automatically move the wiper to the next resistance segment position. The master increment instruction #15 will move all resistor wipers up by one position. Logarithmic Taper Mode Adjustment (6dB/step) Four programming instructions produce logarithmic taper increment and decrement wiper position control by either individual or ganged arrangement. These settings are activated by the 6dB increment and 6dB decrement instructions #12 & #13 and #4 & #5 respectively. For example, starting at zero scale, executing eleven times of the increment instruction #12 will move the wiper in +6B per step from the 0% of the full scale RWB to the full scale RWB. The +6dB increment instruction doubles the value of the RDAC register contents each time the command is executed. When the wiper position is near the maximum setting, the last +6dB increment instruction will cause the wiper to go to the full-scale 1023 code position. Further +6dB per increment instruction will no longer change the wiper position beyond its full scale.
8
REV PrH, 13, AUG 2001
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
6dB step increment and decrement are achieved by shifting the bit internally to the left and right respectively. The following information explains the nonideal 6dB step adjustment at certain conditions. Table 3 illustrates the operation of the shifting function on the individual RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift #12 & #13 commands were modified such that if the data in the RDAC register is equal to zero, and the data is left shifted, the RDAC register is then set to code 1. Similary, if the data in the RDAC register is greater than or equal to mid-scale, and the data is left shifted, then the data in the RDAC register is automatically set to full-scale. This makes the left shift function as ideal logarithmic adjustment as is possible. The right shift #4 & #5 commands will be ideal only if the LSB is zero (i.e. ideal logarithmic - no error). If the LSB is a one then the right shift function generates a linear half LSB error, which translates to a numbers of bits dependent logarithmic error as shown in Figure 4. The plot shows the error of the odd numbers of bits for ADN2850. Left Shift 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0100 00 0000 1000 00 0001 0000 00 0010 0000 00 0100 0000 00 1000 0000 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111 Right Shift 11 1111 1111 01 1111 1111 00 1111 1111 00 0111 1111 00 0011 1111 00 0001 1111 00 0000 1111 00 0000 0111 00 0000 0011 00 0000 0001 00 0000 0000 00 0000 0000 00 0000 0000
ADN2850
Using Additional internal Nonvolatile EEMEM The ADN2850 contains additional internal user storage registers (EEMEM) for saving constants and other 16-bit data. Table 4 provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and 26 bytes of USER EEMEM.
Address 0000 0001 0010 0011 : 1110 1111
EEMEM For RDAC1a,c RDAC2 USER1b USER2 : USER13 Factory Reserved
Table 4: EEMEM Address Map
NOTES: a) RDAC data stored in EEMEM locations are transferred to their corresponding RDAC REGISTER at Power ON, or when instructions Inst#1, #8, and PR are executed. b) USER are internal nonvolatile EEMEM registers available to store and retrieve constants and other 16-bit information using Inst#3 and Inst#9 respectively. c) Execution of instruction #1 leaves the device in the Read Mode power consumption state. After the last Instruction #1 is executed, the user should perform a NOP, Instruction #0 to return the device to the low power idling state.
Left Shift (+6dB/step)
Right Shift (-6dB/step)
Daisy Chain Operation The serial data output pin (SDO) can be used to readout the content of the wiper settings or EEMEM values under instructions 10 and 9 respectively. If these instructions are not used, SDO can be used for daisy chaining multiple devices for simultaneous operations, see Figure 5. SDO pin contains an open drain N-Ch FET and requires a pull-up resistor if SDO function is used. Users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-SDI interface may induce time delay to the subsequent devices, see Figure 5. If two ADN2850 are daisy chained, this requires total 48 bits of data. The first 24 bits (formatted 4-bit instruction, 4-bit address, and 16-bit data) goes to U2 and the second 24 bits with the same format goes to U1. The CS should be kept low until all 48 bits are clocked into their respective serial registers. The CS is then pulled high to complete the operation.
Table 3. Detail Left and Right Shift functions for 6dB step increment and decrement.
Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each Right Shift #4 & #5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in Figure 4 shows plots of Log_Error [i.e. 20*log10 (error/code)] ADN2850. For example, code 3 Log_Error=20*log10 (0.5/3)=-15.56dB, which is the worst case. The plot of Log_Error is more significant at the lower codes.
Figure 4. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits are ideal)
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
V DD
INPUT VDD
ADN2850
ADN2850
Rp 2.2k
ADN2850 U2
SDI CS CL K SDO
300 WP
C
U1
MO SI SDI CS CL K SDO
S CLK SS
GND
Figure 5. Daisy Chain Configuration DIGITAL INPUT/OUTPUT CONFIGURATION All digital inputs are ESD protected. Digital inputs are high impedance and can be driven directly from most digital sources. For PR and WP, which are active at logic low, should be biased to VDD if they are not used. There are no internal pull-up resistors on any digital input pin. As a result, pull-up resistors are needed if these functions are used. For SDO and RDY pins, they are open drain digital outputs. Similarly, pull-up resistors are needed if these functions are used. To optimize the speed and power trade off, use 2.2k pull-up resistors. WP
+5V R PULLUP
Figure 7B. Equivalent WP Input Protection
SERIAL DATA INTERFACE The ADN2850 contains a four-wire SPI compatible digital interface (SDI, SDO, CS, and CLK). The 24-bit serial word must be loaded with MSB first, and the format of the word is shown in Table 1. The Command Bits (C0 to C3) control the operation of the programmable resistor according to the instruction shown in Table 2. A0 to A3 are assigned for address bits. A0 is used to address RDAC 1 or RDAC2. Addresses 2 to 14 are accessable by users. Address 15 is reserved for factory usage. Table 4 provides an address map of the EEMEM locations. The Data Bits (D0 to D15) are the values that are loaded into the RDAC register. The last instruction prior to a period of no programming activity should be applied with the No Operation (NOP), instruction 0. It is recommended to do so to ensure minimum power consumption in the internal logic circuitry TERMINAL VOLTAGE OPERATING RANGE The ADN2850 positive VDD and negative VSS power supply defines the boundary conditions for proper 2-terminal programmable resistance operation. Supply signals present on terminals W and B that exceed VDD or VSS will be clamped by the internal forward biased diodes, see Figure 8.
VDD
PR
VALID COMMAND COUNTER
COMMAND PROCESSOR & ADDRESS DECODE SERIAL REGISTER
CLK
SDO CS SDI GND Figure 6. Equivalent Digital Input-Output Logic The equivalent serial data input and output logic is shown in figure 6. The open drain output SDO is disabled whenever chip select CS is logic high. The SPI interface can be used in two slave modes CPHA=1, CPOL=1 and CPHA=0, CPOL=0.. ESD protection of the digital inputs is shown in figures 7A & 7B.
VDD
W B
VSS
INPUTS 300 LOGIC PINS
Figure 8. Maximum Terminal Voltages Set by VDD & VSS The ground pin of the ADN2850 device is primarily used as a digital ground reference, which needs to be tied to the PCB's common ground. The digital input contol signals to the ADN2850 must be referenced to the device ground pin (GND), and satisfy the logic level defined in the specification table of this data sheet. An internal level shift circuit insures that the common mode voltage range of the 2-terminals extends from VSS to VDD irrespective of the digital input level.
10
GND
Figure 7A. Equivalent ESD Digital Input Protection
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
RDAC STRUCTURE The RDAC contains a string of equal resistor segments, with an array of analog switches, that act as the wiper connection. The number of positions is the resolution of the device. The ADN2850 has 1024 connection points allowing it to provide better than 0.1% set-ability resolution. Figure 8 shows an equivalent structure of the connections between the two terminals that make up one channel of the RDAC. The SWB will always be ON, while one of the switches SW(0) to SW(2N-1) will be ON one at a time depending on the resistance position decoded from the Data Bits. Since the switch is not ideal, there is a 50 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage, the higher the wiper resistance. Similarly, the higher the temperature, the higher the wiper resistance. RW is the sum of the resistance of SW(D) + SWB from Wiper-to-B terminals Users should be aware of the contribution of the wiper resistance when accurate prediction of the output resistance is needed.
SW(2 N -1) RDAC WIPER REGISTER & DECODER
ADN2850
The 10-bit data word in the RDAC latch is decoded to select one of the 1024 possible settings. The following discussion describes the calculation of resistance RWB(D) at different codes of a 25K part. The wiper first connection starts at the B terminal for data 000H. RWB is 50 because of the wiper resistance and it is independent to the full-scale resistance. The second connection is the first tap point where RWB(1) becomes 24.4+50=74.4 for data 01H. The third connection is the next tap point representing RWB(2)=48.8+50=98.8 for data 02H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB(1023)=25026. See Figure 9 for a simplified diagram of the equivalent RDAC circuit.
25 R W B _F S = 25K 20
RW B(D) - K
15
10
RS
SW(2 N -2)
W
5
0 0 256 512
D - C o d e in De cim al
768
1023
RS
SW(1 )
Figure 10. RWB(D) vs Code The general equation, which determines the programmed output resistance between Wx and Bx, is: RWB ( D) = D RWB _ FS + RW 2N (1)
RS RS=RWB_FS/2
N
SW(0 )
DIGITAL CIRCUITRY OMITTED FOR CLARITY
SWB
B
Figure 9. Equivalent RDAC structure
Table 5. Nominal individual segment resistor values Device Resolution 10-Bit 25 K Version 24.4 250 K Version 244
Where D is the decimal equivalent of the data contained in the RDAC register, 2N is the number of steps, RWB_FS is the full scale resistance between terminals W-and-B, and RW is the wiper resistance. For example, the following output resistance values will be set for the following RDAC latch codes (applies to RWB_FS=25K programmable resistors): D (DEC) 1023 512 1 0 RWB(D) () 25026 12550 74.4 50 Output State
CALCULATIING THE PROGRAMMABLE RESISTANCE The nominal full scale resistance of the RDAC between terminals W-and-B, RWB_FS, are available with 25K and 250K with 1024 positions (10-bit resolution). The final digits of the part number determine the nominal resistance value, e.g., 25K = 25; 250K = 250.
Full-Scale Mid-Scale 1 LSB Zero-Scale (Wiper contact resistance)
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
Note that in the zero-scale condition a finite wiper resistance of 50 is present. Care should be taken to limit the current flow between W and B in this state to no more than 20mA to avoid degradation or possible destruction of the internal switches. The typical distribution of full scale RWB from channel-tochannel matches to 0.2% within the same package. Device to device matching is process lot dependent with the worst case of 30% variation. On the other hand, the change in RWB with temperature has a 35ppm/C temperature coefficient.
ADN2850
TEST CIRCUITS Figures 10 to 12 show some of the test conditions used in the product specification table.
Figure 10. Resistor Position Nonlinearity Error (Rheostat Operation; RINL, R-DNL)
Figure 11. Incremental ON Resistance Test Circuit
Figure 12. Common Mode Leakage current test circuit
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
PROGRAMMING EXAMPLES The following programming examples illustrate typical sequence of events for various features of the ADN2850. Users should refer to Table 2 for the instructions and data word format. The Instruction numbers, addresses, and data appearing at SDI and SDO pins are based in hexadecimal in the following examples.
SDI 32AAAAH SDO Action
ADN2850
XXXXXXH Stores data AAAAH into spare EEMEM location USER1 (Allowable to address in 13 locations with maximum 16-bits of Data) 32AAAAH Stores data 5555H into spare EEMEM location USER2. (Allowable to address 13 locations with maximum 16-bits of Data)
335555H
Example 5. Storing additional user data in EEMEM SDI SDO Action SDI 92XXXXH 00XXXXH SDO Action B00100H XXXXXXH Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position B10200H B00100H Loads data 200H into RDAC2 register, Wiper 2 moves to 1/2 full-scale position
XXXXXXH Prepares data read from USER1 location 92AAAAH NOP instruction #0 sends 24-bit word out of SDO where the last 16 bits contain the contents of USER1 location. NOP command insures device returns to idle power dissipation state
Example 1. Set two programmable resistors to independent data
SDI B00100H
SDO
Action
XXXXXXH Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position Increments RDAC1 register by one to 101H SDI
Example 6. Reading back data from various memory locations
E0XXXXH B00100H
SDO
Action
E0XXXXH E0XXXXH Increments RDAC1 register by one to 102H Continue until desired wiper position reached 20XXXXH XXXXXXH Saves RDAC1 register data into EEMEM1 Optionally tie WP to GND to protect EEMEM values Example 2. Incrementing one programmable resistor followed by storing the wiper setting to EEMEM B00200H C0XXXXH A0XXXXH XXXXXXH Sets RDAC1 to mid-scale B00200H C0XXXXH Doubles RDAC1 from mid-scale to full scale Prepares reading wiper setting from RDAC1 register Readback full scale value from RDAC1 register.
XXXXXXH A003FFH
EEMEM values for RDACs can be restored by Power On or Strobing PR pin or Programming shown below SDI 10XXXXH 00XXXXH 8XXXXXH SDO Action
Example 7. Reading back wiper setting
Analog Devices offers a user friendly ADN2850EVAL evaluation kit and it can be controlled by a personal computer through the printer port.
XXXXXXH Restores EEMEM1 value to RDAC1 register 10XXXXXH NOP. Recommended step to minimize power consumption 00XXXXH Restores EEMEM1 and EEMEM2 values to RDAC1 and RDAC2 registers respectively
Example 3. Restoring EEMEM values to RDAC registers
SDI C0XXXXH C1XXXXH
SDO
Action
XXXXXXH Moves wiper #1 to double the present data contained in RDAC1 register C0XXXXH Moves wiper #2 to double the present data contained in RDAC2 register.
Example 4. Using Left shift by one to increment +6dB steps
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
R FB
ADN2850
Post Amp CDR Data
APPLICATIONS Optical Transmitter Calibration with ADN2841 Together with the multi-rate 2.7Gbps Laser Diode Driver ADN2841, the ADN2850 forms an optical supervisory system where the dual programmable resistors can be used to set the laser average optical power and extinction ratio, see Figure 13. ADN2850 is particularly ideal for the optical parameter settings because of its high resolution and superior temperature coefficient characteristics. The ADN2841 is a 2.7 Gbps laser diode driver that utilizes a unique control algorithm to manage both the laser average power and extinction ratio after the laser initial factory calibration. It stabilizes the laser data transmission by continuously monitoring its optical power, and correcting the variations caused by temperature and the laser degradation over time. In ADN2841, the IMPD monitors the laser diode current. Through its dual loop Power and Extinction Ratio control, calibrated by ADN2850, the internal driver controls the bias current IBIAS and consequently the average power. It also regulates the modulation current, IMODP by changing the modulation current linearly with slope efficiency. Any changes in the laser threshold current or slope efficiency are therefore compensated. As a result, this optical supervisory system minimizes the laser characterization efforts and therefore enables designers to apply comparable lasers provided from multiple sources.
VCC VCC
V 1
TIA
LPF 0.75 Bit Rate
Clock
I PD
I
REF (1+100k/R G) *(V2 - V1)
RG V 2
AD623 In Amp
Log Amp Log (Average Power)
Q 1
Q 2
Figure 14. Conceptual Incoming Optical Power Monitoring Circuit. I V1 = VBE1 = VT ln C1 I S1 I V2 = VBE 2 = VT ln C 2 IS 2 (2) (3)
Note IC1 = 1*IPD, IC2 = 2*IREF. Since Q1 and Q2 are matched, therefore 1 equals 2 and IS1 equals IS2. Combining equations 2 and 3 yields I V1-V2 = VT ln( PD ) I REF (4)
IMPD
ADN2841 ADN2850
RDAC1 W1
IMODP BIAS
CONTROL
CS CLK SDI
B1
PSET
E2MEM
RDAC2 W2
Where IS1 and IS2 are saturation current V1, V2 are VBE, base-emitted voltages of the diode-connector transistors VT is the thermal voltage which is equal to k*T/q. VT=26mV at 25oC k = Boltzmann's constant = 1.38E-23 joules/kelvin q = electron charge = 1.6E-19 coulomb T = temperature in kelvin IPD = photo diode current IREF = reference current
B2
IDTONE
DIN DINQ IDTONE
Figure 13. Optical Supervisory System
Incoming Optical Power Monitoring ADN2850 comes with a pair of matched diode-connected PNPs, Q1 and Q2, which can be used to configure an incoming optical power monitoring function. Figure 14 shows such conceptual circuit. With a reference current source, an instrumentation amplifier, and a logarithmic amplifier, this feature can be used to monitor the optical power by knowing the DC average photo diode current from the following properties:
DIN
E2ME M
DINQ
ERSET
With the final logarithmic amplification, the output voltage represents the average incoming optical power. The output voltage of the log stage does not have to be accurate from device to device as the responsivity of the photo diode will change. However, temperature compensation and the aging stability of the photo diode may be required. The user may also calibrate the log amp using two values of input optical power to give an offset and gradient values. This negates the need for a true log base 10 conversion. Resistance Scaling ADN2850 offers either 25K or 250K full scale resistance. For users who need lower resistance and still maintain the numbers of step adjustment, they can parallel multiple devices. Figure 15 shows a simple scheme of paralleling both channel of the RDACs. In order to adjust half of the resistance linearly per step, users need to program the RDACs coherently with the same settings and tie the terminals as shown. Much lower
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
resistance can also be achieved by paralleling a discrete resistor as shown in Figure 16. The equivalent resistance at a given setting is approximated as
Req = D RWB _ FS + 51200 D RWB _ FS + 51200 + 1024 R
ADN2850
Listing I. Macro Model Net List for RDAC .PARAM D=1024, RDAC=25E3 * .SUBCKT RDAC (W,B) * RWB W B {D/1024*RDAC+50} CW W 0 80E-12 CB B 0 8E-12 * .ENDS RDAC
(5)
Figure 15. Reduce Resistance by half with linear adjustment characteristics
Figure 16. Resistor Scaling with log adjustment characteristics
In this approach, the adjustment is not linear but logarithmic. Users should also be aware the need for tolerance matching as well as temperature coefficient matching of the components.
BASIC RDAC SPICE MODEL
RDAC 25k
=8pF CW=80pF
Figure 17. RDAC Circuit Simulation Model for RDAC = 25 k
The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. A general parasitic simulation model is shown in Figure 7. Listing I provides a macro model netlist for the 25 k RDAC:
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
ADN2850 - Typical Performance Characteristics
ADN2850
IDD 1mA/DIV VSDI 5V/DIV
TPC 1 - Supply Current When Writing Data to RDAC
VSDI 5V/DIV
TPC 2 - Supply Current in Storing Data to E2MEM
TPC 3 - Supply Current in Retreiving Data from E2MEM
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
ADN2850
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PRELIMINARY TECHNICAL DATA Nonvolatile Memory Programmable Resistors
16-Lead LFCSP 5mm x 5mm (CP-16)
ADN2850
Note: ADN2850 has 16 pins. Drawing above illustrates a generic LFCSP package outline only. Please see table for details
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