View LB11870_363206.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : ENN7256
Monlithic Digital IC
LB11870
Three-Phase Brushless Motor Driver for Polygonal Mirror Motors
Overview
The LB11870 is a three-phase brushless motor driver developed for driving the motors used with the polygonal mirror in laser printers and plain paper copiers. It can implement, with a single IC chip, all the circuits required for polygonal mirror drive, including speed control and driver functions. The LB11870 can implement motor drive with minimal power loss due to its use of direct PWM drive.
Package Dimensions
unit: mm 3265-HSSOP48
[LB11870]
17.8 (6.2)
48
25
(4.9)
* * * * * * *
Three-phase bipolar drive Direct PWM drive Includes six high and low side diodes on chip. Output current control circuit PLL speed control circuit Phase lock detection output (with masking function) Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip. * Deceleration type switching circuit (free running or reverse torque) * PWM oscillator * Power saving circuit
1
(0.45)
0.65 1.3
0.2
24
(2.2)
0.2
SANYO: HSSOP48 (375 mil)
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg T 500 ms Independent IC Mounted on a PCB (114.3 x 76.1 x 1.6 mm, glass epoxy) Conditions Ratings 30 1.8 0.85 1.72 -20 to +80 -55 to +150 Unit V A W W C C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80102AS (OT) No. 7256 -1/14
0.1
1.5
2.4max
0.65
Functions and Features
10.5
7.9
LB11870 Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage range 5 V constant voltage output current LD pin applied voltage LD pin output current FGS pin applied voltage FGS pin output current Symbol VCC IREG VLD ILD VFGS IFGS Conditions Ratings 9.5 to 28 0 to -20 0 to 28 0 to 15 0 to 28 0 to 10 Unit V mA V mA V mA
Electrical Characteristics at Ta = 25C, VCC = VM = 24 V
Parameter Supply current 1 Supply current 2 [5 V Constant Voltage Output Circuit] Output voltage Voltage regulation Load regulation Temperature coefficient [Output Block] Output saturation voltage 1 Output saturation voltage 2 Output leakage current Lower diode forward voltage 1 Lower diode forward voltage 2 Upper diode forward voltage 1 Upper diode forward voltage 2 [Hall Amplifier Block] Input bias current Common-mode input voltage range Hall input sensitivity Hysteresis width Input voltage: Low to high Input voltage: High to low [FG Schmitt Block] Input bias current Common-mode input voltage range Input sensitivity Hysteresis width Input voltage: Low to high Input voltage: High to low [PWM Oscillator] High-level output voltage Low-level output voltage External capacitor charge current Oscillator frequency Amplitude [FGS Output] Output saturation voltage Output leakage current [CSD Oscillator Circuit] High-level output voltage Low-level output voltage Amplitude External capacitor charge current External capacitor charge current Oscillator frequency VOH (CSD) VOL (CSD) V (CSD) ICHG1 ICHG2 f (CSD) C = 0.068 F 3.2 0.9 2.15 -13.5 6 3.5 1.1 2.4 -9.5 10 29 3.8 1.3 2.65 -5.5 14 V V Vp-p A A Hz VOL (FGS) IFGS = 7 mA IL (FGS) VO = VCC 0.15 0.5 10 V A VOH (PWM) VOL (PWM) ICHG f (PWM) V (PWM) VPWM = 2 V C = 680 pF 1.45 2.65 0.9 -60 2.95 1.2 -45 34 1.75 2.05 3.25 1.5 -30 V V A kHz Vp-p IB (FGS) VICM (FGS) VIN (FGS) VIN (FGS) VSLH (FGS) VSHL (FGS) -2 0 80 15 24 12 -12 42 -0.5 VREG - 2.0 A V mVp-p mV mV mV VIN (HA) VSLH VSHL IHB VICM -2 0 80 15 24 12 -12 42 -0.5 VREG - 2.0 A V mVp-p mV mV mV Vosat1 Vosat2 IOleak VD1-1 VD1-2 VD2-1 VD2-2 ID = -0.5 A ID = -1.2 A ID = 0.5 A ID = 1.2 A 1.0 1.4 1.2 1.9 IO = 0.5 A, VO (SINK) + VO (SOURCE) IO = 1.2 A, VO (SINK) + VO (SOURCE) 1.9 2.6 2.4 3.2 100 1.3 1.8 1.6 2.4 V V A V V V V VREG VREG1 VREG2 VREG3 VCC = 9.5 to 28 V IO = -5 to -20 mA Design target value 4.65 5.0 80 10 0 5.35 130 60 V mV mV mV/C Symbol ICC1 ICC2 In stop mode Conditions Ratings min typ 16 3.5 max 21 5.0 Unit mA mA
Continued on next page. No. 7256 -2/14
LB11870
Continued from preceding page.
Parameter [Phase Comparator Output] High-level output voltage Low-level output voltage Output source current Output sink current [Lock Detection Output] Output saturation voltage Output leakage current [Error Amplifier Block] Input offset voltage Input bias current Output H level voltage Output L level current DC bias level [Current limiter Circuit] Drive gain 1 Drive gain 2 Limiter voltage [Thermal Shutdown Operation] Thermal shutdown operating temperature Hysteresis width [Low-Voltage Protection] Operating voltage Hysteresis width [CLD Circuit] External capacitor charge current Operating voltage [CLK Pin] External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current [S/S Pin] High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current [BRSEL Pin] High-level input voltage Low-level input voltage Input open voltage High-level input current Low-level input current VIH (BRSEL) VIL (BRSEL) VIO (BRSEL) IIH (BRSEL) IIL (BRSEL) VBRSEL = VREG VBRSEL = 0 V 3.5 0 VREG - 0.5 -10 -220 0 -160 VREG 1.5 VREG 10 V V V A A VIH (SS) VIL (SS) VIO (SS) VIS (SS) IIH (SS) IIL (SS) VS/S = VREG VS/S = 0 V 3.5 0 VREG - 0.5 0.35 -10 -280 0.5 0 -210 VREG 1.5 VREG 0.65 10 V V V V A A fI (CLK) VIH (CLK) VIL (CLK) VIO (CLK) VIS (CLK) IIH (CLK) IIL (CLK) VCLK = VREG VCLK = 0 V 0.1 3.5 0 VREG - 0.5 0.35 -10 -280 0.5 0 -210 10 VREG 1.5 VREG 0.65 10 kHz V V V V A A ICLD VH (CLD) -6 3.25 -4.3 3.5 -3 3.75 A V VSD VSD 8.1 0.2 8.45 0.35 8.9 0.5 V V TSD TSD Design target value (junction temperature) Design target value (junction temperature) 150 175 40 C C GDF1 GDF2 VRF When the phase is locked When not locked VCC-VM 0.4 0.8 0.45 0.5 1.0 0.5 0.6 1.2 0.55 deg deg V VIO (ER) IB (ER) VOH (ER) IOH = -500 A VOL (ER) VB (ER) IOL = 500 A -5% Design target value -10 -1 VREG - 1.2 VREG - 0.9 0.9 VREG/2 1.2 5% 10 1 mV A V V V VOL (LD) IL (LD) ILD = 10 mA VO = VCC 0.15 0.5 10 V A VPDH VPDL IPD+ IPD- IOH = -100 A IOL = 100 A VPD = VREG/2 VPD = VREG/2 1.5 VREG - 0.2 VREG - 0.1 0.2 0.3 -0.5 V V mA mA Symbol Conditions Ratings min typ max Unit
No. 7256 -3/14
LB11870 Three-Phase Logic Truth Table (IN = [H] indicates a condition in which: IN+ > IN-)
IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L
Pin Arrangement
FRAME BRSEL VREG FGFIL 25 24 TOC
GND3
OUT3
VCC1
VCC2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
LB11870
1 OUT2
2 NC
3 OUT1
4 NC
5 NC
6 IN3+
7 NC
8 IN3-
9 IN2+
10 IN2-
11 IN1+
12 IN1- FRAME
13 FGIN+
14 FGIN-
15 GND1
16 GND2
17 PWM
18 NC
19 FC
20 NC
21 PD
22 EI
23 EO
Pdmax -- Ta Characteristics Curve
Pd max -- Ta
2.0 1.72W Mounted on a board (114.3 x 76.1 x 1.6mm, glass epoxy)
Power dissipation, Pd max -- W
1.6
1.2 0.85W 0.8 Independent IC 0.963W
0.476W 0.4
-20
0
20
40
60
80
100
Ambient temperature, Ta -- C
CSD
VM2
VM1
FGS
CLK
NC
NC
NC
NC
PH
LD
CLD
S/S
NC
NC
NC
NC
No. 7256 -4/14
LB11870 Pin Functions
Pin OUT1 OUT2 OUT3 IN1+, IN1- IN2+, IN2- IN3+, IN3- FG IN+ FG IN- GND1 GND2 PWM FC PD EI EO TOC FGFIL Pin No. 3 1 46 11, 12 9, 10 6, 8 13 14 15 16 17 19 21 22 23 24 25 Outputs The PWM signal controls the duty from the low side transistor.
Hall inputs for the three phases The logic H state means that VIN+ is greater than VIN-. FG comparator noninverting input FG comparator inverting input Control system ground Subsidiary ground. Sets the PWM oscillator frequency. Insert a capacitor between this pin and ground. Current control circuit frequency characteristics correction. Insert a capacitor between this pin and ground. Phase comparator output. Outputs the phase error as changes in the pulse duty. Error amplifier input Error amplifier output Torque command input. This pin is normally connected to the EO pin. When the TOC potential falls, the low side output transistor on duty is changed and the torque increases. FG filter connection. Insert a capacitor between this pin and ground if noise on the FG signal is a problem. Sets the operating time for the rotor constraint protection circuit and the initial reset operation.
CSD
26
Insert a capacitor between this pin and ground. If the rotor constraint protection circuit is not used, insert a resistor in parallel with this capacitor. Sets the phase locked signal mask time. Insert a capacitor between this pin and ground. Leave this pin open if there is no need to mask. FG Schmitt output. This is an open-collector output. Phase locked state detection output. This output goes to the on state when the PLL phase is locked. This is an opencollector output. Start/stop control input. Low: start, High or open: stop. Clock input. The maximum input frequency is 10 kHz. Deceleration control switching input. Low: Reverse torque control, High or open: free running. An external Schottky barrier diode is required on the output low side if reverse torque control is used. Smoothes the RF waveform. Insert a capacitor between this pin and ground. 5 V regulator output (control circuit power supply). Insert a capacitor between this pin and ground for power supply stabilization. Output block power supply. Short this pin to VM2. Output current detection. Insert a resistor between this pin and VCC1. The maximum output current IOUT is set to be IOUT = 0.5/Rf. Upper diode cathode connection. Short this pin to VCC1. Power supply. Insert a capacitor between this pin and ground to assure that noise does not enter the IC. Output circuit block ground. Connect this pin to ground. The FRAME pin is connected internally to the metal surface on the back of the package. To improve thermal dissipation, solder this metal surface to the PCB.
CLD FGS LD S/S CLK BRSEL PH VREG VM1 VM2 VCC2 VCC1 GND3 FRAME
27 28 29 32 33 34 35 36 37 38 39 40 44
2, 4, 5, 7 18, 20, 30 NC 31, 41, 42 43, 45, 47 48 Since these pins are not connected to the IC internally, they can be used for wiring connections.
No. 7256 -5/14
LB11870 Internal Equivalent Circuit Block Diagram and External Component Reference
VREG
VREG
FGFIL
FGS
LD
CLD PD
FGIN- FGIN+
- +
LD FG FILTER
LDMASK
EI VREG - + EO
CLK CLK PLL TSD VREG TOC VREG
PWM
PWM OSC COMP
CONT AMP
FC
S/S
S/S PEAK HOLD
PH
VCC2 BRSEL BRSEL LOGIC CURR LIM VCC1 VM2 Rf VM1 COUNT OUT1 HALL LOGIC DRIVER OUT2 HALL HYS AMP OUT3
VCC
CSD
CSD OSC
IN1+ IN1- VREG
IN2+ IN2-
IN3+ IN3-
GND1 GND2
GND3
No. 7256 -6/14
LB11870 Pin Functions
Pin No. 3 1 46 44 Pin OUT1 OUT2 OUT3 GND3 Output block ground Output block power supply and current detection. 37 38 VM1 VM2 Insert the resistor Rf between this pin and VCC1. The output current will be limited to the current value IOUT = VRF/Rf. Motor drive output Function Equivalent circuit
39 VCC1 300 38 37
1
3
46
39
VCC2
Upper diode cathode connection. Short this pin to VCC1.
44
VREG
11 12 9 10 6 8 IN1+ IN1- IN2+ IN2- IN3+ IN3- Hall element inputs. The high state is when IN+ is greater than IN-, and the low state is the reverse. An amplitude of at least 100 mVp-p (differential) is desirable for the Hall element signal inputs. If noise on the Hall signals is a problem, insert capacitors between the IN+ and IN- inputs.
6
9
11
300
300
8
10 12
VREG
FG input. 13 14 FGIN+ FGIN- If noise on the FG signal input is a problem, connect a filter consisting of either a capacitor or a capacitor and a resistor.
13
300
300
14
15 16
GND1 GND2
Control circuit block ground SUBGND pin
Continued on next page.
No. 7256 -7/14
LB11870
Continued from preceding page.
Pin No. Pin Function Equivalent circuit
VREG
Sets the PWM oscillator frequency. 17 PWM Insert a capacitor between this pin and ground. The PWM oscillator frequency is set to about 34 kHz when a 680 pF capacitor is used.
200 2k
17
VREG
Frequency characteristics correction for the current control circuit. 19 FC Insert a capacitor (about 0.01 to 0.1 F) between this pin and ground. The output duty is determined by comparing the voltage on this pin to the PWM oscillator waveform.
300
19
VREG
Phase comparator output 21 PD The phase error is converted to a pulse duty and output from this pin.
300
21
VREG
22
EI
Error amplifier input
300
22
VREG
23
EO
Error amplifier output
23
40k
Continued on next page.
No. 7256 -8/14
LB11870
Continued from preceding page.
Pin No. Pin Function Equivalent circuit
VREG
Torque command voltage input. 24 TOC This pin is normally connected to the EO pin. When the TOC voltage falls, the lower output transistor on duty is increased.
300
24
VREG
FG filter connection. 25 FGFIL If noise on the FG signal input is a problem, insert a capacitor (up to about 2200 pF) between this pin and ground.
25
VREG
Sets the rotor constraint protection circuit operating time and the initial reset pulse. A protection operating time of about 8 seconds can be set by insert a capacitor of about 0.068 F between this pin and ground. If the rotor constraint protection circuit is not used, insert a resistor and a capacitor in parallel between this pin and ground. (Values: about 220 k and 4700 pF)
26
CSD
300
26
VREG
Sets the phase lock state signal mask time. 27 CLD A mask time of about 90 ms can be set by inserting a capacitor of about 0.1 F between this pin and ground. Leave this pin open if masking is not required.
300
27
VREG
28
28 FGS FG Schmitt output
Continued on next page. No. 7256 -9/14
LB11870
Continued from preceding page.
Pin No. Pin Function Equivalent circuit
VREG 29
Phase lock state detection output. 29 LD This output goes to the on state (low level) when the phase is locked.
VREG
Start/stop control input Low: 0 to 1.5 V 32 S/S High: 3.5 V to VREG Hysteresis: 0.5 V Low: start. This pin goes to the high level when open.
22k 2k 32
VREG
Clock input. Low: 0 to 1.5 V High: 3.5 V to VREG 33 CLK Hysteresis: 0.5 V fCLK = 10 kHz (maximum) If noise is a problem, use a capacitor to remove that noise at this input.
22k 2k 33
VREG
Deceleration switching control input. Low: 0 to 1.5 V High: 3.5 V to VREG 34 BRSEL This pin goes to the high level when open. Low: reverse torque control, High: free running. An external Schottky barrier diode is required on the output low side if reverse torque control is used.
30k 2k 34
VREG
RF waveform smoothing. 35 PH If noise on the RF waveform is a problem, insert a capacitor between this pin and ground.
500
35
Continued on next page.
No. 7256 -10/14
LB11870
Continued from preceding page.
Pin No. Pin Function Equivalent circuit
Vcc
Stabilized power supply output (5 V output). 36 VREG Insert a capacitor of about 0.1 F between this pin and ground for stabilization.
36
Power supply. 40 VCC1 Insert a capacitor of at least 10 F between this pin and ground to prevent noise from entering the IC.
2, 4, 5 7, 18 20, 30 31, 41 42, 43 45, 47 48 FRAME Connect this pin to ground. NC Since these pins are not connected to the IC internally, they can be used for wiring connections.
No. 7256 -11/14
LB11870 Overview of the LB11870 1. Speed Control Circuit This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter. This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (falling edges on the FGIN+ and FGS signals), and the IC uses the detected error to control motor speed. During this control operation, the FG servo frequency will be the same as the CLK frequency. fFG (servo) = fCLK 2. Output Drive Circuit To minimize power loss in the output circuits, this IC adopts a direct PWM drive technique. The output transistors are always saturated when on, and the IC adjusts the motor drive output by changing the output on duty. The low side output transistor is used for the output PWM switching. Both the high and low side output diodes are integrated in the IC. However, if reverse torque control mode is selected for use during deceleration, or if a large output current is used and problems occur (such as incorrect operation or waveform disruption due to low side kickback), a Schottky diode should be inserted between OUT and ground. Also, if it is necessary to reduce IC heating during steady-state (constant speed) operation, it may be effective to insert a Schottky diode between VCC and OUT. (This is effective because the load associated with the regenerative current during PWM switching is born not by the on-chip diode but by the external diode.) 3. Current Limiter Circuit The current limiter circuit limits the peak level of the current to a level determined by I = VRF/Rf (where VRF = 0.5 V (typical) and Rf is the value of the current detection resistor). The current limiter operates by reducing the output on duty to suppress the current. The current limiter circuit detects the reverse recovery current of the diode due to PWM operation. To assure that the current limiting function does not malfunction, its operation has a delay of about 2 s. If the motor coils have a low resistance or a low inductance, current fluctuations at startup (when there is no reactive power in the motor) will be rapid. The delay in this circuit means that at such times the current limiter circuit may operate at a point well above the set current. Designers must take this increase in the current due to the delay into account when setting the current limiter value. 4. Power Saving Circuit This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is implemented by removing the bias current from most of the circuits in the IC. However, the 5 V regulator output is provided in the power saving state. 5. Reference Clock Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. If the IC is set to the start state when the reference clock signal is not present, if the rotor constraint protection circuit is used, the motor will turn somewhat and then motor drive will be shut off. However, if the rotor constraint protection circuit is not used, and furthermore reverse torque control mode is selected for deceleration, the motor will be driven at ever increasing speed in the reverse direction. (This is because the rotor constraint protection circuit oscillator signal is used for clock cutoff protection.) Applications must implement a workaround for this problem if there is any possibility whatsoever for it to occur. 6. Notes on the PWM Frequency The PWM frequency is determined by the value of the capacitor C (in F) connected to the PWM pin. .=. 1 / (43000 x C) f
PWM
If a 680 pF capacitor is used, the circuit will oscillate at about 34 kHz. If the PWM frequency is too low, the motor will emit switching noise, and if it is too high, the power loss in the output will be excessive. A PWM frequency in the range 15 to 50 kHz is desirable. To minimize the influence of the output on this circuit, the ground lead of this capacitor should be connected as close as possible to the IC control system ground (the GND1 pin).
No. 7256 -12/14
LB11870 7. Hall Input Signals Signals with an amplitude in excess of the hysteresis (42 mV maximum) must be provided as the Hall input signals. However, an amplitude of over 100 mV is desirable to minimize the influence of noise. If the output waveforms are disturbed (at phase switching) due to noise on the Hall inputs, insert capacitors across these inputs. 8. FG Input Signal Normally, one phase of the Hall signals is input as the FG signal. If noise is a problem the input must be filtered with either a capacitor or an RC filter circuit. Although it is also possible to remove FG signal noise by inserting a capacitor between the FGFIL pin and ground, the IC may not be able to operate correctly if this signal is damped excessively. If this capacitor is used, its value must be less than about 2200 pF. If the location of this capacitor's ground lead is inappropriate, it may, inversely, make noise problems even more likely to occur. Thus the ground lead location must be chosen carefully. 9. Rotor Constraint Protection Circuit This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is constrained. If the LD output is high (unlocked) for over a certain fixed period with the IC in the start state, the low side transistor will be turned off. The time constant is determined by the capacitor connected to the CSD pin. .=. 120 x C (F) If a 0.068 F capacitor is used, the protection time will be about 8 seconds. The set time must be selected to have an adequate margin with respect to the motor startup time. This protection circuit will not operate during deceleration when the clock frequency is switched. To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off and reapplied. Since the CSD pin also functions as the initial reset pulse generation pin at startup, the logic circuit will go to the reset state and the IC will not be able to function if this pin is connected to ground. Therefore, both a 220 k resistor and a 4700 pF capacitor must be inserted between this pin and ground if the rotor constraint protection circuit is not used. 10. Phase Lock Signal (1) Phase lock range Since this IC does not include a counter or similar functionality in the speed control system, the speed error range in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at startup and when unlocked due to switching clock frequencies. (2) Masking function for the phase lock state signal A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pullin. However, this results in the lock state signal output being delayed by the masking time. The masking time is determined by the capacitor inserted between the CLD pin and ground. .= 0.9 x C (F) . When a 0.1 F capacitor is used, the masking time will be about 90 ms. In cases where complete masking is required, a masking time with fully adequate margin must be used. If no masking is required, leave the CLD pin open.
No. 7256 -13/14
LB11870 11. Power Supply Stabilization Since this IC provides a large output current and adopts a switching drive technique, the power supply line level can be disrupted easily. Thus capacitors large enough to stabilize the power supply voltage must be inserted between the VCC pins and ground. The ground leads of these capacitors must be connected to the three pins that are the power grounds, and they must be connected as close as possible to the pins themselves. If these capacitors (electrolytic capacitors) cannot be connected close to their corresponding pins, ceramic capacitors of about 0.1 F must be connected near these pins. If reverse torque control mode is selected for use during deceleration, since there are states where power is returned to the power supply system, the power supply line levels will be particularly easily disrupted. Since the power line level is most easily disrupted during lock pull-in at high motor speeds, this state needs extra attention; in particular, capacitors that are adequately large to handle this situation must be selected. If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. 12. VREG Stabilization A capacitor of at least 0.1 F must be used to stabilize the VREG voltage, which is the control circuit power supply. The ground lead of that capacitor must be connected as close as possible to the IC control system ground (GND1). 13. Error Amplifier External Component Values To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC as possible. In particular, they must be located as far from the motor as possible. 14. FRAME Pin and the IC Metallic Rear Surface The FRAME pin must be connected to the GND1 and GND2 pins, and the ground side of the electrolytic capacitor must be connected to GND3. The IC's metallic rear surface is connected to the FRAME pin internally to the IC. Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC package to the PCB with, for example, a solder with good thermal conductivity.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 2002. Specifications and information herein are subject to change without notice. PS No. 7256 -14/14

▲Up To Search▲

Price & Availability of LB11870

	To Download LB11870 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .