View ASM5P2304B-2H_359047.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

August 2004 rev 2.0
3.3 V Zero Delay Buffer
Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer "ASM5P2304A Configurations Table". Input frequency range: 10MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200 ps. Device-device skew less than 500 ps. Two banks of four outputs. Less than 200 ps cycle-to-cycle jitter (-1, -1H, -5H). Available in space saving, 8-pin 150-mil SOIC packages and standard TSSOP. 3.3V operation. Advanced 0.35 CMOS technology. Industrial temperature available. Functional Description
ASM5P2304A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in a 8-pin package. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less
ASMP5P2304A
than 250ps, and the output-to-output skew is guaranteed to be less than 200ps. The ASM5P2304A has two banks of two outputs each. Multiple ASM5P2304A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500ps. The ASM5P2304A is available in two different
configurations (Refer "ASM5P2304A Configurations Table). The ASM5P2304A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2304A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The ASM5P2304A-2 allows the user to obtain Ref, 1/2 X and 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. The ASM5P2304A-5H is a high-drive version with REF/2 on both banks
Block Diagram
FBK CLKA1 REF PLL
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004 rev 2.0
ASM5P2304A Configurations Device ASM5P2304A-1 ASM5P2304A-1H ASM5P2304A-2 ASM5P2304A-2 ASM5P2304A-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference Reference /2
ASM5P2304A
Bank B Frequency Reference Reference Reference /2 Reference Reference /2
Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded.
1500
1000
REF-Input to CLKA/CLKB Delay (ps)
500
0 -30 -500 -25 -20 -15 -10 -5 0
5
10
15
20
25
30
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
To close the feedback loop of the ASM5P2304A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally.
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 13
August 2004 rev 2.0
Pin Configuration
REF CLKA1 CLKA2 GND 1 2 3 4 8 FBK V
DD
ASM5P2304A
ASM5P2304A
7 6
CLKB2
5 CLKB1
Pin Description for ASM5P2304A
Pin # 1 2 3 4 5 6 7 8
Pin Name REF1 CLKA12 CLKA22 GND CLKB12 CLKB2 2 VDD FBK
Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A Ground Buffered clock output, bank B Buffered clock output, bank B 3.3V supply PLL feedback input
Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs.
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 13
August 2004 rev 2.0
Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 >2000
ASM5P2304A
Unit V V V uC uC uC V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability.
Operating Conditions for ASM5P2304A Commercial Temperature Devices
Parameter VDD TA CL CL CIN Supply Voltage
Description
Min 3.0 0
Max 3.6 70 30 15 7
Unit V uC pF pF pF
Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance3
Note: 3. Applies to both Ref Clock and FBK.
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 13
August 2004 rev 2.0
Electrical Characteristics for ASM5P2304A Commercial Temperature Devices
ASM5P2304A
Parameter VIL VIH IIL IIH VOL
Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage 4
Test Conditions
Min
Max 0.8
Unit V V
2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 2.4 50.0 100.0
A A
0.4
V
VOH
Output HIGH Voltage 4
V
TBD TBD mA
IDD
Supply Current
Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2)
TBD
TBD
Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 13
August 2004 rev 2.0
Switching Characteristics for ASM5P2304A Commercial Temperature Devices
Paramete r t1 t1 t1 Description Test Conditions Min
ASM5P2304A
Typ
Max
Unit
Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2,-1H, -5H)
4 4
30-pF load, All devices 20-pF load, -1H, -5H devices 15-pF load, -1, -2 devices Measured at 1.4V, FOUT = 66.66 MHz 30-pF load Measured at 1.4V, FOUT = <50 MHz 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 0.8V and 2.0V 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 2.0V and 0.8V 30-pF load Measured between 2.0V and 0.8V 15-pF load Measured between 2.0V and 0.8V 30-pF load
4
10 10 10 40.0 50.0
100 133.3 133.3 60.0
MHz MHz MHz %
45.0
50.0
55.0
%
t3
Output Rise Time (-1, -2) Output Rise Time (-1, -2) Output Rise Time (-1H, -5H) Output Fall Time (-1, -2) Output Fall Time (-1, -2) Output Fall Time (-1H, -5H)
4
2.20
ns
4
t3
1.50
ns
4
t3
1.50
ns
4
t4
2.20
ns
4
t4
1.50
ns
4
t4
1.25 200 200
ns
Output-to-output skew on same bank (-1, -2) Output-to-output skew (-1H, -5H) Output bank A -to- output bank B skew (-1, 5H) Output bank A to output bank b skew (-2) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge Device-to-Device Skew Output Slew Rate
4 4
All outputs equally loaded All outputs equally loaded
t5
ps All outputs equally loaded All outputs equally loaded
3
200 400 0 0 1 250 500 ps ps V/ns
Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15 pF load
175 ps
tJ
Cycle-to-cycle jitter (-1, -1H, -5H)
4
Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30pF load Measured at 66.67 MHz, loaded outputs, 15 pF load
200
100
tJ
Cycle-to-cycle jitter (-2,)
4
400 ps 375
tLOCK
PLL Lock Time
4
Stable power supply, valid clock presented on REF and FBK pins
1.0
ms
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
6 of 13
August 2004 rev 2.0
Operating Conditions for ASM5I2304A Industrial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance3 Description Min 3.0 -40
ASM5P2304A
Max 3.6 85 30 15 7
Unit V uC pF pF pF
Electrical Characteristics for ASM5I2304A Industrial Temperature Devices
Parameter VIL VIH IIL IIH VOL
Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage 4
Test Conditions
Min
Max 0.8
Unit V V
2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 2.4 TBD TBD TBD 50.0 100.0 0.4
A A V
VOH
Output HIGH Voltage 4
V
IDD
Supply Current
Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2)
mA
TBD
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
7 of 13
August 2004 rev 2.0
Switching Characteristics for ASM5I2304A Industrial Temperature Devices All parameters are specified with loaded outputs
Parameter t1 t1 t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) t3 Output Rise Time (-1, -2) Output Rise Time (-1, -2) Output Rise Time (-1H, -5H) Output Fall Time (-1, -2) Output Fall Time (-1, -2) Output Fall Time (-1H, -5H)
4 4 4
ASM5P2304A
Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices 15-pF load, -1 and -2 devices Measured at 1.4V, FOUT = <66.66 MHz 30-pF load Measured at 1.4V, FOUT = <50 MHz 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 0.8V and 2.0V 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 2.0V and 0.8V 30-pF load Measured between 2.0V and 0.8V 15-pF load Measured between 2.0V and 0.8V 30-pF load
4
Min 10 10 10 40.0
Typ
Max 100 133.3 133.3
Unit MHz MHz MHz %
50.0
60.0
45.0
50.0
55.0
%
2.50
ns
4
t3
1.50
ns
4
t3
1.50
ns
4
t4
2.50
ns
4
t4
1.50
ns
4
t4
1.25 200 200 200 400 0 0 1 250 500
ns
Output-to-output skew on same bank (-1, -2) Output-to-output skew (-1H, -5H)
All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded
t5
ps
Output bank A -to- output bank B skew (-1, -5H) Output bank A -to- output bank B skew (-2) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge Device-to-Device Skew Output Slew Rate
4 4 4
Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15 pF load
ps ps V/ns
180 ps
tJ
Cycle-to-cycle jitter (-1, -1H, -5H)
4
Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load
4
200
100 400 ps 380
tJ
Cycle-to-cycle jitter (-2)
Measured at 66.67 MHz, loaded outputs, 30pF load Measured at 66.67 MHz, loaded outputs, 15 pF load Stable power supply, valid clock presented on REF and FBK pins
tLOCK
PLL Lock Time
4
1.0
ms
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8 of 13
August 2004 rev 2.0
Switching Waveforms Duty Cycle Timing
t1 t2
ASM5P2304A
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
2.0 V OUTPUT 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
V
INPUT
DD
/2
V
OUTPUT
DD
/2
t6
Device - Device Skew
V
FBK, Device 1
DD
/2
V
FBK, Device 2
DD
/2
t7
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9 of 13
August 2004 rev 2.0
Test Circuits
Test Circuit #1 Test Circuit #2
ASM5P2304A
V 0.1 yF
DD
V OUTPUTS C 0.1 yF
DD
1k OUTPUTS 1k
LOAD
10 pF
V 0.1 yF
DD
V GND 0.1 yF
DD
GND
GND
GND
For parameter 8 (output slew rate) on -1H devices t
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
10 of 13
August 2004 rev 2.0
Package Information: 8-lead (150 Mil) Molded SOIC
ASM5P2304A
E
H
D
A
e B
A1
D
L
C
Symbo l
Dimensions in inches
Dimensions in millimeters Min 1.35 0.10 0.33 0.18 4.78 3.80 5.80 Max 1.75 0.25 0.53 0.27 5.00 4.01 6.20
Min A A1 B C D E H e L 0.053 0.004 0.013 0.007 0.188 0.150 0.228
Max 0.069 0.010 0.022 0.012 0.197 0.158 0.244
0.050 BSC 0.016 0u 0.035 8u
1.27 BSC 0.40 0u 0.89 8u
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 13
August 2004 rev 2.0
Ordering Code ASM5P2304A-1-08-SR ASM5P2304A-1-08-ST ASM5I2304A-1-08-SR ASM5I2304A-1-08-ST ASM5P2304A-1H-08-SR ASM5P2304A-1H-08-ST ASM5I2304A-1H-08-SR ASM5I2304A-1H-08-ST ASM5P2304A-2-08-SR ASM5P2304A-2-08-ST ASM5I2304A-2-08-SR ASM5I2304A-2-08-ST ASM5P2304A-5H-08-SR ASM5P2304A-5H-08-ST ASM5I2304A-5H-08-SR ASM5I2304A-5H-08-ST Package Type 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE
ASM5P2304A
Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial
Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920. Preliminary datasheet. Specification subject to change without notice.
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
12 of 13
August 2004 rev 2.0
ASM5P2304A
Use the chart below for device ordering *note Lead Free Option... DEVICE ORDERING INFORMATION
Package Suffix ASM5P2304A F - 08-OR
OR = SOT23/ T/R TT = TSSOP, TUBE TR = TSSOP, T/R VT = TVSOP,TUBE VR = TVSOP, T/R ST = SOIC, TUBE SR = SOIC,T/R JT = SSOP, TUBE JR = SSOP, T/R QR = QFN, T/R QT = QFN, TUBE BT = BGA, TUBE BR = BGA, T/R
DEVICE PIN COUNT F = Pb FREE PART NUMBER X= Automotive 1 2 3 4 5 = = = = =
I= Industrial
P or n/c = Commercial
reserved Non PLL based EMI Reduction DDR support products STD Zero Delay Buffer
6 = Power Management * * * 7 = Power Management * * * 8 = Power Management * * * 9 = Hi Performance 0 = reserved
Alliance Semiconductor Mixed Signal Product
* * * NOTE: Industry Standard Part Numbers May Be used That Differ from this part numbering system...
Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Note: This product utilizes US# 6,646,463 Impedance Emulator Patent issued to Dan Hariton / Alliance Semiconductor, dated 11-11-2003 Part Number: ASM5P2304A Document Version: 2.0 8_30_2004
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3 Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
13 of 13

▲Up To Search▲

Price & Availability of ASM5P2304B-2H

	To Download ASM5P2304B-2H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .