View STLC60135_355579.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
STLC60134 STLC60135
ADSL MODEM CHIP SET
PRODUCT PREVIEW
COMPLETE CHIP SET FOR ADSL MODEM FUNCTIONS COMPLIANCE WITH ANSI T1.413 ISSUE 1 & ISSUE 2 IMPLEMENTS DISCRETE MULTITONE (DMT) MODULATION AND DEMODULATION DATA RATES UP TO 8Mbps DOWNSTREAM AND TO 1Mbps UPSTREAM WITH 32Kbps GRANULARITY BUILT-IN ATM TRANSPORT SUPPORT ADAPTIVE RATE MODE IN 32Mbps INCREMENTS APPLICABLE AT BOTH ENDS OF LOOP: ATU-C (LT) AND ATU-R (NT) 255 CARRIERS WITH 4.3125KHz SPACING DEDICATED SOFTWARE DRIVER AVAILABLE PROCESSOR INDEPENDENT C++ SOURCE COMPILATION FREQUENCY DIVISION MULTIPLEXING (FDM) FOR HIGH ROBUSTNESS IN PRESENCE OF CROSSTALK REED-SOLOMON FORWARD ERROR CORRECTION TRELLIS CODER AND DECODER PROGRAMMABLE SIMULTANEOUS SUPPORT OF INTERLEAVED AND NON-INTERLEAVED CHANNELS (DUAL LATENCY) FULL, REDUCED AND MINIMAL ATM OVERHEAD FRAMING MODES BIT STREAM MODE CAPABLITY FOR STM TRANSPORT DIRECT CONNECTION TO ATM SYSTEMS VIA UTOPIA INTERFACE (LEVEL 1 OR 2) MICROCONTROLLER INTERFACE WITH 16 BITS MULTIPLEXED ADDRESS/DATA BUS LOW POWER TECHNOLOGY: 1.3w TOTAL SINGLE 3.3V POWER SUPPLY -40 TO +85c OPERATING TEMP RANGE Applications HIGH SPEED INTERNET ACCESS REMOTE ACCESS TO CORPORATE NETWORK FOR TELECOMMUTERS AND BRANCH OFFICES VIDEO-ON-DEMAND OVER TWISTED PAIR
November 1998
TQFP64
PQFP144
ORDERING NUMBERS: STLC60134 (TQFP64) STLC60135 (PQFP144)
ADSL MODEMS, DSLAMs, ROUTERS, AND CONCENTRATORS ADSL PC NIC's LITE-ADSL T1.413 BASED FOR NT-SIDE SPLITTERLESS APPLICATIONS GENERAL DESCRIPTION The ADSL modem chip set with ATM interface provides all the active functions required to build a complete ATM-based ADSL modem from line interface to ATM UTOPIA bus. The chip set employs Discrete MultiTone modulation as specified in ANSI T1.413. The chip set can operate at either end of the loop (in ATU-C or ATU-R mode) with only changes in the microcontroller code. Reed-Solomon forward error correction plus Trellis coding with or without interleaving in internal interleaving RAM provides maximum noise immunity. Figure 1. ADSL modem block configuration.
UTOPIA
DMT MODEM
AFE
UTP
STLC60135 STLC60134
CONTROL
MEM
D98TL390
1/7
This is preliminary information on a new product now in development. Details are subject to change without notice.
TOSCA STLC60134/STLC60135
Interleaving is optional and can be used simultaneously on a slow channel (e.g., for data or control info) while a fast channel (e.g., video) operates without interleaving. ICs include rate adaptation capabilities during show time. In transmit direction the chip set allows to select an attenuation of the signal in case of short loops or large echo (politeness). In receive direction the chip set can optionally control an external multiplexer to select an external attenuation of the signal in case of short loops. TOSCA chip set TOSCA is a two-chip ADSL modem transceiver. ST also provides the necessary software for transceiver's external controller. TOSCA can easily be hooked up with ATM systems through the built-in UTOPIA level 2 interface. That allows ATM traffic to be carried, at up to 8Mbit/s downstream and 1Mbit/s upstream, over a very plain and widespread twisted pair. TOSCA can be used at both ends of the loop (ATU-C and ATU-R ends). The modem control software can be compiled as C++ code, independentlyon the processor used. The driver can be interfaced to any external real time operating system. These pages block diagrams show the main functions built-in in STLC60134 and STLC60135. TOSCA chip set supports three different rate adaptation modes: fixed rate adaptation mode, fixed with capability to boost within fixed range, dynamic rate adaptationduring show time. Modem's performances are set by the following Figure 2. Analog Front End block diagram.
35.328MHz
parameters: Rate adaptation mode, Downstream and Upstream bit rate for both latency paths, Noise margins (min, max and target typically at 10E-7 BER without RS, interleaving and trellis), Maximum power spectral density for downstream, Maximum power for both up and downstream, Carrier mask (which tones are disabled), maximum interleaving delay. Tones from number 8 to number 255 can be used: from 8 to 31 for upsteam signals and from 32 to 255 for downstream signals. Numbers 16 and 64 are dedicated to pilot tones which are employed for synchronisation purposes between ATU-C and ATU-R ends. The software sets the use of tones for optimisation of performances. At ATU-R, time recovery is carried out by the chip-set through the pilot tones. This activity is undertaken in two steps in order to achieve no more than 2ppm between ATU-C and ATU-R. The transceiver controller software monitors line and channel. As far as line is concerned noise margin, attenuation, power, carrier load, relative capacity occupation are checked. Channel's monitoring deals with cell-delineation, actual ATM (fast and interleaved) up and downstream rates, achievable ATM DS and US rates (only at ATU-C side). TOSCA ICs TOSCA consists of an Analog Front End (STLC60134) and a Discrete Multitone Modem (STLC60135) integrated circuits which are produced by STMicroelectronics. Here below we will briefly go through the main topics of both the ICs.
TRANSMIT-SIDE VCODAC 12 bits/8.8MHz 4 MUX DAC LPF ATU-C 1.1MHz LPF ATU-R MUX DAC LPF ATU-C 1.1MHz G=0...31dB STEP 1dB 12 bits/8.8MHz 4 MUX ADC LPF ATU-C 138KHz ATU-R LPF 1.1MHz LNA 138KHz AGC LPF 138KHz AGC
XTAL DRIVER G=15...0dB STEP 1dB
ATU-R
12 bits/8.8MHz 4
G=15...0dB STEP 1dB
RECEIVE-SIDE
D98TL391
2/7
TOSCA STLC60134/STLC60135
Analog Front End (STLC60134) HCMOS5A (0.5m) mixed digital and analog technology has been chosen to produce this component that embodies the analog functions of the TOSCA. Automatic gain control amplifiers, placed at the analog functions of the TOSCA. Automatic gain control amplifiers, placed at the analog interface of transmit and receive paths, allow for line's high attenuation in order to keep acceptable noise level of the signal ADC's and DAC's resolution, that is 12-bit wide with 8.8MHz sampling rate. Thanks to the symmetrical architecture the same channel filter can be used as a part of either the upstream or the downstream path: ATU-C or ATU-R end. A built-in driver allows for single external clock generation using a XTAL (ATU-C) or a VCXO (ATU-R). STLC60134 Analog Front End's main features: Rx automatic gain control: 0-31dB in 1dB steps Two input ports allow selection of RX signals, e.g. with or without external attenuation Second transmit port available (i.e. echo cancellation) Programmable low pass and band pass filters 12-bit DAC and ADC, sampling at 8.832MHz Xtal: 35.328MHz, 50ppm, the accuracy of the frequency is determined by the External XTAL Direct connection to STLC60135 DTM modem Error correction on ADC output Test interface for digital and analog sections Analog and digital loop back modes Figure 3. DMT Modem block diagram. Single 3.3V supply, or 3.3V analog and 3.0V digital supplies Power dissipation 0.4W Power-down mode 0.1W TQFP-64 (10 x 10mm body, 0.5mm pitch) Discrete MultiTone Digital Modem (STLC60135) The DMT modem has been developed in HCMOS6 (0.35m) technology. It performs PMD (Physycal Medium Dependant) sub-layer and TC (Transmission Convergence) sub-layer functions. In other words we can think to split up the chip into two separate blocks: the first one which carries out modem functions (PMD sub layer) and a second one in charge of ATM framing. The chip is controlled and programmed by an external processor and is seen as a memory mapped device. MODEM Functions The modem part of the chip includes all the necessary blocks needed for digitally DMT mapping and demapping. A 14-bit code for every carrier allows constellations with up to 16383 points. Internally digital filters carry out Time Equalization to reduce the effects of the inter symbol interfaces. That is followed by Fast Fourier Transform (in transmit direction an Inverse FFT is performed) in order to change from time domain to frequency domain. Afterwards a Frequency Equalization cuts down carrier by carrier the channel distortion; signal's amplitude attenuation and phase rotation. By efficient algorithms, this
FFT Rx DSP FE
DEMAPPER VITERBI
R/S DECODER DEFRAMER CELL BASED FUNCT. Rx INTERF.
INTERLEAVED
FAST
ADSL AFE
SIGNAL MONITORING & FEQ UPDATE & DPLL PMD SUBLAYER MAPPER VITERBI R/S CODER
TC SUBLAYER
ATM (UTOPIA)
IFFT Tx DSP FE
FAST FRAMER CELL BASED FUNCT. Tx INTERF. INTERLEAVED
D98TL406
3/7
TOSCA STLC60134/STLC60135
block drives, through the STLC60134's integrated VCXO controller, the NT crystal oscillator which comes up in an excellent synchronisation (less than 2ppm) between ATU-C and ATU-R. FRAMING Functions STLC60135 performs framing functions for generic and ATM TC sub layers. ATM TC sub layer performs cell level functions: delineation, idle cells or unassigned cells insertion/extraction, payload scrambling, Header Error Correction (HEC) check and data frame generation. In order to comply with T1.413 Issue 2 rules and full interoperability with other manufacturers' modems (providing they guarantee compliance with either Issue 1 or Issue 2) framing features (such as interleaving and fast mode) are implemented with programmable parameters. ATM frames can be bypassed in order to carry non-ATM bit streams, which makes the chip set very fit for applications using dedicated framing such as Frame-relay, etc. STLC60135 DTM modem main features: Time-domain equalisation Decimation, interpolation, FFT and IFFT, with different length and sampling rate at ATU-C and ATU-R side Rotor and frequency-domain equalisation Mapping/demapping Trellis coding and decoding using Viterbi algorithm Error and noise monitoring on individual tones Reed-Solomon encoding and decoding (De) framing and (de) interleaving Cell HEC generation/verification Payload (de) scrambling ATM cell insertion/extraction Idle &/or Unassigned cell insertion/filtering VPI/VCI filtering UTOPIA interface (Level 1 or 2) Microcontroller interface with 16-bit multiplexed address/data bus and big/little endian format supported JTAG test port Single 3.3V supply, 1.0W PQFP144 (28 x 28mm body, 0.65mm pitch) ADSL Modem control software The ADSL transceiver is based on a programmable DMT modem (STLC60135) whose configuration is loaded by an external controller.
4/7
Figure 4. Software Architecture.
USER HIGH LEVEL SOFTWARE
ADSL MANAGEMENT APPLICATION SW
OS INTERFACE
MODEM SW
BOARD SUPPORT PACKAGE
ADSL HARDWARE
D98TL392
Additionally the control functions, STMicroelectronics provides the DTM modem software. The software is written in C++ language, and is designed to be portable to any processor. The driver has to be interfaced with a real time OS kermel, it is compatible with any standard product available on the market. The kernel manages the tasks dedicated to modem software. The modem 5W core comes with three additional two software modules: a Board Support Package (BSP) and two Application Program Interfaces (API). BSP manages the hardware dependent features (i.e. interrupts, peripheral mapping). APIs interface to the higher level application software and to the OS. ADSL Loop performances The hereafter tables show the performances that a system, which houses TOSCA, can achieve for ANSI and ETSI loops. The following results refer to an end-to end ADSLequipment with no external disturbance. ANSI Loop (26awg)
Length 9Kft 12Kft 15Kft Downstream 7.47 E +0.6 3.69 E +0.6 1.56 E +0.6 Upstream 1.05 E +06 9.37 E +05 7.25 E +05
ETSI Loop (Loop 2, noise model A)
Length 2Km 4Km 5Km Downstream 8.00 E +0.6 4.07 E +0.6 1.70 E +0.6 Upstream 8.32 E +05 6.72 E +05 4.72 E +05
TOSCA STLC60134/STLC60135
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12
mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011
OUTLINE AND MECHANICAL DATA
0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393
0(min.), 7(max.)
TQFP64
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
5/7
TOSCA STLC60134/STLC60135
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90
mm TYP. MAX. 4.07 0.010 3.42 3.67 0.38 0.23 31.20 28.00 22.75 0.65 31.20 28.00 22.75 0.80 1.60 0(min.), 7(max.) 0.95 0.026 31.45 28.10 1.219 1.098 31.45 28.10 0.125 0.009 0.005 1.219 1.098 MIN.
inch TYP. MAX. 0.160
OUTLINE AND MECHANICAL DATA
0.135
0.144 0.015 0.009
1.228 1.102 0.896 0.026 1.228 1.102 0.896 0.031 0.063
1.238 1.106
1.238 1.106
0.037
PQFP144
D D1 A D3 A1 108 109 73 72
0. 10mm .004 Seating Plane
A2
B
E3
E1
144 1 e 36
37 C
L1
E
L
K
PQFP144
6/7
B
TOSCA STLC60134/STLC60135
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics ToscaTM is trademark of STMicroelectronics (c) 1998 STMicroelectronics and Alcatel Alsthom, Paris - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
7/7

▲Up To Search▲

Price & Availability of STLC60135

	To Download STLC60135 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .