 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CDB5361 Evaluation Board for CS5361 Features ! Demonstrates Description The CDB5361 evaluation board is an excellent means for quickly evaluating the CS5361 24-bit, stereo A/D converter. Evaluation requires a digital signal analyzer, an analog signal source, and a power supply. Also included is a CS8405A digital audio interface transmitter which generates S/PDIF, and EIAJ-340 compatible audio data. The digital audio data is available via RCA phono and optical connectors. recommended layout and grounding arrangements ! CS8405A generates S/PDIF, and EIAJ-340 compatible digital audio ! Requires only an analog signal source and power supplies for a complete Analog-toDigital-Converter system ORDERING INFORMATION CDB5361 Evaluation Board ANALOG INPUT CS5361 CS8405A AES/EBU S/PDIF TRANSMITTER S/PDIF OUTPUT I/O FOR CLOCKS AND DATA Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved) NOV `01 DS520DB3 1 CDB5361 TABLE OF CONTENTS 1. 2. 3. 4. 5. 6. 7. CDB5361 SYSTEM OVERVIEW .............................................................................................. 3 CS5361 ANALOG TO DIGITAL CONVERTER ........................................................................ 3 CS8405A DIGITAL AUDIO TRANSMITTER ............................................................................ 3 INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 3 POWER SUPPLY CIRCUITRY ................................................................................................. 3 GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 3 ANALOG INPUT FILTER ......................................................................................................... 3 LIST OF FIGURES Figure 1. System Block Diagram and Signal Flow .............................................. 5 Figure 2. Right Channel Analog Audio Input ....................................................... 6 Figure 3. Left Channel Analog Audio Input ......................................................... 7 Figure 4. CS5361 ................................................................................................ 8 Figure 5. Level Shifters ....................................................................................... 9 Figure 6. I/O for Clocks/Data ............................................................................. 10 Figure 7. CS8405A Digital Audio Interface ........................................................ 10 Figure 8. Digital Audio Output ........................................................................... 11 Figure 9. Reset Circuit ....................................................................................... 11 Figure 10.Power Circuit ...................................................................................... 12 Figure 11.Top Layer Silkscreen ......................................................................... 13 Figure 12.Top Layer ........................................................................................... 14 Figure 13.Bottom Layer ...................................................................................... 15 LIST OF TABLES Table 1. System Connections ........................................................................................................ 4 Table 2. CDB5361 Jumper and Switch Settings ............................................................................ 4 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS520DB3 CDB5361 1. CDB5361 SYSTEM OVERVIEW The CDB5361 evaluation board is an excellent means of quickly evaluating the CS5361. The CS8405A digital audio interface transmitter provides an easy interface to digital audio signal analyzers including the majority of digital audio test equipment. The CDB5361 schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics. The CDB5361 allows some flexibility as to the generation of the clocks. When the CS5361 and CS8405A are in slave mode, the SCLK and LRCK must be provided via the header, J3. MCLK must be generated from the on board oscillator, Y1. This oscillator is socketed to allow other frequency oscillators to be used. 5. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by six binding posts (VEE, VCC, VD, VL, GND, +5 V), see Figure 10. VEE and VCC supply the input amplifiers while the VD input supplies the VD pin of the CS5361. VL supplies power to the VL pin of the CS5361 and to the level shifter circuits. The +5 V input supplies power to the +5 V digital circuitry and the VA pin of the CS5361. 2. CS5361 ANALOG TO DIGITAL CONVERTER A description of the CS5361 is included in the CS5361 datasheet. 3. CS8405A DIGITAL AUDIO TRANSMITTER The system generates and encodes standard S/PDIF data using a CS8405A Digital Audio Transmitter, Figure 7. The outputs of the CS8405A are RS422 compatible differential line drivers. The CS8405A supports both Left Justified and I2S data formats, as determined by the DIP switch, S2. A description of the CS8405A is included in the CS8405A datasheet. 6. GROUNDING AND POWER SUPPLY DECOUPLING The CS5361 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 details the power distribution used on this board. The decoupling capacitors are located as close to the CS5361 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise. 7. ANALOG INPUT FILTER The CDB5361 implements a single-ended to differential analog input buffer, as shown in Figures 2 and 3. Note that the first inverting stage attenuates the input by 0.5. This will allow the updated modal dynamics of a 2Vrms signal (single-ended) applied to the board to be 2Vrms (differential) going into the CS5361. 4. INPUT/OUTPUT FOR CLOCKS AND DATA The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J3. The schematic for the clock/data input/output is shown in Figure 6. DS520DB3 3 CDB5361 CONNECTOR VEE VCC VD VL GND +5V AINL AINR Optical Output Coax Output INPUT/OUTPUT Input Input Input Input Input Input Input Input Output Output -5V to -12V power +5V to +12V power SIGNAL PRESENT +3.3V to +5V power for the CS5361 +1.8V to +5V power for the CS5361 Ground connection from power supply + 5 Volt power Analog input left channel Analog input right channel Digital audio output Digital audio output Table 1. System Connections JUMPER/SWITCH J3 S1 S2 PURPOSE Input/Output for clocks/data Reset for the CDB5361 CDB5361 Configuration - POSITION Open Hi *Closed *Low *Open Closed FUNCTION SELECTED M1/M0 5361 HPF DIV CS5361 in Master mode CS5361 in Slave mode Open High-pass filter is disabled *Closed High-pass filter is enabled Open MCLK is divided by two internally by the CS5361 *Closed MCLK is not divided internally by the CS5361 IO_HDR Open Header J3 is an input for clocks *Closed Header J3 is an output for clocks and data *Open Closed Digital interface format set to I2S Digital interface format set to Left Justified DIF 8405A Open CS8405A in Master mode *Closed CS8405A in Slave mode Table 2. CDB5361 Jumper and Switch Settings Notes: * denotes default factory settings 4 DS520DB3 DS520DB3 RESET LEFT CHANNEL ANALOG INPUT CIRCUIT FIG 10 FIG 3 CS8405A CS5361 FIG 4 LEVEL SHIFTER FIG 5 DIGITAL AUDIO INTERFACE DIGITAL OUTPUTS FIG 8 FIG 7 RIGHT CHANNEL ANALOG INPUT FIG 2 I/O FOR CLOCKS AND DATA FIG 6 CRYSTAL OSCILLATOR FIG 10 CDB5361 Figure 1. System Block Diagram and Signal Flow 5 6 CDB5361 DS520DB3 Figure 2. Right Channel Analog Audio Input DS520DB3 CDB5361 Figure 3. Left Channel Analog Audio Input 7 CDB5361 8 DS520DB3 Figure 4. CS5361 DS520DB3 CDB5361 Figure 5. Level Shifters 9 CDB5361 Figure 6. I/O for Clocks/Data Figure 7. CS8405A Digital Audio Interface 10 DS520DB3 CDB5361 Figure 8. Digital Audio Output Figure 9. Reset Circuit DS520DB3 11 12 CDB5361 DS520DB3 Figure 10. Power Circuit DS520DB3 CDB5361 Figure 11. Top Layer Silkscreen 13 14 CDB5361 DS520DB3 Figure 12. Top Layer DS520DB3 CDB5361 Figure 13. Bottom Layer 15 |
Price & Availability of CDB5361
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |