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| PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT PM73122/PM8315 AAL1GATOR-32/TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT PRELIMINARY ISSUE 4: JUNE 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION HISTORY Issue No. 1 2 3 4 Issue Date July 2000 November 2000 December 2000 June 2001 Details of Change Document created. COMET-QUAD details added. Registers in EEPROM (Table 3, register 0x28 and 0x2A) changed for microprocessor bus timing. Updated COMET-QUAD analog decoupling (C45, C48, C54, C65) in the schematics. Updated power calculations PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 1.2 1.3 2 3 4 PURPOSE..................................................................................... 1 SCOPE.......................................................................................... 1 APPLICATION............................................................................... 1 FEATURES .............................................................................................. 2 GENERAL DESCRIPTION....................................................................... 3 BLOCK DESCRIPTION ........................................................................... 5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 PCI BRIDGE.................................................................................. 5 SEEP............................................................................................. 6 POWER SUPPLY.......................................................................... 6 CPLD............................................................................................. 6 PM73122 AAL1GATOR-32............................................................ 9 PM8315 TEMUX ..........................................................................11 PM4354 COMET-QUAD...............................................................11 PM7350 S/UNI-DUPLEX............................................................. 12 5 DESIGN ISSUES ................................................................................... 14 5.1 AAL1GATOR-32 DESIGN CONSIDERATIONS .......................... 14 5.1.1 LINE INTERFACE ............................................................ 14 5.1.2 UTOPIA INTERFACE ....................................................... 14 5.1.3 SRAM ............................................................................... 15 5.1.4 MICROPROCESSOR INTERFACE.................................. 15 5.2 S/UNI-DUPLEX DESIGN CONSIDERATIONS............................ 15 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 5.2.1 PARALLEL BUS INTERFACE .......................................... 15 5.2.2 LVDS CONNECTIONS ..................................................... 16 5.2.3 POWER SUPPLY ............................................................. 17 5.2.4 DECOUPLING .................................................................. 18 5.3 COMET-QUAD DESIGN CONSIDERATIONS ............................ 18 5.3.1 LINE INTERFACE ............................................................ 18 5.3.2 BACKPLANE SYSTEM INTERFACE ............................... 18 5.3.3 MICROPROCESSOR INTERFACE.................................. 18 5.3.4 POWER SUPPLY SEQUENCING .................................... 18 5.3.5 DECOUPLING .................................................................. 19 5.4 TEMUX DESIGN CONSIDERATIONS ........................................ 19 5.4.1 DS3 INTERFACE ............................................................. 19 5.4.2 SYSTEM INTERFACE...................................................... 20 5.4.3 MICROPROCESSOR INTERFACE.................................. 20 5.5 5.6 5.7 6 DS3 LINE INTERFACE DESIGN CONSIDERATIONS................ 20 BUS SWITCH JUMPER CONFIGURATION ............................... 20 POWER REQUIREMENTS......................................................... 20 PHYSICAL AND MECHANICAL DESCRIPTIONS ................................. 22 6.1 6.2 FORM FACTOR .......................................................................... 22 CONNECTORS ........................................................................... 22 6.2.1 LVDS CONNECTOR ........................................................ 22 6.2.2 DS3 CONNECTOR........................................................... 22 6.2.3 MINI-BANTAM CONNECTORS........................................ 23 6.2.4 PCI CARD EDGE CONNECTOR ..................................... 23 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 6.2.5 DEBUG HEADER ............................................................. 23 6.3 LEDS ........................................................................................... 23 6.3.1 CARD STATUS LEDS ...................................................... 23 6.3.2 AUXILIARY LEDS............................................................. 24 7 SOFTWARE INTERFACES ................................................................... 25 7.1 8 PCI 9050 CONFIGURATION ...................................................... 25 LAYOUT DESCRIPTIONS ..................................................................... 28 8.1 8.2 8.3 8.4 COMPONENT PLACEMENT ...................................................... 28 POWER AND GROUND ............................................................. 28 ROUTING.................................................................................... 28 PCI BUS SIGNAL SPECIFICATION............................................ 29 9 MANUFACTURING ISSUES.................................................................. 30 9.1 BOARD ASSEMBLY.................................................................... 30 10 11 12 13 14 15 GLOSSARY ........................................................................................... 31 REFERENCES....................................................................................... 32 APPENDIX A: BILL OF MATERIALS ..................................................... 33 APPENDIX B: SCHEMATICS ................................................................ 40 APPENDIX C: VHDL CODE FOR CPLD................................................ 41 APPENDIX D: LAYOUT ......................................................................... 51 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT LIST OF FIGURES FIGURE 1 AAL1GATOR-32/TEMUX DEVELOPMENT KIT BLOCK DIAGRAM 4 FIGURE 2 CPLD LOGIC ................................................................................... 8 FIGURE 3 AAL1GATOR-32 CONFIGURATIONS ........................................... 10 FIGURE 4 LVDS TERMINATION SCHEME .................................................... 17 FIGURE 5 MOLEX 53984-0611 CONNECTOR................................................ 22 FIGURE 6 MAJOR COMPONENT PLACEMENT ........................................... 28 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 PCI9050 LOCAL ADDRESS SPACE ALLOCATION ........................ 5 POWER REQUIREMENT TABLE.................................................. 20 EEPROM CONTENTS................................................................... 25 MAJOR COMPONENT LIST.......................................................... 33 MISCELLANEOUS PARTS............................................................ 34 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE v PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 1 1.1 INTRODUCTION Purpose The purpose of the AAL1gator-32/TEMUX Development Kit is to provide software designers with a platform on which to implement and test software for the PM73122 AAL1gator-32 and PM8315 TEMUX, as well as the PM7350 S/UNI-DUPLEX, and PM4354 COMET-QUAD. Customers planning to use other variants of the AAL1gator device (i.e. AAL1gator-8 or AAL1gator-4) can also use this development kit by porting the core functions to another platform using a different AAL1gator variant. 1.2 Scope This document details the hardware design of the AAL1gator-32/TEMUX Development Kit. This document includes a detailed description of each of the functional blocks of the kit, as well as schematics, bill of materials and CPLD code for the design. The AAL1gator-32/TEMUX Development Kit system is complete with software to setup the hardware. The software is written in ANSI C for the VxWorks operating system. Details of the software are available in the AAL1gator-32/TEMUX Development Kit Platform document [1]. 1.3 Application Traditional enterprise networks have evolved to comprise two physically separate networks - one for data and one for voice/video traffic. For example, Asynchronous Transfer Mode (ATM) or Frame Relay may be used for data, while traditional copper T1 connections are used for linking voice/private branch exchange (PBX) and videoconferencing devices together. PMC-Sierra's customers want a scalable solution that allows them to easily and efficiently move onto a single physical network by integrating voice, video, and data traffic. The solution is to carry constant bit rate (CBR) or "circuit" traffic over Asynchronous Transfer Mode (ATM) networks. The ATM Forum has defined a circuit emulation service (CES) specification that provides a virtual circuit connection emulating the characteristics of a real, constant-bit-rate, dedicatedbandwidth circuit. PMC-Sierra's PM73122 AAL1gator-32 implements this CES functionality in silicon. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 2 FEATURES * * * * * Provides full access to the AAL1gator-32, TEMUX, S/UNI-DUPLEX, and COMET-QUAD devices. 5V PCI Card Compatible. Internal Diagnostic Loopbacks of the TEMUX, COMET-QUAD, AAL1gator-32, and S/UNI-DUPLEX. A high-speed LVDS Interface capable of data rates up to 200 MB/s. Supports 4 T1, 4 E1, or 1 DS3 link for transport over ATM. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 3 GENERAL DESCRIPTION A block diagram for the AAL1gator-32/TEMUX Development Kit is shown in Figure 1. The T1/E1/DS3 ports of the design are contained within the T1/E1 Line Interface block and the DS3 Line Interface block. Within the T1/E1 Line Interface block 4 T1 or E1 channels interface to the PM4354 COMET-QUAD through 8 bantam connectors and line protection circuitry. PMC-Sierra's PM4354 COMETQUAD is a four channel combined T1 or E1 transceiver and framer. The system side of the COMET-QUAD communicates with the PM73122 AAL1gator-32 using framed T1/E1 clock and data. Within the DS3 Line Interface block one DS3 channel connects to the PM8315 TEMUX through 2 SMB connectors, line protection circuitry and a line interface IC. PMC-Sierra's PM8315 TEMUX is configured as a DS3 framer and SBI bus interface within this design. The TEMUX communicates with the DS3 Line Interface IC on the line side, and the PM73122 AAL1gator-32 on the system side. Note in Figure 1 that both the COMET-QUAD and the TEMUX communicate with the AAL1gator-32 through a bus switch. The COMET-QUAD uses clock and data lines to communicate with the AAL1gator-32 and the TEMUX uses PMCSierra's Scalable Bandwidth Interconnect (SBI) bus. The COMET-QUAD and TEMUX cannot communicate with the AAL1gator-32 simultaneously because two different buses are used that share the same pins. Therefore, a bus switch is used and reconfiguration of the AAL1gator-32 is required when switching between DS3 and T1/E1. As shown in Figure 1, the AAL1gator-32 communicates with PMC-Sierra's PM7350 S/UNI-DUPLEX via a UTOPIA high-speed parallel bus. The S/UNIDUPLEX interfaces the UTOPIA bus to a high speed Low Voltage Differential Signal (LVDS) serial link. This LVDS link is suitable for transmission across a cable and can interface with another AAL1gator-32/TEMUX Development Kit board or any other S/UNI-DUPLEX configured with a UTOPIA interface. A PCI Interface chip allows the card to be controlled and monitored via the PCI bus. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT Figure 1 AAL1gator-32/TEMUX Development Kit Block Diagram DS3 Line Interface Clock & Data PM8315 TEMUX SBI BUS SWITCH SBI/ Clock & Data PM73122 AAL1gator-32 UTOPIA Level 2 PM7350 S/UNI-DUPLEX LVDS T1/E1 Line Interface PM4354 COMET-Quad Clock & Data Status & Control PCI Interface & CPLD Local Bus PCI Connector PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 4 BLOCK DESCRIPTION The following sections describe the function of each hardware block shown in Figure 1. 4.1 PCI Bridge The PCI Bridge used is PLX Technology's PCI9050 PCI Bus Target Interface Chip. The PCI9050 provides a target only interface, and as such does not initiate PCI bus transactions. The local bus interface of the PCI9050 is generic and very flexible supporting: 8, 16, and 32-bit transfers, multiplexed or nonmultiplexed modes, big or little endian, and clock rates asynchronous to the PCI bus up to 40MHz. The local bus is partitioned into 4 distinct user-definable address spaces that can be configured independently. The timing of each address space is specifiable via a set of programmable wait states as well as supporting a ready signal used to insert additional wait states. Please refer to the PCI9050 datasheet [2] for more information. The local address spaces are allocated in the following fashion: Table 1 PCI9050 Local Address Space Allocation Function AAL1gator-32 TEMUX COMET-QUAD S/UNI-DUPLEX Address Space 0 1 2 3 All four address spaces are configured as 32-bit non-multiplexed, big endian, non-burst, and non-prefetchable. Although the devices on the microprocessor bus have only a 16- or 8-bit data bus, the PCI9050 is configured as a 32-bit bus to simplify the timing of the hardware design. Also, the devices do not support burst mode transfers and therefore bursting is disabled. Prefetching is not possible as some of the registers have read side effects (i.e. interrupt status registers). The local bus is clocked at 33MHz by looping the buffered PCI clock output (BCLKO) available from the PCI9050 back to the local bus clock input. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 4.2 SEEP The NM93CS46 Serial EEPROM from National Semiconductor is used to store configuration information for the PCI9050 interface chip. This specific SEEP (or equivalent) is required by the PCI9050 because it supports sequential read operations. The SEEP can be programmed over the PCI bus through a rudimentary interface provided by the PCI9050 or using an EEPROM programmer. The SEEP is 1Kbit deep, 800 bits of which are occupied by the PCI9050 configuration data, leaving 224 bits (28 bytes) unused. Refer to the PCI9050 datasheet [2] for information on the format of the configuration data stored in the SEEP. 4.3 Power Supply Power requirements of the board are +5V, +3.3V and +2.5V. +5V is available from the PCI bus through the PCI edge connector and is used to power the PCI9050 PCI Interface chip. +3.3V is available from the PCI bus, but is regulated from +5V in order to provide cleaner power. +2.5V is provided by a regulator using +3.3V regulated power. LEDs mounted to the card bracket are used to indicate power status. 4.4 CPLD A Xilinx XC95144XL CPLD provides the miscellaneous logic required for the board. A schematic representation of the CPLD logic is shown in Figure 2. This logic is written in VHDL and the code is given in appendix D. The timing requirements of the design require a 7.5 ns CPLD. There are address and data lines routed to the CPLD from the PCI9050 such that registers can be created within the CPLD and modified via the PCI interface. The CPLD logic controls the control lines of the microprocessor port of each PMC-Sierra chip. Yellow LEDs indicate an interrupt from each of the chips. The reset signal RSTB is wired such that the MAX700 Power-supply Monitor or the PCI9050 chip can issue a reset to the board. Also, as TRSTB must go low at least once after reset, TRSTB can be controlled via the JTAG header and goes low with RSTB. Clock dividers inside the CPLD divide down an external network clock for use in the AAL1gator-32 for synchronous residual timestamp (SRTS) support. A 2.43 MHz clock is required for SRTS, which can be derived from a 155.52 MHz network clock supplied through a SMA connector. The AAL1gator-32 has an PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT internal divider but it can only divide a 77.76 MHz clock down to 2.43 MHz, hence the need for another divider within the CPLD. The other CPLD divider divides down the DS3 RCLK from 44.736 MHz to 8 kHz so that it can be transmitted across the LVDS link and used as a timing reference at the far end. Similarly, the development kit is capable of receiving an 8 kHz reference from an external timing source across the LVDS link and multiply it up to a nominal rate of 44.736 MHz for clocking out the DS3 signal. The CPLD is connected to a MK2049 phase locked loop to implement this clock multiplier. A DIP switch is used to select between the two different XCLK rates required by the TEMUX. The switch is also used to select other clocking options as shown in Figure 2. The CPLD is in-system programmable and is programmed via its JTAG port header. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT Figure 2 CPLD Logic LRESETB MAX700 RESET RSTB TRSTB from JTAG port TRSTB 44.736MHz Oscillator CLK2 of MK2049 0 1 TICLK<1> TICLK<2> TL_CLK DIPSW(3) External Network Clock In divide by 2 NCLK RX8K ICLK of MK2049 CTCLK RL_CLK RCLK RSYNC DIPSW(2) 37.056MHz 49.152MHz DIPSW(1) RDB divide by 5592 0 1 TX8K 0 1 TEMUX XCLK RDB_AAL32 RDB_TEMUX RDB_CQ RDB_DUPLEX WRB_AAL32 WRB_TEMUX WRB_CQ WRB_DUPLEX LED(0) LED(1) LED(2) LED(3) INTB WRB INTB_AAL32 INTB_TEMUX INTB_CQ INTB_DUPLEX CSB0 CSB1 CSB2 CSB3 ACKB_AAL32 CSB_AAL32 CSB_TEMUX CSB_CQ CSB_DUPLEX LREADYIB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 4.5 PM73122 AAL1gator-32 The PM73122 AAL1 Segmentation and Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides T1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of configuration, user, and statistics data. Some of the device's important functionality is as follows: * * * * * Compliant with the ATM Forum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1 Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum's DBCES specification (AF-VTOA-0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis. Provides AAL1 segmentation and reassembly of 16 individual E1 or T1 lines in the direct low speed mode, 8 H-MVIP lines at 8 Mb/s in the H-MVIP mode, or 2 E3 or DS3 lines in the high speed mode. Using the Scalable Bandwidth Interconnect (SBI) Interface, provides AAL1 segmentation and reassembly of up to 32 T1, E1, links, or 2 DS3 links. Provides a standard UTOPIA level 2 Interface which optionally supports parity and runs up to 52 MHz. The following modes are supported: * * * * * * 16-bit Level 2, Multi-Phy Mode (MPHY) 8/16-bit Level 1, SPHY 8-bit Level 1, ATM Master * * Provides an optional 8/16-bit Any-PHY slave interface. Supports up to 1024 Virtual Channels (VC). Supports n x 64 (consecutive channels) and m x 64 (non-consecutive channels) structured data format. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT Figure 3 indicates the ways in which an AAL1gator-32 can be used to connect to T1/E1 or DS3/E3/J2 line interfaces. The shaded devices represent the configurations used in the AAL1gator-32/TEMUX Development Kit. Figure 3 AAL1gator-32 Configurations UTOPIA AAL1gator-32 Structured or unstructured T1/E1 with CAS support MVIP TDM Switch 28 T1 Framers + M13 Mux + VT Mapper (TEMUX) SBI Unstructured DS3/E3/J2 T1/E1 Framer+LIU (COMET/ COMETQuad) T1/E1 Framer (TQUAD/EQUAD) M13 Mux (D3MX) DS3 LIU DS3/E3/J2 Framer (S/UNI-QJET) (TUPP-PLUS) T1/E1 LIU (QDSX) (SPECTRA-155) DS3/E3/J2 LIU In this design one AAL1gator-32 is used to interface with either one TEMUX or one COMET-QUAD through a bus switch. A bus switch is used because the AAL1gator-32 communicates with the TEMUX using SBI mode, and the COMETQUAD via Direct Low Speed mode. These two modes are not supported simultaneously by the AAL1gator-32 and therefore a bus switch is needed to switch the common system side signals. When the AAL1gator-32/TEMUX Development Kit is configured for DS3 operation the AAL1gator-32 and TEMUX interface via the SBI bus to support 28 structured/unstructured T1s or 21 structured/unstructured E1s. When the AAL1gator-32/TEMUX Development Kit is configured for T1/E1 operation the AAL1gator-32 communicates with the COMET-QUAD using the clock and data signals from 4 T1s or 4 E1s. For a more detailed description of the AAL1gator-32, please refer to [3] of the references. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 4.6 PM8315 TEMUX The PM8315 TEMUX is an integrated circuit that combines 28 T1 framers, 21 E1 framers, a SONET/SDH VT1.5/V2/TU-11/TU-12 bit asynchronous mapper and a full-featured M13 multiplexer with DS3 framer. The TEMUX also contains a SONET/SDH DS3 mapper for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams. Within the AAL1gator-32/TEMUX Development Kit the TEMUX is configured to support a byte serial Scalable Bandwidth Interconnect (SBI) bus interconnection to the AAL1gator-32. On the line side the TEMUX is configured to support the dual-rail DS3 signals from the DS3 line interface unit. An 8-bit microprocessor bus interface provides configuration, control, and status monitoring. For more information about the TEMUX, please refer to [4] of the references. 4.7 PM4354 COMET-QUAD The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The COMET-QUAD is software configurable, allowing feature selection without changes to external wiring. Analog circuitry is provided to allow direct reception of long haul E1 and T1/J1 compatible signals typically with up to 43 dB cable loss at 1024 kHz (E1) and up to 44 dB cable loss at 772 kHz (T1/J1) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to SF and ESF signal formats. In E1 mode, the COMET-QUAD frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported. The COMET-QUAD supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET-QUAD also supports reception of remote alarm signal, remote multiframe alarm signal, and alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET-QUAD integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMET-QUAD integrates Red and AIS alarms. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events are provided in T1 mode. In E1 mode, CRC-4 errors, far end block errors, framing bit errors, and line code violation are monitored and accumulated. In the transmit path, the COMET-QUAD supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled. Each channel of the COMET-QUAD can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. A low jitter recovered T1 clock can be routed outside the COMET-QUAD for network timing applications. Serial PCM interfaces to each T1/E1 framer allow 1.544 Mbit/s or 2.048 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. For synchronous backplane systems, 8.192 Mbit/s H-MVIP interfaces are provided for access to PCM data, channel associated signaling (CAS) and common channel signaling (CCS) for each T1 or E1. The CCS signaling H-MVIP interface is independent of the 64 Kbit/s PCM and CAS H-MVIP access. The use of the H-MVIP interface requires that common clocks and frame pulse be used along with T1/E1 elastic stores. The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface. For further information, please see the COMET-QUAD Datasheet [5]. 4.8 PM7350 S/UNI-DUPLEX The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit typically used for traffic concentration within a Digital Subscriber Line Access Multiplexer (DSLAM). The DUPLEX is ATM specific and it exchanges contiguous 53 byte cells with PHY devices. The PHY interface can be either clocked serial data or SCIPHY/Any-PHY. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT With a clocked serial data configuration up to sixteen channels are supported. In the AAL1gator-32/TEMUX Development Kit, however, UTOPIA Level 2 is used at this interface. All cell streams are multiplexed into a high-speed serial stream. The high-speed interfaces use NRZ data-only differential signals compatible with LVDS levels. The internal transmit clock is synthesized from a lower frequency reference. An extended cell format provides four extra bytes for the encoding of flow control, timing reference, PHY identification and link maintenance information. A redundant link is provided to allow connection to two cell processing cards. A microprocessor port provides access to internal configuration and monitoring registers. The port may also be used to insert and extract cells in support of a control channel. For further information, please see the S/UNI-DUPLEX Datasheet PMC-1980581 [6]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 5 DESIGN ISSUES The following sections describe detailed design considerations of the reference design. 5.1 AAL1gator-32 Design Considerations 5.1.1 Line Interface The line interface block of the AAL1gator-32 is responsible for passing TDM data to the AAL1 Segmentation and Reassembly Processor. There are 4 possible options, which are selected using the LINE_MODE pins: Direct Low Speed Mode, H-MVIP Mode, SBI Mode, and High Speed Mode. The AAL1gator-32 uses Low Speed Mode to communicate with the COMET-QUAD. In Low Speed Mode the AAL1gator-32 can support up to 16 structured or unstructured T1/E1 links. H-MVIP mode can also be used to communicate with eight COMETQUADs allowing use of all 32 links within the AAL1gator-32. H-MVIP Mode, however, does not allow the use of unstructured data formats. SBI Mode is used to communicate with the TEMUX. Because the AAL1gator-32 Line Interface is configured in both SBI Mode and Direct Low Speed Mode within this design, a bus switch and jumper are required. The jumper configures the LINE_MODE0 pin of the AAL1gator-32 for either Low Speed (0) mode or SBI (1), and the bus switch switches the pins that are common to both bus types. 5.1.2 UTOPIA Interface The AAL1gator-32 UTOPIA Interface manages and responds to all control signals on the UTOPIA bus. The following UTOPIA modes are supported: * * * * UTOPIA Level 1 ATM Master (8-bit only) UTOPIA Level 1 8/16-bit SPHY UTOPIA Level 2 Multi-phy Mode (MPHY) 8/16-bit Any-PHY Slave The AAL1gator-32/TEMUX Development Kit is configured to run with a 25MHz UTOPIA Level 2 bus. The S/UNI-DUPLEX is configured as the bus master, and the AAL1gator-32 is configured as a bus slave. Because the S/UNI-DUPLEX can only run at up to 33 MHz in UTOPIA Level 2 Master mode, the oscillator must be less than or equal to 33 MHz (but large enough to satisfy the required PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT bandwidth of the bus) in order to run the AAL1gator-32 in UTOPIA Level 2 Slave mode. 5.1.3 SRAM The AAL1gator-32 arbitrates access to two external 256K x 18 bit SRAMs for storage of configuration, user, and statistic data. The AAL1gator-32 memory interface is timed by SYSCLK, which is a 38.88MHz clock. There are two possible choices for the external SRAM: pipelined synchronous SRAM or pipelined ZBT SRAM. Standard Synchronous SRAM can be used in most applications. For high performance applications where many RAM accesses are necessary (such as many partial cell VCs), Zero Bus Turnaround (ZBT ) SRAM should be used. ZBT RAM utilizes more bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. The AAL1gator-32/TEMUX Development Kit uses ZBT SRAM so that maximum performance can be obtained if needed. 5.1.4 Microprocessor Interface The Microprocessor Interface provides access to normal mode registers and memory-mapped registers of the AAL1gator-32. The AAL1gator-32 microprocessor interface data and address buses are connected to the PCI9050 PCI Interface chip and the other signals connect through the CPLD for chip select decoding and then to the PCI9050. The microprocessor interface is configured as a non-multiplexed bus by pulling the ALE input high. 5.2 S/UNI-DUPLEX Design Considerations 5.2.1 Parallel Bus Interface The SCI-PHY/Any-PHY Interface (SCIANY pin) input selects either parallel bus or a clocked serial data interface to the S/UNI-DUPLEX. To configure the S/UNIDUPLEX for a UTOPIA Level 2 interface this pin must be logic high. The parallel bus interface supports three types of buses: UTOPIA Level 2, SCI-PHY, and AnyPHY. In this design UTOPIA Level 2 is used, although the other two types will also work. The S/UNI-DUPLEX interface is configured as 16-bit UTOPIA Level 2 master by setting the IBUS8, OBUS8, IANYPHY, and OANYPHY inputs low, and the IMASTER and OMASTER inputs high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 5.2.2 LVDS Connections The LVDS differential signals should be routed together such that any coupling on the TX/RX path is common-mode and not differential. The two traces that form a differential TX/RX path should have equal trace lengths from the chip to the connector. Traces for the LVDS signals should be 50 controlled impedance. The termination scheme used in the LVDS section of the development kit is shown in Figure 4. Two additional termination methods are possible for these LVDS signals: capacitive coupling and transformer coupling. Capacitive coupling, as indicated by the dashed lines offers a low cost, low board space alternative for LVDS signals that originate from shelves on the same ground system. To use the capacitive coupling option, do not install the transformers. Install the 0.22F and 1M resistors instead. For shelf to shelf termination where the shelves are on different ground systems, transformers are required to provide isolation. Common mode chokes are also used to reduce the amount of radiated and received electromagnetic interference (EMI). Only one end of the connection requires transformers, the other can use capacitive coupling. However, when connecting two AAL1gator-32/TEMUX Development Kits both boards could be transformer coupled or capacitively coupled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT Figure 4 LVDS Termination Scheme S/UNI-DUPLEX 50 To Other Card 1M 0.22 uF TXD+ 50 1M 1:1 TXD- 0.22 uF S/UNI-DUPLEX 3.3V 0.22 uF 1M 750 0.1uF 50 To Other Card RXD+ 49.9 49.9 430 50 1M 1:1 RXD0.22 uF 0.1uF In all termination methods, the LVDS receive signals are terminated by two 49.9 resistors and a 0.1uF capacitor. This termination network should be placed as physically close to the S/UNI-DUPLEX as possible. 5.2.3 Power Supply During power-up, the BIAS pin must be equal to or greater than the voltage on the VDD pins. This is accomplished by the configuration of the voltage regulators. The voltage on the BIAS pin is also the same one used to regulate the VDD voltage. Therefore, the worst case is that the regulator malfunctions and shorts, which still leaves the BIAS pin equal to VDD. Also, an extra protection diode is used to limit the VDD to a maximum of 0.5V above the BIAS voltage. Analog power pins QAVD, CAVD, RAVD and TAVD must be applied after VDD or they must be current limited to the maximum latch-up current of 100mA. A simple solution is to use a small filtering network between the VDD and AVD plane to delay the power to the AVD plane, which will delay power to each AVD pin. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 5.2.4 Decoupling A 0.01F capacitor is placed between 3.3 V power and ground for every other VDD pin. The capacitors should be placed as close as possible to the actual pins. The AVD pins require a filtering network between the VDD_A plane and each AVD pin. The network is a single low-pass RC network. Please refer to the bill of materials in Appendix A for component values. 5.3 COMET-QUAD Design Considerations 5.3.1 Line Interface The COMET-QUAD Line Interface is configurable to operate in both E1 and T1 short-haul and long-haul applications without changing external line protection circuitry. The Line Interface circuitry used on the AAL1gator-32/TEMUX Development Kit is the recommended external protection circuitry for designs required to meet surge immunity and electrical safety standards for intra-building communications. Refer to the COMET-QUAD Datasheet [5] for more information on this protection. 5.3.2 Backplane System Interface The Backplane System Interface of the COMET-QUAD provides system side serial clock and data access for 4 T1 or E1 streams. In this design the backplane system interface is configured for serial clock and data. The corresponding signaling and frame pulse signals for each line are routed to the AAL1gator-32 as well, which are optionally used by the AAL1gator-32. 5.3.3 Microprocessor Interface The Microprocessor Interface provides access to normal and test mode registers, as well as memory-mapped registers. The COMET-QUAD microprocessor interface data and address buses are connected to the PCI9050 PCI Interface chip and the other signals connect through the CPLD for chip select decoding and then to the PCI9050. The microprocessor interface is configured as a non-multiplexed bus by tying the ALE input high and not using it. 5.3.4 Power Supply Sequencing The following power up sequence for the COMET-QUAD must be followed: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 1. 2. 3. +3.3V digital pins +3.3V analog pins (TAVDx, CAVD, RAVDx, QAVD) +2.5V digital pins Power to the +3.3V pins, both analog and digital, must be applied before +2.5V. Power to the +3.3V digital pins must be applied before power to the +3.3V analog. A simple solution for the latter statement is to use a small filtering network between the +3.3V digital and +3.3V analog pins to delay the power. 5.3.5 Decoupling 0.01F and 0.1F capacitors are placed between power and ground for the VDD (+2.5 V and +3.3V) pins. The capacitors should be placed as close to the actual pins as possible. The AVD pins require a filtering network between the VDD plane and each AVD pin. The network is a single RC network with the resistor between the VDD plane and the AVD pin and the capacitor from the AVD pin to the GND plane. Please refer to the schematics in Appendix A for component values. 5.4 TEMUX Design Considerations 5.4.1 DS3 Interface The DS3 Interface of the TEMUX interfaces the DS3 Line Interface Unit with the DS3 framer of the TEMUX. The TEMUX DS3 framer decodes the incoming B3ZS-encoded signal and frames to the resulting DS3 stream. In the opposite direction the framer generates the B3ZS-encoded signal from the DS3 stream. Depending on the type of line interface required, the TEMUX can be configured for dual rail or single rail format. The AAL1gator-32/TEMUX Development Kit uses dual rail format to interface with the TDK 78P2241 DS3 Transceiver. Single rail format is used when the LIU handles B3ZS encoding/decoding. When a DS3 signal is not applied to the DS3 Line Interface Unit it is not possible to recover a DS3 line rate clock for the TEMUX (RCLK). When the TEMUX is not receiving RCLK it cannot accurately maintain its registers, and therefore RCLK should be a nominal 44.736 MHz clock at all times. The 78P2241 DS3 Transceiver provides a loss of signal (LOS) active-low signal that is used to switch in a 44.736 MHz clock. Tri-state non-inverting buffers are used to switch in the clock when LOS goes low. A non-inverting buffer is placed on the RPOS and RNEG signals of the TEMUX as well so that timing can be met. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 5.4.2 System Interface The system side interface of the TEMUX can be configured for serial clock and data, H-MVIP, SBI bus, SBI bus with CAS or CCS H-MVIP, and serial clock and data with CCS H-MVIP. In this design the system side interface is configured for SBI bus or SBI bus with CAS, depending on whether the M13 multiplexing capability of the TEMUX is used. 5.4.3 Microprocessor Interface The Microprocessor Interface provides access to normal and test mode registers, as well as memory-mapped registers. The TEMUX microprocessor interface data and address buses are connected to the PCI9050 PCI Interface chip and the other signals connect through the CPLD for chip select decoding and then to the PCI9050. The microprocessor interface is configured as a nonmultiplexed bus by pulling the ALE input high. 5.5 DS3 Line Interface Design Considerations The AAL1gator-32/TEMUX Development Kit uses a 78P2241 line interface transceiver IC by TDK Semiconductor Corp. This transceiver IC recovers clock and data from the B3ZS coded DS3 signal and interfaces to the TEMUX. The 78P2241 also provides diagnostic loopbacks for troubleshooting and testing. 5.6 Bus Switch Jumper Configuration There is one jumper on the board that is used to select the bus switch between the TEMUX and the COMET-QUAD. The jumper should be shorted when using the COMET-QUAD (T1/E1) and left open when using the TEMUX (DS3). 5.7 Power Requirements Table 2 provides the estimated power requirements for the AAL1gator32/TEMUX Development Kit. Table 2 5V Components PCI Bridge PCI9050 SEEP, NM93CS46 Misc, pullups/downs MK2049-01S 3.3V Regulator Total 5V Power Power Requirement Table Quantity 1 1 1 1 1 Current (mA) 130 10 40 55 2876.5 3111.5 Power (mW) 650 50 200 275 14382.5 15557.5 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 3.3V Components 74HC04 74AC125 78P2241 QS53805 CY7C1352 MAX700C Oscillators PI3B16233 XC95144XL-7TQ1 PM8315 PM7350 PM73122 PM4354 Misc, pullups/downs 2.5V Regulator Total 3.3V Power 2.5V Components PM8315 PM73122 PM4354 Total 2.5V Power Quantity Current (mA) Power (mW) 1 4 1 1 2 1 7 1 1 1 1 1 1 1 1 1 40 80 30 600 0.5 119 80 80 4 450 85 441 61 805 2876.5 Current (mA) 3.3 132 264 99 1980 2 393 264 264 13.2 1485 280.5 1455.3 201.3 2656.5 9492.45 Power (mW) Quantity 1 1 1 368 400 38 806 920 1000 95 2115 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 6 6.1 PHYSICAL AND MECHANICAL DESCRIPTIONS Form Factor The AAL1gator-32/TEMUX Development Kit is a standard length, 32-bit, 5V PCI expansion card. The card has a metal mounting bracket for card location and retention. The mechanical specifications of the card comply to the PCI Local Bus Specification revision 2.2 and for more information refer to [7] of the references. 6.2 Connectors There are three groups of connectors for the AAL1gator-32/TEMUX Development Kit: front-edge connectors, top-edge connectors and the PCI card edge connector. The front edge connectors consist of the LVDS connectors and the DS3 connectors. The top edge connectors are the 8 T1/E1 connectors. 6.2.1 LVDS Connector The LVDS connector requires a bandwidth of 100 to 200 Mb/s. The IEEE 13941995 shielded I/O PCB socket is used to meet this bandwidth requirement. The Molex 53984-0611 socket shown in Figure 5 is use to satisfy the physical limitations of a PCI card connecting to Firewire cables. Figure 5 Molex 53984-0611 Connector 6.2.2 DS3 Connector The AAL1gator-32/TEMUX Development Kit uses 50 SMB connectors on the front edge of the card. Right angle SMB connectors are used rather than BNC connectors because they are smaller and allow placement on the front edge of PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT the card. Although the traces and cabling of these signals are 75, 50 SMB connectors are used because 75 require custom manufacturing and are larger. 50 SMB connectors have been found to work adequately in these applications. SMB to BNC adapter cables are available for interfacing with some equipment. 6.2.3 Mini-Bantam Connectors The 4 T1 and E1 links are connected to the AAL1gator-32/TEMUX Development Kit via mini-bantam connectors. 6.2.4 PCI Card Edge Connector The PCI edge connector is implemented as a standard length 5V 32-bit PCI connector. For the dimensions and tolerances of this card edge connector refer to the PCI Local Bus Specification [7]. 6.2.5 Debug Header A 0.64 mm Matched Impedance Connector (MICTOR) by AMP (part number 2767004-2) is used to provide debug access to the board. This connector is used to verify the timing of microprocessor interface and for connection to a logic analyzer. 6.3 LEDs 6.3.1 Card Status LEDs A basic set of LEDs provide visual information about power and reset on the card. These 4 LEDs are positioned on the front edge of the card so that they can be viewed easily at any time. * * * * +5 V, green - indicates presence of +5 V +3.3 V, green - indicates presence of +3.3 V +2.5 V, green - indicates the presence of +2.5 V Reset, green - indicates that the reset signals connected to each of the PMCSierra devices is low (active). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 6.3.2 Auxiliary LEDs Four auxiliary LEDs are easily visible on the front edge of the expansion card. These yellow LEDs are used to indicate an interrupt from each of the PMCSierra devices. By changing the CPLD code these LEDs can indicate other status information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 7 7.1 SOFTWARE INTERFACES PCI 9050 Configuration The following tables specify the values that should be programmed into the SEEP. These values will be loaded into the PCI9050 registers on power-up. The checksum of the EEPROM is 0x3388. Please refer to the PCI9050 datasheet for further details. Table 3 EEPROM Contents PLX Register Device ID Vendor ID Class Code ClassCode Subsystem ID Subsystem Vendor ID Max Latency and Min Grant (not loadable) Interrupt Pin MSW of Address Space 0 Range LSW of Address Space 0 Range MSW of Address Space 1 Range LSW of Address Space 1 Range MSW of Address Space 2 Range LSW of Address Space 2 Range MSW of Address Space 3 Range LSW of Address Space 3 Range MSW of Expansion Rom Range LSW of Expansion Rom Range MSW of Address Space 0 Remap LSW of Address Space 0 Remap EEPROM Offset (Hex) Value (Hex) 0 2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E 20 22 24 26 9050 10B5 0680 0000 2353 11F8 0000 00FF 0FC0 0000 0FFF 0000 0FFF E000 0FFF FC00 0000 0000 0000 0001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT EEPROM Offset (Hex) Value (Hex) 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 0040 0001 0080 0001 00C0 0001 0000 0000 5681 A1A2 5681 A1A0 5681 A1A0 5681 A1A0 0000 0000 0020 0001 0040 8001 0080 1001 00C0 0201 0000 0000 PLX Register MSW of Address Space 1 Remap LSW of Address Space 1 Remap MSW of Address Space 2 Remap LSW of Address Space 2 Remap MSW of Address Space 3 Remap LSW of Address Space 3 Remap MSW of Expansion Rom Remap LSW of Expansion Rom Remap MSW of Space 0 Bus Descriptor LSW of Space 0 Bus Descriptor MSW of Space 1 Bus Descriptor LSW of Space 1 Bus Descriptor MSW of Space 2 Bus Descriptor LSW of Space 2 Bus Descriptor MSW of Space 3 Bus Descriptor LSW of Space 3 Bus Descriptor MSW of Expansion Rom Bus Descriptor LSW of Expansion Rom Bus Descriptor MSW of CS0 Register LSW of CS0 Register MSW of CS1 Register LSW of CS1 Register MSW of CS2 Register LSW of CS2 Register MSW of CS3 Register LSW of CS3 Register MSW of Interrupt Control/Status LSW of Interrupt Control/Status PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT EEPROM Offset (Hex) Value (Hex) 60 62 64 - 7F 0002 46C2 FFFF PLX Register MSW of EEPROM and Misc. Control LSW of EEPROM and Misc. Control Unused PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 8 8.1 LAYOUT DESCRIPTIONS Component Placement Figure 6 shows the approximate placement of the major components of the AAL1gator-32/TEMUX Development Kit. Components are located to minimize trace lengths while taking into account the priority of traces. Figure 6 Major Component Placement RAM LVDS Transformer LVDS S/UNIDUPLEX AAL1gator-32 TEMUX Bantam Connectors Protection Circuitry RAM LEDs DS3 SMB DS3 SMB DS3 LIU PCI Interface Chip COMETQuad PCI Edge Connector 8.2 Power and Ground Four power and ground planes are used on the AAL1gator-32/TEMUX Development Kit PCI expansion board. There are two ground planes, one +2.5V plane and one +3.3 V plane. In addition there is a small +5 V power plane around the PCI9050 and the PCI card edge connector for the +5 V devices. This plane is on one of the inner signal layers of the board and does not have any critical traces routed over it unless they are on an outside layer where a ground plane is in-between. A chassis ground signal is routed around the outside of the board that connects to each mounting hole and connector shielding. 8.3 Routing * All power and ground traces are as wide and short as possible to minimize trace inductance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT * * All high speed traces are routed over continuous image planes (power or ground planes). All traces carrying transmit and receive line rate data are transmission lines with controlled impedances. These traces should be routed on the same side and kept as short as possible. Both signals of a differential pair are of equal length and routed close to each other. All PCI signal traces are 75 impedance. All UTOPIA interface signals are also 75 impedance. For each of the UTOPIA interface signal, a series termination resistor is added at each output. All LVDS signals are 50 controlled impedance. * * * * 8.4 PCI Bus Signal Specification This layout follows the PCI Rev. 2.2 Specification layout restrictions. The PCI Special Interest Group specification has stringent and detailed rules on decoupling, power consumption, trace lengths, routing, trace impedance, and signal loading. It is therefore essential to check the latest PCI specification before proceeding with new designs and layouts. The AAL1gator-32/TEMUX Development Kit PCI expansion board conforms to the following PCI Specifications/Recommendations: * * * * * Component height on the component side does not exceed 0.570 inches, and on the solder side does not exceed 0.105 inches. PCI CLK signal trace is 2.5 inches +/- 0.1 inches and is connected to only one load. All 32-bit interface signals have the maximum trace length of 1.5 inches. Trace impedance for shared PCI signals are within 60-100 range, and trace velocity is between 150 and 190 ps/inch. 20 mil wide traces are used to connect the power and ground pins on PCI connector to their respective planes and the trace lengths are limited to 250 mil. Route all traces over continuous image planes. * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 9 9.1 MANUFACTURING ISSUES Board Assembly The AAL1gator-32/TEMUX Development Kit has one assembly option. The S/UNI-DUPLEX LVDS line interface can be populated as capacitively coupled or transformer coupled. For capacitive coupling, transformer T1 should not be populated on the board. For transformer coupling, capacitors C204 to C211 and resistors R126 to R133 should not be populated on the board. The development kit boards are originally populated with the transformer-coupled option. The above modifications must be made to the hardware to achieve a capacitvelycoupled board. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 10 GLOSSARY ATM AAL1 AAL1gator-32 COMET-QUAD DSLAM LAN LVDS PBGA POTS PSTN SAR S/UNI S/UNI-DUPLEX SCI-PHY TDM TEMUX WAN Asynchronous Transfer Mode ATM Adaptation Layer Type 1 PMC-Sierra's mnemonic for the PM73122 32 Link CES/DBCES ATM AAL1 SAR PMC-Sierra's mnemonic for the PM4354 Combined Fourchannel E1/T1 Framer/Transceiver Digital Subscriber Line Access Multiplexer Local Area Network Low Voltage Differential Signal Plastic Ball Grid Array Plain Old Telephone Service Public Switched Telephone Network Segmentation and Reassembly SATURN User Network Interface PMC-Sierra's mnemonic for the PM7350 Dual Port Serialized UTOPIA Multiplexer PMC-Sierra's enhanced UTOPIA bus Time Division Multiplexing PMC-Sierra's mnemonic for the PM8315 High Density T1/E1 Framer with Integrated VT/TU Mapper and M13 Multiplexer Wide Area Network PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 11 REFERENCES 1. PMC-Sierra, Inc., PMC-2001068, "AAL1gator-32/TEMUX Development Kit Platform", July 2000, Issue 1. 2. PLX Technology, "PCI9050-1 Databook", April 17, 1997, Version 1.01 3. PMC-Sierra, Inc., PMC-1981419, "32 Link CES/DBCES AAL1 SAR Processor (AAL1gator-32) Telecom Standard Product Data Sheet", May 2000, Issue 5. 4. PMC-Sierra, Inc., PMC-1981125, "High Density T1/E1 Framer with Integrated VT/TU Mapper and M13 Multiplexer Telecom Standard Product Data Sheet", April 2001, Issue 6. 5. PMC-Sierra, Inc., PMC-1990315, "COMET-QUAD Datasheet", May 2001, Issue 6. 6. PMC-Sierra, Inc., PMC-1980581, "S/UNI-DUPLEX Dual Serial Link PHY Multiplexer Data Sheet", April 2000, Issue 5. 7. PCI Special Interest Group,"PCI Local Bus Specification", December 1998, Revision 2.2. 8. PMC-Sierra, Inc., PMC-1991820, "AAL1gator-32/8/4 Programmer's Guide", January 2000, Issue 1. 9. ATM Forum, "Circuit Emulation Service Interoperability Specification", January 1997, Version 2.0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 12 APPENDIX A: BILL OF MATERIALS Table 4 Major Component List Part Name - Value BANTAM Connector EPSON 12.288MHZ CRYSTAL Part Number Manufacturer Qty 8 1 8 Ref Des J12, J14J20 Y4 ELECTROSONIC - PC- ADC TELECOM 834-J-(BLACK) MA-505-12.288M-C2 SEMTECH - LC01-6 EPSON ELECTRONICS SEMTECH U23, U24, LC01-6 U26, U27, U29, U30, U32, U33 U28 U1 U11 1.544 HCMOS OSCILLATOR 38.880 HCMOS OSCILLATOR PCI9050_PQFP-BASE M-TRON MB3050H1.544MHZ M-TRON MB3050H38.880MHZ PCI9050-1 TR250-180 CB3LV-3C-25.0000- T MMD MMD PLX TECHNOLOGY RAYCHEM CTS REEVES CYPRESS 1 1 1 16 1 2 TR1-TR16 THERMISTOR Y1 OSCILLATOR, 25MHZ, 3.3V, 50PPM U12, U14 CY7C1352-80MHZ SRAM CY7C1352 PIPELINED 256KX18 TQFP100 J9 Y6 Y3 Y5 Y7 Y2 SMB_VERTICAL-BASE ARF1244-ND OSCILLATOR, 19.44MHZ, H5M943-19.440M 3.3V, 50PPM OSCILLATOR, H5M943-37.056M 37.056MHZ, 3.3V, 32PPM OSCILLATOR, H5M943-44.736M 44.736MHZ, 3.3V, 50PPM OSCILLATOR, H5M943-49.152M 49.152MHZ, 3.3V, 32PPM OSCILLATOR, 25.00MHZ, H5M943-25.000M 3.3V, 50PPM DIGI-KEY CONNOR WINFIELD CONNOR WINFIELD CONNOR WINFIELD CONNOR WINFIELD CONNOR WINFIELD 1 1 1 1 1 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 33 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT U9 U16 J3, J4 J1, J2 U13 U10 U25 NM93CS46_DIP8_SOCKE NM93CS46EN T -BASE MK2049 IC Clock PLL SMB RIGHT ANGLE MK2049-01S 131-3701-341 FAIRCHILD SEMI 1 ICS MICROCLOCK 1 JOHNSON COMPONENTS MOLEX PERICOM PMC-SIERRA PMC-SIERRA 2 2 1 1 1 MOLEX 53984-0611 2MM 53984-0611 PI3B16233 TSSOP56-BA SE AAL1GATOR-32_SBGABA SE COMETQUAD_REVA3_PBG ABASE TEMUX_REVC5_PBGABAS E PI3B16233 PM73122 PM4354 U17 U4 T2 U2 T1 U6 U31 U19 PM8315-PI PMC-SIERRA PMC-SIERRA PULSE PULSE PULSE ENGINEERING 1 1 1 1 1 SUNIDUPLEX_SCIPHY_1 PM7350-PI _ PBGA-BASE PE65967_LS-1-BASE PE65968_LS-1-BASE H1026_SMD-BASE 78P2241_PLCC-BASE T9021 Transformer PE-65967 PE-65968 H1026 78P2241 T9021 TDK 1 SEMICONDUCTOR PULSE XILINX 1 1 XC95144XL-TQ100_TQFP XC95144XL-7TQ100C -7NS Table 5 Miscellaneous Parts Part Name - Value Part Number Ref Des U5, U8, U21, U22 Manufacturer FAIRCHILD SEMI Qty 4 QUAD BUFFER WITH 74ACT125SC THREE STATE OUTPUTS 74HC04_SOICVCC=3_3V CAPACITOR-0.01UF, DIGIKEY U20 C6, C9-C12, C14, 1 139 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT C16, C19-C22, C26, 50V, X7R_603 C30, C35-C39, C42, C44, C46, C47, C49, C50, C53, C56, C62, C66-C71, C73, C74, C76-C79, C81, C82, C84-C90, C92-C119, C121, C122, C124C127, C129-C147, C149, C151-C168, C170-C174, C176, C177, C179, C185, C186, C189, C191C193, C197, C199, C203, C213, C216 C201 C27 PCC103BVCT-ND CAPACITOR-0.047UF, NEWARK - 85F219 25V, X7R_0603 CAPACITOR-0.047UF, ECH-U1H473GB9 50V, PPS_1913 PANASONIC - ECJ-1VB1C104K 1 1 20 C1, C2, C5, C7, C28, CAPACITOR-0.1UF, C29, C41, C55, C61, 16V, X7R_603 C64, C91, C187, C188, C190, C194, C195, C198, C200, C212, C215 C45, C48, C54, C65 CAPACITOR-0.47UF, ECJ-1VB0J474K 6.3V, X5R_603 C204-C211 C148 C3, C4 C184, C196 C31 CAPACITOR-0.22UF, NEWARK -16V, Y5V_805 52F022 PANASONIC 4 8 1 2 2 1 19 CAPACITOR-0.33UF, ECJ-3VB1C334K PANASONIC 16V, X7R_1206 CAPACITOR-10UF, 16V, TANT TEH CAPACITOR-10UF, 6.3V, TANT TE CAPACITOR-22UF, 16V, TANT TEH DIGI-KEY -PCT3106CT-ND DIGI-KEY -PCS1106CT-ND DIGI-KEY -PCT3226CT-ND C13, C17, C18, C63, CAPACITOR-22UF, C72, C75, C80, C83, 6.3V, TANT TE C120, C123, C128, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT C150, C169, C175, C178, C180-C183 C15, C57-C60, C202, C214 CAPACITOR-4.7UF, 10V, TANT TEH DIGI-KEY -PCT2475CT-ND DIGI-KEY -PCT2476CT-ND QUALITY SEMI AMP 7 11 C8, C23-C25, C32- CAPACITOR-47UF, C34, C40, C43, C51, 10V, TANT TEH C52 U7 J10 D4 D5, D6 SW2 F2 F1 J8 J5-J7 J13 J11 L1-L3 D3 U15 CLOCK_BUFFER_QS QS53805 53805 -BASE CON_MICTOR_38PIN 2-767004-2 _2-7 67004-2-BAA 5% 1W SMD ZENER DIODE DIGI-KEY -ZM4735ACT-ND 1 1 1 2 1 1 1 DIODE_SCHOTTKY_ DIGI-KEY -SMB_2 -2A, 20V B220DICT-ND DIPSW4-BASE FUSE__SMD_SOCKE DIGIKEY -T-2.5 00A, NANO F1225CT-ND FUSE__SMD_SOCKE DIGIKEY -T-5.0 00A, NANO F1228CT-ND HEADER2_100MILBASE HEADER3S_100MILBASE HEADER6_100MILBASE HEADER_4X2_100MI L-BASE INDUCTOR-4.7UH, , INDUCTOR_FC LED-SUPER_RED, SURFACE MOUNT 7A LOW DROPOUT 100MV TO 540MV REGULATOR DIGI-KEY DN10472CT-ND SIEMENS -LST670-HK LT1580CQ LINEAR TECHNOLOGY LINEAR PZC36SAAN SULLINS ELECTRONICS PZC36SAAN SULLINS ELECTRONICS 1 3 1 1 3 1 1 U3 4.6A LOW DROPOUT LT1585CT-3.3 FIXED 3.3V 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT REGULATOR U18 POWER-SUPPLY MONITOR WITH RESET MAXIM MAX700CSA TECHNOLOGY 1 SW1 U13 R3, R47, R95 VERT PCB MOUNT DIGIKEY -SPST PUSH BUTTOM P8009S-ND Bus Switch RESISTOR-0, 5%, 603 PI3B16233 PERICOM 1 1 3 15 R1, R37, R39, R40, RESISTOR-1, 5%, 603 R43-R45, R50, R51, R73, R75, R78, R79, R135, R137 R126-R133 RESISTOR-1.00M, 1%, 603 DIGI-KEY -P 8 R6, R83, R136, R138 RESISTOR-1.0K, 5%, DIGI-KEY -603 P 4 8 R41, R52, R72, R80, RESISTOR-100K, 1%, R123 603 R16-R21, R84, R122, R124, R125 R91, R92 RESISTOR-10K, 1%, DIGI-KEY -603 P 5 10 2 R53, R54, R56, R57, RESISTOR-12.7, 1%, DIGI-KEY -R59, R60, R62, R63 603 P12.7HCT-ND R55, R58, R61, R64 RESISTOR-18.2, 1%, DIGI-KEY -603 P18.2HCT-ND R7, R8 R14 RESISTOR-20, 5%, 603 RESISTOR-270, 5%, 603 ? DIGI-KEY -P 8 4 2 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT ND R5 RESISTOR-3.3, 5%, 805 RESISTOR-301, 1%, 805 RESISTOR-330, 5%, 603 RESISTOR-4.7, 5%, 603 RESISTOR-4.75K, 1%, 603 DIGI-KEY -P R2 R24, R25, R94, R100, R106, R116 R42, R48, R49 R112 1 6 3 1 R22, R23, R26, R29, RESISTOR-4.7K, 5%, DIGI-KEY -R30, R46, R81, R82, 603 P 20 2 R9-R12 R27 RESISTOR-49.9, 1%, ? 603 RESISTOR-5.1M, 5%, DIGI-KEY -805 P 4 1 R134 1 R4, R13, R28, R31- RESISTOR-56, 5%, R36, R38, R74, R77, 603 R86, R97-R99, R101, R103-R105, R115, R119-R121, R139, R140 R15 RESISTOR-75, 1%, 805 26 DIGI-KEY -P75.0CCT-ND 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT R111, R114 RESISTOR-750, 5%, 603 RESISTOR-931, 1%, 805 DIGI-KEY -P 2 R85 1 RN24, RN25, RN30, RES_ARRAY_4_SMD- DIGI-KEY -RN31 10K Y4 4 2 RN19, RN21, RN33- RES_ARRAY_4_SMD- DIGI-KEY -RN37, RN40-RN47 330 Y4 15 23 22 1 1 QUAD YELLOW LED. SSF-LXH5147LYD LUMEX PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 13 APPENDIX B: SCHEMATICS The schematics for the development kit are revision 2.0. The schematics contain 13 pages as follows: Sheet 1: Root Drawing This sheet provides a block view of the interface signals between each block of the AAL1gator-32/TEMUX Development Kit. Sheet 2: DS3 Line Interface This sheet shows the connection surrounding the TDK Semiconductor 78P2241 Transceiver and the SMB connectors. Sheet 3-4: TEMUX Block These sheets shows the connections required for PMC-Sierra's PM8315 TEMUX. Sheet 5-6: COMET Line Interface These sheets contain the connectors and line protection circuitry required by the COMET-QUAD. Sheet 7: COMET-QUAD Block This sheet contains PMC-Sierra's PM4354 COMET-QUAD and its important power pin filtering circuitry. Sheet 8-10: AAL1gator-32 Block These sheets show the PM73122 AAL1gator-32 and the two SRAMs. Sheet 11: S/UNI-DUPLEX This sheet shows the PM7350 S/UNI-DUPLEX and the LVDS connectors and line interface circuitry. Sheet 12-13: PCI and CPLD These sheets show the PCI9050, CPLD, MK2049 PLL, and power supplies. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H PAGE 2 PAGES 3-4 TEMUX_BLOCK RPOS_DS3 RNEG_DS3 RCLK_DS3 TPOS_DS3 TNEG_DS3 TCLK_DS3 RPOS_DS3 RNEG_DS3 RCLK_DS3 TPOS_DS3 TNEG_DS3 TCLK_DS3 LOS TICLK<2..1> RCLK XCLK SADATA<7..0> SADP SAPL SAV5 SAJUST SADATA<7..0> SADP SAPL SAV5 SAJUST SREFCLK SC1FP SDDATA<7..0> SDDP SDPL SDV5 DS3 LINE INTERFACE RPOS_DS3 RNEG_DS3 RCLK_DS3 G TPOS_DS3 TNEG_DS3 TCLK_DS3 LOS PAGES 8-10 AAL1GATOR_32_BLOCK PAGE 11 S/UNI-DUPLEX SREFCLK SC1FP SDDATA<7..0> SDDP SDPL SDV5 SREFCLK SC1FP SDDATA<7..0> SDDP SDPL SDV5 SADATA<7..0> SADP SAPL SAV5 SAJUST RDAT<15..0> RADDR<4..0> RPRTY RENB RCA RSOC RCLK RDAT<15..0> RADDR<4..0> RPRTY RDENB RCA RSOC RCLK RDAT<15..0> RADDR<4..0> RPRTY RENB RCA RSOC RCLK G F BRCLK<4..1> BRSIG<4..1> BRFP<4..1> BRPCM<4..1> BTCLK<4..1> BTSIG<4..1> BTFP<4..1> BTPCM<4..1> TE_MICRO<3..0> BRCLK<4..1> BRSIG<4..1> BRFP<4..1> BRPCM<4..1> BTCLK<4..1> BTSIG<4..1> BTFP<4..1> BTPCM<4..1> AAL_MICRO<4..0> TDAT<15..0> TADDR<4..0> TPRTY TENB TCA TSOC TCLK TDAT<15..0> TADDR<4..0> TPRTY TENB TCA TSOC TCLK TDAT<15..0> TADDR<4..0> TPRTY TENB TCA TSOC TCLK F JTAG<2..0> TDO6 TDO1 JTAG<2..0> TDO1 TDO3 JTAG<2..0> TDO3 TDO4 E DUP_MICRO<3..0> BUSSEL NCLK RL_CLK TL_CLK ADDR<19..0> DATA<15..0> ADDR<19..0> DATA<15..0> ADDR<19..0> DATA<15..0> E RSTB RSTB RX8K TX8K TDO1 RSTB TDO3 JTAG<2..0> TDO4 TE_MICRO<3..0> DATA<15..0> ADDR<19..0> D TICLK<2..1> PAGE 7 PAGES 5-6 COMET_LINE_INTERFACE TXTIP<4..1> TXRING<4..1> TXCM<4..1> RXTIP<4..1> RXRING<4..1> COMET_QUAD_BLOCK RCLK TXTIP<4..1> TXRING<4..1> TXCM<4..1> RXTIP<4..1> C RXRING<4..1> TXTIP<4..1> TXRING<4..1> TXCM<4..1> RXTIP<4..1> RXRING<4..1> BTCLK<4..1> BTSIG<4..1> BTFP<4..1> BTPCM<4..1> TDO4 TDO5 JTAG<2..0> CTCLK RSYNC ADDR<19..0> DATA<15..0> CQ_MICRO<3..0> TDO6 TDO5 JTAG<2..0> CTCLK RSYNC CQ_MICRO<3..0> B CQ_MICRO<3..0> BRCLK<4..1> BRSIG<4..1> BRFP<4..1> BRPCM<4..1> TICLK<2..1> AAL_MICRO<4..0> DATA<15..0> ADDR<19..0> TE_MICRO<3..0> XCLK PAGES 12-13 PCI AND CPLD TL_CLK RL_CLK NCLK BUSSEL DUP_MICRO<3..0> RX8K TX8K RSTB D DUP_MICRO<3..0> RSTB C B RSTB DRAWING: TITLE=AAL32 DEVKIT ROOT ABBREV=ROOT LAST_MODIFIED=Tue Dec 12 09:46:10 2000 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 ISSUE DATE: NOVEMBER 2000 A TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: ROOT DRAWING 2.0 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 PAGE:1 1 OF 13 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H DS3 LINE INTERFACE G 3.3 V R135 1 G 3.3 V R137 3.3 V R1 4.7UF C15 0.1UF C212 1 4.7UF 4.7UF C202 0.1UF C2 J3 2 C214 0.1UF C1 RX 5 3 SMB 4 1 1.0K R136 1 T2 1:1 1 6 6 R15 75 1 F F PLCC U6 LIN+ LINTCLK TPOS TNEG RCLK RPOS TXEN RNEG MON ICKP 78P2241 LOUT+ E3 LOUTLPBK ENDEC LOS RFO LF1 VCC VCC VCC GND GND GND GND GND LBO 2 4 6 8 22 12 7 17 26 33 44 PE65967 3E10> 3E10> 3E10> TCLK_DS3\I TPOS_DS3\I TNEG_DS3\I 3.3 V R19 10K 75 OHM 75 OHM 75 OHM 3.3 V 10K R125 1 3 16 14 15 18 21 10 10K R122 13 28 20 10K 5 19 75 OHM 23 25 24 9 11 27 RCLK_DS3\I RPOS_DS3\I J4 2 RN66 RN66 RN66 RN66 4 1 3 2 5 8 6 7 56 56 56 56 3.3 V 1 4F10< 4E10< 4E10< 75 OHM 75 OHM RNEG_DS3\I 1:2 1 U2 6 3 5 3 R2 3.3 V 2 301 6 2 J6 E H3 R124 2 33 0.1UF C215 SMB 1 TX E 44 1.0K R138 1 3.3 V R18 10K R17 5.23K 3 C201 R123 R134 0.047UF 3.3 V PE-65968 100K 10K J5 2 H3 LOS\I 3.3 V 4E10< 1 10K R16 10K R21 3 1 270 D3 R14 3.3 V 2 2 1 H3 D J7 4 D C 10K R20 C B DRAWING TITLE=DS3_LINE_INTERFACE ABBREV=DS3_LINE_INTERFACE LAST_MODIFIED=Thu May 17 10:45:25 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT DS3_LINE_INTERFACE ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: NOVEMBER 2000 REVISION NUMBER: 2.0 PAGE:2 1 OF 13 A 10 2.5 V 0.01UF C108 0.01UF 9 8 3.3 V 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR C106 0.01UF C92 0.01UF C105 0.01UF C77 0.01UF C93 0.01UF C101 0.01UF 0.01UF C94 0.01UF C79 0.01UF C96 0.01UF C113 C78 H H PLACE DECOUPLING CAPS PHYSICALLY CLOSE TO TEMUX POWER PINS G G 3.3 V AA12 AA15 L21 C12 AA8 R21 H21 A15 2.5 V RN24 RN24 RN24 RN24 RN25 RN25 RN25 RN25 1 3 1 4 2 1 2 3 4 6 8 5 7 8 7 6 5 3.3 V 10K 10K 10K 10K 10K 10K 10K 10K F SADATA<7..0>\I 8G10> N2 J2 R2 U17 VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDD2V5<8> VDD2V5<7> VDD2V5<6> VDD2V5<5> VDD2V5<4> VDD2V5<3> VDD2V5<2> VDD2V5<1> C9 CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1> P1 N1 P4 M3 N4 M2 C5 A4 L2 L1 B5 A5 E22 C20 B6 D4 M1 P2 C7 D6 M22 N19 B4 A3 R4 T2 A2 A7 N22 N21 N20 P19 AA3 AB4 F2 E4 K4 L3 D20 B22 U22 T20 F1 D3 R1 U4 C21 D21 V19 U21 G3 G2 T1 AB1 T22 T21 V22 AB22 AA21 Y19 Y4 AB3 3.3 V 4.7K 4.7K F W12 AB10 AA10 Y10 W9 AB9 W8 W7 AB8 W13 AA11 W10 Y11 AB11 AB7 W6 AA6 AA7 A16 D16 B16 C15 D17 LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB CSB RDB WRB ALE D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB TP11 CTCLK 7 6 5 4 3 2 1 0 2F9< 2F9< 13D4> 2F9< 13E4<> TPOS_DS3\I TNEG_DS3\I TICLK<1>\I TCLK_DS3\I TE_MICRO<3..0>\I RN22 RN22 RN22 3 2 1 0 2 3 1 7 6 8 56 56 56 TE_INTB TE_CSB TE_RDB TE_WRB 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E R82 R81 SAPL\I SAV5\I SADP\I 8E10> 8F10> 8F10> E 13D9<> 12G1<> 11C1<> 9F5<> 7H6<> DATA<15..0>\I D13 A13 B13 C13 D14 A14 B14 C14 B21 C19 A21 B20 B19 C18 A20 A19 A18 B17 D19 D18 C16 A17 A22 TEMUX PM8315 1 OF 2 D D UNUSED INPUTS 13D9<> 12E1> 13D4> 9E5<> ADDR<19..0>\I RSTB\I C VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> C L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12 P11 P10 P9 N3 Y12 L20 B12 J3 R3 Y8 Y15 R20 H20 B15 B9 B DRAWING: TEMUX_1.1 TMX1 Thu May 17 10:44:54 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 ISSUE DATE: NOVEMBER 2000 A TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: TEMUX_BLOCK 1 2.0 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 PAGE:3 1 OF 13 10 3.3 V 0.01UF C110 0.01UF C98 0.01UF C100 0.01UF C102 0.01UF C112 0.01UF C111 0.01UF 9 8 3.3 V C95 0.01UF C97 0.01UF 7 6 5 4 3 2 1 REVISIONS ZONE C39 C103 0.01UF C99 0.01UF C109 0.01UF C104 0.01UF 0.01UF C37 0.01UF C36 0.01UF REV DESCRIPTION DATE APPR C107 H H PLACE DECOUPLING CAPS PHYSICALLY CLOSE TO TEMUX POWER PINS 9 U22 10 ACT125 8 56 R35 19.44 MHZ 1 TP45 SREFCLK 3.3 V Y6 OSC_EP26 G 0.01UF C38 4 2 5 3 1 56 R77 U22 4 ACT125 6 56 R33 SREFCLK\I 8D2< G VCC GND OUTPUT TS/PD 3.3 V AA14 AA9 Y18 U20 M21 F20 C17 B11 U22 1 2 ACT125 19.44MHZ 3 56 R34 F3 M4 U3 Y5 U17 VDD3V3<9> VDD3V3<8> VDD3V3<7> VDD3V3<6> VDD3V3<5> VDD3V3<4> VDD3V3<3> VDD3V3<2> VDD3V3<13> VDD3V3<12> VDD3V3<11> VDD3V3<10> VDD3V3<1> D5 SBI C1FP TP33 330 R99 P3 W17 AB15 W16 W15 AB14 W14 Y13 AA13 Y16 AB16 AA16 AB17 AB12 AB13 AA17 AB18 W18 AA18 AB19 W19 CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TCK TMS TDI TDO TRSTB CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1> T4 B7 A6 D7 A8 C8 C10 B10 H4 J1 A10 D10 L19 M19 A11 D11 V4 U2 D12 A12 P22 P21 H2 G4 W2 Y2 G21 G22 P20 R19 T19 AA20 Y6 AA5 D2 E3 J4 K3 F21 E19 G19 H19 C1 D1 U1 T3 G20 F22 K19 L22 H1 H3 AA1 W3 F19 H22 Y20 W22 AB21 AB20 AB2 Y3 1 F 13D4< 9A4< 11H4> KEEP INPUT CLOSE TO INPUT ON TEMUX U22 13 RN27 RN33 RN28 RN28 RN28 RN28 RN29 RN29 RN29 RN29 8 4 3 2 1 4 4 3 1 2 RES_ARRAY_4 1 5 6 7 8 5 5 6 8 7 56 330 56 56 56 56 56 56 56 56 7 6 5 4 3 2 1 0 SC1FP\I SAJUST\I 8F2< 8F2< F SDDATA<7..0>\I 8F2< RCLK\I 56 R36 13 11 ACT125 12 2F2> RCLK_DS3\I 13 U20 HC04 U21 11 12 12 9 ACT125 10 13 4 10 13C4> 2E4> 2F2> TICLK<2>\I LOS\I RPOS_DS3\I U21 8 ACT125 U21 6 5 ACT125 E 2E2> RNEG_DS3\I 2 ACT125 3 RN23 RN23 RN23 RN23 13D3> 13D3> 9E5< 3 5 1 2 6 56 4 56 8 56 7 56 14 1 U21 13D9> XCLK\I JTAG<2..0>\I TDO6\I TDO1\I W5 Y7 AB6 E20 0 1 2 C3 C2 C4 B3 B1 3.3 V RN31 RN31 RN31 RN31 RN30 RN30 RN30 RN30 2 1 3 4 4 1 2 3 RES_ARRAY_4 TEMUX PM8315 2 OF 2 7 8 6 5 5 8 7 6 10K 10K 10K 10K 10K 10K 10K 10K E 8F2< 8E2< SDV5\I SDPL\I RN27 RN27 4 2 5 7 56 56 D 8E2< SDDP\I RN27 3 6 56 A9 D8 K2 K1 J20 J22 R22 U19 D9 E1 V1 W4 J19 K20 Y22 V20 G1 F4 W1 Y1 K21 K22 W21 Y21 AA22 W20 V3 AB5 C22 D22 IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1 TEMUXSELB D C RECVCLK2TP32 RECVCLK1TP23 VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1> 1 1 C VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> AA2 J14 J13 J12 J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11 E2 L4 V2 AA4 Y9 W11 Y14 Y17 AA19 V21 M20 J21 E21 B18 D15 C11 B8 C6 B DRAWING: TEMUX_1.2 TMX1 Thu May 17 10:44:59 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 ISSUE DATE: NOVEMBER 2000 A TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: TEMUX_BLOCK 2 2.0 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 PAGE:4 1 OF 13 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H TR250-180 R76 T 100 TN RN R S J12 T TN RN R S 7G10> TXTIP<1>\I 12.7 R53 16 15 14 13 12 11 10 9 PLACE CLOSE TO TRANSFORMER TX1 TR7 7F10< TXCM<1>\I 12.7 R54 4.7UF + C60 1 U31 T9021 1:2.42 40 U23 LC01-6 BANTAM 1 2 3 4 5 6 7 8 G TR250-180 G 7F10> TXRING<1>\I 3 38 TR4 3.3 V 2 TR250-180 R71 16 15 14 13 12 11 10 9 7 TR8 T 100 TN RN R S J14 T TN RN R S RX1 F BANTAM F U24 7G6< RXTIP<1>\I 4 1:2.42 37 18.2 5 R55 36 1 2 3 4 5 6 7 8 LC01-6 TR250-180 7G6< RXRING<1>\I TR5 E E TR250-180 R70 T 100 TN RN R S J15 T TN RN R S D 7G10> TXTIP<2>\I 12.7 R56 6 1:2.42 16 15 14 13 12 11 10 9 PLACE CLOSE TO TRANSFORMER 35 TR1 TX2 D BANTAM 8 4.7UF + C59 33 1 2 3 4 5 6 7 8 7F10< TXCM<2>\I 12.7 R57 U26 LC01-6 TR250-180 TR2 7F10> TXRING<2>\I C 9 C 1:2.42 32 TR250-180 R69 10 31 16 15 14 13 12 11 10 9 TR3 T 100 TN RN R S J16 T TN RN R S RX2 BANTAM 7G6< 18.2 R58 U27 RXTIP<2>\I 1 2 3 4 5 6 7 8 LC01-6 B RXRING<2>\I B TR250-180 7G6< TR6 PMC-Sierra, Inc. A DRAWING TITLE=T1E1_LINE_INTERFACE_1 ABBREV=LINE1 LAST_MODIFIED=Thu May 17 10:45:14 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 TITLE: AAL1GATOR_32/TEMUX DEVELOPMENT KIT LINE INTERFACE 1 ENGINEER: BW 2 ISSUE DATE: NOVEMBER 2000 REVISION NUMBER: 2.0 PAGE:5 TRUE 1 OF 13 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H TR250-180 R68 T 100 TN RN R S J17 T TN RN R S 7G10> TXTIP<3>\I 12.7 R59 16 15 14 13 12 11 10 9 PLACE CLOSE TO TRANSFORMER TR15 TX3 BANTAM 7F10< TXCM<3>\I 12.7 R60 4.7UF + C58 11 U31 T9021 1:2.42 30 U29 LC01-6 1 2 3 4 5 6 7 8 G TR250-180 G 13 28 TR12 7F10> TXRING<3>\I 3.3 V 12 TR250-180 17 16 15 14 13 12 11 10 9 TR16 R67 T 100 TN RN R S J18 T TN RN R S RX3 F BANTAM F RXTIP<3>\I 14 7G6< 1:2.42 27 18.2 15 R61 26 1 2 3 4 5 6 7 8 U30 LC01-6 TR250-180 7G6< RXRING<3>\I TR13 E E TR250-180 J19 R66 T 100 TN RN R S PLACE CLOSE TO TRANSFORMER 7G10> 16 25 D 12.7 R62 18 23 16 15 14 13 12 11 10 9 TXTIP<4>\I 1:2.42 TR9 T TN RN R S TX4 D BANTAM 1 2 3 4 5 6 7 8 7F10< TXCM<4>\I 12.7 R63 4.7UF + C57 U32 LC01-6 TR250-180 TR10 7G10> TXRING<4>\I C 19 C 1:2.42 22 TR250-180 20 21 TR11 16 15 14 13 12 11 10 9 R65 T 100 TN RN R S J20 T TN RN R S RX4 BANTAM 7G6< 18.2 R64 U33 RXTIP<4>\I 1 2 3 4 5 6 7 8 LC01-6 B RXRING<4>\I B TR250-180 7G6< TR14 PMC-Sierra, Inc. A DRAWING TITLE=T1E1_LINE_INTERFACE_2 ABBREV=LINE2 LAST_MODIFIED=Thu May 17 10:45:17 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT LINE INTERFACE 2 ENGINEER: BW 2 ISSUE DATE: NOVEMBER 2000 REVISION NUMBER: 2.0 PAGE:6 TRUE 1 OF 13 A 10 9 U25 8 7 6 5 4 3 2 1 13D9<> 12E1> ADDR<19..0>\I H 10 9 8 7 6 5 4 3 2 1 0 D15 D16 C16 C15 B16 A16 B15 A15 B14 A14 B13 T1 T3 T2 R3 P3 13D3< 11B6> 13D3> TDO5\I TDO4\I JTAG<2..0>\I 0 1 2 COMET-QUAD PM4354 3 OF 4 A<10> D<7> A<9> D<6> A<8> D<5> A<7> D<4> A<6> D<3> A<5> D<2> A<4> D<1> A<3> D<0> A<2> A<1> A<0> RDB WRB TDO CSB TDI ALE TCK INTB TMS RSTB TRSTB MICRO_JTAG REVISIONS D3 D2 C2 C1 B1 A1 A2 B3 D14 E15 E16 E14 F15 E13 7 6 5 4 3 2 1 0 DATA<15..0>\I 3.3 V ZONE 3D10<> 9F5<> 11C1<> 12G1<> 13D9<> REV DESCRIPTION DATE APPR H 4.7K R46 CQ_RDB CQ_WRB CQ_CSB CQ_INTB 1 0 2 3 CQ_MICRO<3..0>\I 13E4<> RSTB\I 9E5<> 13D4> U25 COMET-QUAD PM4354 1 OF 4 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 3 4 1 2 1 2 M14 L2 H16 F3 M15 M3 J14 G3 N13 M1 H14 H4 M16 M4 H13 F4 K2 K1 L4 K3 F1 F2 U25 G 6D10< 6G10< 5D10< 5G10< 8D2> BTCLK<4..1>\I TXTIP<4>\I TXTIP<3>\I TXTIP<2>\I TXTIP<1>\I R13 P4 A13 B4 T11 R6 A11 B6 COMET-QUAD PM4354 TXTIP1<4> 2 OF 4 TXTIP1<3> TXTIP1<2> TXTIP1<1> TXTIP2<4> TXTIP2<3> TXTIP2<2> TXTIP2<1> TXRING1<4> TXRING1<3> TXRING1<2> TXRING1<1> TXRING2<4> TXRING2<3> TXRING2<2> TXRING2<1> TXCM<4> TXCM<3> TXCM<2> TXCM<1> RXTIP<4> RXTIP<3> RXTIP<2> RXTIP<1> N10 P7 D10 C7 P10 T7 C10 A7 P9 T8 C9 A8 T15 J13 L16 R16 R15 T16 P8 D8 J4 1 1 J15 N3 1 1 L14 RXTIP<4>\I RXTIP<3>\I RXTIP<2>\I RXTIP<1>\I RXRING<4>\I RXRING<3>\I RXRING<2>\I RXRING<1>\I TCLKO TP56 1 6B10> 6F10> 5B10> 5F10> 6B10> 6E10> 5B10> 5E10> BTCLK<4> BTCLK<3> BTCLK<2> BTCLK<1> BTSIG<4> BTSIG<3> BTSIG<2> BTSIG<1> BTFP<4> BTFP<3> BTFP<2> BTFP<1> BTPCM<4> BTPCM<3> BTPCM<2> CASBTD_BTPCM<1> BRCLK<4> BRCLK<3> BRCLK<2> BRCLK<1> BRSIG<4> BRSIG<3> BRSIG<2> BRSIG<1> BRFP<4> BRFP<3> BRFP<2> BRFP<1> BRPCM<4> BRPCM<3> BRPCM<2> CASBRD_BRPCM<1> N16 N1 F16 E2 P16 P2 G15 E3 P15 R1 G14 E4 N15 P1 F13 E1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 BRCLK<4..1>\I 8D10< G BRSIG<4..1>\I 8E10< 8E2> BTSIG<4..1>\I RXRING<4> RXRING<3> RXRING<2> RXRING<1> RVREF<4> RVREF<3> RVREF<2> RVREF<1> RES<8> XCLK CTCLK RSYNC PIO RES<7> RES<6> RES<5> RES<4> RES<3> RES<2> RES<1> 8G2> BTFP<4..1>\I BRFP<4..1>\I 8G10< 6C10< 6G10< 5C10< 5G10< TXRING<4>\I TXRING<3>\I TXRING<2>\I TXRING<1>\I T13 R4 C13 A3 R11 N5 B11 D5 8D2> BTPCM<4..1>\I 3.3 V RN21 RN21 RN21 RN21 RN19 RN19 BRPCM<4..1>\I 8E10< CTCLK\I RSYNC\I 1 13D4> 13D4< F 0.1UF C61 LINE TP48 TP52 TP49 TP53 R47 6D10> 6G10> 5D10> 5G10> TXCM<4>\I TXCM<3>\I TXCM<2>\I TXCM<1>\I N12 P5 D12 C5 TP54 RDAT 3.3 V 0 8 4 6 5 8 7 8 7 330 330 330 330 330 330 COMET-QUAD XCLK U28 VDD OUT 5 1 CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK CMVFPC CMVFPB SYSTEM F 56 R74 GND NC/TS T1: 1.544 MHZ E1: 2.048 MHZ R41 0.01UF R72 0.01UF R80 0.01UF R52 0.01UF E 100K E C76 C62 100K C47 100K C46 100K 3.3 V 4.7 C72 0.01UF R48 22UF + 3.3 V 4.7 C56 C63 0.01UF R42 22UF + C42 U25 R14 C8 T9 R8 B9 B8 D 3.3 V 1 1 0.01UF C74 0.47UF R50 1 0.01UF C90 0.47UF C54 R40 1 0.01UF C49 0.47UF C45 R44 0.01UF C66 0.47UF C65 R43 3.3 V 3.3 V 3.3 V QAVD<2> QAVD<1> RAVD1<4> RAVD1<3> RAVD1<2> RAVD1<1> RAVD2<4> RAVD2<3> RAVD2<2> RAVD2<1> TAVD1<4> TAVD1<3> TAVD1<2> TAVD1<1> TAVD2<4> TAVD2<3> TAVD2<2> TAVD2<1> TAVD3<4> TAVD3<3> TAVD3<2> TAVD3<1> COMET-QUAD PM4354 4 OF 4 QAVS<2> QAVS<1> RAVS1<4> RAVS1<3> RAVS1<2> RAVS1<1> RAVS2<4> RAVS2<3> RAVS2<2> RAVS2<1> TAVS1<4> TAVS1<3> TAVS1<2> TAVS1<1> TAVS2<4> TAVS2<3> TAVS2<2> TAVS2<1> TAVS3<4> TAVS3<3> TAVS3<2> TAVS3<1> VSSC2_5<7> VSSC2_5<6> VSSC2_5<5> VSSC2_5<4> VSSC2_5<3> VSSC2_5<2> VSSC2_5<1> VSS3_3<9> VSS3_3<8> VSS3_3<7> VSS3_3<6> VSS3_3<5> VSS3_3<4> VSS3_3<3> VSS3_3<2> VSS3_3<1> VSSQ3_3<2> VSSQ3_3<1> GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 POWER D T14 D9 R9 N7 A9 D7 R10 N6 B10 D6 N11 P6 D11 C6 R12 N4 B12 C4 T12 R5 A12 B5 L15 K16 G13 L3 J3 H1 G2 0.01UF C14 M2 P14 L13 F14 R2 J2 D1 B2 K13 G4 3.3 V 1 0.01UF R51 3.3 V 1 3.3 V 1 3.3 V T10 R7 A10 B7 P11 T6 C11 A6 C41 P13 T4 D13 A4 P12 T5 C12 A5 C48 C73 0.1UF 0.01UF C55 R39 1 C44 0.1UF 0.01UF C91 R45 C50 0.1UF 0.01UF C64 R37 C82 0.1UF C 3.3 V 1 1 0.01UF R75 1 0.01UF C71 47UF C52 R79 1 0.01UF C89 47UF C43 R73 0.01UF C67 47UF C51 R78 C 3.3 V 3.3 V 3.3 V 2.5 V C68 0.01UF C88 0.01UF 0.01UF 0.01UF C85 0.01UF C86 0.01UF C69 0.01UF J16 M13 K15 H15 L1 J1 H3 G1 N14 G16 N2 K4 D4 C3 VDDC2_5<8> VDDC2_5<7> VDDC2_5<6> VDDC2_5<5> VDDC2_5<4> VDDC2_5<3> VDDC2_5<2> VDDC2_5<1> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDDQ3_3<2> VDDQ3_3<1> CAVS CAVD GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 C81 47UF C40 DECOUPLING CAPS: ONE PER TWO POWER PINS 3.3 V 2.5 V C87 C84 C70 B B 3.3 V 3.3 V 4.7 0.01UF R49 K14 H2 N8 N9 G7 G8 G9 G10 H7 H8 H9 H10 DRAWING: COMET_QUAD COMETQ Thu May 17 10:45:29 2001 J7 J8 J9 J10 K7 K8 K9 K10 C53 22UF C75 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 4 ISSUE DATE: MAY 2001 A A TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: COMET_QUAD_BLOCK 2.1 ENGINEER: 10 9 8 7 6 5 4 3 WT 2 PAGE:7 1 OF 13 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H U10 AAL1GATOR-32 PM73122 1 OF 5 TL_SYNC15 TL_SYNC14 TL_SYNC13 TL_SYNC12 TL_SYNC11 TL_SYNC10 TL_SYNC9 TL_SYNC8 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA15 TL_DATA14 TL_DATA13 TL_DATA12 TL_DATA11 TL_DATA10 TL_DATA9 TL_DATA8 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG15 TL_SIG14 TL_SIG13 TL_SIG12 TL_SIG11 TL_SIG10 TL_SIG9 TL_SIG8 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK15 TL_CLK14 TL_CLK13 TL_CLK12 TL_CLK11 TL_CLK10 TL_CLK9 TL_CLK8 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE1 LINE_MODE0 LINE INTERFACE RN42 10D7< 8 RAM2_A<17..0> G 10B7< 10C7< 3F2< 7G2> 14 11 7 6 2 RAM2_OEB RAM2_CSB RN46 RN36 SADATA<7..0>\I BRFP<4..1>\I 4 3 2 1 17 15 12 8 4 3 0 7 4 R141 R143 7 7 F 10C7< RAM2_WE0B RN37 RN35 6 3 1 0 1 2 16 13 10 9 5 1 0 1 2 R144 R145 R146 R147 R148 7 7 3E2< 3E2< SADP\I SAV5\I 1 10C7< 10B7< RAM2_WE1B RAM2_R/WB BRPCM<4..1>\I 4 3 2 5 2 0 0 1 2 3 4 5 5 4 3 3 4 5 E 7F2> RN37 RN36 RN34 R149 R150 R151 R152 8 5 3 3E2< 7G2> SAPL\I BRSIG<4..1>\I 1 2 3 4 7G2> BRCLK<4..1>\I D 13D4> 4 3 2 1 RN42 RN42 RN41 RN41 RN43 RN44 RN45 RN45 RN47 RN36 RN35 RN34 6 6 7 6 7 8 7 7 6 5 6 8 8 2 6 RL_CLK\I N24 AE15 AF8 Y4 AB1 M2 C7 B11 2 330 C4 2 330 E2 G2 56 K3 56 R1 U2 W2 AB4 AD16 AD15 AE9 AA3 Y3 M1 B6 C11 D3 2 330 F3 2 330 H3 56 J1 56 R2 56 T4 56 Y1 56 AC3 AE16 AF15 AC10 AB2 AA2 M3 D8 D12 A3 1 330 F4 4 330 H4 6 330 H1 56 P3 56 U1 56 U4 56 AC2 2 330 N23 3 330 P25 2 330 R24 1 330 R23 2 330 K23 2 330 H25 3 330 B15 4 330 A16 D5 3 330 D1 1 330 F1 1 330 J2 7 330 L1 T3 V3 AD1 B7 1 330 R100 330 RL_SYNC15 RL_SYNC14 RL_SYNC13 RL_SYNC12 RL_SYNC11 RL_SYNC10 RL_SYNC9 RL_SYNC8 RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA15 RL_DATA14 RL_DATA13 RL_DATA12 RL_DATA11 RL_DATA10 RL_DATA9 RL_DATA8 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG15 RL_SIG14 RL_SIG13 RL_SIG12 RL_SIG11 RL_SIG10 RL_SIG9 RL_SIG8 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK15 RL_CLK14 RL_CLK13 RL_CLK12 RL_CLK11 RL_CLK10 RL_CLK9 RL_CLK8 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK K24 AC15 AC11 AF7 AA1 N3 A5 B10 A4 E4 G4 G1 L4 R3 V1 W3 J26 AF16 AF9 AD9 P2 M4 C6 A9 B4 E3 G3 K4 K1 T2 W1 AB3 L23 AC14 AD10 AE8 N2 L2 D7 D11 C5 D2 F2 J3 L3 R4 V2 AA4 J25 N25 R25 T26 H26 J24 A15 C15 D6 C1 E1 H2 K2 T1 U3 Y2 C8 B5 AC1 RN43 RN40 1 3 8 6 330 330 15 10 9 7 2 0 RAM2_D<15..0> 10D2<> G RN46 RN37 RN35 RN35 3 4 4 3 6 5 5 6 330 330 330 330 4 3 2 1 BTFP<4..1>\I 7G6< RN44 RN40 1 2 8 7 330 330 14 12 8 6 4 1 F SDDATA<7..0>\I 4F2> RN46 4 5 330 6 4 2 0 15 14 13 12 15 14 13 12 SDV5\I SAJUST\I SC1FP\I 13 11 1 5 3 0 RN43 RN40 3 4 6 5 330 330 RAM2_PAR<1..0> 4D9> 4F2> 4F2> 10D2<> RN47 4 5 330 7 5 3 1 E SDDP\I SDPL\I RN33 3 6 11 10 9 8 11 10 9 8 330 BTSIG<4..1>\I 4D9> 4D9> RN44 RN43 RN42 RN41 RN45 RN44 RN47 RN45 RN47 RN37 RN36 RN34 3 4 4 3 1 4 1 2 2 3 3 5 6 5 5 6 8 5 8 7 7 6 6 4 330 330 330 330 330 330 330 330 330 330 330 330 11 10 9 8 15 14 13 12 4 3 2 1 4 3 2 1 4 3 2 1 7G6< BTPCM<4..1>\I 7F6< BTCLK<4..1>\I 7G6< 7 7 7 D SREFCLK\I TL_CLK\I 4G2> 13D4> RN46 1 8 330 COMMON<15..0> TEMUX<15..0> COMET<15..0> 3.3 V 43 14 TEMUX/COMET-QUAD SELECT JUMPER FOR COMET-QUAD J8 R26 1 2 4.7K H2 3.3 V TSSOP56 U13 VCC 1 54 4 51 7 48 10 45 15 40 18 37 21 34 24 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C VCC 0.01UF C137 0.01UF B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 55 3 52 6 49 9 46 12 41 17 38 20 35 23 32 26 C138 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 56 2 53 5 50 8 47 11 42 16 39 19 36 22 33 25 1A 1B1 2A 2B1 3A 3B1 4A 4B1 5A 5B1 6A 6B1 7A 7B1 8A 8B1 9B1 9A 10A 10B1 11A 11B1 12A 12B1 13A 13B1 14A 14B1 15A 15B1 16A 16B1 PI3B16233 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 SEL1 13B2 SEL2 14B2 15B2 TEST1 16B2 TEST2 GND GND C 3.3 V BUSSEL\I 13C9< B DRAWING: AAL1GATOR_32_1.1 AAL1 30 29 27 28 Thu May 17 10:45:04 2001 RN33 RN33 1 2 8 7 330 330 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 ISSUE DATE: NOVEMBER 2000 A 44 A 13 TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: AAL1GATOR-32 LINE INTERFACE 2.0 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 PAGE:8 1 OF 13 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE 3.3 V 2.5 V REV DESCRIPTION DATE APPR H 0.01UF H 0.01UF C172 0.01UF C152 0.01UF C160 0.01UF C162 0.01UF C163 0.01UF C159 0.01UF C161 0.01UF C158 0.01UF C170 0.01UF C174 0.01UF C156 0.01UF C155 0.01UF C153 0.01UF 0.01UF 0.01UF C154 C164 C157 DECOUPLING CAPS ONE CAP PER TWO POWER PINS C171 G U10 13D9<> 12E1> G ADDR<19..0>\I F 3.3 V NCLK\I RN38 RN38 RN38 7 6 8 13C4> E AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 AC8 AF10 AE7 AD8 AD5 AC6 AF4 AE5 AD6 AF3 AE4 AD7 2 4.7K AE6 3 4.7K AC7 1 4.7K AF5 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AAL1GATOR-32 PM73122 2 OF 5 A19 A18 A17 A16 A15 D15 A14 D14 A13 D13 A12 D12 A11 D11 A10 D10 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 CGC_DOUT3 ALE CGC_DOUT2 WRB CGC_DOUT1 RDB CGC_DOUT0 CSB CGC_LINE4 ACKB CGC_LINE3 INTB CGC_LINE2 TRSTB CGC_LINE1 RSTB CGC_LINE0 SYSCLK SCAN_MODEB SRTS_STBH TCLK ADAP_STBH NCLK TMS TL_CLK_OE TDI CGC_SER_D TDO CGC_VALID MICRO/JTAG 3.3 V V23 V4 P23 N4 J4 J23 D23 D18 D14 D9 D4 C24 C3 B25 B2 AE25 AE2 AD24 AD3 AC23 AC18 AC13 AC9 AC4 A21 A10 P4 W4 AF6 AF17 AA26 L26 G23 U10 AAL1GATOR-32 PM73122 VDD23 3 OF 5 VSS27 VSS26 VDD22 VSS25 VDD21 VSS24 VDD20 VSS23 VDD19 VSS22 VDD18 VSS21 VDD17 VSS20 VDD16 VSS19 VDD15 VSS18 VDD14 VSS17 VDD13 VSS16 VDD12 VSS15 VDD11 VSS14 VDD10 VSS13 VDD9 VSS12 VDD8 VSS11 VDD7 VSS10 VDD6 VSS9 VDD5 VSS8 VDD4 VSS7 VDD3 VSS6 VDD2 VSS5 VDD1 VSS4 VDD0 VSS3 PCH_9 VSS2 PCH_8 VSS1 PCH_7 VSS0 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 POWER SUPPLY AF26 AF25 AF14 AF13 AF2 AF1 AE26 AE3 AE24 AE1 AD25 AD2 P26 P1 N26 N1 C25 C2 B26 B24 B3 B1 A26 A25 A14 A13 A2 A1 AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AD12 AF11 AC12 AE11 AD11 AE10 AC5 AD4 B23 AC24 D22 A24 C23 A23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA<15..0>\I 3D10<> 7H6<> 11C1<> 12G1<> 13D9<> 3.3 V RN39 RN39 RN39 RN38 2 3 1 4 7 6 8 5 1K 1K 1K 4.7K F AAL_WRB AAL_RDB AAL_CSB AAL_ACKB AAL_INTB 2 0 1 2 4 3 AAL_MICRO<4..0>\I 13E4<> RSTB\I 0 1 13D4> 3D10< 7G6< 11B1< 2.5 V JTAG<2..0>\I TDO1\I TDO3\I 13D3> 4E9> 11B6< E 3.3 V 50PPM 3.3V 38.880MHZ HCMOS U1 8 U5 13 12 ACT125 11 56 R121 VDD OUT 5 1 56 R120 0.01UF 0.1UF C200 C199 4 GND NC/TS U5 10 9 ACT125 8 56 R13 RAM1_CLK 10E7< D 3.3 V 0.01UF 5 C14 D U5 4 ACT125 6 56 R97 RAM2_CLK 10B7< U5 1 2 ACT125 3 56 R98 38.88 MHZ 1 TP10 C U10 11G1> C TDAT<15..0>\I B 11F1> TADDR<4..0>\I 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 3 6 11F1> 11F1> 11F1< TPRTY\I TENB\I TCA\I RN50 56 AB24 AA23 AC26 AB25 Y23 AB26 AA25 Y24 V25 U24 V26 T23 T24 U26 T25 R26 AA24 W23 W24 W25 V24 Y25 U25 U23 RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV AAL1GATOR-32 PM73122 5 OF 5 TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 RATM_CLK RATM_SOC TATM_PAR TATM_ENB TATM_CLAV TATM_CLK TATM_SOC D24 E23 C26 D25 F23 D26 E25 F24 K25 L24 K26 L25 P24 M24 M25 M26 E24 G24 F25 H23 G25 Y26 W26 E26 H24 M23 F26 G26 RN59 RN57 RN59 RN59 RN57 RN59 RN57 RN57 RN55 RN55 RN55 RN55 RN52 RN52 RN52 RN52 7 7 8 6 6 5 8 5 8 6 7 5 5 6 7 8 2 2 1 3 3 4 1 4 1 3 2 4 4 3 2 1 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 RDAT<15..0>\I 11E1< B RADDR<4..0>\I 11D1> DRAWING: AAL1GATOR_32_1.2 AAL1 Thu May 17 10:45:07 2001 RN58 RN60 RN56 8 6 7 1 3 2 56 56 56 TCLK\I TSOC\I RPRTY\I RENB\I RCA\I RCLK\I RSOC\I 11H4> 11F1> 11D1< 11D1> 11D1< 4F10> 11D1< 11H4> PMC-Sierra, Inc. 820 820 R104 UTOPIA INTERFACE R4 A DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 ISSUE DATE: NOVEMBER 2000 A TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: AAL1GATOR-32_BLOCK 2 2.0 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 PAGE:9 1 OF 13 10 9 8 7 6 5 4 3 2 1 REVISIONS 3.3 V 0.01UF C141 0.01UF C140 0.01UF 0.01UF C125 0.01UF C127 0.01UF C144 0.01UF C146 0.01UF 0.01UF C139 0.01UF C142 0.01UF ZONE C126 C145 C143 REV DESCRIPTION DATE APPR H H RAM1_D<15..0> 3.3 V 91 66 65 41 16 15 80MHZ U14 RAM1_A<17..0> 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> 77 70 61 54 27 20 14 11 4 G G U10 AAL1GATOR-32 PM73122 4 OF 5 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A18 C17 B18 A19 D17 C18 B19 A20 B20 A17 D19 C20 A22 D20 C21 B22 D21 C22 F RAM1_A17 RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0 9D5> RAM1_CLK RAM INTERFACE E 3.3 V RN61 VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB A7 B8 C9 D10 B9 C10 A6 A11 B12 A12 D13 C13 B13 B14 C14 D15 A8 B16 D16 C19 B21 C16 B17 C12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.3 V A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 0 7 6 5 4 3 2 1 0 1 15 14 13 12 11 10 9 8 CY71352 (256K X 18) F RAM1_WEB0 RAM1_WEB1 R90 4.7K RAM1_OEB RAM1_CSB RAM1_R/WB 1 0 R88 4.7K BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE E 5 4 4.7K RAM1_PAR<1..0> 3.3 V D 91 66 65 41 16 15 90 76 71 67 64 60 55 40 26 21 17 10 5 D 80MHZ U12 8G10> 77 70 61 54 27 20 14 11 4 VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> RAM2_A<17..0> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> C 3.3 V 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 0 7 6 5 4 3 2 1 0 1 15 14 13 12 11 10 9 8 RAM2_PAR<1..0> RAM2_D<15..0> 8E2<> 8G1<> C CY71352 (256K X 18) 8F10> 8E10> 8G10> 8G10> 8E10> 9D5> RAM2_WE0B RAM2_WE1B RAM2_CSB RAM2_OEB RAM2_R/WB RAM2_CLK R87 4.7K R89 4.7K VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE B B DRAWING: AAL1GATOR_32_1.3 AAL1 Thu May 17 10:45:11 2001 3.3 V 0.01UF C131 0.01UF C135 0.01UF 0.01UF C132 0.01UF C122 0.01UF C134 0.01UF C136 0.01UF 0.01UF C121 0.01UF C129 0.01UF 90 76 71 67 64 60 55 40 26 21 17 10 5 C133 C124 C130 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 ISSUE DATE: NOVEMBER 2000 A A TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: AAL1GATOR-32_BLOCK 3 2.0 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 PAGE:10 1 OF 13 10 9 8 7 6 3.3 V 5 4 3 2 1 REVISIONS U7 VDD VDD CLOCK BUFFER DUAL 1-TO-5 ALL LVDS TRACES 50 OHM NOTE: POPULATE BOARD WITH EITHER TRANSFORMERS OR CAPACITORS/RESISTORS, NOT BOTH. H 1.00M 1.00M R133 R132 C211 C210 0.22UF C5 0.01UF 0.22UF 0.1UF 1 OA1 OA2 OA3 2 3 4 6 7 13 19 18 17 15 14 RN62 RN62 RN62 RN62 1 2 3 4 8 7 6 5 56 56 56 56 TPHY_CLK TCLK\I RPHY_CLK RCLK\I REFCLK ZONE 11F1< 9B4< 11D1< 13D4< 4F10> 9A4< 11F6< REV DESCRIPTION DATE APPR 3.3 V 4 2 C6 Y2 OSC_CTF_CB3 VCC GND OUTPUT OE/NC 25MHZ 3 1 56 R103 330 R101 20 H 10 INA OA4 OA5 MON OB1 OB2 OB3 OB4 OB5 R153 56 T1 39 11 9 12 INB OEA# OEB# GND GND GND TXP TDP 2 RN63 RN63 RN63 RN63 1 2 3 4 8 7 6 5 56 56 56 56 U4 ODAT<15> ODAT<14> ODAT<13> ODAT<12> ODAT<11> ODAT<10> ODAT<9> ODAT<8> ODAT<7> ODAT<6> ODAT<5> ODAT<4> ODAT<3> ODAT<2> ODAT<1> ODAT<0> OADDR<4> OADDR<3> OADDR<2> OADDR<1> OADDR<0> OMASTER OBUS8 OANYPHY OAVALID J4 K3 K2 L3 L2 M1 M3 N2 P2 N4 M4 L5 N6 L6 N7 P7 N9 M10 N10 L10 P11 M11 P4 M5 M9 P9 J2 L7 P8 N8 N5 C7 B1 C2 C1 D2 D3 D1 E1 E3 E4 F2 F1 G1 G4 H3 G3 H1 D6 A5 D5 A4 C4 3.3 V U4 0.01UF TXN TDN H14 C21 TXD1+ C20 0.01UF 50 OHM 37 4 5 8 16 TO AAL1GATOR-32 TO AAL1GATOR-32 G J2 P1 P2 P3 P4 P5 P6 MH1 MH2 MH3 MH4 1 2 3 4 5 6 MH1 MH2 MH3 MH4 3 0.1UF C198 50 OHM H13 H1026 TXD1- RN561 RN564 RN542 RN531 RN532 RN533 RN534 RN512 RN514 RN513 RN511 RN544 RN501 RN543 RN502 RN504 RN493 RN492 RN481 RN491 RN482 RN3 RN40 RN41 8 5 7 8 7 6 5 7 5 6 8 5 8 6 7 5 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 6 8 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 TDAT<15..0>\I 9C9< G 1 2 6 7 8 8 7 34 7 0.1UF C195 TADDR<4..0>\I 3.3 V 9B9< 50 OHM MOLEX 53984-0611 3.3 V G14 R114 3.3 V RXD1+ 4.7K R96 49.9 3 1 4 4.7K 330 330 R12 750 OUTPUT: 16-BIT UTOPIA LEVEL 2 MASTER F 50 OHM 35 RXP RDP 6 C194 10UF 0.1UF C196 430 A2 F RN494 RN563 RN541 5 6 8 R113 49.9 R11 RSTOB G13 OENB 56 56 56 TENB\I TPRTY\I TSOC\I TCA\I TPHY_CLK 9B9< 9B9< 9B4< 9B9> 11H4> 33 8 RXN RDN RXD1- REFCLK P12 REFCLK 56 R115 11H4> OPRTY OSOC OSX OCA OFCLK 13D4< 13D4> 1.00M 1.00M 1.00M 1.00M R130 R131 R129 R128 C208 C209 C207 C206 0.22UF 0.22UF 0.22UF 0.22UF RX8K TX8K E13 B14 RX8K\I TX8K\I T1 E 29 K14 TXD2+ RCLK E11 56 R119 1 TXP TDP 12 TP1 K13 50 OHM 27 14 TXD2- TXN TDN SCIANY -----------IDAT<15> IDAT<14> IDAT<13> IDAT<12> IDAT<11> IDAT<10> IDAT<9> IDAT<8> IDAT<7> IDAT<6> IDAT<5> IDAT<4> IDAT<3> IDAT<2> IDAT<1> IDAT<0> IADDR<4> IADDR<3> IADDR<2> IADDR<1> IADDR<0> RN61 1 8 4.7K 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDAT<15..0>\I 9C4> E 49.9 750 R10 D R111 J1 P1 P2 P3 P4 P5 P6 MH1 MH2 MH3 MH4 13 1 2 3 4 5 6 MH1 MH2 MH3 MH4 0.1UF C190 RN583 RN601 RN584 RN602 RN582 8 330 330 6 8 5 7 7 56 56 56 56 56 4 3 2 1 0 RADDR<4..0>\I 9B4< 3.3 V INPUT: 16-BIT UTOPIA LEVEL 2 MASTER 50 OHM 3.3 V J14 H1026 RXD2+ S/UNI-DUPLEX PM7350 LVDS 1 OF 4 IMASTER IBUS8 IANYPHY IAVALID S/UNI-DUPLEX SCI-PHY PM7350 2 OF 4 IENB IPRTY ISOC ICA ISX IFCLK A6 RN3 1 C6 R116 J1 R24 B6 B4 B2 H2 A3 H4 F4 4.7K D RN604 5 56 24 17 0.1UF C187 C188 10UF C184 430 0.1UF 49.9 R110 RENB\I RPRTY\I RSOC\I RCA\I RPHY_CLK 9A4< 9B4> 9A4> 9A4> 11H4> MOLEX 53984-0611 R9 RN613 6 5 7 4.7K 4.7K 4.7K J13 25 RXD2- RXP RDP 16 LTXD3 LTXD0 N1 RN3 4 N12 RN3 2 3.3 V 50 OHM 50 OHM DATA<15..0>\I C R126 23 18 RXN RDN 7 6 5 4 3 2 1 0 C14 D13 D12 D14 F11 F13 F12 F14 U4 D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> S/UNI-DUPLEX PM7350 TDO TDI TCK TMS TRSTB MICRO/JTAG 3 OF 4 13D9<> 3D10<> 9F5<> 12E1> 7H6<> 12G1<> C 1.00M C204 C205 0.22UF 0.22UF 1.00M R127 4.7K R118 1.0K R6 0.01UF 0.01UF 22UF + 22UF + C183 C182 R7 20 3.3 V VCC B3 C5 C13 D10 E2 E14 F3 K1 L1 L4 L9 M7 M12 N3 N13 P6 ALE RDB WRB CSB INTB RSTB B8 A8 D9 D8 B7 A10 1 0 2 3 7H10< TDO4\I TDO3\I 0 1 4.7K R117 A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> C9 A9 B9 B10 D11 A11 C11 B11 7 6 5 4 3 2 1 0 ADDR<19..0>\I 3.3 V 13D9<> P13 A12 B13 B12 A13 DUP_MICRO<3..0>\I 13E4<> VDD<0> VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10> VDD<11> VDD<12> VDD<13> VDD<14> VDD<15> VDD_A 20 R8 C10 C9 U4 9E5> M13 L11 J11 K11 QAVD CAVD RAVD TAVD<1> TAVD<0> BIAS A7 B B RSTB\I 9E5<> 13D4> RES G12 4.75K R112 13D3> JTAG<2..0>\I 2 0.01UF 0.01UF 22UF + 22UF + C180 C181 C12 C11 R5 3.3 G11 S/UNI-DUPLEX PM7350 POWER 4 OF 4 VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10> VSS<11> VSS<12> VSS<13> VSS<14> VSS<15> VSS<16> VSS<17> VSS<18> VSS<19> RESK ATP1 ATP0 GND<3> GND<2> GND<1> GND<0> H11 L13 L14 H8 H7 G8 G7 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF C173 C191 C186 C189 C185 C197 C192 M14 L12 J12 K12 H12 QAVS CAVS RAVS TAVS<1> TAVS<0> S/UNI-DUPLEX NOTE: VCC = +5V 3.3 V PMC-Sierra, Inc. C193 B5 C3 C8 C10 C12 D4 D7 E12 G2 J3 K4 L8 M2 M6 M8 N11 N14 P3 P5 P10 A DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 DRAWING TITLE=DUPLEX ABBREV=DUPLEX LAST_MODIFIED=Thu May 17 10:45:21 2001 4 3 ISSUE DATE: NOVEMBER 2000 A TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: S/UNI-DUPLEX BLOCK 2.0 ENGINEER: BW 2 PAGE:11 1 OF 13 NOTE: PLACE FILTER NETWORKS AS PHYSICALLY CLOSE TO THE DEVICE AS POSSIBLE. 10 9 8 7 ALTERNATE CAPS ON SUNI-DUPLEX VDD PINS 6 5 10 9 8 7 6 5 4 3 2 1 REVISIONS VCC PCI_VCC_3.3V F1 VCC 5.000A H 0.01UF 0.01UF C166 0.01UF C168 0.01UF C151 0.01UF C177 0.01UF C165 0.01UF 0.01UF C147 0.01UF C176 C167 C149 ZONE REV DESCRIPTION DATE APPR H P1 A1 A2 A3 A4 A5 A6 A7 A8 PCI_VCC_3.3V -12V TCK GROUND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# GROUND GROUND RESERVED GROUND CLK GROUND REQ# +5V AD[31] AD[29] GROUND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GROUND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GROUND IRDY# +3.3V DEVSEL# GROUND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GROUND AD[12] AD[10] GROUND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V RESERVED GROUND GROUND 3.3VAUX RST# +5V GNT# GROUND PME# AD[30] +3.3V AD[28] AD[26] GROUND AD[24] IDSEL +3.3V AD[22] AD[20] GROUND AD[18] AD[16] +3.3V FRAME# GROUND TRDY# GROUND STOP# +3.3V RESERVED RESERVED GROUND PAR AD[15] +3.3V AD[13] AD[11] GROUND AD[09] U11 VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 43 42 39 38 37 36 35 34 32 31 30 29 28 25 24 23 11 8 7 6 5 4 3 2 157 156 155 154 153 152 151 150 33 22 12 158 21 13 14 15 17 159 16 19 20 149 148 44 18 144 143 145 142 1 2 3 4 1 10 27 41 50 66 81 103 121 146 91 90 89 88 87 86 85 84 83 82 79 78 77 76 75 74 73 72 71 70 69 62 61 60 59 58 57 56 55 54 53 52 92 93 94 95 96 97 98 100 101 102 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 122 49 48 47 46 137 136 135 134 133 132 63 130 131 138 139 140 141 123 124 127 126 125 128 129 64 68 C179 0.01UF VCC RN10 4.7K RN11 4.7K RN12 4.7K RN13 4.7K G VCC G A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 PCICLK F 30 A19 A20 A21 28 26 A22 A23 A24 24 A25 A26 A27 AD<31..0> B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 17 2 21 19 23 3 27 25 31 29 CBE<3..0> E 22 20 A28 A29 A30 18 16 A31 A32 A33 A34 A35 A36 A37 A38 AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> AD<8> AD<9> AD<10> AD<11> AD<12> AD<13> AD<14> AD<15> AD<16> AD<17> AD<18> AD<19> AD<20> AD<21> AD<22> AD<23> AD<24> AD<25> AD<26> AD<27> AD<28> AD<29> AD<30> AD<31> C/BEB<0> C/BEB<1> C/BEB<2> C/BEB<3> PAR FRAMEB IRDYB TRDYB STOPB IDSEL DEVSELB PERRB SERRB CLK RSTB INTAB LOCKB EESK EEDO EEDI EECS TEST VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10> D A39 A40 A41 A42 A43 15 A44 A45 13 11 A46 A47 A48 RN64 4.7K RN65 8 7 5 6 5 6 7 8 TP18 TEST U9 1 99 9 26 40 51 65 80 104 120 147 160 NM93CS46 B43 B44 B45 B46 B47 B48 B49 12 10 14 1 VCC PRE PE GND VCC 4.7K R108 4.7K R109 C 9 A49 0 A52 A53 6 4 A54 A55 A56 2 0 A57 A58 A59 A60 A61 A62 C/BE[0]# +3.3V AD[06] AD[04] GROUND AD[02] AD[00] +5V REQ64# +5V +5V AD[08] AD[07] +3.3V AD[05] AD[03] GROUND AD[01] +5V ACK64# +5V +5V B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 8 7 5 3 LAD<0> LAD<1> LAD<2> LAD<3> LAD<4> LAD<5> LAD<6> LAD<7> LAD<8> LAD<9> LAD<10> LAD<11> LAD<12> LAD<13> LAD<14> LAD<15> LAD<16> LAD<17> LAD<18> LAD<19> LAD<20> LAD<21> LAD<22> LAD<23> LAD<24> LAD<25> LAD<26> LAD<27> LAD<28> LAD<29> LAD<30> LAD<31> LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LBEB<0> LBEB<1> LBEB<2> LBEB<3> LINTI1 LINTI2 LCLK LHOLD LHOLDA LRESETB BCLKO CSB<0> CSB<1> USER0/WAITOB USER1/LLOCKOB USER2/CS2B USER3/CS3B ADSB BLASTB LWR RDB WRB LRDYIB BTERMB ALE MODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA<15..0>\I 13D9<> 9F5<> 3D10<> 7H6<> 11C1<> 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 F 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 RN14 4.7K RN15 4.7K RN16 4.7K RN17 4.7K 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VCC RN9 4.7K RN8 4.7K RN7 4.7K RN6 4.7K RN5 4.7K RN4 4.7K VCC 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 ADDR<19..0>\I 11C1< 7H10< 13D9<> 3D10< 9G9< E D CPLD_ADDR<22..20> 13D9<> VCC VCC 4.7K R107 4.7K 4.7K R102 CS SK DI DO 4.7K 1 2 4 3 4 3 2 1 R93 INTB 13D4> LCLK LRESETB 0 R95 0 1 2 3 13H9< 13D9< 13E9< 13D5<> 13D5<> 8 7 6 5 CSB<3..0> USER0 USER1 C RDB WRB LRDYIB 13E9< 13E9< 13C9> R94 330 1 330 R25 PCI-9050-1 B B PCI_5V_32BIT_CARD_CONNECTOR PMC-Sierra, Inc. A DRAWING TITLE=PCI_INTERFACE ABBREV=PCI_INTERFACE LAST_MODIFIED=Thu May 17 10:45:33 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT PCI INTERFACE ENGINEER: BW 2 ISSUE DATE: NOVEMBER 2000 REVISION NUMBER: 2.0 PAGE:12 TRUE 1 OF 13 A 10 9 8 7 6 5 4 3 2 1 REVISIONS J10 MICTOR 38 PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 +5V GND_D A-CLK A-D15 A-D14 A-D13 A-D12 A-D11 A-D10 A-D9 A-D8 A-D7 A-D6 A-D5 A-D4 A-D3 A-D2 A-D1 A-D0 SCL DSA B-CLK B-D15 B-D14 B-D13 B-D12 B-D11 B-D10 B-D9 B-D8 B-D7 B-D6 B-D5 B-D4 B-D3 B-D2 B-D1 B-D0 ZONE 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 REV DESCRIPTION DATE APPR H 12C1> LCLK ADDR<19..0>\I RDB WRB CSB<3..0> TP29 19 18 17 0 1 3 2 1 0 3 2 1 0 47UF 47UF C32 47UF C34 VCC 0.1UF 15 C28 4 6 5 7 VCC 0.1UF 17 14 19 C29 47UF TE_MICRO<3..0>\I 15 14 0 3 2 1 0 3 2 1 0 4 3 2 1 0 DATA<15..0>\I DUP_MICRO<3..0>\I 3.3 V VCC 2.5 V H CQ_MICRO<3..0>\I F2 5 U15 LT1580CQ 2.5 V VPOWER VCONT SENSE 4 1 3 6 110 0.33UF R91 47UF C23 47UF C148 C24 AAL_MICRO<4..0>\I 2.500A 3.3 V VCC RN2 2 1 3 4 VOUT ADJ TAB C25 2 22UF C31 C33 270 7 8 6 5 A1 A2 A3 A4 GREEN D2 K1 K2 K3 K4 LED SSF-LXH5147 39 40 41 42 43 R92 110 G 13 U16 VDD GND GND GND GND VDD VDD VDD PCI_VCC_3.3V CLK1 9 1 1 RSTB\I G ICLK FS3 FS2 FS1 FS0 X1 X2 TP58 TP59 VCC 12.288MHZ Y4 1 2 12 11 1 20 3 2 MK2049 CLK2 CAP1 CAP2 8 56 R32 VCC U3 LT1585 10UF 10UF 1 2A 20V 8K 10 VCC 3.3 V 0 VDD_A D5 1 50PPM 0.047UF 16 18 3 0.1UF 5.1M 47UF 1W D4 2 R3 C3 6.2V VIN VOUT 2 3.3 V F 2.5 V 2 C27 R27 C4 C8 C7 1 2A 20V GND VOUT_TAB 4 2 3.3 V YELLOW D1 A1 A2 A3 A4 11 12 13 14 15 16 17 18 19 20 6 7 8 9 10 7 6 5 4 3 2 1 0 3 2 1 0 22 21 20 24 25 28 29 30 32 33 34 87 89 90 91 92 93 94 95 96 97 22 23 27 3 4 1 2 99 3.3 V Y7 OSC_EP26 0.01UF 4 C216 2 5 57 98 VCCINT1 VCCINT2 VCCINT3 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCC GND OUTPUT TS/PD 3 1 56 R139 3 4 2 1 6 5 7 8 K1 K2 K3 K4 26 38 51 88 RN1 270 U19 LED SSF-LXH5147 49.152MHZ 12C1> E CSB<3..0> 3 2 1 0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO/GCK1 IO/GCK2 IOGCK3 IOGTS1 IOGTS2 IOGTS3 IO/GTS4 IO/GSR IO73 IO72 IO71 IO70 IO69 IO68 IO67 IO66 IO65 IO64 IO63 IO62 IO61 IO60 IO59 IO58 IO57 IO56 IO55 IO54 73 72 71 70 68 67 66 65 64 63 61 60 59 58 56 55 54 53 52 50 86 85 82 81 80 79 78 77 76 74 49 46 43 42 41 40 39 37 36 35 48 45 83 47 3 2 1 0 3 2 1 0 4 3 2 1 0 3 2 1 0 CQ_MICRO<3..0>\I 7H6<> TE_MICRO<3..0>\I 3E10<> AAL_MICRO<4..0>\I 3.3 V DUP_MICRO<3..0>\I 4.7K RN26 5 6 7 8 D6 1 F 9F5<> E 3.3 V 12C1> 12C1> RDB WRB 11B1< SW2 4 3 2 1 1 2 3 4 DIPSW4 12G1<> 11C1<> 9F5<> 7H6<> 3D10<> DATA<15..0>\I 4.7K RN20 JTAG PORT 8 7 6 5 1 2 3 4 8 7 6 5 XC95144XL-TQ100 7NS D 11C1< 9G9< 7H10< 3D10< 12E1> ADDR<19..0>\I CPLD_ADDR<22..20> XCLK\I LRESETB 56 R140 12D1> IO53 IO52 IO51 IO50 IO49 IO48 IO47 IO46 IO45 IO44 IO43 IO42 IO41 IO40 IO39 IO38 IO37 IO36 IO35 IO34 11B6< 9E5< 12C1<> 7H10< 4E9< 7H10> 4E9< JTAG<2..0>\I TDO5\I TDO6\I 2 0 1 USER0 USER1 12C1<> 1 2 3 4 5 6 56 R86 R38 56 RCLK\I TICLK<1>\I RSYNC\I CTCLK\I 56 56 56 56 J11 1 3 5 7 J13 P_1 P_2 P_3 P_4 P_5 P_6 D 4F10> 3E10< 7F6> 7F6< 12C1< 9E5<> 8D2< 8D10< 11E6> 11E6< 9E10< 4E10< 11H4> TEMUX TICLK 3.3 V Y5 OSC_EP26 0.01UF 4 C30 2 4E9< 12C1> RN18 RN18 RN18 RN18 1 2 3 4 8 7 6 5 VCC GND OUTPUT TS/PD 3 1 56 R28 44.736MHZ 8B2> 12C1< BUSSEL\I LRDYIB TP40 TP41 TP38 TP37 TP39 1 1 1 1 1 INTB RSTB\I TL_CLK\I RL_CLK\I RX8K\I TX8K\I NCLK\I TICLK<2>\I 3.3 V P_2 P_4 P_6 P_8 2 4 6 8 3D10< 7G6< 11B1< EXTERNAL NETWORK CLOCK FOR SRTS TIMING 2 3 SW1 C 2 1 PBNO 3.3 V 1 2 10K 3 4 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 TCK TDI TDO TMS P_1 P_3 P_5 P_7 5 RN32 7 6 5 8 21 31 44 62 69 75 84 100 U18 MR SENSE HYST GND 4.7K C J9 HEADER 4X2 VCC CTL RESET RESET 8 7 6 5 SMB 1 4 0.01UF C35 R84 2 3 4 1 3.3 V 3.3 V 931 R85 1.0K R83 TEMUX XCLK Y3 3.3 V 0.01UF 0.01UF MAX700 CPLD DECOUPLING CAPS 0.01UF 0.01UF 0.01UF 0.01UF 3.3 V 4 2 0.01UF OSC_EP26 56 R31 3 1 OUTPUT TS/PD VCC GND C114 C116 C119 C117 C118 C115 37.056MHZ C26 B B OPTIONAL PARTS TL<7..0> TP16 TP8 TP2 TP4 TP13 TP20 TP47 TP51 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 BULK CAPACITORS 3.3 V 1 TP34 TP27 TP24 TP25 TP26 TP28 TP35 TP36 TP57 TP50 TP46 TP22 TP7 TP17 TP3 TP14 TP42 TP9 3.3 V VCC 1 1 1 TP21 TP55 2.5 V 1 1 HOLE_SIZE= 125MIL MOUNTING HOLE TP19 TP15 22UF + C169 22UF + C123 22UF + C128 22UF + C83 1 4.7K R29 1 4.7K 1 4.7K R22 1 4.7K R30 R23 HOLE_SIZE= 125MIL MOUNTING HOLE 22UF + C13 22UF + 22UF + C17 22UF + C175 22UF + C80 22UF + 22UF + C178 22UF + C120 C150 C18 1 1 HOLE_SIZE= 125MIL MOUNTING HOLE PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1991144 DOCUMENT ISSUE NUMBER: 3 ISSUE DATE: NOVEMBER 2000 A A TP43 TP44 TP5 TP6 HOLE_SIZE= 125MIL MOUNTING HOLE DRAWING TITLE=PCI_CPLD_BLOCK ABBREV=PCI_CPLD_BLOCK LAST_MODIFIED=Thu May 17 10:45:38 2001 10 9 8 7 6 5 4 3 TITLE: AAL1GATOR-32/TEMUX DEVELOPMENT KIT REVISION NUMBER: CPLD BLOCK 2.0 ENGINEER: BW 2 PAGE:13 1 OF 13 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 14 --------------- APPENDIX C: VHDL CODE FOR CPLD --------------------------------------------------------------Project : PMC-991144 File Name : AAL32.vhd Path : Designer : Revision History Issue Date 1 02/12/00 Initials BW Description Initial Release Function Implements the functionality of the AAL1gator-32/TEMUX Development kit CPLD. ------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; entity AAL32_CPLD is port ( LRESETB RSTB MAXRESET TRSTB TRSTB_JTAG NETCLKIN NCLK : OSC44M CLK2 : TICLK1 TICLK2 CSB0 : CSB1 : CSB2 : CSB3 : CSB_DUPLEX CSB_AAL32 CSB_CQ CSB_TEMUX RDB : RDB_DUPLEX RDB_AAL32 : in STD_LOGIC; : out STD_LOGIC; : in STD_LOGIC; : out STD_LOGIC; : in STD_LOGIC; : in STD_LOGIC; out STD_LOGIC; : in STD_LOGIC; in STD_LOGIC; : out STD_LOGIC; : out STD_LOGIC; in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; : out STD_LOGIC; : out STD_LOGIC; : out STD_LOGIC; : out STD_LOGIC; in STD_LOGIC; : out STD_LOGIC; : out STD_LOGIC; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT RDB_CQ : out STD_LOGIC; RDB_TEMUX : out STD_LOGIC; WRB : in STD_LOGIC; WRB_DUPLEX : out STD_LOGIC; WRB_AAL32 : out STD_LOGIC; WRB_CQ : out STD_LOGIC; WRB_TEMUX : out STD_LOGIC; LRDYIB : out STD_LOGIC; ACKB_AAL32 : in STD_LOGIC; INTB : out STD_LOGIC; INTB_DUPLEX : in STD_LOGIC; INTB_AAL32 : in STD_LOGIC; INTB_CQ : in STD_LOGIC; INTB_TEMUX : in STD_LOGIC; TEMUX_XCLK : out STD_LOGIC; OSC49M : in STD_LOGIC; OSC37M : in STD_LOGIC; DIPSW : in STD_LOGIC_VECTOR (3 downto 1); LED : out STD_LOGIC_VECTOR (3 downto 0); TX8K : out STD_LOGIC; RX8K : in STD_LOGIC; ICLK : out STD_LOGIC; CTCLK : out STD_LOGIC; RCLK : in STD_LOGIC; RSYNC : in STD_LOGIC; TL_CLK : out STD_LOGIC; RL_CLK : out STD_LOGIC ); end AAL32_CPLD; architecture AAL32_CPLD_arch of AAL32_CPLD is component divide_2 port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out : out STD_LOGIC ); end component; component divide_5592 port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out : out STD_LOGIC ); PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT end component; component Mux_2 port ( sel Din_A Din_B Dout ); end component; -- Mux: sel = '0' selects Din_A -sel = '1' selects Din_B : : : : in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; out STD_LOGIC component T_delay port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; sig_in : in STD_LOGIC; sig_out : out STD_LOGIC ); end component; signal DS3_8k signal TICLK signal reset begin RDB_DUPLEX <= RDB; RDB_AAL32 <= RDB; RDB_CQ <= RDB; RDB_TEMUX <= RDB; WRB_DUPLEX <= WRB; WRB_AAL32 <= WRB; WRB_CQ <= WRB; WRB_TEMUX <= WRB; -- Provide Read enable to DUPLEX -- Provide Read enable to AAL1gator-32 -- Provide Read enable to COMET-Quad -- Provide Read enable to TEMUX -- Provide -- Provide -- Provide Write -- Provide Write Strobe to DUPLEX Write Strobe to AAL1gator-32 Strobe to COMET-Quad Write Strobe to TEMUX : STD_LOGIC; : STD_LOGIC; : STD_LOGIC; CSB_DUPLEX <= CSB3; -- Provide Chip Select to DUPLEX CSB_AAL32 <= CSB0; -- Provide Chip Select to AAL1gator-32 CSB_CQ <= CSB2; -- Provide Chip Select to COMET-Quad CSB_TEMUX <= CSB1; -- Provide Chip Select to TEMUX LRDYIB <= ACKB_AAL32; LED(0) LED(1) LED(2) LED(3) <= <= <= <= -- Provide Chip Select to TEMUX ----Displays Displays Displays Displays a a a a AAL1gator-32 interrupt TEMUX interrupt COMET-Quad interrupt DUPLEX interrupt not(INTB_AAL32); not(INTB_TEMUX); not(INTB_CQ); not(INTB_DUPLEX); PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT ICLK <= RX8K; then AAL1gator-32 CTCLK <= RX8K; for reference TICLK1 <= TICLK; TICLK2 <= TICLK; TL_CLK <= TICLK; RL_CLK <= RCLK; -- 8k reference clk from DUPLEX to PLL and -- 8k reference clk from DUPLEX to COMET-Quad -- First TICLK for TEMUX input -- Second TICLK for TEMUX when LOS on LIU -- TL_CLK for AAL1gator-32 -- RL_CLK for AAL1gator-32 reset <= LRESETB AND MAXRESET; RSTB <= reset; TRSTB <= reset AND TRSTB_JTAG; INTB <= INTB_DUPLEX AND INTB_AAL32 AND INTB_CQ AND INTB_TEMUX; -- instantiate the network clock divider Network_Clk_Divider : divide_2 port map( clk_in => NETCLKIN, reset => reset, clk_out => NCLK ); -- instantiate the TEMUX XCLK mux TEMUX_XCLK_Mux : Mux_2 -- '0' selects Din_A port map( -- '1' selects Din_B sel => not(DIPSW(1)), -- This allows the selection of clocks Din_A => OSC37M, -- T1 Mode Din_B => OSC49M, -- E1 Mode Dout => TEMUX_XCLK ); -- instantiate the RCLK divider RClk_Divider : divide_5592 port map( clk_in => RCLK, reset => reset, clk_out => DS3_8k ); -- instantiate the TX8K_Mux PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT TX8K_Mux : Mux_2 -- '0' selects Din_A port map( -- '1' selects Din_B sel => not(DIPSW(2)), -- This allows the selection of clocks Din_A => DS3_8k, -- TEMUX Reference Din_B => RSYNC, -- COMET-Quad Reference Dout => TX8K ); -- instantiate the TICLK mux TICLK_Mux : Mux_2 -- '0' selects Din_A port map( -- '1' selects Din_B sel => not(DIPSW(3)), -- This allows the selection of clocks Din_A => OSC44M, -- From oscillator Din_B => CLK2, -- PLL Clock from DUPLEX RX8K Dout => TICLK ); end AAL32_CPLD_arch; ---------------- --------------------------------------------------------------Project : PMC-1991144 File Name : Mux_2.vhd Path : Designer : Revision History Issue Date 1 07/00 Initials BW Description Initial Release Function This is a Mux with one select line that will select between one input or a second input. ------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; entity mux_2 is port( sel Din_A Din_B Dout ); end mux_2; : : : : in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; out STD_LOGIC architecture mux_2_arch of mux_2 is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT begin Mux : process(sel, Din_A, Din_B) begin if sel = '0' then Dout <= Din_A; elsif sel = '1' then Dout <= Din_B; end if; end process; end mux_2_arch; -----------------------------------------------------------------------------Project : PMC-1991144 File Name : Clk_Divide2.vhd Path : Designer : Revision History Issue Date 1 07/00 Initials BW Description Initial Release Function This code implements a clock divider. It will divide the clock by 2. ------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; entity divide_2 is port( clk_in : in STD_LOGIC := '1'; reset : in STD_LOGIC := '1'; clk_out : out STD_LOGIC ); end divide_2; architecture divide_2_arch of divide_2 is constant divide_by : integer := 2; signal clk : STD_LOGIC := '1'; begin divide : process(clk_in, reset) -- this clock divides a clock by 2 variable count : integer := 0; begin if reset = '0' then count := 0; clk_out <= '0'; elsif (clk_in'event and clk_in = '1') then -- rising edge count := count + 1; if count = (divide_by / 2) then clk_out <= clk; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT clk <= not(clk); count := 0; end if; end if; end process; end divide_2_arch; -----------------------------------------------------------------------------Project : PMC-991144 File Name : Clk_Divide5592.vhd Path : Designer : Revision History Issue Date 1 07/00 Initials BW Description Initial Release Function This code implements a clock divider. It will divide the clock by 5592. ------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; entity divide_5592 is port( clk_in : in STD_LOGIC := '1'; reset : in STD_LOGIC := '1'; clk_out : out STD_LOGIC ); end divide_5592; architecture divide_5592_arch of divide_5592 is constant divide_by : integer := 5592; signal clk : STD_LOGIC := '1'; begin divide : process(clk_in, reset) 5592 variable count : integer := 0; begin if reset = '0' then count := 0; clk_out <= '0'; elsif (clk_in'event and clk_in = '1') then count := count + 1; if count = (divide_by / 2) then clk_out <= clk; clk <= not(clk); count := 0; -- this clock divides a clock by -- rising edge PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 47 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT end if; end if; end process; end divide_5592_arch; // UCF file -- locking pin names to locations #PINLOCK_BEGIN NET "rsync" NET "rclk" NET "dipsw<1>" NET "osc37m" NET "osc49m" NET "netclkin" NET "intb_aal32" NET "intb_temux" NET "intb_cq" NET "intb_duplex" NET "csb0" NET "csb2" NET "csb3" NET "csb1" NET "rx8k" NET "rdb" NET "maxreset" NET "lresetb" NET "trstb_jtag" LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = "S:PIN76"; "S:PIN78"; "S:PIN53"; "S:PIN35"; "S:PIN15"; "S:PIN37"; "S:PIN63"; "S:PIN68"; "S:PIN73"; "S:PIN58"; "S:PIN19"; "S:PIN17"; "S:PIN16"; "S:PIN18"; "S:PIN41"; "S:PIN6"; "S:PIN97"; "S:PIN96"; "S:PIN80"; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 48 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT NET "wrb" NET "dipsw<3>" NET "osc44m" NET "clk2" NET "dipsw<2>" NET "led<0>" NET "led<1>" NET "led<2>" NET "led<3>" NET "csb_aal32" NET "csb_cq" NET "csb_duplex" NET "csb_temux" NET "ctclk" NET "iclk" NET "intb" NET "nclk" NET "rdb_aal32" NET "rdb_cq" NET "rdb_duplex" NET "rdb_temux" NET "rstb" NET "temux_xclk" NET "ticlk1" NET "ticlk2" LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = "S:PIN7"; "S:PIN50"; "S:PIN22"; "S:PIN9"; "S:PIN52"; "S:PIN11"; "S:PIN12"; "S:PIN13"; "S:PIN14"; "S:PIN61"; "S:PIN72"; "S:PIN56"; "S:PIN67"; "S:PIN74"; "S:PIN10"; "S:PIN49"; "S:PIN39"; "S:PIN60"; "S:PIN71"; "S:PIN55"; "S:PIN66"; "S:PIN46"; "S:PIN95"; "S:PIN77"; "S:PIN36"; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 49 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT NET "wrb_aal32" NET "wrb_cq" NET "wrb_duplex" NET "wrb_temux" NET "trstb" NET "lrdyib" NET "ackb_aal32" NET "tx8k" NET "tl_clk" NET "rl_clk" LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = "S:PIN59"; "S:PIN70"; "S:PIN54"; "S:PIN65"; "S:PIN79"; "S:PIN4"; "S:PIN64"; "S:PIN40"; "S:PIN43"; "S:PIN42"; #PINLOCK_END PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 50 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT 15 APPENDIX D: LAYOUT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 51 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 52 PRELIMINARY REFERENCE DESIGN PMC-1991144 ISSUE 4 PM73122 AAL1GATOR-32 PM8315 TEMUX AAL1GATOR-32/TEMUX DEVELOPMENT KIT CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-1991144 (P4) Issue date: June 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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