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4-Bit Serial/Parallel Converter
HIGH-PER.ORMANCE PRODUCTS Description
The SK10/100E445 is an integrated 4-bit serial-toparallel data converter. The device is designed to operate for NRZ data rates of up to 2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1, etc. Two selectable serial inputs provide a loopback capability for testing purposes when the device is used in conjunction with the R446 parallel to serial converter. The start bit for conversion can be moved using the SYNC input. A single pulse applied asynchronously for at least two input clock cycles shifts the start bit for conversion from Qn to Qn-1. For each additional shift required, an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to "swallow" a clock pulse, effectively shifting a bit from the Qn to the Qn-1 output (see Timing Diagram B). The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH, the data on the output will change on every eighth clock cycle, thus allowing for an 8-bit conversion scheme using two E445's. When cascaded in an 8-bit conversion scheme, the devices will not operate at the 2.0 Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E445. For lower data rate applications, a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates above 500 MHz, differential input signals are recommended. For single-ended inputs, the VBB pin is tied to the inverting differential input and bypassed via a 0.01 F capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal. Upon power-up, the internal flip-flops will attain a random state. To synchronize multiple E445's in a system, the master reset must be asserted.
SK10/100E445
.eatures
* * * * * * * * * * * On-Chip Clock / 4 and /8 2.0 Gb/s Data Rate Capability Differential Clock and Serial Inputs VBB Output for Single-Ended Input Applications Asynchronous Data Synchronization Mode Select to Expand to 8-Bits Internal 75 k Input Pulldown Resistors ESD Protection of >4000V Extended 100E VEE Range of -4.2V to -5.46V Fully Compatible with MC10/100E445 Available in 28-Pin PLCC Package
.unctional Block Diagram
SINB SINB* SINA SINA* SEL D Q D Q Q2
D
Q
D
Q
Q3
D
Q
D
Q
Q1
D
Q
D
Q
Q0
SOUT SOUT* 0 1 MODE
Out
CL/4 CL/4*
CLK CLK*
In Out Latch EN
SYNC
D
Q
D
Q* RESET
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1
4
R Out
CL/8 CL/8*
2
R
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SK10/100E445
HIGH-PER.ORMANCE PRODUCTS PIN Description
Pinout
RESET MODE SYNC VCCO SINA* SINA NC
Pin Names
Pin
18 17 16 SOUT SOUT* VCC Q0 Q1 VCC0 Q2
25 SINB SINB* SEL VEE CLK CLK* VBB 26 27 28
24
23
22
21
20
19
.unction Differential Serial Data Input A Differential Serial Data Input B Serial Input Selector Pin Parallel Data Outputs Differential Clock Inputs Differential 4Clock Output Differential 8Clock Output Conversion Mode 4-Bit/8Bit Conversion Synchronizing Input
SinA, SINA* SINB, SINB* SEL Q0 - Q3 CLK, CLK* CL/4, CL/4* CL/8, CL/8* MODE SYNCH
28 Lead PLCC
1 (Top View) 2 3 4 5
CL/8*
15 14 13 12 6
CL/8
7
VCC0
8
CL/4
9
CL/4*
10
VCC0
11
Q3
Function Table
Mode L H Conversion 4-Bit 8-Bit SEL H L Serial Input A B
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SK10/100E445
HIGH-PER.ORMANCE PRODUCTS Application Information
The SK10/100E445 is an integrated 4-bit serial-toparallel data converter. The chip is designed to work with the E446 device to provide both transmission and receiving of a high speed serial data path. The E445 can convert up to a 2.0 GB/s NRZ data stream into 4-bit parallel data. The device also provides a divide by four clock output to be used to synchronize the parallel data with the rest of the system. The E445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 1 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. The SINA serial input of the E446 has an extra buffer delay and should be used as the loopback serial input.
SOUT SOUT* TO SERIAL MEDIUM
The clock frequency is significantly lower than that of a single converter. To increase this frequency, some games can be played with the clock input of the higher order E445. By delaying the clock feeding the second E445 relative to the clock of the first E445, the frequency of operation can be increased. The delay between the two clocks can be increased until the minimum delay of clock to serial out would potentially cause a serial bit to be swallowed (Figure 3).
CLOCK CLOCK*
E445a
E445b
SERIAL INPUT DATA
SIN SIN* Q3
SOUT SOUT* Q2 Q1 Q0
SIN SIN* Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
Q3
Q2 Q1 Q0
PARALLEL OUTPUT DATA
PARALLEL DATA
100 ps
PARALLEL DATA
SINA SINA* FROM SERIAL MEDIUM
CLOCK
Tpd CLK to SOUT
800 ps
1150 ps
Figure 1. Loopback Test Architecture Figure 2. Cascaded 1:8 Converter Architecture The E445 features a differential serial output and a divide by 8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. Figure 2 illustrates the architecture for a 1:8 demultiplexer using two E445's; the timing diagram for this configuration can be found in Figure 6. Notice the serial outputs (SOUT of the lower order converter feed the serial inputs of the higher order device. This feedthrough of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the datasheet, TPD CLK to SOUT = 1150 ps and tS for SIN = -100 ps, yields a minimum period of 1050 ps or a clock frequency of 950 MHz. With a minimum delay of 800 ps on this output, the clock for the lower order E445 cannot be delayed more than 800 ps relative to the clock of the first E445 without potentially missing a bit of information. Because the setup time on the serial input pin is negative, coincident excursions on the data and clock inputs of the E445 will result in correct operation.
CLOCK A
CLOCK B Tpd CLK to SOUT
800 ps
1150 ps
Figure 3. Cascade Frequency Limitation
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SK10/100E445
HIGH-PER.ORMANCE PRODUCTS Application Information (continued)
Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs on the E445. By connecting the clock for the second E445 to the complimentary clock input pin, the device will clock a half a clock period after the first E445 (Figure 5). Utilizing this simple technique will raise the potential conversion frequency up to 1.4 GHz. The divide by eight clock of the second E445 should be used to synchronize the parallel data to the rest of the system as the parallel data of the two E445's will no longer by synchronized. This skew problem between the outputs can be worked around as the parallel information will be static for eight more clock pulses.
CLOCK CLOCK* 100 ps
E445a E445b
CLOCK A
SERIAL INPUT DATA SIN SIN* SOUT SOUT* SIN SIN*
CLOCK B
Q3 Q2 Q1 Q0
Q3
Q2
Q1 Q0
Tpd CLK to SOUT
800 ps
1150 ps
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
PARALLEL OUTPUT DATA
Figure 7. Extended Frequency 1:8 Demultiplexer
CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3
Q0 Q1 Q2 Q3 Q4 (Q0 a) Q5 (Q1 a) Q6 (Q2 a) Q7 (Q3 a) SOUTa SOUTa Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn-4 Dn+1 Dn-3
Dn-4 Dn-3 Dn-2 Dn-41 Dn Dn+1 Dn+2 Dn+3 Dn+2 Dn-2 Dn+3 Dn1 Dn Dn+1
CL/4a CL/4b
CL/8a CL/8b
Figure 8. Timing Diagram A: 1:8 Serial to Parallel Conversion
Revision 1/.ebruary 21, 2001 4 www.semtech.com
SK10/100E445
HIGH-PER.ORMANCE PRODUCTS Package Information
Y BRK -N-
B 0.007 (0.180) U
M
T
L-M
M
S
N
S
0.007 (0.180) +
T
L-M
S
N
S
D
Z
PIN Descriptions
-L-
-M-
+ X G1 0.010 (0.250)
S
T L-M
S
N
S
W
D
V 28 1
H
0.007(0.180) M T L - M S N S
A Z R
0.007 (0.180) M T L - M 0.007 (0.180)
M
S S
NS NS
K1
T L-M
VIEW S
C
+ +
E G J G1 0.010 (0.250) S T L - M S N S VIEW S 0.004 (0.100) -T- SEATING PLANE
K F 0.007 (0.180) M T L - M
S
N
S
NOTES: 1. Datums -L-, -M-, and -N- determined where top of lead shoulder exits plastic body at mold parting line. 2. DIM G1, true position to be measured at Datum -T-, Seating Plane. 3. DIM R and U do not include mold flash. Allowable mold flash is 0.010 (0.250) per side. 4. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 5. Controlling Dimension: Inch. 6. The package top may be smaller than the package bottom by up to 0.012 (0.300). Dimensions R and U are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. Dimension H does not include Dambar protrusion or intrusion. The Dambar protrusion(s) shall not cause the H dimension to be greater than 0.037 (0.940). The Dambar intrusion(s) shall not cause the H dimension to be smaller than 0.025 (0.635).
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INCHES
DIM A B C E . G H J K R U V W X Y Z G1 K1 MIN 0.485 0.485 0.165 0.090 0.013 MAX 0.495 0.495 0.180 0.110 0.019
MILLIMETERS
MIN 12.32 12.32 4.20 2.29 0.33 MAX 12.57 12.57 4.57 2.79 0.48
0.050 BSC 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 -2o 0.410 0.040 0.032 --0.456 0.456 0.048 0.048 0.056 0.020 10o 0.430 --
1.27 BSC 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 -2o 10.42 1.02 0.81 --11.58 11.58 1.21 1.21 1.42 0.50 10o 10.92 --
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SK10/100E445
HIGH-PER.ORMANCE PRODUCTS DC Characteristics
SK10E445 DC Electrical Characteristics
(VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
TA = 0oC
Symbol IIN VOH VBB IEE Characteristic Input Current (Diff) (SE) Output High Current (SOUT Only) Output Reference Voltage Power Supply Current Min -150 Typ Max 150 150 -790 -1.27 154 185
TA = +25oC
Min -150 Typ Max 150 150 -760 -1.25 154 185 Min -150
TA = +85oC
Typ Max 150 150 -670 -1.19 154 185 Unit A A V V mA Note 1 Condition
-1020 -1.38
-980 -1.35
-910 -1.31
SK100E445 DC Electrical Characteristics
(VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
TA = 0oC
Symbol IIN VOH VBB IEE Characteristic Input Current (Diff) (SE) Output High Current (SOUT Only) Output Reference Voltage Power Supply Current Min -150 -1025 -1.38 154 Typ Max 150 150 -830 -1.26 185
TA = +25oC
Min -150 -1025 -1.38 154 Typ Max 150 150 -830 -1.26 185
TA = +85oC
Min -150 -1025 -1.38 177 Typ Max 150 150 -830 -1.26 211 Unit A A V V mA Note 1 Condition
Note 1: The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E and 100E VOH levels.
Revision 1/.ebruary 21, 2001
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SK10/100E445
HIGH-PER.ORMANCE PRODUCTS AC Characteristics
SK10/100E445 AC Electrical Characteristics
(VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
TA = 0oC
Symbol fmax Characteristic Maximum Conversion .requency Propagation Delay to Output CLK to Q CLK to SOUT CLK to CL/4 CLK to CL/8 Setup Time SINA, SINB SEL Hold Time SINA, SINB, SEL Reset Recover y Time Minimum Pulse Width CLK, MR Rise/.all Times SOUT CL/4. CL/8 Qn Min 2.0 1500 800 1100 1100 -100 0 450 500 400 130 200 370 225 425 490 270 520 700 1800 975 1325 1325 -250 -200 300 300 2100 1150 1500 1500 Typ Max
TA = +25oC
Min 2.0 1500 800 1100 1100 -100 0 450 500 400 130 200 370 225 425 490 270 520 700 1800 975 1325 1325 -250 -200 300 300 2100 1150 1500 1500 Typ Max Min 2.0 1500 800 1100 1100 -100 0 450 500 400 130 200 370
TA = +85oC
Typ Max Unit GB/s NRZ 1800 975 1325 1325 -250 -200 300 300 2100 1150 1500 1500 ps ps ps ps ps ps ps ps ps 225 425 490 270 520 700 ps ps ps Condition
tPLH tPHL
ts th tRR tPW
tr, tf
20% - 80%
Note: 1. For Standard ECL DC Specifications, refer to the ECL Logic Family Standard DC Specification Data Sheet. 2. For part ordering description, see HPP Part Ordering Information Data Sheet.
CLK SIN RESET Q0 Q1 Q2 Q3 SOUT Dn-4 Dn-4 Dn-3 Dn-2 Dn-1 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn Dn+1 Dn+2 Dn+3 Dn+2 Dn+3 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3
CL/4 CL/8
Timing Diagram A. 1:4 Serial to Parallel Conversion
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SK10/100E445
HIGH-PER.ORMANCE PRODUCTS AC Characteristics (continued)
CLK SIN RESET Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4
SYNC Q0 Q1 Q2 Q3 SOUT Dn-4 Dn-4 Dn-3 Dn-2 Dn-1 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+1 Dn+2 Dn+3 Dn+4 Dn+2 Dn+3 Dn+4
CL/4 CL/8
Timing Diagram B. 1:4 Serial to Parallel Conversion with SYNC Pulse
Ordering Information
Ordering Code SK10E445PJ SK10E445PJT SK100E445PJ SK100E445PJT Package ID 28-PLCC 28-PLCC 28-PLCC 28-PLCC Temperature Range Industrial Industrial Industrial Industrial
Contact Information
Division Headquarters 10021 Willow Creek Road San Diego, CA 92131 Phone: (858) 695-1808 FAX: (858) 695-2633
Semtech Corporation High-Performance Products Division
Marketing Group 1111 Comstock Street Santa Clara, CA 95054 Phone: (408) 566-8776 FAX: (408) 727-8994
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