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LH7A400
Preliminary Data Sheet
FEATURES
* ARM922TTM Core: - 32-bit ARM9TDMITM RISC Core - 16KB Cache: 8KB Instruction Cache and 8KB Data Cache - MMU (Windows CE Enabled) * High Performance (200 MHz) * 80KB On-Chip Memory * External Bus Interface - 100 MHz - Asynchronous SRAM/ROM/Flash - Synchronous DRAM/Flash - PCMCIA - CompactFlash * Clock and Power Management - 32.768 kHz and 14.7456 MHz Oscillators - Programmable PLL * Low Power Modes - Run (147 mA), Halt (41 mA), Standby (42 A) * Programmable LCD Controller - Up to 1,024 x 768 Resolution - Supports STN, Color STN, AD-TFT, HR-TFT, TFT - Up to 64,000 Colors and 15 Gray Shades * DMA (10 Channels) - AC97 - MMC - USB * USB Device Interface (USB 1.1) * Synchronous Serial Port (SSP) - Motorola SPITM - Texas Instruments SSI - National MICROWIRETM
32-Bit System-on-Chip
* Three Programmable Timers * Three UARTs - Classic IrDA (115 kbit/s) * Smart Card Interface (ISO7816) * DC-to-DC Converters * MultiMediaCardTM Interface * AC97 Codec Interface * Smart Battery Monitor Interface * Real Time Clock (RTC) * Up to 60 General Purpose I/Os * Programmable Interrupt Controller * Watchdog Timer * JTAG Debug Interface and Boundary Scan * Operating Voltage - 1.8 V Core - 3.3 V Input/Output (1.8 V I/O Optional1) * 5 V Tolerant Inputs (except oscillator pins2) * Operating Temperature - 0C to +70C Commercial - -40C to +85C Industrial (With Clock Frequency Reduction1) * 256-Ball PBGA or 256-Ball CABGA Package
DESCRIPTION
The LH7A400, powered by an ARM922T, is a complete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. This high degree of integration lowers overall system costs, reduces development cycle time and accelerates product introduction.
Motorola SPI is a trademark of Motorola, Inc. National Semiconductor MICROWIRE is a trademark of National Semiconductor Corporation. Windows CE is a trademark of Microsoft Corporation.
NOTES: 1. Under development. Results pending further characterization. 2. Oscillator pins R13, T13, P15, and P16 are 1.8 V 10%
Preliminary Data Sheet
12/8/03
1
LH7A400
32-Bit System-on-Chip
14.7456 MHz
32.768 kHz
OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL
REAL TIME CLOCK WATCHDOG TIMER
ARM922T INTERRUPT CONTROLLER STATIC (ASYNCHRONOUS) MEMORY CONTROLLER (SMC) EXTERNAL BUS INTERFACE PCMCIA/CF CONTROLLER SYNCHRONOUS DYNAMIC RAM CONTROLLER (SDMC) LCD AHB BUS 80KB SRAM
TIMER (3) GENERAL PURPOSE I/O (60) SYNCHRONOUS SERIAL PORT BATTERY MONITOR INTERFACE UART (3) IrDA INTERFACE USB DEVICE INTERFACE MULTIMEDIACARD INTERFACE ADVANCED AUDIO CODEC (AC97)
ADVANCED PERIPHERAL BUS BRIDGE
COLOR LCD CONTROLLER
DMA CONTROLLER
ADVANCED LCD INTERFACE
AUDIO CODEC INTERFACE SMART CARD INTERFACE (ISO7816) DC to DC INTERFACE (2)
ADVANCED HIGH-PERFORMANCE BUS (AHB)
ADVANCED PERPHERAL BUS (APB)
LH7A400-1
Figure 1. LH7A400 Block Diagram
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12/8/03
Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 1. Functional Pin List
PBGA CABGA PIN PIN G7 F1 K7 M1 M5 T6 R14 M14 J11 J12 F13 B14 E10 B8 H7 G3 K4 N5 P6 T14 R16 N16 K13 H9 C15 A11 E8 A5 F7 E1 J4 P3 T8 K9 L13 E15 D12 A7 H5 M3 L9 T10 N15 H12 B15 C9 G6 C10 F9 F11 F14 G8 H13 J9 K15 L7 N6 N8 N12 N13 P11 B8 C6 D5 D13 E8 F7 G13 H9 J14 K7 L8 L10 L12 M11 M14 C4 D7 D10 F4 F10 J4 J8 K8 L6 G7 H4 H8 L4 L9 N3 N7 N10 R5 SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE
VDD
I/O Ring Power
VSS
I/O Ring Ground
VDDC
Core Power
VSSC
Core Ground
Preliminary Data Sheet
12/8/03
3
LH7A400
32-Bit System-on-Chip
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN R11 N12 P12 T11 D3 H6 D4 E4 C2 R13 T13 P16 P15 P14 J6 K11 K10 P13 M12 P12 M10 R13 N11 E4 D1 E2 F2 D2 R14 R15 N14 M13 M12 J5 P14 P16 N15 N16 SIGNAL VDDA VSSA nPOR nURESET WAKEUP nPWRFL nEXTPWR XTALIN XTALOUT XTAL32IN XTAL32OUT CLKEN PGMCLK nCS0 nCS1 nCS2 nCS3/ nMMSPICS DESCRIPTION Analog Power for PLL Analog Ground for PLL Power On Reset User Reset; should be pulled HIGH for normal or JTAG operation. Wake Up Power Fail Signal External Power 14.7456 MHz Crystal Oscillator pins. An external clock source can be connected to XTALIN leaving XTALOUT open. 32.768 kHz Real Time Clock Crystal Oscillator pins. An external clock source can be connected to XTAL32IN leaving XTAL32OUT open. External Oscillator Clock Enable Output Programmable Clock (14.7456 MHz MAX.) Asynchronous Memory Chip Select 0 Asynchronous Memory Chip Select 1 Asynchronous Memory Chip Select 2 * Asynchronous Memory Chip Select 3 * MultiMediaCard SPI Mode Chip Select Input Input RESET STATE STANDBY STATE OUTPUT DRIVE
Input (Schmitt) Input Input (Schmitt) Input Input (Schmitt) Input Input (Schmitt) Input Input LOW Input Output LOW LOW HIGH HIGH HIGH HIGH: nCS3 Input LOW Input Output LOW LOW HIGH HIGH HIGH HIGH 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA
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12/8/03
Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN L12 M15 N13 L16 L15 L14 H11 K12 J15 J13 J10 H15 H13 G15 G11 G12 F15 F12 E14 D16 H10 D14 F10 A16 A14 B13 C13 E12 G10 B12 B11 D11 M16 N14 L11 L13 L14 K11 L16 K14 J15 J12 J10 H16 H14 H11 G16 G9 G14 G12 F15 E15 D16 F12 E13 D14 E12 B16 D12 A16 B13 B14 C12 A14 B12 A12 M15 M16 SIGNAL D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A0/nWE1 A1/nWE2 DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE
Data Bus
LOW
LOW
12 mA
* * * *
Asynchronous Address Bus Asynchronous Memory Write Byte Enable 1 Asynchronous Address Bus Asynchronous Memory Write Byte Enable 2
HIGH: nWE1 HIGH: nWE2
HIGH HIGH
12 mA 12 mA
Preliminary Data Sheet
12/8/03
5
LH7A400
32-Bit System-on-Chip
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN M13 K16 K15 K14 J8 J16 J14 J9 H16 H14 G16 G14 G13 F16 F14 E16 E13 F11 D15 C16 B16 A15 A13 G8 F8 A8 D8 C8 D10 B10 C10 G9 L15 K12 K13 K16 J13 J11 J16 H15 H10 H12 G15 G10 G11 F16 E16 F13 E14 D15 C16 C15 C14 B15 E11 D8 B7 A7 C8 F8 D9 E9 A10 A11 SIGNAL A2/SA0 A3/SA1 A4/SA2 A5/SA3 A6/SA4 A7/SA5 A8/SA6 A9/SA7 A10/SA8 A11/SA9 A12/SA10 A13/SA11 A14/SA12 A15/SA13 A16/SB0 A17/SB1 A18 A19 A20 A21 A22 A23 A24 A25/SCIO DESCRIPTION RESET STATE LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW STANDBY STATE LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW OUTPUT DRIVE 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA
* Asynchronous Address Bus * Synchronous Address Bus
* * * *
Asynchronous Address Bus Synchronous Device Bank Address 0 Asynchronous Address Bus Synchronous Device Bank Address 1
Asynchronous Address Bus
LOW
LOW
12 mA
* Asynchronous Memory Address Bus * Smart Card Interface I/O (Data) * Asynchronous Memory Address Bus A26/SCCLK * Smart Card Interface Clock * Asynchronous Memory Address Bus A27/SCRST * Smart Card Interface Reset nOE Asynchronous Memory Output Enable nWE0 Asynchronous Memory Write Byte Enable 0 nWE3 Asynchronous Memory Write Byte Enable 3 * Asynchronous Memory Chip Select 6 CS6/SCKE1_2 * Synchronous Memory Clock Enable 1 OR 2 * Asynchronous Memory Chip Select 7 CS7/SCKE0 * Synchronous Memory Clock Enable 0 SCKE3 Synchronous Memory Clock Enable 3
LOW: A25 LOW: A26 LOW: A27 HIGH HIGH HIGH LOW: CS6 LOW: CS7 LOW
LOW LOW LOW HIGH HIGH HIGH LOW LOW LOW
12 mA 12 mA 12 mA 12 mA 12 mA 8 mA 12 mA 12 mA 12 mA 20 mA (sink) 12 mA (source) 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA
A10
B10
SCLK
Synchronous Memory Clock
LOW
LOW
C14 D13 E11 A12 C12 C11
C13 A15 D11 E10 A13 B11
nSCS0 nSCS1 nSCS2 nSCS3 nSWE nCAS
Synchronous Memory Chip Select 0 Synchronous Memory Chip Select 1 Synchronous Memory Chip Select 2 Synchronous Memory Chip Select 3 Synchronous Memory Write Enable Synchronous Memory Column Address Strobe Signal
HIGH HIGH HIGH HIGH HIGH HIGH
HIGH HIGH HIGH HIGH HIGH HIGH
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN F9 A9 B9 D9 E9 J5 C11 C9 A9 B9 A8 K1 SIGNAL nRAS DQM0 DQM1 DQM2 DQM3 DESCRIPTION RESET STATE HIGH HIGH HIGH HIGH HIGH Input: PA0 STANDBY STATE HIGH HIGH HIGH HIGH HIGH No Change OUTPUT DRIVE 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA
K1 K2 K3 K5 L1 L2 L3 L4
K2 K3 K4 K6 K5 L1 L2 L3
Synchronous Memory Row Address Strobe Signal Synchronous Memory Data Mask 0 Synchronous Memory Data Mask 1 Synchronous Memory Data Mask 2 Synchronous Memory Data Mask 3 * GPIO Port A PA0/LCDVD16 * LCD Data bit 16. This CLCDC output signal is always LOW. * GPIO Port A PA1/LCDVD17 * LCD Data bit 17. This CLCDC output signal is always LOW. PA2 PA3 PA4 GPIO Port A PA5 PA6 PA7 * GPIO Port B PB0/UARTRX1 * UART1 Receive Data Input * GPIO Port B * UART3 Transmit Data Out * * * * * * * * GPIO Port B UART3 Receive Data In GPIO Port B UART3 Clear to Send GPIO Port B UART3 Data Carrier Detect GPIO Port B UART3 Data Set Ready
Input: PA1
No Change
8 mA
Input
No Change
8 mA
Input: PB0
No Change LOW if UART3 is Enabled, otherwise No Change No Change No Change No Change No Change Input if SMB is Enabled, otherwise No Change Input if SMB is Enabled, otherwise No Change No Change No Change No Change No Change No Change No Change
8 mA
L5
M1
PB1/UARTTX3
Input: PB1
8 mA
L7 M2 M4 N1
M2 M3 L5 N1
PB2/UARTRX3 PB3/ UARTCTS3 PB4/ UARTDCD3 PB5/ UARTDSR3 PB6/SWID/ SMBD
Input: PB2 Input: PB3 Input: PB4 Input: PB5
8 mA 8 mA 8 mA 8 mA
N2
N2
* GPIO Port B * Single Wire Data * Smart Battery Data * GPIO Port B * Smart Battery Clock * * * * * * * * * * * * GPIO Port C UART1 Transmit Data Output GPIO Port C HR-TFT Power Save GPIO Port C HR-TFT Power Sequence Control GPIO Port C HR-TFT Gray Scale Voltage Reverse GPIO Port C HR-TFT Reset Row Driver Counter GPIO Port C HR-TFT Row Driver Clock
Input: PB6
8 mA
N3
M4
PB7/SMBCLK
Input: PB7
8 mA
P1 P2 R1 K6 L8 T1
P1 P2 R1 M5 P3 N4
PC0/UARTTX1 PC1/LCDPS PC2/ LCDVDDEN PC3/LCDREV PC4/LCDSPS PC5/LCDCLS
LOW: PC0 LOW: PC1 LOW: PC2 LOW: PC3 LOW: PC4 LOW: PC5
12 mA 12 mA 12 mA 12 mA 12 mA 12 mA
Preliminary Data Sheet
12/8/03
7
LH7A400
32-Bit System-on-Chip
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN T2 R2 M11 L11 K8 N11 R9 T9 P10 R10 L10 N10 M9 M10 A6 B6 C6 H8 R2 N5 M9 K10 P10 T11 T12 R11 R12 T13 T9 K9 T10 R10 A5 B4 E7 B3 SIGNAL PC6/LCDHRLP PC7/LCDSPL PD0/LCDVD8 PD1/LCDVD9 PD2/LCDVD10 PD3/LCDVD11 PD4/LCDVD12 PD5/LCDVD13 PD6/LCDVD14 PD7/LCDVD15 PE0/LCDVD4 PE1/LCDVD5 PE2/LCDVD6 PE3/LCDVD7 PF0/INT0 PF1/INT1 PF2/INT2 PF3/INT3 * * * * DESCRIPTION GPIO Port C LCD Latch Pulse GPIO Port C LCD Start Pulse Left RESET STATE LOW: PC6 LOW: PC7 LOW: PD0 LOW: PD1 LOW: PD2 LOW: PD3 LOW: PD4 LOW: PD5 LOW: PD6 LOW: PD7 Input: PE0 Input: PE1 Input: PE2 Input: PE3 * GPIO Port F Input: PF0 * External FIQ Interrupt. Interrupts can be level or (Schmitt) edge triggered and are internally debounced. Input: PF1 * GPIO Port F (Schmitt) * External IRQ Interrupts. Interrupts can be level or edge triggered and are internally debounced. Input: PF2 (Schmitt) * GPIO Port F Input: PF3 * External IRQ Interrupt. Interrupts can be level or (Schmitt) edge triggered and are internally debounced. * GPIO Port F * External IRQ Interrupt. Interrupts can be level or Input: PF4 edge triggered and are internally debounced. (Schmitt) * Smart Card Supply Voltage Enable * GPIO Port F * External IRQ Interrupt. Interrupts can be level or Input: PF5 edge triggered and are internally debounced. (Schmitt) * Smart Card Detection * GPIO Port F * External IRQ Interrupt. Interrupts can be level or Input: PF6 edge triggered and are internally debounced. (Schmitt) * Ready for Card 1 for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port F * External IRQ Interrupt. Interrupts can be level or Input: PF7 edge triggered and are internally debounced. (Schmitt) * Ready for Card 2 for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port G * Output Enable for PC Card (PCMCIA or LOW: PG0 CompactFlash) in single or dual card mode * GPIO Port G * Write Enable for PC Card (PCMCIA or LOW: PG1 CompactFlash) in single or dual card mode STANDBY STATE No Change No Change OUTPUT DRIVE 12 mA 12 mA
* GPIO Port D * LCD Video Data Bus
LOW if Dual-Panel LCD is Enabled; otherwise, No Change
12 mA
* GPIO Port E * LCD Video Data Bus
LOW if 8-bit LCD is Enabled, otherwise No Change No Change No Change No Change No Change LOW if SCI is Enabled; otherwise, No Change No Change
12 mA
8 mA 8 mA 8 mA 8 mA
B5
C5
PF4/INT4/ SCVCCEN
8 mA
D6
D6
PF5/INT5/ SCDETECT
8 mA
E6
A4
PF6/INT6/ PCRDY1
No Change
8 mA
C5
A3
PF7/INT7/ PCRDY2
No Change
8 mA
R3
M6
PG0/nPCOE
No Change
8 mA
T3
T1
PG1/nPCWE
No Change
8 mA
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN L6 P4 SIGNAL DESCRIPTION * GPIO Port G * I/O Read Strobe for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port G * I/O Write Strobe for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port G * Register Memory Access for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port G * Card Enable 1 for PC Card (PCMCIA or CompactFlash) in single or dual card mode. This signal and nPCCE2 are used by the PC Card for decoding low and high byte accesses. * GPIO Port G * Card Enable 2 for PC Card (PCMCIA or CompactFlash) in single or dual card mode. This signal and nPCCE1 are used by the PC Card for decoding low and high byte accesses. * GPIO Port G * Direction for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port H * Reset Card 1 for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port H * Address Bit 8 for PC Card (CompactFlash) in single card mode * Reset Card 2 for PC Card (PCMCIA or CompactFlash) in dual card mode * GPIO Port H * Enable Card 1 for PC Card (PCMCIA or CompactFlash) in single or dual card mode. This signal is used for gating other control signals to the appropriate PC Card. * GPIO Port H * Address Bit 9 for PC Card (CompactFlash) in single card mode * Address Bit 25 for PC Card (PCMCIA) in single card mode * Enable Card 2 for PC Card (PCMCIA or CompactFlash) in dual card mode. This signal is used for gating other control signals to the appropriate PC Card. * GPIO Port H * WAIT Signal for Card 1 for PC Card (PCMCIA or CompactFlash) in single or dual card mode * GPIO Port H * Address Bit 10 for PC Card (CompactFlash) in single card mode * Address Bit 24 for PC Card (PCMCIA) in single card mode * WAIT Signal for Card 2 for PC Card (PCMCIA or CompactFlash) in dual card mode RESET STATE LOW: PG2 STANDBY STATE No Change OUTPUT DRIVE 8 mA
PG2/nPCIOR
M6
R3
PG3/nPCIOW
LOW: PG3
No Change
8 mA
N6
T2
PG4/nPCREG
LOW: PG4
No Change
8 mA
M7
P5
PG5/nPCCE1
LOW: PG5
No Change
8 mA
M8
R4
PG6/nPCCE2
LOW: PG6
No Change
8 mA
N4
T3
PG7/PCDIR PH0/ PCRESET1
LOW: PG7
No Change
8 mA
P4
P6
Input: PH0
No Change
8 mA
R4
T4
PH1/CFA8/ PCRESET2
Input: PH1
No Change
8 mA
T4
M7
PH2/ nPCSLOTE1
Input: PH2
No Change
8 mA
N7
T5
PH3/CFA9/ PCMCIAA25/ nPCSLOTE2
Input: PH3
No Change
8 mA
P8
R6
PH4/ nPCWAIT1
Input: PH4
No Change
8 mA
P5
R7
PH5/CFA10/ PCMCIAA24/ nPCWAIT2
Input: PH5
No Change
8 mA
Preliminary Data Sheet
12/8/03
9
LH7A400
32-Bit System-on-Chip
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN R5 T5 R6 R8 P9 N9 P7 R7 T7 N8 T15 T16 E7 D7 C7 P7 T6 T7 R9 P9 N9 M8 P8 R8 T8 T16 R16 C7 A6 B6 SIGNAL PH6/ AC97RESET PH7/nPCSTATRE LCDFP LCDLP LCDENAB/ LCDM LCDDCLK LCDVD0 LCDVD1 LCDVD2 LCDVD3 USBDP USBDN nPWME0 nPWME1 PWM0 * * * * DESCRIPTION GPIO Port H Audio Codec (AC97) Reset GPIO Port H Status Read Enable for PC Card (PCMCIA or CompactFlash) in single or dual card mode LCD Frame Synchronization pulse LCD Line Synchronization pulse * LCD TFT Data Enable * LCD STN AC Bias LCD Data Clock RESET STATE Input: PH6 Input: PH7 LOW LOW LOW: LCDENAB LOW STANDBY STATE No Change No Change LOW LOW LOW LOW OUTPUT DRIVE 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA
LCD Video Data Bus
LOW
LOW
12 mA
USB Data Positive (Differential Pair) USB Data Negative (Differential Pair) DC-DC Converter Pulse Width Modulator 0 Enable DC-DC Converter Pulse Width Modulator 1 Enable DC-DC Converter Pulse Width Modulator 0 Output during normal operation and Polarity Selection input at reset DC-DC Converter Pulse Width Modulator 1 Output during normal operation and Polarity Selection input at reset * Audio Codec (AC97) Clock * Audio Codec (ACI) Clock * Audio Codec (AC97) Output * Audio Codec (ACI) Output * Audio Codec (AC97) Synchronization * Audio Codec (ACI) Synchronization * Audio Codec (AC97) Input * Audio Codec (ACI) Input * MultiMediaCard Clock (20 MHz MAX.) * MultiMediaCard SPI Mode Clock * MultiMediaCard Command * MultiMediaCard SPI Mode Data Input * MultiMediaCard Data * MultiMediaCard SPI Mode Data Output UART2 Clear to Send Signal. This pin is an output for JTAG boundary scan only. UART2 Data Carrier Detect Signal. This pin is output for JTAG boundary scan only. UART2 Data Set Ready Signal IrDA Transmit IrDA Receive. This pin is an output for JTAG boundary scan only. UART2 Transmit Data Output
Input Input Input Input Input
Input Input Input Input Input
75 mA (NOM.) 75 mA (NOM.)
8 mA
B7 C4 D5 B4 A4 A3 B3 A2 E2 E3 E5 F2 F3 F4
B5 A2 A1 B2 E6 C3 B1 D4 E1 F3 G4 G5 G6 F1
PWM1 ACBITCLK ACOUT ACSYNC ACIN MMCCLK/ MMSPICLK MMCCMD/ MMSPIDIN MMCDATA/ MMSPIDOUT UARTCTS2 UARTDCD2 UARTDSR2 UARTIRTX1 UARTIRRX1 UARTTX2
Input Input LOW LOW Input LOW: MMCCLK Input: MMCCMD Input: MMCDATA Input Input Input LOW Input HIGH
Input Input LOW LOW Input LOW Input Input Input Input Input LOW Input HIGH
8 mA
8 mA 8 mA
8 mA 8 mA 8 mA
8 mA
8 mA
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 1. Functional Pin List (Cont'd)
PBGA CABGA PIN PIN J7 H4 J1 J2 J3 F6 F5 G1 G2 G4 G5 H1 H2 H3 C3 P11 R12 D1 D2 A1 B1 B2 C1 T12 R15 G3 J3 J6 J7 J2 G2 G1 H3 H5 H6 H7 H2 H1 J1 F5 T14 T15 E3 F6 E5 C2 D3 C1 P15 P13 SIGNAL UARTRX2 SSPCLK SSPRX SSPTX SSPFRM/ nSSPFRM COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 TBUZ MEDCHG WIDTH0 WIDTH1 BATOK nBATCHG TDI TCK TDO TMS nTEST0 nTEST1 DESCRIPTION UART2 Receive Data Input. This pin is an output for JTAG boundary scan only. Synchronous Serial Port Clock Synchronous Serial Port Receive Synchronous Serial Port Transmit Synchronous Serial Port Frame Sync RESET STATE Input LOW Input LOW Input: nSSPFRM STANDBY STATE Input LOW Input LOW Input 8 mA 8 mA 8 mA OUTPUT DRIVE
Keyboard Interface
HIGH
HIGH
8 mA
Timer Buzzer (254 kHz MAX.) LOW LOW Boot Device Media Change. Used with the WIDTH0 and WIDTH1 pins to specify boot mem- Input (Schmitt) Input ory device. External Memory Width Pins. Also, used with Input (Schmitt) Input MEDCHG to specify the boot memory device size. Battery OK Battery Change JTAG Data In. This signal is internally pulled-up to VDD. JTAG Clock. This signal should be externally pulled-up to VDD. JTAG Data Out. This signal should be externally pulled up to VDD with a 33 k resistor. JTAG Test Mode select. This signal is internally pulled-up to VDD. Test Pin 0. Internally pulled up to VDD. For Normal mode, leave open. For JTAG mode, tie to GND. See Table 2. Test Pin 1. internally pulled up to VDD. For Normal and JTAG mode, leave open. See Table 2. Input (Schmitt) Input (Schmitt) Input with Pull-up Input Input Input with Pull-up Input with Pull-up Input with Pull-up Input Input Input with Pull-up Input No Change Input with Pull-up Input with Pull-up Input with Pull-up
8 mA
4 mA
NOTES: *Signals beginning with `n' are Active LOW.
Table 2. nTest Pin Function
MODE JTAG Normal nTEST0 0 1 nTEST1 1 1 nURESET 1 x
Preliminary Data Sheet
12/8/03
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LH7A400
32-Bit System-on-Chip
Table 3. LCD Data Multiplexing
STN PBGA PIN CABGA PIN LCD DATA SIGNAL LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN7 MLSTN6 MLSTN5 MLSTN4 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 CLSTN7 CLSTN6 CLSTN5 CLSTN4 CLSTN3 CLSTN2 CLSTN1 CLSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 Intensity BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 RED0 MONO 4-BIT SINGLE PANEL DUAL PANEL MONO 8-BIT SINGLE PANEL DUAL PANEL COLOR SINGLE PANEL DUAL PANEL TFT AD-TFT/ HR-TFT
K1 J5 R10 P10 T9 R9 N11 K8 L11 M11 M10 M9 N10 L10 N8 T7 R7 P7
K2 K1 T13 R12 R11 T12 T11 P10 K10 M9 R10 T10 K9 T9 T8 R8 P8 M8
LOW LOW Intensity BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 RED0
NOTES: 1. The Intensity bit is identically generated for all three colors. 2. MU = Monochrome Upper 3. CU = Color Upper 4. CL = Color Lower
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 4. 256-Ball PBGA Package Numerical Pin List
BGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 TDI MMCDATA/MMSPIDOUT MMCCLK/MMSPICLK ACIN VSS PF0/INT0 VDDC A27/SCRST DQM0 SCLK VSS nSCS3 A24 D24 A23 D23 TCK TDO MMCCMD/MMSPIDIN ACSYNC PF4/INT4/SCVCCEN PF1/INT1 PWM1 VDD DQM1 CS6/SCKE1_2 D30 D29 D25 VDD VSSC A22 TMS nEXTPWR MEDCHG ACBITCLK PF7/INT7/PCRDY2 PF2/INT2 PWM0 nWE0 VSSC CS7/SCKE0 nCAS nSWE D26 LOW: CS7 HIGH HIGH LOW LOW HIGH HIGH LOW LOW Input with Pull-up Input Input Input Input: PF7 PF2/INT2 Input HIGH LOW Input with Pull-up Input Input Input No Change No Change Input HIGH HIGH LOW: CS6 LOW LOW LOW LOW LOW LOW LOW LOW HIGH LOW LOW LOW LOW Input Input Input: MMSPIDIN LOW Input: PF4 Input: PF1 Input HIGH LOW LOW LOW LOW Input No Change LOW LOW LOW if SCI is Enabled; otherwise, No Change No Change Input LOW: A27 HIGH LOW LOW LOW LOW Input: PF0 No Change SIGNAL RESET STATE Input with Pull-up LOW: MMSPICLK Input Input: MMSPIDOUT LOW LOW Input STANDBY STATE Input with Pull-up
Preliminary Data Sheet
12/8/03
13
LH7A400
32-Bit System-on-Chip
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont'd)
BGA PIN C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 nSCS0 VSS A21 BATOK nBATCHG nPOR WAKEUP ACOUT PF5/INT5/SCDETECT nPWME1 nOE DQM2 nWE3 D31 VDDC nSCS1 D21 A20 D19 VDDC UARTCTS2 UARTDCD2 nPWRFL UARTDSR2 PF6/INT6/PCRDY1 nPWME0 VSS DQM3 VDD nSCS2 D27 A18 D18 VDDC A17/SB1 VDD UARTIRTX1 UARTIRRX1 UARTTX2 COL1 COL0 VSS A26/SCCLK nRAS D22 LOW: A26 HIGH LOW LOW HIGH LOW LOW Input HIGH HIGH HIGH LOW Input HIGH HIGH HIGH LOW: SBANK1 LOW HIGH LOW LOW LOW HIGH LOW LOW LOW HIGH LOW Input Input Input Input Input: PF6 Input Input Input Input Input No Change Input HIGH LOW LOW LOW HIGH LOW LOW LOW LOW Input Input Input Input LOW Input: PF5 Input HIGH HIGH HIGH LOW LOW Input Input Input Input LOW No Change Input HIGH LOW HIGH LOW SIGNAL RESET STATE HIGH HIGH STANDBY STATE
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12/8/03
Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont'd)
BGA PIN F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 A19 D17 VDD A16/SB0 D16 A15/SA13 COL2 COL3 VSS COL4 COL5 VSSC VDD A25/SCIO SCKE3 D28 D14 D15 A14/SA12 A13/SA11 D13 A12/SA10 COL6 COL7 TBUZ SSPCLK VSSC nURESET VSS PF3/INT3 VSS D20 D6 VSSC D12 A11/SA9 D11 A10/SA8 SSPRX SSPTX SSPFRM/nSSPFRM VDDC PA0/LCDVD16 PGMCLK UARTRX2 Input: PA0 LOW Input No Change LOW Input LOW LOW: SA9 LOW LOW: SA8 Input LOW Input: nSSPFRM LOW LOW LOW LOW Input LOW Input LOW LOW LOW LOW Input: PF3 No Change Input Input LOW: A25 LOW LOW LOW LOW LOW: SA12 LOW: SA11 LOW LOW: SA10 HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH LOW: SBANK0 LOW LOW: SA13 HIGH HIGH LOW LOW LOW HIGH HIGH SIGNAL RESET STATE LOW LOW LOW LOW STANDBY STATE
Preliminary Data Sheet
12/8/03
15
LH7A400
32-Bit System-on-Chip
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont'd)
BGA PIN J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 A6/SA4 A9/SA7 D10 VDD VDD D9 A8/SA6 D8 A7/SA5 PA1/LCDVD17 PA2 PA3 VSS PA4 PC3/LCDREV VDD PD2/LCDVD10 VDDC nCS1 nCS0 D7 VSS A5/SA3 A4/SA2 A3/SA1 PA5 PA6 PA7 PB0/UARTRX1 PB1/UARTTX3 PG2/nPCIOR PB2/UARTRX3 PC4/LCDSPS VSSC PE0/LCDVD4 PD1/LCDVD9 D0 VDDC D5 D4 D3 VDD PB3/UARTCTS3 VSSC Input: PB3 No Change LOW LOW LOW LOW LOW LOW Input: PE0 LOW: PD1 LOW LOW if 8-bit LCD is Enabled, otherwise No Change LOW if Dual-Panel LCD is Enabled; otherwise, No Change LOW LOW: SA3 LOW: SA2 LOW: SA1 Input Input Input Input: PB0 Input: PB1 LOW: PG2 Input: PB2 LOW: PC4 LOW LOW LOW No Change No Change No Change No Change LOW if UART3 is Enabled, otherwise No Change No Change No Change No Change HIGH HIGH LOW HIGH HIGH LOW LOW: PD2 LOW if Dual-Panel LCD is Enabled; otherwise, No Change Input LOW: PC3 No Change No Change LOW LOW: SA6 LOW LOW: SA5 Input: PA1 Input Input LOW LOW LOW LOW No Change No Change No Change SIGNAL RESET STATE LOW: SA4 LOW: SA7 LOW LOW LOW LOW STANDBY STATE
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont'd)
BGA PIN M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 VDD PG3/nPCIOW PG5/nPCCE1 PG6/nPCCE2 PE2/LCDVD6 PE3/LCDVD7 PD0/LCDVD8 nCS3/nMMSPICS A2/SA0 VDD D1 A0/nWE1 PB5/UARTDSR3 PB6/SWID/SMBD PB7/SMBCLK PG7/PCDIR VSS PG4/nPCREG LCDVD3 LCDDCLK PE1/LCDVD5 PD3/LCDVD11 VDDA D2 A1/nWE2 VSSC VSS PC0/UARTTX1 PC1/LCDPS VDDC PH0/PCRESET1 PH5/CFA10/PCMCIAA24/nPCWAIT2 VSS LCDVD0 PH4/nPCWAIT1 LCDENAB/LCDM PD6/LCDVD14 WIDTH0 VSSA nCS2 CLKEN HIGH LOW HIGH LOW LOW Input: PH4 LOW: LCDENAB LOW: PD6 Input LOW No Change LOW LOW if Dual-Panel LCD is Enabled; otherwise, No Change Input Input: PH0 Input: PH5 No Change No Change LOW: PC0 LOW: PC1 No Change No Change LOW HIGH: nWE2 LOW HIGH LOW: PG4 LOW LOW Input: PE1 LOW: PD3 No Change No Change LOW LOW LOW if 8-bit LCD is Enabled; otherwise No Change LOW if Dual-Panel LCD is Enabled; otherwise, No Change PH3/CFA9/PCMCIAA25/nPCSLOTE2 Input: PH3 LOW HIGH: nWE1 Input: PB5 Input: PB6 Input: PB7 LOW: PG7 LOW HIGH No Change Input if SMB is Enabled; otherwise No Change Input if SMB is Enabled; otherwise No Change No Change LOW: PG3 LOW: PG5 LOW: PG6 Input: PE2 Input: PE3 LOW: PD0 HIGH: nCS3 LOW: SA0 No Change No Change No Change LOW if 8-bit LCD is Enabled; otherwise No Change LOW if 8-bit LCD is Enabled; otherwise No Change LOW if Dual-Panel LCD is Enabled; otherwise, No Change HIGH LOW SIGNAL PB4/UARTDCD3 RESET STATE Input: PB4 No Change STANDBY STATE
Preliminary Data Sheet
12/8/03
17
LH7A400
32-Bit System-on-Chip
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont'd)
BGA PIN P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 XTAL32OUT XTAL32IN PC2/LCDVDDEN PC7/LCDSPL PG0/nPCOE PH1/CFA8/PCRESET2 PH6/nAC97RESET LCDFP LCDVD1 LCDLP PD4/LCDVD12 PD7/LCDVD15 VDDA WIDTH1 XTALIN VDD nTEST1 VSS PC5/LCDCLS PC6/LCDHRLP PG1/nPCWE PH2/nPCSLOTE1 PH7/nPCSTATRE VDD LCDVD2 VDDC PD5/LCDVD13 VSSC VSSA nTEST0 XTALOUT VSS USBDP USBDN HIGH LOW HIGH LOW Input with Pull-up LOW Input with Pull-up LOW LOW: PD5 LOW if Dual-Panel LCD is Enabled; otherwise, No Change LOW LOW LOW: PC5 LOW: PC6 LOW: PG1 Input: PH2 Input: PH7 No Change No Change No Change No Change No Change Input with Pull-up Input with Pull-up Input Input Input Input SIGNAL RESET STATE Output Input LOW: PC2 LOW: PC7 LOW: PG0 Input: PH1 Input: PH6 LOW LOW LOW LOW: PD4 LOW: PD7 Output Input No Change No Change No Change No Change No Change LOW LOW LOW LOW if Dual-Panel LCD is Enabled; otherwise, No Change LOW if Dual-Panel LCD is Enabled; otherwise, No Change STANDBY STATE
NOTE: `No Change' means the pin remains as it was programmed prior to entering the Standby state.
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 5. 256-Ball CABGA Package Numerical Pin List
CABGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 ACOUT ACBITCLK PF7/INT7/PCRDY2 PF6/INT6/PCRDY1 PF0/INT0 nPWME1 A27/SCRST DQM3 DQM1 CS7/SCKE0 SCKE3 D31 nSWE D29 nSCS1 D25 MMCCMD/MMSPIDIN ACSYNC PF3/INT3 PF1/INT1 PWM1 PWM0 A26/SCCLK VSS DQM2 SCLK nCAS D30 D26 D27 A23 D23 TMS TCK MMCCLK/MMSPICLK VDDC PF4/INT4/SCVCCEN VSS nPWME0 nOE DQM0 VDD nRAS HIGH HIGH Input HIGH HIGH Input HIGH HIGH Input: PF4 (Schmitt) LOW if SCI is Enabled; otherwise, No Change HIGH LOW HIGH LOW LOW LOW LOW LOW Input with Pull-up Input LOW: MMCCLK HIGH LOW HIGH LOW LOW LOW LOW LOW Input with Pull-up Input LOW SIGNAL RESET STATE LOW Input LOW Input STANDBY STATE
Input: PF7 (Schmitt) No Change Input: PF6 (Schmitt) No Change Input: PF0 (Schmitt) No Change Input LOW: A27 HIGH HIGH LOW: CS7 LOW LOW HIGH LOW HIGH LOW Input: MMCCMD LOW Input LOW HIGH HIGH LOW LOW LOW HIGH LOW HIGH LOW Input LOW
Input: PF3 (Schmitt) No Change Input: PF1 (Schmitt) No Change Input Input LOW: A26 Input Input LOW
Preliminary Data Sheet
12/8/03
19
LH7A400
32-Bit System-on-Chip
Table 5. 256-Ball CABGA Package Numerical Pin List
CABGA PIN C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 D28 nSCS0 A22 A21 A20 nURESET nEXTPWR TDO MMCDATA/MMSPIDOUT VSS PF5/INT5/SCDETECT VDDC A25/SCIO nWE3 VDDC nSCS2 D24 VSS D21 A19 D18 UARTCTS2 WAKEUP BATOK nPOR TDI ACIN PF2/INT2 VSS CS6/SCKE1_2 nSCS3 A24 D22 D20 A18 D17 A16/SB0 UARTTX2 nPWRFL UARTDCD2 VDDC MEDCHG nBATCHG Input (Schmitt) Input (Schmitt) Input Input LOW: CS6 HIGH LOW LOW LOW LOW LOW LOW HIGH Input (Schmitt) Input LOW HIGH LOW LOW LOW LOW LOW LOW HIGH Input Input LOW LOW LOW Input Input (Schmitt) Input (Schmitt) Input Input with Pull-up Input LOW LOW LOW Input Input Input Input Input with Pull-up Input HIGH LOW HIGH LOW LOW: A25 HIGH LOW HIGH Input: PF5 (Schmitt) No Change SIGNAL RESET STATE LOW HIGH LOW LOW LOW Input (Schmitt) Input (Schmitt) Input Input: MMCDATA LOW HIGH LOW LOW LOW Input Input No Change Input STANDBY STATE
Input: PF2 (Schmitt) No Change
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 5. 256-Ball CABGA Package Numerical Pin List
CABGA PIN F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 E5 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 VSS nWE0 VDD VDDC VDD D19 A17/SB1 VDD D16 A15/SA13 COL1 COL0 UARTRX2 UARTDSR2 UARTIRTX1 UARTIRRX1 VSSC VDD D13 A13/SA11 A14/SA12 D15 VSS D14 A12/SA10 D12 COL7 COL6 COL2 VSSC COL3 COL4 COL5 VSSC VSS A10/SA8 D11 A11/SA9 VDD D10 A9/SA7 D9 TBUZ LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW LOW HIGH HIGH HIGH LOW LOW LOW HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH Input Input LOW Input LOW LOW HIGH HIGH Input Input LOW Input LOW LOW LOW LOW HIGH HIGH SIGNAL RESET STATE STANDBY STATE
Preliminary Data Sheet
12/8/03
21
LH7A400
32-Bit System-on-Chip
Table 5. 256-Ball CABGA Package Numerical Pin List
CABGA PIN J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 SIGNAL SSPFRM/nSSPFRM SSPCLK VDDC PGMCLK SSPRX SSPTX VDDC VDD D8 A7/SA5 D7 A6/SA4 VSS D6 A8/SA6 PA0/LCDVD16 PA1/LCDVD17 PA2 PA3 PA5 PA4 VSS VDDC PE1/LCDVD5 PD1/LCDVD9 D3 A3/SA1 A4/SA2 D5 VDD A5/SA3 PA6 PA7 PB0/UARTRX1 VSSC PB4/UARTDCD3 VDDC VDD VSS VSSC VSS D0 VSS LOW LOW Input: PB4 No Change LOW Input Input Input: PB0 LOW No Change No Change No Change Input: PE1 LOW: PD1 LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW Input: PA0 Input: PA1 Input Input Input Input LOW LOW No Change No Change No Change No Change No Change No Change LOW LOW LOW LOW LOW LOW LOW LOW LOW Input LOW LOW Input LOW RESET STATE Input: nSSPFRM LOW Input LOW STANDBY STATE
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Table 5. 256-Ball CABGA Package Numerical Pin List
CABGA PIN L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 D1 D2 A2/SA0 D4 PB1/UARTTX3 PB2/UARTRX3 PB3/UARTCTS3 PB7/SMBCLK PC3/LCDREV PG0/nPCOE PH2/nPCSLOTE1 LCDVD0 PD0/LCDVD8 VDDA VSS CLKEN XTAL32OUT VSS A0/nWE1 A1/nWE2 PB5/UARTDSR3 PB6/SWID/SMBD VSSC PC5/LCDCLS PC7/LCDSPL VDD VSSC VDD LCDDCLK VSSC VSSA VDD VDD XTAL32IN nCS2 nCS3/nMMSPICS PC0/UARTTX1 PC1/LCDPS PC4/LCDSPS PG2/nPCIOR PG5/nPCCE1 PH0/PCRESET1 Input HIGH HIGH: nCS3 LOW: PC0 LOW: PC1 LOW: PC4 LOW: PG2 LOW: PG5 Input: PH0 Input HIGH HIGH No Change No Change No Change No Change No Change No Change LOW LOW LOW: PC5 LOW: PC7 No Change No Change HIGH: nWE1 HIGH: nWE2 Input: PB5 Input: PB6 HIGH HIGH No Change Input if SMB is Enabled, otherwise No Change LOW Output LOW Output SIGNAL RESET STATE LOW LOW LOW LOW Input: PB1 Input: PB2 Input: PB3 Input: PB7 LOW: PC3 LOW: PG0 Input: PH2 LOW LOW: PD0 LOW LOW LOW LOW LOW if UART3 is Enabled, otherwise No Change No Change No Change Input if SMB is Enabled, otherwise No Change No Change No Change No Change LOW LOW if Dual-Panel LCD is Enabled; otherwise, No Change STANDBY STATE
Preliminary Data Sheet
12/8/03
23
LH7A400
32-Bit System-on-Chip
Table 5. 256-Ball CABGA Package Numerical Pin List
CABGA PIN P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 SIGNAL PH6/AC97RESET LCDVD1 LCDENAB/LCDM PD2/LCDVD10 VDD VDDA nTEST1 nCS0 nTEST0 nCS1 PC2/LCDVDDEN PC6/LCDHRLP PG3/nPCIOW PG6/nPCCE2 VSSC PH4/nPCWAIT1 PH5/CFA10/PCMCIAA24/nPCWAIT2 LCDVD2 LCDLP PE3/LCDVD7 PD5/LCDVD13 PD6/LCDVD14 VSSA XTALIN XTALOUT USBDN PG1/nPCWE PG4/nPCREG PG7/PCDIR PH1/CFA8/PCRESET2 PH7/nPCSTATRE LCDFP LCDVD3 PE0/LCDVD4 PE2/LCDVD6 PD3/LCDVD11 PD4/LCDVD12 PD7/LCDVD15 WIDTH0 WIDTH1 USBDP Input LOW Input LOW: PG1 LOW: PG4 LOW: PG7 Input: PH1 Input: PH7 LOW LOW Input: PE0 Input: PE2 LOW: PD3 LOW: PD4 LOW: PD7 Input (Schmitt) Input (Schmitt) Input Input LOW Input No Change No Change No Change No Change No Change No Change LOW LOW LOW if 8-bit LCD is Enabled, otherwise No Change No Change No Change No Change No Change Input Input Input Input: PH4 Input: PH5 LOW LOW Input: PE3 LOW: PD5 LOW: PD6 No Change No Change LOW LOW No Change No Change No Change Input with Pull-up HIGH Input with Pull-up HIGH LOW: PC2 LOW: PC6 LOW: PG3 LOW: PG6 Input with Pull-up HIGH Input with Pull-up HIGH No Change No Change No Change No Change RESET STATE Input: PH6 LOW LOW: LCDENAB LOW: PD2 No Change LOW LOW No Change No Change STANDBY STATE
PH3/CFA9/PCMCIAA25/nPCSLOTE2 Input: PH3
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12/8/03
Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
TOUCH SCREEN CONTR. ROM FLASH
1 4 7 2 5 8 0 3 6 9 #
*
SMART CARD STN/TFT/ AD-TFT SSP UART SCI MULTIMEDIA CARD
SRAM GPIO
MMC SDRAM
LH7A400
COMPACT FLASH
DMA CODEC AC97
PC CARD
PCMCIA UART USB IR BMI DC to DC VOLTAGE GENERATION CIRCUITRY
BATTERY
LH7A400-3
Figure 2. Application Diagram
SYSTEM DESCRIPTIONS ARM922T Processor
The LH7A400 microcontroller features the ARM922T cached core with an Advanced High Performance Bus (AHB) interface. The processor is a member of the ARM9T family of processors. For more information, see the ARM document, `ARM922T Technical Reference Manual', available on ARM's website at www.arm.com.
The 32.768 kHz clock provides the source for the Real Time Clock tree and power-down logic.This clock is used for the power state control in the design and is the only clock in the LH7A400 that runs permanently. The 32.768 kHz clock is divided down to 1 Hz using a ripple divider to save power. This generated 1 Hz clock is used in the Real Time Clock counter. The 14.7456 MHz source is used to generate the main system clocks for the LH7A400. It is the source for PLL1 and PLL2, it acts as the primary clock to the peripherals and is the source clock to the Programmable clock (PGM) divider. PLL1 provides the main clock tree for the chip, it generates the following clocks: FCLK, HCLK and PCLK. FCLK is the clock that drives the ARM922T core. HCLK is the main bus (AHB) clock, as such it clocks all memory interfaces, bus arbitrators and the AHB peripherals. HCLK is generated by dividing FCLK by 1, 2, 3, or 4. HCLK can be gated by the system to enable low power operation. PCLK is the peripheral bus (APB) clock. It is generated by dividing HCLK by either 2, 4, or 8. PLL2 is used to generate a fixed frequency of 48 MHz for the USB peripheral.
Clock and State Controller
The clocking scheme in the LH7A400 is based around two primary oscillator inputs. These are the 14.7456 MHz input crystal and the 32.768 kHz real time clock oscillator. See Figure 3. The 14.7456 MHz oscillator is used to generate the main system clock domains for the LH7A400, where as the 32.768 kHz is used for controlling the power down operations and real time clock peripheral. The clock and state controller provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and to the rest of the system. The amount of clock gating that actually takes place is dependent on the current power saving mode selected.
Preliminary Data Sheet
12/8/03
25
LH7A400
32-Bit System-on-Chip
14.7456 MHz MAIN OSC.
32.768 kHz RTC OSC.
FCLK STATE CONTROLLER HCLK (TO PROCESSOR CORE)
DIVIDE REGISTER
HCLK /2, /4, /8 PCLKs
LH7A400-4
Figure 3. Clock and State Controller Block Diagram
Power Modes
The LH7A400 has three operational states: Run, Halt, and Standby. In Run mode, all clocks are hardware-enabled and the processor is clocked. Halt mode stops the processor clock while waiting for an event such as a key press, but the device continues to function. Finally, Standby equates to the computer being switched `off', i.e. no display (LCD disabled) and the main oscillator is shut down. The 32.768 kHz oscillator operates in all three modes.
Data Paths
The data paths in the LH7A400 are: * The AMBA AHB bus * The AMBA APB bus * The External Bus Interface * The LCD AHB bus * The DMA busses. AMBA AHB BUS The Advanced Microprocessor Bus Architecture Advanced High-performance Bus (AMBA AHB) bus is a high speed 32-bit-wide data bus. The AMBA AHB is for high-performance, high clock frequency system modules. Peripherals that have high bandwidth requirements are connected to the LH7A400 core processor using the AHB bus. These include the external and internal memory interfaces, the LCD registers, palette RAM and the bridge to the Advanced Peripheral Bus (APB) interface. The APB Bridge transparently converts the AHB access into the slower speed APB accesses. All of the control registers for the APB peripherals are programmed using the AHB - APB bridge interface. The main AHB data and address lines are configured using a multiplexed bus. This removes the need for tri-state buffers and bus holders, and simplifies bus arbitration.
Reset Modes
There are three external signals that can generate resets to the LH7A400; these are nPOR (power on reset), nPWRFL (power failure) and nURESET (user reset). If any of these are active, a system reset is generated internally. A nPOR reset performs a full system reset. The nPWRFL and nURESET resets will perform a full system reset except for the SDRAM refresh control, SDRAM Global Configuration, SDRAM Device Configuration and the RTC peripheral registers. The SDRAM controller will issue a self-refresh command to external SDRAM before the system enters this reset (the nPWRFL and nURESET resets only, not so for the nPOR reset). This allows the system to maintain its Real Time Clock and SDRAM contents. On coming out of reset, the chip enters Standby mode. Once in Run mode the PWRSR register can be interrogated to determine the nature of the reset, and the trigger source, after which software can then take appropriate actions.
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
AMBA APB BUS The AMBA APB bus is a lower-speed 32-bit-wide peripheral data bus. The speed of this bus is selectable to be a divide-by-2, divide-by-4 or divide-by-8 of the speed of the AHB bus. EXTERNAL BUS INTERFACE The External Bus Interface (EBI) provides a 32-bit wide, high speed gateway to external memory devices. The memory devices supported include: * Asynchronous RAM/ROM/Flash * Synchronous DRAM/Flash * PCMCIA interfaces * CompactFlash interfaces. The EBI can be controlled by either the Asynchronous memory controller or Synchronous memory controller. There is an arbiter on the EBI input, with priority given to the Synchronous Memory Controller interface. LCD AHB BUS The LCD controller has its own local memory bus that connects it to the system's embedded memory and external SDRAM. The function of this local data bus is to allow the LCD controller to perform its video refresh function without congesting the AHB bus. This leads to better system performance and lower power consumption. There is an arbiter on both the embedded memory and the synchronous memory controller. In both cases the LCD bus is given priority. DMA BUSES The LH7A400 has a DMA system that connects the higher speed/higher data volume APB peripherals (MMC, USB and AC97) to the AHB bus. This enables the efficient transfer of data between these peripherals and external memory without the intervention of the ARM922T core. The DMA engine does not support memory to memory transfers.
The LH7A400 can boot from either synchronous or asynchronous ROM/Flash. The selection is determined by the value of the MEDCHG pin at Power On Reset as shown in Table 6. When booting from synchronous memory, then synchronous bank 4 (nSCS3) is mapped into memory location zero. When booting from asynchronous memory, asynchronous memory bank 0 (nSCS0) is mapped into memory location zero. Figure 4 shows the memory map of the LH7A400 system for the two boot modes. Once the LH7A400 has booted, the boot code can configure the ARM922T MMU to remap the low memory space to a location in RAM. This allows the user to set the interrupt vector table. Table 6. Boot Modes
BOOT MODE 8-bit ROM 16-bit ROM 32-bit ROM 32-bit ROM 16-bit SFlash (Initializes Mode Register) 16-bit SROM (Initializes Mode Register) 32-bit SFlash (Initializes Mode Register) 32-bit SROM (Initializes Mode Register) LATCHED BOOTWIDTH1 0 0 1 1 0 0 1 1 LATCHED BOOTWIDTH0 0 1 0 1 0 1 0 1 LATCHED MEDCHG 0 0 0 0 1 1 1 1
Interrupt Controller
The LH7A400 interrupt controller is designed to control the interrupts from 28 different sources. Four interrupt sources are mapped to the FIQ input of the ARM922T and 24 are mapped to the IRQ input. FIQs have a higher priority than the IRQs. If two interrupts with the same priority become active at the same time, the priority must be resolved in software. When an interrupt becomes active, the interrupt controller generates an FIQ or IRQ if the corresponding mask bit is set. No latching of interrupts takes place in the controller. After a Power On Reset all mask register bits are cleared, therefore masking all interrupts. Hence, enabling of the mask register must be done by software after a power-on-reset.
Memory Map
The LH7A400 system has a 32-bit-wide address bus. This allows it to address up to 4GB of memory. This memory space is subdivided into a number of memory banks; see Figure 4. Four of these banks (each of 256MB) are allocated to the Synchronous memory controller. Eight of the banks (again, each 256MB) are allocated to the Asynchronous memory controller. Two of these eight banks are designed for PCMCIA systems. Part of the remaining memory space is allocated to the embedded SRAM, and to the control registers of the AHB and APB. The rest is unused.
Preliminary Data Sheet
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27
LH7A400
32-Bit System-on-Chip
F000.0000 E000.0000 D000.0000 C000.0000 B001.4000 B000.0000 8000.3800 8000.2000 8000.0000 7000.0000 6000.0000 5000.0000 4000.0000 3000.0000 2000.0000 1000.0000 0000.0000
ASYNCHRONOUS MEMORY (nCS0) SYNCHRONOUS MEMORY (nSCS2) SYNCHRONOUS MEMORY (nSCS1) SYNCHRONOUS MEMORY (nSCS0) RESERVED EMBEDDED SRAM RESERVED AHB INTERNAL REGISTERS APB INTERNAL REGISTERS ASYNCHRONOUS MEMORY (CS7) ASYNCHRONOUS MEMORY (CS6) PCMCIA/CompactFlash (nPCSLOTE2) PCMCIA/CompactFlash (nPCSLOTE1) ASYNCHRONOUS MEMORY (nCS3) ASYNCHRONOUS MEMORY (nCS2) ASYNCHRONOUS MEMORY (nCS1) SYNCHRONOUS ROM (nSCS3) SYNCHRONOUS MEMORY BOOT
SYNCHRONOUS MEMORY (nSCS3) SYNCHRONOUS MEMORY (nSCS2) SYNCHRONOUS MEMORY (nSCS1) SYNCHRONOUS MEMORY (nSCS0) RESERVED EMBEDDED SRAM RESERVED AHB INTERNAL REGISTERS APB INTERNAL REGISTERS ASYNCHRONOUS MEMORY (CS7) ASYNCHRONOUS MEMORY (CS6) PCMCIA/CompactFlash (nPCSLOTE2) PCMCIA/CompactFlash (nPCSLOTE1) ASYNCHRONOUS MEMORY (nCS3) ASYNCHRONOUS MEMORY (nCS2) ASYNCHRONOUS MEMORY (nCS1) ASYNCHRONOUS ROM (nCS0) ASYNCHRONOUS MEMORY BOOT
256MB 256MB 256MB 256MB
80KB
256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB
LH7A400-6
Figure 4. Memory Mapping for Each Boot Mode
External Bus Interface
The external bus interface allows the ARM922T, LCD controller and DMA engine access to an external memory system. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in Synchronous Memory for large displays. The processor and DMA engine share the main system bus, providing access to all external memory devices and the embedded SRAM frame buffer. An arbitration unit ensures that control over the External Bus Interface (EBI) is only granted when an existing access has been completed. See Figure 5.
set the MMU (in the LCD controller) page tables such that the two memory areas appear contiguous. Byte, Half-Word and Word accesses are permissible.
Asynchronous Memory Controller
The Asynchronous memory controller is incorporated as part of the memory controller to provide an interface between the AMBA AHB system bus and external (off-chip) memory devices. The Asynchronous Memory Controller provides support for up to eight independently configurable memory banks simultaneously. Each memory bank is capable of supporting: * SRAM * ROM * Flash EPROM * Burst ROM memory. Each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. The memory controller can be configured to support either littleendian or big-endian operation. The memory banks can be configured to support: * Non-burst read and write accesses only to highspeed CMOS static RAM. * Non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory.
Embedded SRAM
The amount of Embedded SRAM contained in the LH7A400 is 80KB. This Embedded memory is designed to be used for storing code, data, or LCD frame data and to be contiguous with external SDRAM. The 80KB is large enough to store a QVGA panel (320 x 240) at 8 bits per pixel, equivalent to 70KB of information. Containing the frame buffer on chip reduces the overall power consumed in any application that uses the LH7A400. Normally, the system has to perform external accesses to acquire this data. The LCD controller is designed to automatically use an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any 4KB page boundary in SDRAM, allowing software to
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
EXTERNAL TO THE LH7A400
INTERNAL TO THE LH7A400
ARM922T
SDRAM
SRAM EXTERNAL BUS INTERFACE ADDRESS (EBI) and CONTROL DATA ARBITER
PCMCIA/CF SUPPORT SYNCHRONOUS DYNAMIC MEMORY CONTROLLER (SDMC) ARBITER
SDRAM
ROM
80KB EMBEDDED SRAM LCD AHB
LCD MEMORY MANAGEMENT UNIT (MMU)
COLOR LCD CONTROLLER (CLCDC) DMA CONTROLLER AD-TFT LCD TIMING CONTROLLER ADVANCED HIGH-PERFORMANCE BUS (AHB)
LH7A400-8
Figure 5. External Bus Interface Block Diagram
Preliminary Data Sheet
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ARBITER
ARBITER
ASYNCHRONOUS STATIC MEMORY CONTROLLER (SMC)
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LH7A400
32-Bit System-on-Chip
The Asynchronous Memory Controller has six main functions: * * * * * * Memory bank select Access sequencing Wait states generation Byte lane write control External bus interface CompactFlash or PCMCIA interfacing.
MMC bus lines can be divided into three groups: * Power supply: VDD and VSS * Data Transfer: MMCCMD, MMCDATA * Clock: MMCLK. MULTIMEDIACARD ADAPTER The MultiMediaCard Adapter implements MultiMediaCard specific functions, serves as the bus master for the MultiMediacard Bus and implements the standard interface to the MultiMediaCard Cards (card initialization, CRC generation and validation, command/response transactions, etc.).
Synchronous Memory Controller
The Synchronous memory controller provides a high speed memory interface to a wide variety of Synchronous memory devices, including SDRAM, Synchronous Flash and Synchronous ROMs. The key features of the controller are: * LCD DMA port for high bandwidth * Up to four Synchronous Memory banks that can be independently set up * Special configuration bits for Synchronous ROM operation * Ability to program Synchronous Flash devices using write and erase commands * On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset * Data is transferred between the controller and the SDRAM in quad-word bursts. Longer transfers within the same page are concatenated, forming a seamless burst * Programmable for 16- or 32-bit data bus size * Two reset domains are provided to enable SDRAM contents to be preserved over a `soft' reset * Power saving Synchronous Memory SCKE and external clock modes provided.
Smart Card Interface (SCI)
The SCI (ISO7816) interfaces to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES * Supports asynchronous T0 and T1 transmission protocols * Supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2, or 4 supported * Eight-character-deep buffered Tx and Rx paths * Direct interrupts for Tx and Rx FIFO level monitoring * Interrupt status register * Hardware-initiated card deactivation sequence on detection of card removal * Software-initiated card deactivation sequence on transaction complete * Limited support for synchronous Smart Cards via registered input/output. PROGRAMMABLE PARAMETERS * Smart Card clock frequency * Communication baud rate * Protocol convention * Card activation/deactivation time * Check for maximum time for first character of Answer to Reset - ATR reception * Check for maximum duration of ATR character stream * Check for maximum time of receipt of first character of data stream * Check for maximum time allowed between characters * Character guard time * Block guard time * Transmit/receive character retry.
MultiMediaCard (MMC)
The MMC adapter combines all of the requirements and functions of an MMC host. The adapter supports the full MMC bus protocol, defined by the MMC Definition Group's specification v.2.11. The controller can also implement the SPI interface to the cards. INTERFACE DESCRIPTION AND MMC OVERVIEW The MMC controller uses the three-wire serial data bus (clock, command, and data) to transfer data to and from the MMC card, and to configure and acquire status information from the card's registers.
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Direct Memory Access Controller (DMA)
The DMA Controller interfaces streams from the following three peripherals to the system memory: * USB (1 Tx and 1 Rx DMA Channel) * MMC (1 Tx and 1 Rx DMA Channel) * AC97 (3 Tx and 3 Rx DMA Channels). Each has its own bi-directional peripheral DMA bus capable of transferring data in both directions simultaneously. All memory transfers take place via the main system AHB bus. DMA Specific features are: * Independent DMA channels for Tx and Rx * Two Buffer Descriptors per channel to avoid potential data under/over-flows due to software introduced latency * No Buffer wrapping * Buffer size may be equal to, greater than or less than the packet size. Transfers can automatically switch between buffers. * Maskable interrupt generation * Internal arbitration between DMA Channels and external bus arbiter. * For DMA Data transfer sizes, byte, word and quadword data transfers are supported. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. A system interrupt is generated when any or all of the DMA channels wish to inform the processor that a new buffer needs to be allocated. The DMA controller services three peripherals using ten DMA channels, each with its own peripheral DMA bus capable of transferring data in both directions simultaneously. The MMC and USB peripherals each use two DMA channels, one for transmit and one for receive. The AC97 peripheral uses six DMA channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overheads. The DMA Controller does not support memory to memory transfers.
Color LCD Controller
The LH7A400's LCD Controller is programmable to support up to 1,024 x 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A400's LCD Controller incorporates the timing conversion logic from TFT to HR-TFT, allowing a direct interface to HR-TFT and minimizing external chip count. The Color LCD Controller features support for: * Up to 1,024 x 768 Resolution * 16-bit Video Bus * STN, Color STN, AD-TFT, HR-TFT, TFT panels * Single and Dual Scan STN panels * Up to 15 Gray Shades * Up to 64,000 Colors
AC97 Advanced Audio Codec Interface
The AC97 Advanced Audio Codec controller includes a 5-pin serial interface to an external audio codec. The AC97 LINK is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AC97 controller contains logic that controls the AC97 link to the Audio Codec and an interface to the AMBA APB. Its main features include: * Serial-to-parallel conversion for data received from the external codec * Parallel-to-serial conversion for data transmitted to the external codec * Reception/Transmission of control and status information via the AMBA APB interface * Supports up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored independently in both transmit and receive modes. The outgoing data for the FIFOs can be written via either the APB interface or with DMA channels 1 - 3.
USB Device
The features of the USB are: * Fully compliant to USB 1.1 specification * Provides a high level interface that shields the firmware from USB protocol details * Compatible with both OpenHCI and Intel's UHCI standards * Supports full-speed (12 Mbps) functions * Supports Suspend and Resume signalling.
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
Audio Codec Interface (ACI)
The ACI provides: * A digital serial interface to an off-chip 8-bit CODEC * All the necessary clocks and timing pulses to perform serialization or de-serialization of the data stream to or from the CODEC device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACICLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchronization output signal that is synchronous with the bit clock.
The transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: * Four individually maskable interrupts from the receive, transmit and modem status logic blocks * A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is prevented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3.
Synchronous Serial Port (SSP)
The LH7A400 SSP is a master-only interface for synchronous serial communication with device peripheral devices that has either Motorola SPI, National Semiconductor MICROWIRE or Texas Instruments Synchronous Serial Interfaces. The LH7A400 SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A400 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usually be determined by peripheral devices.
Timers
Two identical timers are integrated in the LH7A400. Each of these timers has an associated 16-bit read/write data register and a control register. Each timer is loaded with the value written to the data register immediately, this value will then be decremented on the next active clock edge to arrive after the write. When the timer underflows, it will immediately assert its appropriate interrupt. The timers can be read at any time. The clock source and mode is selectable by writing to various bits in the system control register. Clock sources are 508 kHz and 2 kHz. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. It has the same register arrangement as Timer 1 and Timer 2, providing a load, value, control and clear register. Once the timer has been enabled and is written to, unlike the Timer 1 and Timer 2, will decrement the timer on the next rising edge of the 7.3728 MHz clock after the data register has been updated. All the timers can operate in two modes, free running mode or pre-scale mode. FREE-RUNNING MODE In free-running mode, the timer will wrap around to 0xFFFF when it underflows and continue counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a programmable frequency to drive the buzzer or generate a periodic interrupt.
UART/IrDA
The LH7A400 contains three UARTs, UART1, UART2, and UART3. The UART performs: * Serial-to-Parallel conversion on data received from the peripheral device * Parallel-to-Serial conversion on data transmitted to the peripheral device.
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Real Time Clock (RTC)
The RTC can be used to provide a basic alarm function or long time-base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in one second intervals is achieved by use of a 1 Hz clock input to the RTC.
DC-to-DC Converter
The features of the DC-DC Converter interface are: * Dual drive PWM outputs, with independent closed loop feedback * Software programmable configuration of one of 8 output frequencies (each being a fixed divide of the input clock). * Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. * Output polarity (for positive or negative voltage generation) is hardware-configured during power-on reset via the polarity select inputs * Each PWM output can be dynamically switched to one of a pair of preprogrammed frequency/duty cycle combinations via external pins.
Battery Monitor Interface (BMI)
The LH7A400 BMI is a serial communication interface specified for two types of Battery Monitors/Gas Gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. A brief overview of these two interface types are given here. SINGLE WIRE INTERFACE The Single Wire Interface performs: * Serial-to-parallel conversion on data received from the peripheral device * Parallel-to-serial conversion on data transmitted to the peripheral device * Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol, in which the host initiates a data transfer by sending a WriteData/Command word to the Battery Monitor. This word will always contain the Command section, which tells the Single Wire Interface device the location for the current transaction. The most significant bit of the Command determines if the transaction is Read or Write. In the case of a Write transaction, then the word will also contain a WriteData section with the data to be written to the peripheral. SMART BATTERY INTERFACE The SMBus Interface performs: * Serial-to-Parallel conversion on data received from the peripheral device * Parallel-to-Serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multimaster bus (the SMBus), meaning that more than one device capable of controlling the bus can be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data provided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism, by relying on the wired-AND connection of all SMBus interfaces to the SMBus.
Watchdog Timer (WDT)
The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause a FIQ interrupt. Failure to service the FIQ interrupt will then generate a System Reset. The WDT features are: * Driven by the system clock * 16 programmable time-out periods: 216 through 231 clock cycles * Generates a system reset (resets LH7A400) or a FIQ Interrupt whenever a time-out period is reached * Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes * Protection mechanism guards against interrupt-service-failure: - The first WDT time-out triggers FIQ and asserts nWDFIQ status flag - If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a System Reset.
General Purpose I/O (GPIO)
The LH7A400 GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and GPIOFEOI registers are used to control edge-triggered Interrupts on Port F. The PINMUX register controls what signals are output of Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and H.
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) Storage Temperature MINIMUM -0.3 V -0.3 V -0.3 V -55C MAXIMUM 2.4 V 4.6 V 2.4 V 125C
NOTE: These ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage for PLLs (VDDA) Clock Frequency (Commercial) Clock Frequency (Industrial) Operating Temperature (Commercial) Operating Temperature (Industrial) MINIMUM TYPICAL MAXIMUM 1.62 V 3.0 V 1.62 V 10 MHz 10 MHz 0C -40C 25C 25C 1.8 V 3.3 V 1.8 V 1.98 V 3.6 V 1.98 V 200 MHz 195 MHz 70C +85C 3, 4, 5 3, 4, 5 NOTES 1 2
NOTES: 1. Core Voltage should never exceed I/O Voltage. 2. USB is not functional below 3.0 V. 3. Using 14.756 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal. 4. VDDC = 1.62 V to 1.98 V. 5. VDD = 3.0 V to 3.6 V.
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
DC/AC SPECIFICATIONS (COMMERCIAL AND INDUSTRIAL)
Unless otherwise noted, all data provided under commercial DC/AC specifications are based on -40C to +85C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6 V, VDDA = 1.62 V to 1.98 V.
DC Specifications
SYMBOL VIH VIL VHST PARAMETER CMOS and Schmitt Trigger Input HIGH Voltage CMOS and Schmitt Trigger Input LOW Voltage Schmitt Trigger Hysteresis CMOS Output HIGH Voltage, Output Drive 1 VOH Output Drive 2 Output Drive 3 Output Drive 4 and 5 CMOS Output LOW Voltage, Output Drive 1 VOL Output Drive 2 Output Drive 3 Output Drive 4 Output Drive 5 IIN IOZ ISTARTUP CIN COUT Input Leakage Current Output Tri-state Leakage Current Startup Current Input Capacitance Output Capacitance -10 -10 0.25 2.6 2.6 2.6 2.6 0.4 0.4 0.4 0.4 0.4 10 10 50 4 4 MIN. TYP. MAX. UNIT 2.0 0.8 V V V V V V V V V V V V A A A pF pF VIL to VIH IOH = -2 mA IOH = -4 mA IOH = -8 mA IOH = -12 mA IOL = 2 mA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 20 mA VIN = VDD or GND VOUT = VDD or GND 2 1 1 CONDITIONS NOTES
NOTES: 1. Output Drive 5 can sink 20 mA of current, but sources 12 mA of current. 2. Current consumption until oscillators are stabilized.
AC Test Conditions
PARAMETER DC I/O Supply Voltage (VDD) DC Core Supply Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels RATING 3.0 to 3.6 1.62 to 1.98 VSS to 3 2 VDD/2 UNIT V V V ns V
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 7 were derived under the conditions presented here. Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: * All IP blocks either operating or enabled at maximum frequency and size configuration * Core operating at maximum power configuration * All voltages at maximum specified values * Maximum specified ambient temperature. Typical The values in the TYPICAL column were determined using a `typical' application under `typical' environmental conditions and the following operating characteristics: * LINUX operating system running from SDRAM * UART and AC97 peripherals operating; all other peripherals as needed by the OS * LCD enabled with 320 x 240 x 16-bit color, 60 Hz refresh rate, data in SDRAM * I/O loads at nominal * Cache enabled * FCLK = 200 MHz; HCLK = 100 MHz; PCLK = 50 MHz * All voltages at typical values * Nominal case temperature. Table 7. Current Consumption by Mode
SYMBOL PARAMETER TYP. MAX. UNITS
PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 8 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the peripheral clock running at maximum frequency, typical conditions, and no I/O loads. This current is supplied by the 1.8 V power supply. Table 8. Peripheral Current Consumption PERIPHERAL AC97 UART (each) RTC Timers (each) LCD (+I/O) MMC SCI PWM (each) BMI-SWI BMI-SBus SDRAM (+I/O) USB (+PLL) ACI TYPICAL 1.3 1.0 0.005 0.1 5.4 (1.0) 0.6 23 <0.1 1.0 1.0 1.5 (14.8) 5.6 (3.3) 0.8 UNITS mA mA mA mA mA mA mA mA mA mA mA mA mA
ACTIVE MODE ICORE IIO ICORE IIO ICORE IIO Current drawn by core Current drawn by I/O Current drawn by core Current drawn by I/O Current drawn by core Current drawn by I/O 132 15 40 1 38 4 180 58 44 1 mA mA mA mA A A
HALT MODE (ALL PERIPHERALS DISABLED)
STANDBY MODE (TYPICAL CONDITIONS ONLY)
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
AC Specifications
All signals described in Table 9 relate to transitions after a reference clock signal. The illustration in Figure 6 represents all cases of these sets of measurement parameters. The reference clock signals in this design are: * HCLK, internal System Bus clock (`C' in timing data) * PCLK, Peripheral Bus clock * SSPCLK, Synchronous Serial Port clock * UARTCLK, UART Interface clock * LCDDCLK, LCD Data clock from the LCD Controller * ACBITCLK, AC97 clock * SCLK, Synchronous Memory clock. All signal transitions are measured from the 50% point of the clock to the 50% point of the signal.
For outputs from the LH7A400, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from a valid address bus, or rising edge of the peripheral clock. Maximum requirements for tOVXXX are shown in Table 9. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid from the valid address bus, or rising edge of the peripheral clock. Minimum requirements for tOHXXX are listed in Table 9. For Inputs, tISXXX (e.g. tISD) represents the amount of time the input signal must be valid after a valid address bus, or rising edge of the peripheral clock. Maximum requirements for tISXXX are shown in Table 9. The signal tIHXXX (e.g. tIHD) represents the amount of time the output must be held valid from the valid address bus, or rising edge of the peripheral clock. Minimum requirements are shown in Table 9.
REFERENCE CLOCK
tOVXXX tOHXXX
OUTPUT SIGNAL (O)
tISXXX tIHXXX
INPUT SIGNAL (I)
7A400-28
Figure 6. LH7A400 Signal Timing
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LH7A400
32-Bit System-on-Chip
Table 9. AC Signal Characteristics
SIGNAL TYPE LOAD SYMBOL tOVD tOHD tISD tIHD tOVCSR nCS[3:0]/CS[7:6] Output 30 pF tOVCSW tOHCS tOVWE nWE[3:0] Output 30 pF tOHWE tOHWECS nOE Output 30 pF tOVOE tOHOE tOVA tOVB tOVD tISD tIHD 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF tOVCA tOHCA tOVRA tOHRA tOVSDW tOHSDW tOVC tOVDQ tOVSC tOHSC tOVDREG tOHDREG tOVD tOHD tISD tIHD 30 pF 30 pF 30 pF 30 pF 30 pF tOVCE1 tOHCE1 tOVCE2 tOHCE2 tOVOE tOHOE tOVWE tOHWE tOVPCD tOHPCD tOVCMD tOHCMD tOVDAT tOHDAT 3 ns 3 ns 3 ns 4C - 5 ns 3 ns MMC INTERFACE SIGNALS MMCCMD MMCDATA Output Output 100 pF 100 pF MMC Command Valid MMC Command Hold MMC Data Valid MMC Data Hold 3C - 5 ns 1C 3C - 5 ns 1C + 1 ns 4C - 5 ns 1C + 1 ns 4C - 5 ns 1C 4C - 15 ns 1C 4C - 5 ns 1C 4C - 5 ns 1C 2 ns 2 ns 1 ns 2 ns 0.0 ns 2 ns 0.0 ns 2 ns 0.0 ns 2 ns 2 ns 2 ns 0.0 ns 1C 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 3C - 10 ns 7.5 ns 7.5 ns 7.5 ns 2C - 10 ns 0 1C 1C 3C - 10 ns 1C 3C - 7 ns 3C - 20 ns 3C - 3 ns 0 ns 1C MIN. MAX.
1
DESCRIPTION Data Valid Data Hold Data Setup Data Hold Chip Select Valid (Read) Chip Select Valid (Write) Chip Select Hold Write Enable Valid Write Enable Hold Deassertion delay between nWE[3:0] and nCS[3:0]/CS[7:6] Ouput Enable Valid Ouput Enable Hold Address Valid Bank Select Valid Data Valid Data Setup Data Hold CAS Valid CAS Hold RAS Valid RAS Hold Write Enable Valid Write Enable Hold Clock Enable Valid Data Mask Valid Synchronous Chip Select Valid Synchronous Chip Select Hold nREG Valid nREG Hold Data Valid Data Hold Data Setup Time Data Hold Time Chip Enable 1 Valid Chip Enable 1 Hold Chip Enable 2 Valid Chip Enable 2 Hold Output Enable Valid Output Enable Hold Write Enable Valid Write Enable Hold Card Direction Valid Card Direction Hold
ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ wait states x C) Output D[31:0] Input 50 pF 1C + 1 ns
SYNCHRONOUS MEMORY INTERFACE SIGNALS SA[13:0] SA[17:16]/SB[1:0] D[31:0] Output Output Output Input Output Output Output Output Output Output 50 pF 50 pF 50 pF
nCAS nRAS nSWE SCKE[1:0] DQM[3:0] nSCS[3:0]
PCMCIA INTERFACE SIGNALS (+ wait states x C)1 nPCREG Output Output D[31:0] Input nPCCE1 nPCCE2 nPCOE nPCWE PCDIR Output Output Output Output Output 30 pF 50 pF
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32-Bit System-on-Chip
LH7A400
Table 9. AC Signal Characteristics (Cont'd)
SIGNAL MMCDATA MMCCMD TYPE Input Input LOAD SYMBOL tISDAT tIHDAT tISCMD tIHCMD tOVAC97 tOHAC97 tISAC97 tIHAC97 tACBITCLK tISSSPFRM 50 pF tOVSSPOUT tISSSPIN 14 ns AUDIO CODEC INTERFACE (ACI) ACOUT/ACSYNC Output 30 pF tOS tOH ACIN Input tIS tIH TBD TBD TBD TBD TBD TBD TBD TBD ACOUT delay from rising clock edge ACOUT Hold ACIN Setup ACIN Hold 10 ns 10 ns 2.5 ns 72 ns 14 ns 14 ns 90 ns MIN. 5 ns 5 ns 5 ns 5 ns 15 ns MAX. DESCRIPTION MMC Data Setup MMC Data Hold MMC Command Setup MMC Command Hold AC97 Output Valid/Sync Valid AC97 Output Hold/Sync Hold AC97 Input Setup AC97 Input Hold AC97 Clock Period SSPFRM Input Valid SSP Transmit Valid SSP Receive Setup
AC97 INTERFACE SIGNALS ACOUT/ACSYNC ACIN ACBITCLK SSPFRM SSPTX SSPRX Output Input Input Input Output Input 30 pF
SYNCHRONOUS SERIAL PORT (SSP)
NOTES: 1. `nC' in the MIN./MAX. columns indicates the number of system clock (HCLK) periods after valid address. 2. For Output Drive strength specifications, refer to Table 1.
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
SMC Waveforms
Figure 7 shows the waveform and timing for an External Asynchronous Memory Write. Note that the deassertion of nWE can preceed the deassertion of
nCS by a maximum of one HCLK, or at minimum, can coincide (see Table 9). Figure 8 shows the waveform and timing for an External Asynchronous Memory Read, with one Wait State.
0 HCLK (See Note 2) A[27:0] (See Note 1)
1
2
3
4
ADDRESS
tOVD
D[31:0]
DATA
tOHD
nCSx, CSx
tOVCSW tOHCS
nWE[3:0]
tOVWE tOHWE
NOTES: 1. A[24:0] when SCI used. 2. HCLK is an internal signal, shown for reference only.
LH7A400-20
tOHWECS
Figure 7. External Asynchronous Memory Write
0 HCLK (See Note) A[25:0]
1
2
3
ADDRESS
tISD
D[31:0]
DATA
tIHD tOVCSR
nCSx, CSx
tOHCS
nOE
tOVOE tOHOE
NOTE: HCLK is an internal signal, shown for reference only.
LH7A400-21
Figure 8. External Asynchronous Memory Read
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Synchronous Memory Controller Waveforms
Figure 9 shows the waveform and timing for a Synchronous Burst Read (page already open). Figure 10 shows the waveform and timing for Synchronous memory to Activate a Bank and Write.
tSCLK
SCLK
tOHXXX
SDRAMcmd
READ tOVA tOVXXX
nDQM SA[13:0], SB[1:0] tOVA D[31:0] NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC. 4. DQM[3:0] is static LOW. 5. SCKE is static HIGH.
BANK, COLUMN
tISD tIHD
DATA n + 2 DATA n DATA n + 1 DATA n + 3
LH7A400-23
Figure 9. Synchronous Burst Read
tSCLK
SCLK tOVC SCKE tOVXXX tOHXXX
SDRAMcmd
ACTIVE tOVA
WRITE
SA[13:0], SB[1:0] BANK, ROW tOVA D[31:0] tOVD NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC. 4. DQM[3:0] is static LOW. tOHD DATA BANK, COLUMN
LH7A400-24
Figure 10. Synchronous Bank Activate and Write
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
PC Card (PCMCIA) Waveforms
Figure 11 shows the waveforms and timing for a PCMCIA Read Transfer, Figure 12 shows the waveforms and timing for a PCMCIA Write Transfer.
PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1)
HCLK
A[25:0]
ADDRESS
nPCREG tOVDREG tOHDREG nPCCEx (See Note 2)
tOVCEx tOHCEx
PCDIR tOVPCD
D[15:0] tISD tIHD nPCOE tOVOE tOHOE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None
DATA
LH7A400-11
Figure 11. PCMCIA Read Transfer
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1)
HCLK
A[25:0]
ADDRESS
nPCREG tOVDREG tOHDREG nPCCEx (See Note 2)
tOVCEx tOHCEx
PCDIR tOVPCD DATA tOVD tOHD
D[15:0]
nPCWE tOVWE tOHWE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None
LH7A400-12
Figure 12. PCMCIA Write Transfer
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
MMC Interface Waveforms
Figure 13 shows the waveforms and timing for an MMC command or data Write, and Figure 14 shows the waveforms and timing for an MMC command or data Read.
AC97 Interface Waveforms
Figure 15 shows the waveforms and timing for the AC97 interface Data Setup and Hold.
MMCCLK
MMCCMD tOVCMD MMCDAT tOVDAT tOHDAT
LH7A400-14
tOHCMD
Figure 13. MMC Command/Data Write
MMCCLK
MMCCMD tISCMD tIHCMD MMCDAT tISDAT tIHDAT
LH7A400-15
Figure 14. MMC Command/Data Read
tACBITCLK
ACBITCLK tOVAC97 ACOUT/ACSYNC tISAC97 tIHAC97 ACIN
LH7A400-16
tOHAC97
Figure 15. AC97 Data Setup and Hold
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Audio Codec Interface Waveforms
Figure 16 and Figure 17 show the timing for the ACI. Transmit data is clocked on the rising edge of ACBITCLK (whether transmitted by the LH7A404 ACI
or by the external codec chip); receive data is clocked on the falling edge. This allows full-speed, full duplex operation.
ACBITCLK
ACSYNC/ACOUT tOS tOH ACIN tIS tIH
LH7A400-169
Figure 16. ACI Signal Timing
ACBITCLK
ACSYNC BIT ACIN/ACOUT 7 6 5 4 3 2 1 0 7 6
ACIN/ACOUT SAMPLED ON FALLING EDGE
LH7A400-181
Figure 17. ACI Datastream
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
Clock and State Controller (CSC) Waveforms
Figure 18 shows the behavior of the LH7A400 when coming out of Reset or Power On. Figure 19 shows external reset timing, and Table 10 gives the timing parameters. Figure 20 depicts signal timing following a Reset.
Figure 21 shows the recommended components for the SHARP LH7A400 32.768 kHz external oscillator circuit. Figure 22 shows the same for the 14.7456 MHz external oscillator circuit. In both figures, the NAND gate represents the internal logic of the chip.
Table 10. Reset AC Timing
PARAMETER tOSC32 tPORH tOSC14 tPLLL tURESET/tPWRFL DESCRIPTION 32 kHz Oscillator Stabilization Time after Power On* nPOR Hold Time after tOSC32 14.7456 MHz Oscillator Stabilization Time after Wake UP Phase Locked Loop Lockup Time nURESET/nPWRFL Pulse Width (once sampled LOW) 2 0 4 250 MIN. MAX. 550 UNIT ms ms ms s System Clock Cycles
NOTE: *VDDC = VDDCmin
VDDCmin VDDC
XTAL32
tOSC32 tPORH
XTAL14
tOSC14
nPOR
LH7A400-25
Figure 18. Oscillator Start-up
tURESET tPWRFL
nURESET nPWRFL
LH7A400-26
Figure 19. External Reset
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
WAKEUP (asynchronous) 7.8125 ms
CLKEN 7.8125 ms
HCLK
START UP
STABLE CLOCK
LH7A400-175
Figure 20. Signal Timing After Reset
ENABLE INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 XTALIN XTALOUT
Y1
32.768 kHz R1 18 M C1 15 pF GND NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. C2 18 pF GND
RECOMMENDED CRYSTAL SPECIFICATIONS PARAMETER 32.768 kHz Crystal Tolerance Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION Parallel Mode 30 ppm 3 ppm 12.5 pF 50 k 1.0 W (MAX.) MTRON SX1555 or equivalent
LH7A400-187
Figure 21. 32.768 kHz External Oscillator Components and Schematic
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
ENABLE INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 XTALIN XTALOUT
Y1
14.7456 MHz R1 1 M C1 18 pF GND C2 22 pF GND
RECOMMENDED CRYSTAL SPECIFICATIONS NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 18 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. PARAMETER 14.7456 MHz Crystal Tolerance Stability Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION (AT-Cut) Parallel Mode 50 ppm 100 ppm 5 ppm 18 pF 40 100 W (MAX.) MTRON SX2050 or equivalent
LH7A400-188
Figure 22. 14.7456 MHz External Oscillator Components and Schematic
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
Printed Circuit Board Layout Practices
LH7A400 POWER SUPPLY DECOUPLING The LH7A400 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power to the core logic, and VDDA/VSSA supply analog power to the PLLs. Each of the VDD and VDDC pins must be provided with a low impedance path to the corresponding board power supply. Likewise, the VSS and VSSC pins must be provided with a low impedance path to the board ground. Each power supply must be decoupled to ground using at least one 0.1 F high frequency capacitor located as close as possible to a VDDx, VSSx pin pair on each of the four sides of the chip. If room on the circuit board allows, add one 0.01 F high frequency capacitor near each VDDx, VSSx pair on the chip. To be effective, the capacitor leads and associated circuit board traces connecting to the chip VDDx, VSSx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. There must be one bulk 10 F capacitor for each power supply placed near one side of the chip. REQUIRED LH7A400 PLL, VDDA, VSSA FILTER The VDDA pins supplies power to the chip PLL circuitry. VSSA is the ground return path for the PLL circuit. These pins must have a low-pass filter attached as shown in Figure 23. The Schottky diode shown in the schematic must have a low forward drop specification to allow VDDA to quickly transition through the entire input voltage range. The power pin VDDA path must be a single wire from the IC package pin to the high frequency capacitor, then to the low frequency capacitor, and finally through the series resistor to the board power supply. The distance from the IC pin to the high frequency capacitor must be kept as short as possible. Similarly, the VSSA path is from the IC pin to the high frequency capacitor, then to the low frequency capacitor, keeping the distance from the IC pin to the high frequency cap as short as possible.
VDDC (SOURCE) VDDC LH7A400 100 VDDA
+
22 F 0.1 F VSSA
LH7A400-189
Figure 23. VDDA, VSSA Filter Circuit UNUSED INPUT SIGNAL CONDITIONING Floating input signals can cause excessive power consumption. Unused inputs without internal pull-up or pull-down resistors should be pulled up or down externally, to tie the signal to its inactive state. Some GPIO signals may default to inputs. If the pins that carry these signals are unused, software can program these signals as outputs, eliminating the need for pull-ups or pull-downs. Power consumption may be higher than expected until software completes programming the GPIO. Some LH7A400 inputs have internal pull-ups or pull-downs. If unused, these inputs do not require external conditioning. OTHER CIRCUIT BOARD LAYOUT PRACTICES All outputs have fast rise and fall times. Printed circuit trace interconnection length must therefore be reduced to minimize overshoot, undershoot and reflections caused by transmission line effects of these fast output switching times. This recommendation particularly applies to the address and data buses. When considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. Capacitance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. Attention to power supply decoupling and printed circuit board layout becomes more critical in systems with higher capacitive loads. As these capacitive loads increase, transient currents in the power supply and ground return paths also increase.
CAUTION
Note that the VSSA pin specifically does not have a connection to the circuit board ground. The LH7A400 PLL circuit has an internal DC ground connection to VSS (GND), so the external VSSA pin must NOT be connected to the circuit board ground, but only to the filter components.
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
PACKAGE SPECIFICATIONS
256-BALL PBGA
TOP VIEW
17.00 A1 BALL PAD CORNER 15.00 -0.05 B 6.00 11.64 MAX. 15.00 -0.05
+0.70 +0.70
0.20 (4X) A
6.00
2.90
AVAILABLE MARKING AREA 2.90 45 CHAMFER 4 PLACES 11.64 MAX. 0.35 C 0.25 C 1.21 TYP.
BOTTOM VIEW (256 solder balls)
A1 BALL PAD CORNER
1.21 TYP.
A1 BALL PAD INDICATOR, 1.0 DIA.
17.00
0.15 C
16 14 12 10 8 6 42 15 13 11 9 7 5 31 A B C D E F G H J K L M N P R T
SIDE VIEW
C
30 TYP.
0.50 -0.10 0.30 M 0.10 M CAB C
+0.10
1.00 REF.
1.00
SEATING PLANE
1.00 REF.
1.00
0.80 0.05 1.76 0.21 0.40 0.10 1.56 0.06
0.50 R, 3 PLACES
NOTE: Dimensions in mm.
256PBGA
Figure 24. 256-Ball PBGA Package Specification
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
256-BALL CABGA
0.10 (4X)
TOP VIEW
14.00 A
A1 BALL PAD CORNER
14.00
B
0.10 C 0.12 C
BOTTOM VIEW (256 solder balls)
16 14 12 10 8 6 4 2 15 13 11 9 7 5 31 A B C D E F G H J K L M N P R T
SIDE VIEW
C
5 0.46 TYP. 0.15 M C A B 0.08 M C
0.80
6
SEATING PLANE
1.0
1.0
0.80
0.36 0.04 0.70 0.05 1.70 MAX.
NOTE: Dimensions in mm.
256CABGA
Figure 25. 256-Ball CABGA Package Specification
Preliminary Data Sheet
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LH7A400
32-Bit System-on-Chip
ORDERING INFORMATION
Table 11. Ordering Information
PART NUMBER LH7A400N0B000 LH7A400N0E000 LH7A400N0C000* LH7A400N0W000* PACKAGE PBGA CABGA Scribed Die Probed Wafer SPEED (MHz) AT TEMP. (C) 200 at 0+70 195 at -40+85 200 at 0+70 195 at -40+85 200 at 0+70 195 at -40+85 200 at 0+70 195 at -40+85
NOTE: *Requires Factory Approval.
CONTENT REVISIONS
This document contains the following changes to content, causing it to differ from previous versions. Table 12. Record of Revisions
DATE PAGE NO. 1 3-11 12 12-18 18-24 8-19-2003 39 41-42 44 PARAGRAPH OR ILLUSTRATION Features Table 1 Table 3 Table 4 Table 5 Figure 7 and Figure 8 Figures 11 and 12 Table 10 and Figure 16 Figures 19-21 and Printed Circuit Board Layout Practices Figure 23 Text Figure 1 SUMMARY OF CHANGES 256-ball CABGA package added CABGA Pins added; VDDA1/VDDA2 combined to VDDA; VSSA1/VSSA2 combined to VSSA Signal ordering corrected Table title added to differentiate between PBGA and CABGA packages CABGA numerical pin list table added `CSx' added to figures PCDIR signal corrected in PCMCIA timing diagrams tOSC14 added to both table and figure; XTAL14 added to figure; tPLLL added to table Figures and text added Figure added for CABGA package Corrected minor text errors; added separate Commercial and Industrial temperature specification. Updated to show ALI Interface
45-47 49 1 2 34 11-15-03 37-38 39 49 51
`Recommended Broke out "Commercial" and "Industrial" speed ranges. Operating Conditions' Table 9 Table 9 Figure 24 Table 11 Minor corrections to type. Added ACI timing. PBGA package drawing added. Added ordering information
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Preliminary Data Sheet
32-Bit System-on-Chip
LH7A400
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
JAPAN
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 www.sharpsma.com
SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com
SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com
TAIWAN
SINGAPORE
KOREA
SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328
SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855
SHARP Electronic Components (Korea) Corporation RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819
CHINA
HONG KONG
SHARP Microelectronics of China (Shanghai) Co., Ltd. 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd. 3rd Business Division, 17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower C, Electronics Science & Technology Building Shen Nan Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735
(c)2003 by SHARP Corporation
Reference Code SMA01012

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