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LRS1329A
* Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. * When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). *Office electronics *Instrumentation and measuring equipment *Machine tools *Audiovisual equipment *Home appliance *Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, and other transportation equipment *Mainframe computers *Traffic control systems *Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *Aerospace equipment *Communications equipment for trunk lines *Control equipment for the nuclear power industry *Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. * Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 1.00
LRS1329A
1
Contents 1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2. Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3. Write Protection Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 7 7
6. Status Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Write Cycle (F-WE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Write Cycle (F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Block Erase and Word/Byte Write Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. AC Electrical Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 SRAM AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 14 15 16 17 21 22 22 22 22 23
14. Data Retention Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15. Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16. Flash Memory Data Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 18. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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1. Description The LRS1329A is a combination memory organized as 2,097,152 x 8 / 1,048,576 x 16 bit flash memory and 262,144 x 8 bit static RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72 pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon. Flash Memory - Access Time **** 100ns 25 mA 57 mA 42 mA 15A 65A (Max.) (Max. tCYCLE = 200ns, CMOS Input) (Max.) (Max.) (Max. F-RP = GND 0.2V, IOUT(F-RY/BY) = 0mA) (Max. F-CE = F-RP = F-VCC 0.2V) - Power Supply current (The current for F-VCC pin and F-VPP pin) Read **** Word/Byte write **** Block erase **** Reset Power-Down **** Standby - Optimized Array Blocking Architecture for each Bank. Two 4k-word/8k-byte Boot Blocks Six 4k-word/8k-byte Parameter Blocks Thirty-one 32k-word/64k-byte Main Blocks Top Boot Location - Extended Cycling Capability 100,000 Block Erase Cycles - Enhanced Automated Suspend Options Word/Byte Write Suspend to Read Block Erase Suspend to Word/Byte Write Block Erase Suspend to Read SRAM - Access Time - Power Supply current Operating current Standby current Data retention current **** * * * * * * * * * * * * * * * * 85 ns 35mA 6 mA 30A 30A (Max.) (Max. tRC,tWC = Min.) (Max. tRC,tWC = 1s, CMOS Input) (Max.) (Max.) **** **** **** 2.7V to 3.6V -25C to +85C
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2. Pin Configuration
INDEX
1 A
NC
(TOP View)
4
A11
2
NC
3
NC
5
A12
6
A13
7
S-OE
8
F-GND
9
F-DQ15 /F-A-1
10
NC
11
NC
12
NC
B
S-CE2
S-WE
A10
A9
A16
S-CE1
DQ7
F-DQ14
C
FRY/BY
F-WE
F-RP
T1
F-DQ12
DQ6
F-DQ13
DQ5
D
F-GND
S-VCC
A8
T2
F-BYTE
F-DQ11
DQ4
F-VCC
E
F-VPP
F-WP
F-A19
T3
T4
DQ3
F-DQ10
S-GND
F
F-A18
F-A17
A7
NC
A14
DQ2
DQ1
F-DQ9
G
A6
A5
A4
A1
F-GND
A15
F-DQ8
DQ0
H
NC
NC
NC
A3
A2
A0
F-CE
F-OE
S-A17
NC
NC
NC
Note) From T1 to T4 pins are needed to be open. Two NC pins at the corner are connected. Do not float any GND pins.
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4
Pin A0 to A16 F-A-1, F-A17 to F-A19 S-A17 F-CE S-CE1, S-CE2 F-WE S-WE F-OE S-OE Address Inputs (Common) Address Inputs (Flash) Address Inputs (SRAM) Chip Enable Inputs (Flash) Chip Enable Inputs (SRAM) Write Enable Input (Flash) Write Enable Input (SRAM) Output Enable Input (Flash) Output Enable Input (SRAM)
Description F-A-1 : Not used in x16 mode. F-A-1 : L.S.B in x8 mode.
Type Input Input Input Input Input Input Input Input Input
F-RP
Reset Power Down Input (Flash) Block erase and Word/Byte Write : VIH or VHH Read : VIH or VHH Reset Power Down : VIL Write Protect Input (Flash) Two Boot Blocks Locked : VIL (With F-RP = VHH Erase of Write can operate to all block) Byte Enable (Flash); x8 mode : VIL, x16 mode : VIH Ready/Busy Output (Flash) During an Erase or Write operation : VOL Block Erase and Word/Byte Write Suspend : High-Z (High impedance) Reset Power Down : High-Z (High impedance) Data Inputs and Outputs (Common) Data Inputs and Outputs (Flash) ; Not used in x8 mode. Power Supply (Flash) Power Supply (SRAM) Write, Erase Power Supply (Flash) Block Erase and Word/Byte Write : F-VPP = VPPH All Blocks Locked : F-VPP < VPPLK GND (Flash) GND (SRAM) Non Connection (Should be all open) Test pin (Should be all open)
Input
F-WP F-BYTE
Input Input Open Drain Output Input / Output Input / Output Power Power Power Power Power -
F-RY/BY DQ0 to DQ7 F-DQ8 to F-DQ15 F-VCC S-VCC F-VPP F-GND S-GND NC T1 to T4
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3. Truth Table(1)
Flash Read Output Disable Write Read Standby Output Disable Write Read Reset Power Output Down Disable Write Standby Reset Power Standby Down Standby SRAM Notes 4,5,6 5,6
2,3,4,5,6
F-CE
F-RP F-OE F-WE F-BYTE S-CE1 S-CE2 S-OE S-WE L H H L H L H L H L L H H L L H H L (7) X X
DQ0 to DQ7 DOUT
F-DQ8 to F-DQ15 DOUT High-Z
L
H
High-Z DIN DIN DOUT High-Z DIN DOUT High-Z DIN High-Z High-Z High-Z High-Z
6 6 6 6 6 6 6 6 H X H L X X X (7) X L X X X L H H H X X X L H
X
X
Notes: 1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics. High-Z = High impedance. 2. Command Writes involving block erase or word/byte write are reliably executed when F-VPP = VPPH and F-VCC = 2.7V to 3.6V. Block erase or word/byte write with VIH < F-RP < VHH produce spurious results and should not be attempted. 3. Refer Section 5. Command Definitions for valid address input and DIN during a write operation. 4. Never hold F-OE low and F-WE low at the same timing. 5. F-A-1 set to VIL or VIH in byte mode (F-BYTE = VIL) 6. F-WP set to VIL or VIH. 7. SRAM Standby Mode S-CE1 S-CE2 H X X L
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4. Block Diagram
F-VCC F-VPP F-GND
F-A-1, F-A17 to F-A19 A0 to A16 F-CE F-OE F-WE F-WP F-RP F-BYTE DQ0 to DQ7 F-RY/BY
16M (x8/x16) bit Flash memory
F-DQ8 to F-DQ15
S-A17 S-CE1 S-CE2 S-OE S-WE
2M (x8) bit SRAM
S-VCC
S-GND
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5. Command Definitions for Flash Memory(1) 5.1 Command Definitions Command Read Array / Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word/Byte Write Block Erase and Word/Byte Write Suspend Block Erase and Word/Byte Write Resume Bus Cycles Required 1 2 2 1 2 2 1 1 5 5 5 5 4 First Bus Cycle Note Oper(2) Write Write Write Write Write Write Write Write Address(3) XA XA XA XA BA WA XA XA Data(3) FFH 90H 70H 50H 20H 40H or 10H B0H D0H Write Write BA WA D0H WD Read Read IA XA ID SRD Second Bus Cycle Oper(2) Address(3) Data(3)
Notes: 1. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. 2. Bus operations are defined in 3. Truth Table. 3. XA = Any valid address within the device. IA = Identifier code address. BA = Address within the block being erased. WA = Address of memory location to be written. SRD = Data read from status register (See 6. Status Register Definition). WD = Data to be written at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first). ID = Data read from identifier codes (See 5.2 Identifier Codes). 4. See Identifier Codes in section 5.2. 5. See Write Protection Alternatives in section 5.3. 5.2 Identifier Codes(1) Codes Manufacture Code Device Code Address [A19 - A0] 00000H 00001H Data [DQ7 - DQ0] B0H 48H
Notes: 1. Read Identifier Codes command is defined in 5.1 Command Definitions. 5.3 Write Protection Alternatives F-VPP F-RP Operation VIL Block Erase or Word/Byte Write X VIL >VPPLK(1) VHH VIH
F-WP X X X VIL VIH All Blocks Locked. All Blocks Locked. All Blocks Unlocked.
Effect
2 Boot Blocks Locked. All Blocks Unlocked.
Note: 1. F-VPP is guaranteed only with the nominal voltages.
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6. Status Register Definition WSMS 7 ESS 6 ES 5 WBWS 4 Notes: Check SR.7 or F-RY/BY to determine Block Erase or Word/ Byte Write completion. SR.6 - SR.0 are invalid while SR.7 = "0". If both SR.5 and SR.4 are "1"s after a Block Erase attempt, an improper command sequence was entered. VPPS 3 WBWSS 2 DPS 1 R 0
SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error in Block Erase 0 = Successful Block Erase SR.4 = WORD/BYTE WRITE STATUS (WBWS) 1 = Error in Word/Byte Write 0 = Successful Word/Byte Write SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP Low Detect, Operation Abort 0 = F-VPP OK SR.2 = WORD/BYTE WRITE SUSPEND STATUS (WBWSS) 1 = Word/Byte Write Suspended 0 = Word/Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = F-WP or F-RP Lock Detected, Operation Abort 0 = Unlocked
SR.3 does not provide a continuous indication of F-VPP level. The WSM (Write State Machine) interrogates and indicates the F-VPP level only after Block Erase or Word/Byte Write command sequences. SR.3 is not guaranteed to reports accurate feedback only when F-VPP VPPH. SR.1 does not provide a continuous indication of F-WP and FRP values. The WSM interrogates the F-WP and F-RP only after Block Erase or Word/Byte Write command sequences. It informs the system, depending on the attempted operation, if the F-WP is not VIH, F-RP is not VHH.
SR.0 is reserved for future use and should be masked out when SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) polling the status register.
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7. Memory Map for Flash Memory
Top Boot
[A19 ~ A0]
FFFFF FF000 FEFFF FE000 FDFFF FD000 FCFFF FC000 FBFFF FB000 FAFFF FA000 F9FFF F9000 F8FFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 1FFFF 10000 0FFFF 08000 07FFF 00000
[A19 ~ A-1]
4K-word/8K-byte Boot Block 0 4K-word/8K-byte Boot Block 1 4K-word/8K-byte Parameter Block 0 4K-word/8K-byte Parameter Block 1 4K-word/8K-byte Parameter Block 2 4K-word/8K-byte Parameter Block 3 4K-word/8K-byte Parameter Block 4 4K-word/8K-byte Parameter Block 5 32K-word/64K-byte Main Block 0 32K-word/64K-byte Main Block 1 32K-word/64K-byte Main Block 2 32K-word/64K-byte Main Block 3 32K-word/64K-byte Main Block 4 32K-word/64K-byte Main Block 5 32K-word/64K-byte Main Block 6 32K-word/64K-byte Main Block 7 32K-word/64K-byte Main Block 8 32K-word/64K-byte Main Block 9 32K-word/64K-byte Main Block 10 32K-word/64K-byte Main Block 11 32K-word/64K-byte Main Block 12 32K-word/64K-byte Main Block 13 32K-word/64K-byte Main Block 14 32K-word/64K-byte Main Block 15 32K-word/64K-byte Main Block 16 32K-word/64K-byte Main Block 17 32K-word/64K-byte Main Block 18 32K-word/64K-byte Main Block 19 32K-word/64K-byte Main Block 20 32K-word/64K-byte Main Block 21 32K-word/64K-byte Main Block 22 32K-word/64K-byte Main Block 23 32K-word/64K-byte Main Block 24 32K-word/64K-byte Main Block 25 32K-word/64K-byte Main Block 26 32K-word/64K-byte Main Block 27 32K-word/64K-byte Main Block 28 32K-word/64K-byte Main Block 29 32K-word/64K-byte Main Block 30
1FFFFF 1FE000 1FDFFF 1FC000 1FBFFF 1FA000 1F9FFF 1F8000 1F7FFF 1F6000 1F5FFF 1F4000 1F3FFF 1F2000 1F1FFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
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8. Absolute Maximum Ratings Symbol VCC VIN TA TSTG F-VPP F-RP Parameter Supply voltage Input voltage Operating temperature Storage temperature F-VPP voltage F-RP voltage 1,4,5 1,4,5 Notes 1,2 1,3,4,6 Ratings -0.2 to +4.0 -0.2 to VCC+0.3 -25 to +85 -55 to +125 -0.2 to +14.0 -0.5 to +14.0 Unit V V C C V V
Notes: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F-VPP. 3. Except F-RP. 4. -1.0V undershoot and VCC + 1.0V overshoot are allowed when the pulse width is less than 20 nsec. 5. +14.0V overshoot is allowed when the pulse width is less than 20 nsec. 6. VIN should not be over VCC + 0.3V. 9. Recommended DC Operating Conditions (TA = -25C to +85C) Symbol VCC VIH VIL VHH Notes: 1. VCC is the lower one of F-VCC and S-VCC. 2. VCC includes both F-VCC and S-VCC. 3. This voltage is applicable to F-RP Pin only. 10. Pin Capacitance (TA = 25C, f = 1MHz) Symbol CIN CI/O Parameter Input capacitance I/O capacitance Notes 1 1 Min. Typ. Max. 20 22 Unit pF pF Condition VIN = 0V VI/O = 0V Input Voltage 3 Parameter Supply Voltage Notes 2 1 Min. 2.7 2.2 -0.2 11.4 Typ. 3.0 Max. 3.6 VCC+0.2 0.8 12.6 Unit V V V V
Note: 1. Sampled but not 100% tested.
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11. DC Electrical Characteristics(6) DC Electrical Characteristics (TA = -25C to +85, VCC = 2.7V to 3.6V) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current 25 ICCS F-VCC Standby Current 2,4,9 0.2 ICCD F-VCC Reset Power-Down Current 4,9 5 2 10 25 ICCR F-VCC Read Current 3,4 30 ICCW ICCE F-VCC Word/Byte Write Current F-VCC Block Erase Current 7 7 17 17 6 4 4 7 7 2 10 0.1 12 8 10 15 200 5 40 25 200 30 3 35 Notes Min. Typ.
(1)
Max. 1.5 1.5 50
Unit
Conditions
A VIN = VCC or GND A VOUT = VCC or GND CMOS Input A F-CE = F-RP = F-V 0.2V CC TTL Input mA F-CE = F-RP = V IH F-RP = GND 0.2V A I OUT(F-RY/BY) = 0mA CMOS Input mA F-CE = GND, f = 5MHz, I OUT = 0mA TTL Input mA F-CE = V , f = 5MHz, I IL OUT = 0mA mA F-VPP = VPPH mA F-VPP = VPPH mA F-CE = VIH A F-VPP F-VCC A F-VPP > F-VCC A CMOS Input F-RP = GND 0.2V
ICCWS F-VCC Word/Byte Write or Block ICCES Erase Suspend Current IPPS IPPR IPPD IPPW IPPE F-VPP Standby or Read Current F-VPP Reset Power-Down Current F-VPP Word/Byte Write Current F-VPP Block Erase Current
mA F-VPP = VPPH mA F-VPP = VPPH A F-VPP = VPPH A S-CE1, S-CE2 S-VCC - 0.2V or S-CE2 0.2V
IPPWS F-VPP Word/Byte Write or Block Erase IPPES Suspend Current ISB ISB1 ICC1 S-VCC Standby Current S-VCC Standby Current S-VCC Operation Current
mA S-CE1 = VIH or S-CE2 = VIL S-CE1 = VIL, mA S-CE2 = VIH VIN = VIL or VIH S-CE1 = 0.2V, S-CE2 = SVCC -0.2V, mA VIN = S-VCC -0.2V or 0.2V tCYCLE =Min. II/O = 0mA
ICC2
S-VCC Operation Current
6
tCYCLE = 1s II/O = 0mA
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DC Electrical Characteristics (Continue) (TA = -25C to +85C, VCC = 2.7V to 3.6V) Symbol VIL VIH VOL VOH VPPLK VPPH VLKO VHH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage F-VPP Lockout during Normal Operations F-VPP Word/Byte Write Block Erase Operations F-VCC Lockout Voltage F-RP Unlock Voltage 8 Notes 7 7 2,7 2,7 5,7 2.7 1.5 11.4 12.6 2.4 1.5 3.6 Min. -0.2 2.2 Typ.(1) Max. 0.8 VCC +0.2 0.4 Unit V V V V V V V V Unavailable F-WP IOL = 2.0mA IOH = -1.0mA Conditions
Notes: 1. All currents are in RMS unless otherwise noted. Reference values at VCC = 3.0V and TA = +25C. 2. Includes F-RY/BY. 3. Automatic Power Savings (APS) for Flash Memory reduces typical ICCR to 3mA at 2.7V in static operation. 4. CMOS inputs are either VCC 0.2V or GND 0.2V. TTL inputs are either VIL or VIH. 5. Block erases and word/byte writes are inhibited when F-VPP VPPLK and not guaranteed in the range between VPPLK (Max.) and VPPH (Min.), and above VPPH (Max.). 6. VCC includes both F-VCC and S-VCC. 7. Sampled, not 100% tested. 8. F-RP connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. 9. F-BYTE is VCC 0.2V in word mode and is GND 0.2V in byte mode. F-WP is VCC 0.2V or GND 0.2V
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12. AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load
0V to 2.7V 5ns 1.35V 1TTL + CL (30pF)
12.2 Read Cycle (TA = -25C to +85C, F-VCC = 2.7V to 3.6V) Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFVQV tFLQZ tELFV Read Cycle Time Address to Output Delay F-CE to Output Delay F-RP High to Output Delay F-OE to Output Delay F-CE to Output in Low-Z F-CE High to Output in High-Z F-OE to Output in Low-Z F-OE High to Output in High-Z Output Hold form Address, F-CE or F-OE Change, Whichever Occurs First F-BYTE and A-1 to Output Delay F-BYTE Low to Output in High-Z F-CE to F-BYTE High or Low 0 100 30 5 0 20 1 0 45 1 Parameter Notes Min. 100 100 100 10 45 Max. Unit ns ns ns s ns ns ns ns ns ns ns ns ns
Note: 1. F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-CE without impact on tELQV.
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12.3 Write Cycle (F-WE Controlled)(1,5) (TA = -25C to +85C, F-VCC = 2.7V to 3.6V) Symbol tAVAV tPHWL tELWL tWLWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVPH tQVSL tFVWH tWHFV Write Cycle Time F-RP High Recovery to F-WE Going to Low F-CE Setup to F-WE Going Low F-WE Pulse Width 2 2 2 3 3 2 Parameter Notes Min. 100 10 0 50 100 100 100 50 50 0 0 0 30 100 0 2,4 2,4 2,4 0 0 0 50 100 Max. Unit ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tPHHWH F-RP VHH Setup to F-WE Going High F-WP VIH Setup to F-WE Going High F-VPP Setup to F-WE Going High Address Setup to F-WE Going High Data Setup to F-WE Going High Data Hold from F-WE High Address Hold from F-WE High F-CE Hold from F-WE High F-WE Pulse Width High F-WE High to F-RY/BY Going Low Write Recovery before Read F-VPP Hold from Valid SRD, F-RY/BY High-Z F-RP VHH Hold from Valid SRD, F-RY/BY High-Z F-WP VIH Hold from Valid SRD, F-RY/BY High-Z F-BYTE Setup to F-WE Going High F-BYTE Hold from F-WE High
Notes: 1. Read timing characteristics during block erase and word/byte write operations. Refer to AC Characteristics for read cycle. 2. Sampled, not 100% tested. 3. Refer to Section 5. Command Definitions for Flash Memory for valid AIN and DIN for block erase or word/byte write. 4. F-VPP should be held at VPPH until determination of block erase or word/byte write success (SR.1/3/4/5 = 0). 5. It is written when F-CE and F-WE are active. The address and data needed to execute a command are latched on the rising edge of F-WE or F-CE (Whichever goes high first).
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12.4 Write Cycle (F-CE Controlled)(1,2,6) (TA = -25C to +85C, F-VCC = 2.7V to 3.6V) Symbol tAVAV tPHEL tWLEL tELEH tPHHEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVPH tQVSL tFVEH tEHFV Write Cycle Time F-RP High Recovery to F-CE Going Low F-WE Setup to F-CE Going Low F-CE Pulse Width F-RP VHH Setup to F-CE Going High F-WP VIH Setup to F-CE Going High F-VPP Setup to F-CE Going High Address Setup to F-CE Going High Data Setup to F-CE Going High Data Hold from F-CE High Address Hold from F-CE High F-WE Hold from F-CE High F-CE Pulse Width High F-CE High to F-RY/BY Going Low Write Recovery before Read F-VPP Hold from Valid SRD, F-RY/BY High-Z F-RP VHH Hold from Valid SRD, F-RY/BY High-Z F-WP VIH Hold from Valid SRD, F-RY/BY High-Z F-BYTE Setup to F-WE Going High F-BYTE Hold from F-WE High 3,5 3,5 3,5 0 0 0 0 50 100 3 3 3 4 4 3 Parameter Notes Min. 100 10 0 70 100 100 100 50 50 0 0 0 25 100 Max. Unit ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Read timing characteristics during block erase and word/byte write operations. Refer to AC Characteristics for read cycle. 2. In systems where F-CE defines the write pulse width (within a longer F-WE timing waveform), all setup, hold and inactive F-WE times should be measured relative to the F-CE waveform. 3. Sampled, not 100% tested. 4. Refer to Section 5. Command Definitions for Flash Memory for valid AIN and DIN for block erase or word/byte write. 5. F-VPP should be held at VPPH until determination of block erase or word/byte write success (SR.1/3/4/5 = 0). 6. It is written when F-CE and F-WE are active. The address and data needed to execute a command are latched on the rising edge of F-WE or F-CE (Whichever goes high first).
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12.5 Block Erase and Word/Byte Write Performance(3) (TA = -25C to +85C, F-VCC = 2.7V to 3.6V) Symbol tWHQV1 tEHQV1 Parameter 32K/64K-Word/Byte Block 4K/8K-Word/Byte Block 32K-Word Block 4K-Word Block 64K-Byte Block 8K-Byte Block 32K/64K-Word/Byte Block 4K/8K-Word/Byte Block Notes 2 2 2 2 2 2 2 2 4 4 F-VPP = 2.7V to 3.6V Typ.(1) 55 60 1.8 0.3 3.6 0.6 1.2 0.5 7.5 19.3 8.6 23.6 Max. Unit
Word/Byte Write Time Block Write Time (at word mode) Block Write Time (at byte mode)
s s s s s s s s s s
tWHQV2 tEHQV2 tWHRZ1 tEHRZ1 tWHRZ2 tEHRZ2
Block Erase Time
Word/Byte Write Suspend Latency Time to Read Erase Suspend Latency Time to Read
Notes: 1. Reference values at TA = +25C and F-VCC = 3.0V, F-VPP = 3.0V. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled, not 100% tested. 4. A Latency time is required from issuing suspend command (F-WE or F-CE going high ) until F-RY/BY going High-Z or SR.7 going "1".
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12.6 Flash Memory AC Characteristics Timing Chart Read Cycle Timing Chart
Device VIH Address(A) VIL Standby Address Selection Address Stable tAVAV Data Valid
VIH F-CE(E) VIL tEHQZ
VIH F-OE(G) VIL tGHQZ
VIH F-WE(W) VIL tELQV tGLQX tELQX High - Z tAVQV
tGLQV
tOH High - Z
VOH Data(D/Q) VOL
Valid Output
F-VCC tPHQV VIH F-RP(P) VIL
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F-BYTE Timing Waveform
Device VIH Address(A) VIL Standby Address Selection Address Stable tAVAV Data Valid
VIH F-CE VIL tEHQZ
VIH F-OE(G) VIL tELFV tGLQV tFVQV VIH F-BYTE(F) VIL tELQV tGLQX tELQX Data(D/Q) (DQ0 - DQ7) VOH High - Z Data Output VOL tAVQV tFLQZ Data(D/Q) (DQ8 - DQ15) VOH High - Z Valid Output High - Z tOH Valid Output High - Z tGHQZ
VOL
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Write Cycle Timing Chart (F-WE Controlled)
1 VIH Address(A) VIL VIH F-CE(E) VIL tELWL VIH F-OE(G) VIL VIH F-WE(W) VIL VOH Data(D/Q) VOL VIH F-BYTE(F) VIL High-Z F-RY/BY(R) ("1") (SR.7) VOL ("0") VIH F-WP(S) VIL VHH F-RP(P) VIH VIL VPPH F-VPP(V) VPPLK tPHWL tPHHWH tQVPH tWHRL tWLWH tDVWH tWHDX High - Z DIN tFVWH DIN tWHFV Data Valid SRD DIN tWHWL tWHQV1,2,3,4 tWHEH tWHGL AIN tAVAV AIN tAVWH tWHAX 2 3 4 5 6
tSHWH
tQVSL
tVPWH
tQVVL
VIL Notes: 1. F-VCC power-up and standby. 2. Write each setup command. 3. Write each comfirm command or valid address and data. 4. Automated erase or program delay 5. Read status register data. 6. Write Read Array command.
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Write Cycle Timing Chart (F-CE Controlled)
1 VIH Address(A) VIL VIH F-CE(E) VIL VIH F-OE(G) VIL VIH F-WE(W) VIL tWLEL VOH Data(D/Q) VOL tFVEH VIH F-BYTE(F) VIL High-Z ("1") VOL ("0") VIH F-WP(S) VIL tPHWL VHH F-RP(P) VIH VIL VPPH F-VPP(V) VPPLK tPHHWH tQVPH tEHRL tEHFV High - Z tEHWH tEHDX DIN DIN Data Valid SRD DIN tEHQV1,2,3,4 tEHEL tELEH tDVEH tEHGL AIN tAVAV AIN tAVEH tEHAX 2 3 4 5 6
F-RY/BY(R) (SR.7)
tSHEH
tQVSL
tVPEH
tQVVL
VIL Notes: 1. F-VCC power-up and standby. 2. Write each setup command. 3. Write each comfirm command or valid address and data. 4. Automated erase or program delay 5. Read status register data. 6. Write Read Array command.
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12.7 Reset Operations(1,2) (TA = -25C to +85C, F-VCC = 2.7V to 3.6V) Symbol tPLPH tPLRZ tVPH Parameter F-RP Pulse Low Time (If F-RP is tied to F-VCC, this specification is not applicable.) F-RP Low to Reset during Block Erase or Word/Byte Write F-VCC = 2.7V to F-RP High 3 100 Notes Min. 100 23.6 Max. Unit ns s ns
Notes: 1. If F-RP is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100ns. 2. A reset time, tPHQV, is required from the later of F-RY/BY(SR.7) going High-Z ("1") or F-RP going high until outputs are valid. Refer to AC Characteristics-Read Cycle for tPHQV. 3. When the device power-up, holding F-RP low minimum 100ns is required after F-VCC has been in predefined range and also has been in stable there. AC Waveform for Reset Operation
High-Z F-RY/BY(R) ("1") (SR.7) VOL ("0") VIH F-RP(P) VIL tPLPH (A) Reset During Read Array Mode
High-Z F-RY/BY(R) ("1") (SR.7) VOL ("0") VIH F-RP(P) VIL
tPLRZ
tPLPH (B) Reset During Block Erase or Word/Byte Write
2.7V F-VCC VIL VIH F-RP(P) VIL (C) F-RP Rising Timing tVPH
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13. AC Electrical Characteristics for SRAM 13.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle (TA = -25C to +85C, S-VCC = 2.7V to 3.6V) Symbol tRC tAA tACE1 tACE2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ Read Cycle Time Address access time Chip enable access time (S-CE1) Chip enable access time (S-CE2) Output enable to output valid Output hold from address change S-CE1 Low to output active S-CE2 Low to output active S-OE Low to output active S-CE1 High to output in High-Z S-CE2 High to output in High-Z S-OE High to output in High-Z 1 1 1 1 1 1 10 10 10 5 0 0 0 25 25 25 Parameter Notes Min. 85 85 85 85 45 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns
0.4V to 2.2V 5ns 1.5V 1TTL + CL (30pF)(1)
Note: 1. Active output to High-Z and High-Z to output active tests specified for a 200mV transition from steady state levels into the test load. 13.3 Write Cycle (TA = -25C to +85C, S-VCC = 2.7V to 3.6V) Symbol tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Input data setup time Input data hold time S-WE High to output active S-WE Low to output in High-Z 1 1 Parameter Notes Min. 85 70 70 0 60 0 35 0 5 0 25 Max. Unit ns ns ns ns ns ns ns ns ns ns
Note: 1. Active output to High-Z and High-Z to output active tests specified for a 200mV transition from steady state levels into the test load. Rev. 1.00
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13.4 SRAM AC Characteristics Timing Chart Read cycle timing chart
Device Standby Address Selection Data V alid
VIH Address VIL
Address Stable
tRC
VIH S-CE1 VIL tLZ1,2 tHZ1,2
VIH S-CE2 VIL tACE1,2
tOLZ VIH S-OE VIL tOE
tOHZ
VIH S-WE VIL tAA VOH DQOUT VOL High - Z Data V alid High - Z tOH
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Write cycle timing chart (S-OE Controlled)
Device VIH Address VIL Standby Address Selection Address Stable tWC Data Valid
VIH S-OE VIL tAW VIH S-CE1 VIL tCW
(2)
tWR
(4)
VIH S-CE2 VIL tAS
(3)
tWP
(1)
VIH S-WE VIL tOHZ VOH DQOUT
(6,7)
Data Undefined
tOW
VOL tDW VIH DQIN
(5)
tDH
High - Z
Data Valid
VIL
Notes: 1. A write occurs during the overlap of a low S-CE1, a high S-CE2 and a low S-WE. A write begins at the latest transition among S-CE1 going low, S-CE2 going high and S-WE going low. A write ends at the earliest transition among S-CE1 going high, S-CE2 going low and S-WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going low or S-CE2 going high to the end of write. 3. tAS is measured from the address valid to beginning of write. 4. tWR is measured from the end of write to the address change. tWR applies in case a write ends at S-CE1 going high, S-CE2 going low or S-WE going high. 5. During this period DQ pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If S-CE1 goes low or S-CE2 goes high simultaneously with S-WE going low or after S-WE going low, the outputs remain in high impedance state. 7. If S-CE1 goes high or S-CE2 goes low simultaneously with S-WE going high or before S-WE going high, the outputs remain in high impedance state.
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Write cycle timing chart (S-OE Low fixed)
Device VIH Address VIL Standby Address Selection Address Stable tWC tAW VIH S-OE VIL tWR
(4)
Data Valid
VIH S-CE1 VIL tAS
(3)
tCW
(2)
VIH S-CE2 VIL tAS VIH S-WE VIL tWZ VOH DQOUT
(6,7) (3)
tWP
(1)
tOW
Data Undefined
VOL tDW VIH DQIN
(5)
tDH
High - Z
Data Valid
VIL
Notes: 1. A write occurs during the overlap of a low S-CE1, a high S-CE2 and a low S-WE. A write begins at the latest transition among S-CE1 going low, S-CE2 going high and S-WE going low. A write ends at the earliest transition among S-CE1 going high, S-CE2 going low and S-WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going low or S-CE2 going high to the end of write. 3. tAS is measured from the address valid to beginning of write. 4. tWR is measured from the end of write to the address change. tWR applies in case a write ends at S-CE1 going high, S-CE2 going low or S-WE going high. 5. During this period DQ pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If S-CE1 goes low or S-CE2 goes high simultaneously with S-WE going low or after S-WE going low, the outputs remain in high impedance state. 7. If S-CE1 goes high or S-CE2 goes low simultaneously with S-WE going high or before S-WE going high, the outputs remain in high impedance state.
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14. Data Retention Characteristics for SRAM (TA = -25C to +85C) Symbol VCCDR Parameter Data Retention Supply voltage Note 2 Min. 2.0 Typ.(1) Max. 3.6 Unit V Conditions S-CE2 0.2V or S-CE1 S-VCC - 0.2V S-VCC = 3.0V S-CE2 0.2V or S-CE1 S-VCC - 0.2V
ICCDR tCDR tR
Data Retention Supply current Chip enable setup time Chip enable hold time
2 0 5
1
30
A ns ms
Notes 1. Reference value at TA = 25C, S-VCC = 3.0V. 2. S-CE1 S-VCC - 0.2V, S-CE2 S-VCC - 0.2V (S-CE1 controlled) or S-CE2 0.2V (S-CE2 controlled). Data Retention timing chart (S-CE1 Controlled)(1)
Data Retention mode S-VCC 2.7V tCDR tR
2.2V VCCDR
S-CE1 0V
S-CE1
S-VCC-0.2V
Note: 1. To control the data retention mode at S-CE1, fix the input level of
S-CE2 between VCCDR and VCCDR-0.2V or 0V or 0.2V and during the data retention mode.
Data Retention timing chart (S-CE2 Controlled)
Data Retention mode 2.7V S-CE2 VCCDR
S-VCC tCDR
tR
0.4V 0V S-CE2
0.2V
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15. Notes This product is a stacked CSP package that a 16M (x8/x16) bit Flash Memory and a 2M (x8) bit SRAM are assembled into. - Supply Power Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3V. - Power Supply and Chip Enable of Flash Memory and SRAM S-CE1 should not be "low" and S-CE2 should not be "high" when F-CE is "low" simultaneously. If the two memories are active together, possibly they may not operate normally by interference noises or data collision on DQ bus. Both F-VCC and S-VCC are needed to be applied by the recommended supply voltage at the same time expect SRAM data retention mode. - Power Up Sequence When turning on Flash memory power supply, keep F-RP "low". After F-VCC reaches over 2.7V, keep F-RP "low" for more than 100nsec. - Device Decoupling The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2).
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16. Flash Memory Data Protection
Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate. s The below describes data protection method. 1. Protecting data in specific block * By setting a F-WP to low, only the boot block can be protected against overwriting. Parameter and main blocks cannot be locked. System program, etc., can be locked by storing them in the boot block. * When a high voltage (VHH) is applied to F-RP, overwrite operation is enabled for all blocks. * For further information on controlling of F-WP and F-RP refer to the specification. (See Chapter 5. Command Definitions for Flash Memory) 2. Data Protection through F-VPP * When the level of F-VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. * For the lockout voltage, refer to specification. (See Chapter 11. DC Electrical Characteristics) s Data Protection during voltage transition
1. Data protection thorough F-RP
* When the F-RP is kept low during power up and power down sequence, write operation on the flash memory is disabled, write protecting all blocks. * For the details of F-RP control, refer to the specification. (See Chapter 12. AC Electrical Characteristics for Flash Memory)
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17. Design Considerations
1. Power Supply Decoupling To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1F ceramic capacitor connected between its F-VCC and GND and between its F-VPP and GND. Low inductance capacitors should be placed as close as possible to package leads. 2. F-VPP Trace on Printed Circuit Boards Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the F-VPP Power Supply trace. Use similar trace widths and layout considerations given to the F-VCC power bus. 3. The Inhibition of Overwrite Operation Please do not execute reprogramming "0" for the bit which has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprogramming "0" to the data which has been programed "1". * Program "0" for the bit in which you want to change data from "1" to "0". * Program "1" for the bit which has already been programmed "0". For example, changing data from "1011110110111101" to "1010110110111100" requires "1110111111111110" programming. 4. Power Supply Block erase and word/byte write with an invalid F-VPP (See Chapter 11.DC Electrical Characteristics) produce spurious results and should not be attempted. Device operations at invalid F-VCC voltage (See Chapter 11.DC Electrical Characteristics) produce spurious results and should not be attempted.
18. Related Document Information(1) Document No. FUM99903 Document Name
LH28F400BV, LH28F800BV, LH28F160BV Appendix
Note: 1. International customers should contact their local SHARP or distribution sales offices.
Rev. 1.00
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Fax: (360) 834-8903 http://www.sharpsma.com
SHARP Microelectronics Europe Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Fax: (49) 40 2376-2232 http://www.sharpsme.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: +81-743-65-1321 Fax: +81-743-65-1532 http://www.sharp.co.jp

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