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K6F8016V3A Family
Document Title
CMOS SRAM
512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial draft -Design Target Finalize
Draft Date
July 4, 2001
Remark
Preliminary
1.0
September 26, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 September 2001
K6F8016V3A Family
FEATURES
* Process Technology: Full CMOS * Organization: 512K x16 * Power Supply Voltage: 3.0~3.6V * Low Data Retention Voltage: 1.5V(Min) * Three State Outputs * Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6F8016V3A families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support various operating temperature ranges. The families also support low data retention voltage for battery back-up operation with low data retention current.
512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
PRODUCT FAMILY
Power Dissipation Product Family K6F8016V3A-F Operating Temperature Industrial(-40~85C) Vcc Range 3.0~3.6V Speed Standby (ISB1, Typ.) 0.5A2) Operating (ICC1, Max) 4mA PKG Type 44-TSOP2-400F/R
551)/70ns
1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=3.3V, TA=25C and not 100% tested.
PIN DESCRIPTION
A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 A8 A9 A10 A11 A12 A13 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 A8 A9 A10 A11 A12 A13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A18 A17 A16 A15 A14
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
Vcc Vss Row Addresses
44-TSOP2 Forward
44-TSOP2 Reverse
Row select
Memory array 1024 rows 512x16 columns
I/O1~I/O8
Data cont Data cont Data cont
I/O Circuit Column select
I/O9~I/O16
Name CS OE WE A0~A18
Function Chip Select Input Output Enable Input Write Enable Input Address Inputs
Name Vcc Vss UB LB
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8)
CS1 CS2 OE WE UB LB
Column Addresses
Control Logic
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.0 September 2001
K6F8016V3A Family
PRODUCT LIST
Industrial Temperature Products(-40~85C) Part Name K6F8016V3A-TF55 K6F8016V3A-TF70 K6F8016V3A-RF55 K6F8016V3A-RF70 Function
CMOS SRAM
44-TSOP2-F, 55ns, 3.3V 44-TSOP2-F, 70ns, 3.3V 44-TSOP2-R, 55ns, 3.3V 44-TSOP2-R, 70ns, 3.3V
FUNCTIONAL DESCRIPTION
CS H L L L L L L L L OE X H X L L L X X X WE X H X H H H L L L LB X X H L H L L H L UB X X H H L L H L L I/O1~8 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Active Active Active Active Active Active Active Active
Note : X means dont care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V(max.4.0V) -0.2 to 4.0 1.0 -65 to 150 -40 to 85 Unit V V W C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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K6F8016V3A Family
RECOMMENDED DC OPERATING CONDITIONS 1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 3.0 0 2.2 -0.33) Typ 3.3 0 -
CMOS SRAM
Max 3.6 0 Vcc+0.3 0.6
2)
Unit V V V V
Note: 1. Industrial products: TA=-40 to 85C, otherwise specified. 2. Overshoot: VCC+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB1 VIN=Vss to Vcc CS=VIH, or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, WE=VIH, VIN=VIH or VIL Cycle time=1s, 100%duty, IIO=0mA, CS0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CSVcc-0.2V, Other inputs=0~Vcc Test Conditions Min -1 -1 2.4 Typ1) 0.5 Max 1 1 2 4 45 0.4 30 Unit A A mA mA mA V V A
1. Typical values are measured at VCC=3.3V, TA=25C and not 100% tested.
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K6F8016V3A Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V
AC CHARACTERISTICS (Vcc=3.0~3.6V)
Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Read Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 55 10 5 5 0 0 0 10 55 45 0 45 45 40 0 0 25 0 5 55ns Max 55 55 25 25 20 20 20 20 Min 70 10 5 5 0 0 0 10 70 60 0 60 60 50 0 0 30 0 5 70ns Max 70 70 35 35 25 25 25 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V
1) 1)
Min 1.5 0 tRC
Typ2) 0.5 -
Max 3.6 6 -
Unit V A ns
Vcc=1.5V, CS1Vcc-0.2V
See data retention waveform
1. CS1Vcc-0.2V,CS2Vcc-0.2V(CS1 controlled) or CS2Vcc-0.2V(CS2 controlled). 2. Typical value are measured at TA=25C and not 100% tested.
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K6F8016V3A Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
(Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Data Valid
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH)
tRC Address tAA tCO tOH
CS
tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ
Data out
High-Z
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 1.0 September 2001
K6F8016V3A Family
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
CMOS SRAM
tWC Address tCW(2) CS tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH High-Z tWR(4)
UB, LB
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC Address tAS(3) CS tAW tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 1.0 September 2001
K6F8016V3A Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC Address tCW(2) CS tAW tBW tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
CMOS SRAM
UB, LB
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 3.0V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V CS GND
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Revision 1.0 September 2001
K6F8016V3A Family
PACKAGE DIMENSION
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
CMOS SRAM
Unit: millimeters
0~8 0.25 ( ) 0.010
#44
#23 0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
10.16 0.400
( 0.50 ) 0.020
#1
#22 1.000.10 0.0390.004 1.20 MAX. 0.047
0.15 0.0
0 + 0.1 5 - 0.0 .0 04 +0 06 - 0.002
18.81 MAX. 0.741 18.410.10 0.7250.004
( 0.805 ) 0.032
0.35 0.10 0.0140.004
0.80 0.0315
0.05 MIN. 0.002
0.10 MAX 0.004
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
( #1 #22 0.25 ) 0.010
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
10.16 0.400
( 0.50 ) 0.020
#44
#23 1.000.10 0.0390.004 1.20 MAX. 0.047
0.15 0
0 + 0.1 5 - 0.0 .004 +0 02 .006 - 0.0
18.81 MAX. 0.741 18.41 0.10 0.7250.004
( 0.805 ) 0.032
0.350.10 0.0140.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004 MAX
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Revision 1.0 September 2001

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