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80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
s High-Performance Embedded Architecture s Built-in Interrupt Controller
-- 16 MIPS* Burst Execution at 16 MHz -- 5 MIPS Sustained Execution at 16 MHz s 512-Byte On-Chip Instruction Cache -- Direct Mapped -- Parallel Load/Decode for Uncached Instructions s Multiple Register Sets -- Sixteen Global 32-Bit Registers -- Sixteen Local 32-Bit Registers -- Four Local Register Sets Stored On-Chip -- Register Scoreboarding s Pin Compatible with 80960SA
-- 4 Direct Interrupt Pins -- 31 Priority Levels, 256 Vectors s Built-In Floating Point Unit -- Fully IEEE 754 Compatible s Easy to Use, High Bandwidth 16-Bit Bus -- 25.6 Mbytes/s Burst -- Up to 16 Bytes Transferred per Burst s 32-Bit Address Space, 4 Gigabytes
s 80-Lead Quad Flat Pack (EIAJ QFP)
-- 84-Lead Plastic Leaded Chip Carrier (PLCC) s Software Compatible with 80960KA/KB/CA/CF Processors
The 80960SB is a member of Intel's i960(R) 32-bit processor family, which is designed especially for low cost embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in interrupt controller. The 80960SB has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess of 5 million instructions per second*. The 80960SB is well-suited for a wide range of cost sensitive embedded applications including non-impact printers, network adapters and I/O controllers.
FOUR 80-BIT FP REGISTERS 80-BIT FPU SIXTEEN 32-BIT GLOBAL REGISTERS 64- BY 32-BIT LOCAL REGISTER CACHE 32-BIT INSTRUCTION EXECUTION UNIT
INSTRUCTION FETCH UNIT
512-BYTE INSTRUCTION CACHE
INSTRUCTION DECODER
MICROINSTRUCTION SEQUENCER
MICROINSTRUCTION ROM
32-BIT BUS CONTROL LOGIC
32-BIT ADDRESS 16-BIT BURST BUS
Figure 1. The 80960SB Processor's Highly Parallel Architecture
* Relative to Digital Equipment Corporation's VAX-11/780 at 1 MIPS (VAX-11TM is a trademark of Digital Equipment Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. (c) INTEL CORPORATION, 1993 November 1993 Order Number: 272207-002
80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
CONTENTS
(R)
PAGE
1.0 THE i960 PROCESSOR ...........................................................................................................................1 1.1 Key Performance Features .................................................................................................................2 1.1.1 Memory Space And Addressing Modes ................................................................................... 4 1.1.2 Data Types ...............................................................................................................................4 1.1.3 Large Register Set ...................................................................................................................4 1.1.4 Multiple Register Sets ..............................................................................................................5 1.1.5 Instruction Cache .....................................................................................................................5 1.1.6 Register Scoreboarding ........................................................................................................... 5 1.1.7 Floating-Point Arithmetic .......................................................................................................... 6 1.1.8 High Bandwidth Bus ................................................................................................................6 1.1.9 Interrupt Handling ....................................................................................................................7 1.1.10 Debug Features .....................................................................................................................7 1.1.11 Fault Detection .......................................................................................................................7 1.1.12 Built-in Testability ...................................................................................................................7 1.1.13 CHMOS .................................................................................................................................. 7 2.0 ELECTRICAL SPECIFICATIONS............................................................................................................. 11 2.1 Power and Grounding ....................................................................................................................... 11 2.2 Power Decoupling Recommendations .............................................................................................. 11 2.3 Connection Recommendations ......................................................................................................... 11 2.4 Characteristic Curves ....................................................................................................................... 11 2.5 Test Load Circuit ............................................................................................................................... 13 2.6 ABSOLUTE MAXIMUM RATINGS* .................................................................................................. 14 2.7 DC Characteristics ............................................................................................................................ 14 2.8 AC Specifications .............................................................................................................................. 15 3.0 MECHANICAL DATA ............................................................................................................................... 20 3.1 Packaging ......................................................................................................................................... 20 3.2 Pin Assignment ................................................................................................................................. 20 3.3 Pinout ................................................................................................................................................ 22 3.4 Package Thermal Specifications ...................................................................................................... 26 4.0 WAVEFORMS ........................................................................................................................................... 27 5.0 REVISION HISTORY ................................................................................................................................ 33
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LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22
PAGE
The 80960SB Processor's Highly Parallel Architecture ................................................................ 0 80960SB Programming Environment ........................................................................................... 1 Instruction Formats ...................................................................................................................... 4 Multiple Register Sets Are Stored On-Chip .................................................................................. 6 Connection Recommendation for LOCK .................................................................................... 11 Typical Supply Current vs. Case Temperature ........................................................................... 12 Typical Current vs. Frequency (Room Temp) ............................................................................. 12 Typical Current vs. Frequency (Hot Temp) ................................................................................. 13 Capacitive Derating Curve ......................................................................................................... 13 Test Load Circuit for Three-State Output Pins ............................................................................ 13 Drive Levels and Timing Relationships for 80960SB Signals ..................................................... 15 Processor Clock Pulse (CLK2) ................................................................................................... 18 RESET Signal Timing ................................................................................................................. 18 HOLD Timing .............................................................................................................................. 19 80-Lead EIAJ Quad Flat Pack (QFP) Package .......................................................................... 20 84-Lead Plastic Leaded Chip Carrier (PLCC) Package ............................................................. 21 Non-Burst Read and Write Transactions Without Wait States .................................................... 27 Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States ................................ 28 Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred) .............................. 29 Accesses Generated by Quad Word Read Bus Request, Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States 30
Interrupt Acknowledge Cycle ...................................................................................................... 31 Cold Reset Waveform ................................................................................................................ 32
LIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 80960SB Instruction Set .............................................................................................................. 3 Memory Addressing Modes ......................................................................................................... 4 Sample Floating-Point Execution Times (s) at 16 MHz .............................................................. 6 80960SB Pin Description: Bus Signals ........................................................................................ 8 80960SB Pin Description: Support Signals ................................................................................ 10 DC Characteristics ..................................................................................................................... 14 80960SB AC Characteristics (10 MHz) ...................................................................................... 16 80960SB AC Characteristics (16 MHz) ...................................................................................... 17 80960SB QFP Pinout -- In Pin Order ........................................................................................ 22 80960SB QFP Pinout -- In Signal Order ................................................................................... 23 80960SB PLCC Pinout -- In Pin Order ...................................................................................... 24 80960SB PLCC Pinout -- In Signal Order ................................................................................. 25 80960SB QFP Package Thermal Characteristics ...................................................................... 26 80960SB PLCC Package Thermal Characteristics .................................................................... 26
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80960SB
1.0
THE i960(R) PROCESSOR
The 80960SB is a member of the 32-bit architecture from Intel known as the i960 processor family. These microprocessors were especially designed to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and networking. These types of applications require high integration, low power consumption, quick interrupt response times and high performance.
Since time to market is critical, embedded microprocessors need to be easy to use in both hardware and software designs. All members of the i960 processor family share a common core architecture which utilizes RISC technology so that, except for special functions, the family members are object-code compatible. Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market.
0000 0000H
FFFF FFFFH
ADDRESS SPACE ARCHITECTURALLY DEFINED DATA STRUCTURES
FETCH INSTRUCTION CACHE
LOAD
STORE
INSTRUCTION STREAM INSTRUCTION EXECUTION PROCESSOR STATE REGISTERS INSTRUCTION POINTER ARITHMETIC CONTROLS PROCESS CONTROLS TRACE CONTROLS SIXTEEN 32-BIT LOCAL REGISTERS
r0 r15
SIXTEEN 32-BIT GLOBAL REGISTERS
g0 g15
FOUR 80-BIT FLOATING POINT REGISTERS CONTROL REGISTERS
Figure 2. 80960SB Programming Environment
1
80960SB
1.1
Key Performance Features
The 80960SB architecture is based on the most recent advances in microprocessor technology and is grounded in Intel's long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960SB's exceptional performance: 1. Large Register Set. Having a large number of registers reduces the number of times that a processor needs to access memory. Modern compilers can take advantage of this feature to optimize execution speed. For maximum flexibility, the 80960SB provides thirty-two 32-bit registers and four 80-bit floating point registers. (See Figure 2.) 2. Fast Instruction Execution. Simple functions make up the bulk of instructions in most programs so that execution speed can be improved by ensuring that these core instructions are executed as quickly as possible. The most frequently executed instructions -- such as register-register moves, add/subtract, logical operations and shifts -- execute in one to two cycles. (Table 1 contains a list of instructions.) 3. Load/Store Architecture. One way to improve execution speed is to reduce the number of times that the processor must access memory to perform an operation. As with other processors based on RISC technology, the 80960SB has a Load/Store architecture. As such, only the LOAD and STORE instructions reference memory; all other instructions operate on registers. This type of architecture simplifies instruction decoding and is used in combination with other techniques to increase parallelism. 4. Simple Instruction Formats. All instructions in the 80960SB are 32 bits long and must be aligned on word boundaries. This alignment makes it possible to eliminate the instruction alignment stage in the pipeline. To simplify the instruction decoder, there are only five instruction formats; each instruction uses only one format. (See Figure 3.)
5. Overlapped Instruction Execution. Load operations allow execution of subsequent instructions to continue before the data has been returned from memory, so that these instructions can overlap the load. The 80960SB manages this process transparently to software through the use of a register scoreboard. Conditional instructions also make use of a scoreboard so that subsequent unrelated instructions may be executed while the conditional instruction is pending. 6. Integer Execution Optimization. When the result of an arithmetic execution is used as an operand in a subsequent calculation, the value is sent immediately to its destination register. At the same time, the value is put on a bypass path to the ALU, thereby saving the time that otherwise would be required to retrieve the value for the next operation. 7. Bandwidth Optimizations. The 80960SB gets optimal use of its memory bus bandwidth because the bus is tuned for use with the onchip instruction cache: instruction cache line size matches the maximum burst size for instruction fetches. The 80960SB automatically fetches four words in a burst and stores them directly in the cache. Due to the size of the cache and the fact that it is continually filled in anticipation of needed instructions in the program flow, the 80960SB is relatively insensitive to memory wait states. The benefit is that the 80960SB delivers outstanding performance even with a low cost memory system. 8. Cache Bypass. If a cache miss occurs, the processor fetches the needed instruction then sends it on to the instruction decoder at the same time it updates the cache. Thus, no extra time is spent to load and read the cache.
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80960SB
Table 1. 80960SB Instruction Set Data Movement Load Store Move Load Address Add Subtract Multiply Divide Remainder Modulo Shift Extended Multiply Extended Divide Arithmetic And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Rotate Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Debug Modify Trace Controls Mark Force Mark Miscellaneous Atomic Add Atomic Modify Flush Local Registers Modify Arithmetic Controls Scan Byte for Equal Test Condition Code Move Add with Carry Subtract with Carry Branch Unconditional Branch Conditional Branch Compare and Branch Call Call Extended Call System Return Branch and Link Decimal Floating Point Move Real Scale Round Square Root Sine Cosine Tangent Arctangent Log Log Binary Log Natural Exponent Classify Copy Real Extended Compare Synchronous Synchronous Load Synchronous Move Conversion Convert Real to Integer Convert Integer to Real Call/Return Fault Conditional Fault Synchronize Faults Logical Bit and Bit Field Set Bit Clear Bit Not Bit Check Bit Alter Bit Scan For Bit Scan Over Bit Extract Modify
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80960SB
Control
Opcode
Displacement
Compare and Branch Register to Register
Opcode
Reg/Lit
Reg
M
Displacement
Opcode
Reg
Reg/Lit
Modes
Ext'd Op
Reg/Lit
Memory Access--Short Memory Access--Long
Opcode
Reg
Base
M
X
Offset
Opcode
Reg
Base
Mode
Scale
xx
Offset
Displacement
Figure 3. Instruction Formats 1.1.1 Memory Space And Addressing Modes 1.1.2 Data Types
The 80960SB offers a linear programming environment so that all programs running on the processor are contained in a single address space. Maximum address space size is 4 Gigabytes (232 bytes). For ease of use the 80960SB has a small number of addressing modes, but includes all those necessary to ensure efficient execution of high-level languages such as C. Table 2 lists the memory addressing modes. Table 2. Memory Addressing Modes * * * * * * * * 12-Bit Offset 32-Bit Offset Register-Indirect Register + 12-Bit Offset Register + 32-Bit Offset Register + (Index-Register x Scale-Factor) Register x Scale Factor + 32-Bit Displacement Register + (Index-Register x Scale-Factor) + 32-Bit Displacement
The 80960SB recognizes the following data types: Numeric: * * * 8-, 16-, 32- and 64-bit ordinals 8-, 16-, 32- and 64-bit integers 32-, 64- and 80-bit real numbers
Non-Numeric: * * * * Bit Bit Field Triple Word (96 bits) Quad-Word (128 bits) Large Register Set
1.1.3
The 80960SB programming environment includes a large number of registers. In fact, 32 registers are available at any time. The availability of this many registers greatly reduces the number of memory accesses required to perform algorithms, which leads to greater instruction processing speed. There are two types of general-purpose register: local and global. The global registers consist of sixteen 32-bit registers (g0 though g15) and four
Scale-Factor is 1, 2, 4, 8 or 16 4
80960SB
80-bit registers (fp0 through fp3). These registers perform the same function as the general-purpose registers provided in other popular microprocessors. The term global refers to the fact that these registers retain their contents across procedure calls. The local registers, on the other hand, are procedure specific. For each procedure call, the 80960SB allocates 16 local registers (r0 through r15). Each local register is 32 bits wide. Any register can also be used for single or double-precision floating-point operations; the 80-bit floating-point registers are provided for extended precision. 1.1.4 Multiple Register Sets
jumping back and forth in the same small section of code. Thus, by maintaining a block of instructions in cache, the number of memory references required to read instructions into the processor is greatly reduced. To load the instruction cache, instructions are fetched in 16-byte blocks; up to four instructions can be fetched at one time. An efficient prefetch algorithm increases the probability that an instruction will already be in the cache when it is needed. Code for small loops often fits entirely within the cache, leading to a great increase in processing speed since further memory references might not be necessary until the program exits the loop. Similarly, when calling short procedures, the code for the calling procedure is likely to remain in the cache so it will be there on the procedure's return. 1.1.6 Register Scoreboarding
To further increase the efficiency of the register set, multiple sets of local registers are stored on-chip (See Figure 4). This cache holds up to four local register frames, which means that up to three procedure calls can be made without having to access the procedure stack resident in memory. Although programs may have procedure calls nested many calls deep, a program typically oscillates back and forth between only two to three levels. As a result, with four stack frames in the cache, the probability of having a free frame available on the cache when a call is made is very high. In fact, runs of representative C-language programs show that 80% of the calls are handled without needing to access memory. If four or more procedures are active and a new procedure is called, the 80960SB moves the oldest local register set in the stack-frame cache to a procedure stack in memory to make room for a new set of registers. Global register g15 is the frame pointer (FP) to the procedure stack. Global and floating point registers are not exchanged on a procedure call, but retain their contents, making them available to all procedures for fast parameter passing. 1.1.5 Instruction Cache
The instruction decoder is optimized in several ways. One optimization method is the ability to overlap instructions by using register scoreboarding. Register scoreboarding occurs when a LOAD moves a variable from memory into a register. When the instruction initiates, a scoreboard bit on the target register is set. Once the register is loaded, the bit is reset. In between, any reference to the register contents is accompanied by a test of the scoreboard bit to ensure that the load has completed before processing continues. Since the processor does not need to wait for the LOAD to complete, it can execute additional instructions placed between the LOAD and the instruction that uses the register contents, as shown in the following example: ld data_2, r4 ld data_2, r5 Unrelated instruction Unrelated instruction add r4, r5, r6 In essence, the two unrelated instructions between LOAD and ADD are executed "for free" (i.e., take no apparent time to execute) because they are executed while the register is being loaded. Up to three load instructions can be pending at one time with three corresponding scoreboard bits set. By exploiting this feature, system programmers and compiler writers have a useful tool for optimizing execution speed.
To further reduce memory accesses, the 80960SB includes a 512-byte on-chip instruction cache. The instruction cache is based on the concept of locality of reference; most programs are not usually executed in a steady stream but consist of many branches, loops and procedure calls that lead to
5
80960SB
ONE OF FOUR LOCAL REGISTER SETS
REGISTER CACHE LOCAL REGISTER SET
r0
31
r 0 15
Figure 4. Multiple Register Sets Are Stored On-Chip 1.1.7 Floating-Point Arithmetic Table 3. Sample Floating-Point Execution Times (s) at 16 MHz Function Add Subtract Multiply Divide Square Root Arctangent Exponent Sine Cosine 32-Bit 0.6 0.6 1.1 2.0 5.8 15.8 17.7 23.8 23.8 64-Bit 0.8 0.8 2.0 4.5 6.1 20.5 19.5 25.9 25.9
In the 80960SB, floating-point arithmetic has been made an integral part of the architecture. Having the floating-point unit integrated on chip provides two advantages. First, it improves the performance of the chip for floating-point applications, since no additional bus overhead is associated with floatingpoint calculations, thereby leaving more time for other bus operations such as I/O. Second, the cost of using floating-point operations is reduced because a separate coprocessor chip is not required. The 80960SB floating-point (real-number) data types include single-precision (32-bit), double-precision (64-bit) and extended precision (80-bit) floating-point numbers. Any registers may be used to execute floating-point operations. The processor provides hardware support for both mandatory and recommended portions of IEEE Standard 754 for floating-point arithmetic, including all arithmetic, exponential, logarithmic and other transcendental functions. Table 3 shows execution times for some representative instructions. 1.1.8 High Bandwidth Bus
memory and I/O subsystem interfaces. The processor uses the bus to fetch instructions, manipulate memory and respond to interrupts. Bus features include: * * * 16-bit data path multiplexed onto the lower bits of the 32-bit address path Eight 16-bit half-word burst capability which allows transfers from 1 to 16 bytes at a time High bandwidth reads and writes with 25.6 MBytes/s burst (at 16 MHz)
The 80960SB CPU resides on a high-bandwidth address/data bus. The bus provides a direct communication path between the processor and the
Table 4 defines bus signal names and functions; Table 5 defines other component-support signals such as interrupt lines.
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80960SB
1.1.9
Interrupt Handling
1.1.11 Fault Detection The 80960SB has an automatic mechanism to handle faults. Fault types include floating point, trace and arithmetic faults. When the processor detects a fault, it automatically calls the appropriate fault handling routine and saves the current instruction pointer and necessary state information to make efficient recovery possible. Like interrupt handling routines, fault handling routines are usually written to meet the needs of specific applications and are often included as part of the operating system or kernel. For each of the fault types, there are numerous subtypes that provide specific information about a fault. For example, a floating point fault may have the subtype set to an Overflow or Zero-Divide fault. The fault handler can use this specific information to respond correctly to the fault. 1.1.12 Built-in Testability Upon reset, the 80960SB automatically conducts an exhaustive internal test of its major blocks of logic. Then, before executing its first instruction, it does a zero check sum on the first eight words in memory to ensure that the memory image was programmed correctly. If a problem is discovered at any point during the self-test, the 80960SB asserts its FAIL pin and will not begin program execution. Self test takes approximately 47,000 cycles to complete. System manufacturers can use the 80960SB's selftest feature during incoming parts inspection. No special diagnostic programs need to be written. The test is both thorough and fast. The self-test capability helps ensure that defective parts are discovered before systems are shipped and, once in the field, the self-test makes it easier to distinguish between problems caused by processor failure and problems resulting from other causes. 1.1.13 CHMOS The 80960SB is fabricated using Intel's CHMOS IV (Complementary High Speed Metal Oxide Semiconductor) process. The 80960SB is available at 10 MHz in the QFP package and at 10 and 16 MHz in the PLCC package.
The 80960SB can be interrupted in one of two ways: by the activation of one of four interrupt pins or by sending a message on the processor's data bus. The 80960SB is unusual in that it automatically handles interrupts on a priority basis and can keep track of pending interrupts through its on-chip interrupt controller. Two of the interrupt pins can be configured to provide 8259A-style handshaking for expansion beyond four interrupt lines. 1.1.10 Debug Features The 80960SB has built-in debug capabilities. There are two types of breakpoints and six trace modes. Debug features are controlled by two internal 32-bit registers, the Process-Controls Word and the TraceControls Word. By setting bits in these control words, a software debug monitor can closely control how the processor responds during program execution. The 80960SB provides two hardware breakpoint registers on-chip which, by using a special command, can be set to any value. When the instruction pointer matches either breakpoint register value, the breakpoint handling routine is automatically called. The 80960SB also provides software breakpoints through the use of two instructions: MARK and FMARK. These can be placed at any point in a program and cause the processor to halt execution at that point and call the breakpoint handling routine. The breakpoint mechanism is easy to use and provides a powerful debugging tool. Tracing is available for instructions (single step execution), calls and returns and branching. Each trace type may be enabled separately by a special debug instruction. In each case, the 80960SB executes the instruction first and then calls a trace handling routine (usually part of a software debug monitor). Further program execution is halted until the routine completes, at which time execution resumes at the next instruction. The 80960SB's tracing mechanisms, implemented completely in hardware, greatly simplify the task of software test and debug.
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80960SB
Table 4. 80960SB Pin Description: Bus Signals (Sheet 1 of 2) NAME CLK2 A31:16 AD15:1, D0 TYPE I O T.S. I/O T.S. O T.S. DESCRIPTION SYSTEM CLOCK provides the fundamental timing for 80960SB systems. It is divided by two inside the 80960SB to generate the internal processor clock. ADDRESS BUS carries the upper 16 bits of the 32-bit physical address to memory. It is valid throughout the burst cycle; no latch is required. ADDRESS/DATA BUS carries the low order 32-bit addresses and 16-bit data to and from memory. AD15:4 must be latched since the cycle following the address cycle carries data on the bus. ADDRESS BUS carries the word addresses of the 32-bit address to memory. These three bits are incremented during a burst access indicating the next word address of the burst access. Note that A3:1 are duplicated with AD3:1 during the address cycle. ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is asserted during a Ta cycle and deasserted before the beginning of the Td state. It is active HIGH and floats to a high impedance state during a hold cycle (Th). ADDRESS STATUS indicates an address state. AS is asserted every Ta state and deasserted during the following Td state. AS is driven HIGH during reset. WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read. It is latched on-chip and remains valid during Td cycles. DATA ENABLE is asserted during Td cycles and indicates transfer of data on the AD lines. The AD lines should not be driven by an external source unless DEN is asserted. When DEN is asserted, outputs from the previous cycle are guaranteed to be three-stated. In addition, DEN deasserted indicates inputs have been captured; therefore input hold times can be disregarded. DEN is driven HIGH during reset. DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment; it is high during Ta and Td cycles for a write. DT/R never changes state when DEN is asserted. DT/R is driven HIGH during reset. READY indicates that data on AD lines can be sampled or removed. If READY is not asserted during a Td cycle, the Td cycle is extended to the next cycle by inserting a wait state (Tw).
A3:1
ALE
O T.S. O T.S. O T.S. O T.S.
AS W/R DEN
DT/R
O T.S.
READY
I
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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80960SB
Table 4. 80960SB Pin Description: Bus Signals (Sheet 2 of 2) NAME LOCK TYPE I/O O.D. DESCRIPTION BUS LOCK prevents bus masters from gaining control of the bus during Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert LOCK. At the start of a RMW operation, the processor examines the LOCK pin. If the pin is already asserted, the processor waits until it is not asserted. If the pin is not asserted, the processor asserts LOCK during the Ta cycle of the read transaction. The processor deasserts LOCK in the Ta cycle of the write transaction. While LOCK is asserted, a bus agent can perform a normal read or write but not a RMW operation. The processor also asserts LOCK during interrupt-acknowledge transactions. Do not leave LOCK unconnected. It must be pulled high for the processor to function properly. ONCE MODE: The LOCK pin is sampled during reset. If it is asserted LOW at the end of reset, all outputs will be three-stated until the part is reset again. ONCE mode is used in conjunction with an in-circuit emulator. BE1:0 O T.S. BYTE ENABLE LINES specify which data bytes (up to two) on the bus take part in the current bus cycle. BE1 corresponds to AD15:8; BE0 corresponds to AD7:1, D0. The byte enable lines are asserted appropriately during each data cycle. INITIALIZATION FAILURE indicates that the processor has failed to initialize correctly. The failure state is indicated by a combination of BLAST asserted and BE1:0 not asserted. This condition occurs after RESET is deasserted and before the first bus transaction begins. FAIL is asserted while the processor performs a self-test. If the self-test completes successfully, FAIL is deasserted. The processor then performs a zero checksum on the first eight words of memory, If it fails, FAIL is asserted for a second time and remains asserted; if it passes, system initialization continues and FAIL remains deasserted. HOLD I HOLD indicates a request from an external bus master to acquire the bus. When the processor receives HOLD and grants bus control to another master, it floats its three-state bus lines, then asserts HLDA and enters the Th state. When HOLD is deasserted, the processor deasserts HLDA and enters the Ti or Ta state. HOLD ACKNOWLEDGE notifies an external bus master that the processor has relinquished control of the bus. This signal is always driven. At reset it is driven LOW. BURST LAST indicates the last data cycle (Td) of a burst access. It is asserted low during the last Td and associated with Tw cycles in a burst access. INITIALIZATION FAILURE indicates that the processor has failed to initialize correctly. The failure state is indicated by a combination of BLAST asserted and BE1:0 not asserted. This condition occurs after RESET is deasserted and before the first bus transaction begins. FAIL is asserted while the processor performs a self-test. If the self-test completes successfully, FAIL is deasserted. The processor then performs a zero checksum on the first eight words of memory, If it fails, FAIL is asserted for a second time and remains asserted; if it passes, system initialization continues and FAIL remains deasserted. I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
HLDA
O T.S. O T.S.
BLAST/FAIL
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80960SB
Table 5. 80960SB Pin Description: Support Signals NAME RESET TYPE I DESCRIPTION RESET clears the processor's internal logic and causes it to reinitialize. During RESET assertion, the input pins are ignored (except for INT0, INT1, INT3, LOCK), the three-state output pins are placed in a HIGH impedance state (except for DT/R, DEN, and AS) and other output pins are placed in their non-asserted states. RESET must be asserted for at least 41 CLK2 cycles for a predictable reset. Optionally, for a synchronous reset, the LOW and HIGH transition of RESET should occur after the rising edge of both CLK2 and the external bus CLK and before the next rising edge of CLK2. The interrupt pins indicate the initialization sequence executed. Typical initialization requires driving only INT0 and INT3 to a HIGH state. The reset conditions follow: INT0 1 0 0 x x INT0 I INT1 x 0 1 x x INT3 1 1 x 0 x LOCK 1 1 x x 0 Action Taken Run self test (core initialization) Disable self-test Reserved Reserved ONCE mode (see LOCK pin)
INTERRUPT 0 indicates a pending interrupt. To signal an interrupt in a synchronous system, this pin -- as well as the other interrupt pins -- must be enabled by being deasserted for at least one bus cycle and then asserted for at least one additional bus cycle. In an asynchronous system, the pin must remain deasserted for at least two system clock cycles and then asserted for at least two more system clock cycles. The interrupt control register must be programmed with an interrupt vector before using this pin. INT0 is sampled during reset to determine if the self-test sequence is to be executed.
INT1 INT2/INTR
I I
INTERRUPT 1, like INT0, provides direct interrupt signaling. INT1 is sampled during reset to determine if the self-test sequence is to be executed. INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines how this pin is interpreted. If INT2, it has the same interpretation as the INT0 and INT1 pins. If INTR, it is used to receive an interrupt request from an external interrupt controller. INTERRUPT3/INTERRUPT ACKNOWLEDGE: The interrupt control register determines how this pin is interpreted. If INT3, it has the same interpretation as the INT0 and INT1 pins. If INTA, it is used as an output to control interrupt acknowledge transactions. The INTA output is latched on-chip and remains valid during Td cycles; as an output, it is open-drain. INT3 must be pulled HIGH during reset. NOT CONNECTED indicates pins should not be connected. Never connect any pin marked NC; these pins may be reserved for factory use.
INT3/INTA
I/O T.S.
NC
N/A
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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80960SB
2.0 2.1
ELECTRICAL SPECIFICATIONS Power and Grounding
The LOCK open-drain pin requires a pullup resistor whether or not the pin is used as an output. Figure 5 shows the recommended resistor value. Do not connect external logic to pins marked NC.
The 80960SB is implemented in CHMOS IV technology and therefore has modest power requirements. Its high clock frequency and numerous output buffers (address/data, control, error and arbitration signals) can cause power surges as multiple output buffers simultaneously drive new signal levels. For clean on-chip power distribution, VCC and VSS pins separately feed the device's functional units. Power and ground connections must be made to all 80960SB power and ground pins. On the circuit board, all VCC pins must be strapped closely together, preferably on a power plane; all VSS pins should be strapped together, preferably on a ground plane.
VCC OPEN-DRAIN OUTPUT 910
Figure 5. Connection Recommendation for LOCK
2.4 2.2 Power Decoupling Recommendations
Characteristic Curves
Place a liberal amount of decoupling capacitance near the 80960SB. When driving the bus the processor can cause transient power surges, particularly when connected to a large capacitive load. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance is reduced by shortening board traces between the processor and decoupling capacitors as much as possible.
Figure 6 shows typical supply current requirements over the operating temperature range of the processor at supply voltage (VCC) of 5V. Figure 7 shows the typical power supply current (ICC) that the 80960SB requires at various operating frequencies when measured at three input voltage (VCC) levels. For a given output current (IOL) the curve in Figure 8 shows the worst case output low voltage (VOL). Figure 9 shows the typical capacitive derating curve for the 80960SB measured from 1.5V on the system clock (CLK) to 0.8V on the falling edge and 2.0V on the rising edge of the bus address/data (AD) signals.
2.3
Connection Recommendations
For reliable operation, always connect unused inputs to an appropriate signal level. In particular, if one or more interrupt lines are not used, they should be pulled up. No inputs should ever be left floating.
11
80960SB
VCC = 5.0V
350
POWER SUPPLY CURRENT (mA)
300
250
16 MHz 10 MHz
200
150
100 -60 -40 -20
0
20
40
60
80 100 120 140
CASE TEMPERATURE (C)
Figure 6. Typical Supply Current vs. Case Temperature
TEMP = +22C
500 450 TYPICAL SUPPLY CURRENT (mA)
4.5V 5.0V 5.5V
400 350 300 250 200 150 100 50 0 0 5 10 15 20 25 OPERATING FREQUENCY (MHz)
Figure 7. Typical Current vs. Frequency (Room Temp)
12
80960SB
TEMP = +85C TYPICAL SUPPLY CURRENT (mA)
(TEMP = +85C, VCC = 4.5V)
30
FALLING
THREE-STATE OUTPUT VALID DELAY (NS)
4.5V 5.0V 5.5V
300 250 200 150 100 50 0 0 5 10 15 20 25
X X
25 20 X 15 10 5 0 0 20 40
RISING
60
80
100
OPERATING FREQUENCY (MHz)
CAPACITIVE LOAD (pF)
Figure 8. Typical Current vs. Frequency (Hot Temp)
Figure 9. Capacitive Derating Curve
2.5
Test Load Circuit
Figure 10 illustrates the load circuit used to test the 80960SB's output pins.
THREE-STATE OUTPUT
CL
CL = 50 pF for all signals
Figure 10. Test Load Circuit for Three-State Output Pins
13
80960SB
2.6
ABSOLUTE MAXIMUM RATINGS*
Parameter Maximum Rating
NOTICE: This is a production data sheet. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Operating Temperature (PLCC) ............ 0C to +85C Case Operating Temperature (QFP) ............ 0C to +100C Case Storage Temperature .............................. -65C to +150C Voltage on Any Pin (PLCC)................. -0.5V to VCC +0.5V Voltage on Any Pin (QFP)............... -0.25V to VCC +0.25V Power Dissipation ......................................... 1.9W(16MHz)
2.7
DC Characteristics
TCASE = 0C to +100C, VCC = 5V 5% TCASE = 0C to +85C, VCC = 5V 10% Table 6. DC Characteristics
80960SB (10 MHz QFP) 80960SB (10 and 16 MHz PLCC)
Symbol VIL VIH VCL VCH VOL VOH ICC
Parameter Input Low Voltage Input High Voltage CLK2 Input Low Voltage CLK2 Input High Voltage Output Low Voltage Output High Voltage Power Supply Current: 10 MHz-QFP 10 MHz-PLCC 16 MHz-PLCC Input Leakage Current, Except INT0, LOCK Input Leakage Current, INT0, LOCK Output Leakage Current Input Capacitance Output Capacitance Clock Capacitance
Min -0.3 2.0 -0.3 0.7 VCC
Max +0.8 VCC + 0.3 +0.8 VCC + 0.3 0.45 0.45
Units V V V V V V V
Notes
IOL = 4.0 mA IOL = 6 mA, LOCK Pin All TS, -2.5 mA (1) TCASE = 00C TCASE = 00C TCASE = 00C 0 VIN VCC VIN = 0.45V (2)
2.4 280 280 350 15 -300 15 10 12 10
mA mA mA A A A pF pF pF
ILI1 ILI2 IOL CIN CO CCLK
fC = 1 MHz (3) fC = 1 MHz (3) fC = 1 MHz (3)
NOTES: 1. Not measured for open-drain output. 2. INT0 and LOCK have internal pullup devices. 3. Input, output and clock capacitance are not tested.
14
80960SB
2.8
AC Specifications
This section describes the AC specifications for the 80960SB pins. All input and output timings are specified relative to the 1.5V level of the rising edge of CLK2 and refer to the time at which the signal
crosses 1.5V (for output delay and input setup). All AC testing should be done with input voltages of 0.4V and 2.4V, except for the clock (CLK2) which should be tested with input voltages of 0.45V and 0.7 x VCC. See Figure 11 and Tables 7 and 8 for timing relationships for the 80960SB signals.
EDGE
A
B
C
D
A
B
C
CLK2 OUTPUTS: AD15:1, A3:1, D0, A 31:16, BE1:0, W/R, DEN, BLAST, HLDA, LOCK, INTA AS
1.5V T6
1.5V
1.5V T9
1.5V
1.5V VALID OUTPUT1.5V T6AS T6AS
T8
T8 T13
T14
ALE
1.5V T7
1.5V
T6 DT/R 1.5V T10 INPUTS: AD15:1, D0, INT0, INT1, INT2, INT3 HOLD LOCK READY
2.0V 0.8V
T9 VALID OUTPUT T11
2.0V 0.8V
1.5V
T12
2.0V 0.8V
T11
2.0V 0.8V
VALID INPUT
Figure 11. Drive Levels and Timing Relationships for 80960SB Signals
15
80960SB
Table 7. 80960SB AC Characteristics (10 MHz) Symbol Input Clock T1 T2 T3 T4 T5 T6 T6AS T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 Processor Clock Period (CLK2) Processor Clock Low Time (CLK2) Processor Clock High Time (CLK2) Processor Clock Fall Time (CLK2) Processor Clock Rise Time (CLK2) 50 8 8 10 10 125 ns ns ns ns ns VIN VT VT VT VT = 1.5V = 10% Point = VCL + (VCH - VCL) x 0.1 = 90% Point = VCL + (VCH - VCL) x 0.9 = 90% to 10% Point (1) = 10% to 90% Point (1) Parameter Min Max Units Notes
Synchronous Outputs Output Valid Delay AS Output Valid Delay ALE Width ALE Output Valid Delay Output Float Delay 2 2 T1 - 11 4 2 33 20 31 25 ns ns ns ns ns (2)
Synchronous Inputs Input Setup 1 Input Hold Input Setup 2 Setup to ALE Inactive Hold after ALE Inactive RESET Hold RESET Setup RESET Width 10 2 13 10 8 3 5 2050 ns ns ns ns ns ns ns ns (3) (3) 41 CLK2 Periods Minimum
NOTES: 1. Processor clock (CLK2) rise time and fall time are not tested. 2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested, but should be no longer than the valid delay. 3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asynchronous reset, synchronizing the clock can be accomplished by using AS.
16
80960SB
Table 8. 80960SB AC Characteristics (16 MHz) Symbol Input Clock T1 T2 T3 T4 T5 T6 T6AS T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 Processor Clock Period (CLK2) Processor Clock Low Time (CLK2) Processor Clock High Time (CLK2) Processor Clock Fall Time (CLK2) Processor Clock Rise Time (CLK2) 31.25 8 8 10 10 125 ns ns ns ns ns VIN = 1.5V VT = 10% Point = VCL + (VCH - VCL) x 0.1 VT = 90% Point = VCL + (VCH - VCL) x 0.9 VT = 90% to 10% Point (1) VT = 10% to 90% Point (1) Parameter Min Max Units Notes
Synchronous Outputs Output Valid Delay AS Output Valid Delay ALE Width ALE Output Valid Delay Output Float Delay 2 2 T1 - 11 2 2 22 20 25 21 ns ns ns ns ns (2)
Synchronous Inputs Input Setup 1 Input Hold Input Setup 2 Setup to ALE Inactive Hold after ALE Inactive RESET Hold RESET Setup RESET Width 10 2 13 10 8 3 5 1281 ns ns ns ns ns ns ns ns (3) (3) 41 CLK2 Periods Minimum
NOTES: 1. Processor clock (CLK2) rise time and fall time are not tested. 2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested, but should be no longer than the valid delay. 3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asynchronous reset, synchronizing the clock can be accomplished by using AS.
17
80960SB
T1 T3
HIGH LEVEL (MIN) 0.7VCC
90%
1.5 V
LOW LEVEL (MAX) 0.8V
10% T5 T2
T4
Figure 12. Processor Clock Pulse (CLK2)
A
B
C
D
A
B
C
CLK2
CLK
OUTPUTS T16
T17 RESET T15 INT0, INT1, INT3, LOCK
INITIALIZATION PARAMETERS
NOTE: Initialization parameters must be set up at least four CLK2 periods before the first CLK2 "A" edge.
Figure 13. RESET Signal Timing
18
80960SB
Th CLK2
Th
Th
CLK T12 HOLD T6 HLDA T6 T11
Figure 14. HOLD Timing
19
80960SB
3.0 3.1
* *
MECHANICAL DATA Packaging
3.2
Pin Assignment
The 80960SB is available in two package types: 80-lead quad flat pack (EIAJ QFP). Shown in Figure 15. 84-lead plastic leaded chip carrier (PLCC). Shown in Figure 16.
The QFP and PLCC have different pin assignments. The QFP pins are numbered in order from 1 to 80 around the package perimeter. The PLCC pins are numbered in order from 1 to 84 around the package perimeter. Tables 9 and 10 list the function of each QFP pin; Tables 11 and 12 list the function of each PLCC pin. VCC and GND connections must be made to multiple VCC and GND pins. Each VCC and GND pin must be connected to the appropriate voltage or ground and externally strapped close to the package. It is recommended that you include separate power and ground planes in your circuit board for power distribution. Pins identified as NC (No Connect) should never be connected.
Dimensions for both package types are given in the Intel Packaging handbook (Order #240800).
INT2/INTR
INT3/INTA
RESET
BLAST
HOLD
LOCK
HLDA
CLK2
DT/R
INT1
INT0
DEN
W/R
VSS ALE READY A31 A30 A29 A28 VSS VCC A27 A26 A25 VCC VSS A24 A23
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 39 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1
A22
BE0
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
NC
AS
BE1 NC A1 VSS VCC A2 A3 VCC VSS D0 AD1 AD2 AD3 AD4 AD5 AD6
38 37 36 35
S80960SB-16
XXXXXXXX XXXXXX XXXXXX
34 33 32 31 30 29 28 27 26 25
23
A21 A20
4
A19
5
A18
6
A17
78
A16
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 VSS VSS VSS VSS
VCC
VCC
VCC
Figure 15. 80-Lead EIAJ Quad Flat Pack (QFP) Package 20
VCC
80960SB
.
READY
ALE
VCC
VCC
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
VSS
VSS
VSS
NC
A20 A19 A18 A17 A16 VCC VSS AD15 AD14 VCC VSS NC AD13 AD12 AD11 AD10 AD9 AD8 AD7 VCC VSS
11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
NC
AS
VSS VCC VSS VCC LOCK BLAST DT/R DEN W/R NC HOLD VSS VCC HLDA INT3/INTA INT2/INTR INT1 INT0 RESET CLK2 VSS
N80960SB-16
XXXXXXXX XXXXXX XXXXXX
65 64 63 62 61 60 59 58 57 56 55
32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
NC AD6 AD5 AD4 AD3 AD2 AD1 NC D0 A3 A2 A1 BE1 BE0 VCC VCC VCC VCC VSS VSS VSS
Figure 16. 84-Lead Plastic Leaded Chip Carrier (PLCC) Package
21
80960SB
3.3
Pinout
Table 9. 80960SB QFP Pinout -- In Pin Order
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Signal A22 A21 A20 A19 A18 A17 A16 VCC V SS AD15 AD14 V CC VSS AD13 AD12 AD11 AD10 AD9 AD8 AD7
Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS
Signal VCC VCC V SS AD6 AD5 AD4 AD3 AD2 AD1 D0 VSS VCC A3 A2 V CC V SS A1 NC BE1
Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Signal BE0 VCC VSS CLK2 RESET INT0 INT1 INT2/INTR INT3/INTA HLDA VCC VSS HOLD W/R DEN DT/R BLAST LOCK VCC VSS
Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VSS NC AS VSS
Signal VCC
ALE READY A31 A30 A29 A28 VSS VCC A27 A26 A25 VCC VSS A24 A23
NOTES: Do not connect any external logic to any pins marked NC.
22
80960SB
Table 10. 80960SB QFP Pinout -- In Signal Order Signal A1 A2 A3 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 Pin 38 35 34 30 29 28 27 26 25 20 19 18 17 16 15 14 11 10 7 6 Signal A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ALE AS BE0 BE1 BLAST CLK2 Pin 5 4 3 2 1 80 79 76 75 74 71 70 69 68 66 64 41 40 57 44 D0 DEN DT/R HLDA HOLD INT0 INT1 INT2/INTR INT3/INTA LOCK NC NC READY RESET V CC VCC VCC VCC VCC V CC Signal Pin 31 55 56 50 53 46 47 48 49 58 39 63 67 45 12 21 23 33 36 42 Signal VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R Pin 51 59 61 73 77 8 13 22 24 32 37 43 52 60 62 72 78 9 65 54
NOTES: Do not connect any external logic to any pins marked N.C.
23
80960SB
Table 11. 80960SB PLCC Pinout -- In Pin Order Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NC A27 A26 A25 VCC VSS A24 A23 A22 A21 A20 A19 A18 A17 A16 VCC VSS AD15 AD14 VCC Signal VCC Pin 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NC AD13 AD12 AD11 AD10 AD9 AD8 AD7 VCC VSS VCC VSS AD6 AD5 AD4 AD3 D2 D1 D0 NC Signal VSS Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Signal VSS VCC A3 A2 VCC VSS A1 NC BE1 BE0 VCC VSS CLK2 RESET INT0 INT1 INT2/INTR INT3/INTA HLDA VCC VSS Pin 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 NC W/R DEN DT/R BLAST LOCK VCC VSS VCC VSS NC AS VSS ALE READY A31 A30 A29 A28 VSS Signal HOLD
NOTES: Do not connect any external logic to any pins marked NC.
24
80960SB
Table 12. 80960SB PLCC Pinout -- In Signal Order Signal A1 A2 A3 D0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 A17 Pin 49 46 45 41 40 39 38 37 36 35 30 29 28 27 26 25 24 20 19 16 15 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ALE AS BE0 BE1 BLAST CLK2 DEN Signal Pin 14 13 12 11 10 9 8 5 4 3 83 82 81 80 78 76 52 51 69 55 67 Signal DT/R HLDA HOLD INT0 INT1 INT2/INTR INT3/INTA LOCK NC NC NC NC NC NC READY RESET VCC VCC VCC VCC VCC Pin 68 61 64 57 58 59 60 70 2 23 42 50 65 75 79 56 1 17 21 31 33 VCC V CC V CC VCC V CC V CC VCC VSS V SS V SS V SS V SS V SS V SS VSS VSS VSS VSS VSS VSS W/R Signal Pin 44 47 53 6 62 71 73 18 22 32 34 43 48 54 63 7 72 74 77 84 66
NOTES: Do not connect any external logic to any pins marked NC.
25
80960SB
3.4
Package Thermal Specifications
The 80960SB is specified for operation when case temperature is within the range 0C to +85C (PLCC) or 0C to 100C (QFP). Measure case temperature at the top center of the package. Ambient temperature can be calculated from: TJ = TC + P*JC TA = TJ - P*JA TC = TA + P*[JA-JC]
Compute P by multiplying the maximum voltage by the typical current at maximum temperature. Values for JA and JC for various airflows are given in Table 13 for the QFP package and in Table 14 for the PLCC package. ICC at maximum temperature is typically 80 percent of specified ICC maximum (cold).
Table 13. 80960SB QFP Package Thermal Characteristics Thermal Resistance -- C/Watt Parameter
Junction-to-Ambient (Case measured in the middle of the top of the package) (No Heatsink) Junction-to-Case
Airflow -- ft./min (m/sec) 0 54 50 52 100 49 200 45 400 39 600 35 800 33
11
11
11
11
11
11
11
NOTES: This table applies to 80960SB QFP soldered directly to board.
Table 14. 80960SB PLCC Package Thermal Characteristics Thermal Resistance -- C/Watt Parameter
Junction-to-Ambient (No Heatsink) Junction-to-Case
Airflow -- ft./min (m/sec) 0 33 11 50 31 11 100 28.5 11 200 27 11 400 24 11 600 22 11 800 20 11 1000 19.5 11
NOTES: This table applies to 80960SB PLCC soldered directly to board.
26
80960SB
4.0
WAVEFORMS
Figures 17, 18, 19, 20 and 21 show waveforms for various transactions on the 80960SB's bus. Figure 22 shows a cold reset functional waveform.
Ta CLK2
Td
Tr
Ta
Td
Tr
CLK ALE
AS
A31:16
VALID
VALID
A15:4, D15:0
ADDR
D
ADDR
DATA
A3:1
VALID
INVALID
VALID
BE1:0
BLAST
W/R
DT/R
DEN
READY
Figure 17. Non-Burst Read and Write Transactions Without Wait States
27
80960SB
Ta CLK2
Tw
Td
Td
Td
Td
Td
Td
Td
Td
Tr
CLK
ALE
AS
A31:16
VALID
A15:4, D15:0
ADDR
D
D
D
D
D
D
D
D
A3:1
000
001
010
011
100
101
110
111
BE1:0
BLAST
W/R
DT/R
DEN
READY
Figure 18. Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States
28
80960SB
Ta CLK2
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
CLK
ALE
AS
A31:16
VALID
A15:4, D15:0
ADDR
DATA
DATA
DATA
DATA
A3:1
VALID
VALID
VALID
VALID
BE1:0
0x
00
00
x0
BLAST
W/R
DT/R
DEN
READY
Figure 19. Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred)
29
80960SB
Tr
VALID
Td
D
Tw
Tr
D
ADDR
Ta
Td
D
Td
D
Td
D
Td
VALID
D
Td
D
Td
D
Td
Td
D
Tw
Ta
ADDR
000
001
010
011
100
101
110
111
000
DT/R
W/R
A31:16
A15:4, D15:0
DEN
BE1
CLK
ALE
BE0
AS
Figure 20. Accesses Generated by Quad Word Read Bus Request, Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States 30
READY
CLK2
A3:1
BLAST
80960SB
Ta
Td
Tr
Ti
Ti
Ti
Ti
Ti
Ta
Tw
Td
Tr
CLK2
CLK
ALE
AS A31:16 A15:4, D15:0 A3:1
ADD
ADDR
DATA
110
BE1:0
10
10
INTA
BLAST W/R
DT/R
DEN
LOCK
READY
Figure 21. Interrupt Acknowledge Cycle
31
32
AB C D AB C DAB C D AB C D AB C DAB C D
80960SB
Ta
CLK2
CLK VCC AS, DT/R, DEN, LOCK (O) HLDA
BLAST/FAIL
ALE, A31:16, A15:4, A3:1, D15:0, BE1:0, W/R RESET
Figure 22. Cold Reset Waveform
INT0, INT1, INT3, LOCK (I) VALID VCC and CLK2 stable to RESET high, minimum 41 CLK2 periods
Internal self-test, approximately 94,000 CLK2 Initialization parameters periods (if selected) set up to first A edge, minimum 4 CLK2 periods
First Bus Activity
80960SB
5.0
REVISION HISTORY
This data sheet supersedes data sheet 272207-001. The sections significantly changed since the previous revision are: Section 2.3 Connection Recommendations (pg. 11) Last Rev. -001 Description Removed two LOCK pin Connection Recommendation figures and added Figure 5 to reflect the new LOCK pin connection recommendation of a single 910 pullup resistor. Obsolete figure (Test Load Circuit for Open-Drain Output Pins) removed to reflect current test conditions. IOL value improved. WAS: WAS: 2.5 mA 12 mA IS: IS: 4.0 mA 6 mA LOCK pin IOL value at 0.45V relaxed. LOCK pin IOL value at 0.60V deleted. Data sheet 270917-004 applied to both the 80960SA and the 80960SB. The 80960SB was then documented alone in data sheet 272207-001. The sections significantly changed between revisions -004 of the SA/SB data sheet and 272207-001 of the SB data sheet were: Section 2.3 Connection Recommendations (pg. 11) Figure 7. Typical Supply Current vs. Case Temperature (pg. 12) Figure 8. Typical Current vs. Frequency (Room Temp) (pg. 12) Figure 9. Typical Current vs. Frequency (Hot Temp) (pg. 13) Table 6. DC Characteristics (pg. 15) Table 7. 80960SA AC Characteristics (10 MHz) (pg. 17) Table 8. 80960SA AC Characteristics (16 MHz) (pg. 18) -004 -004 Input Leakage Current (ILI2) Specification added to accurately describe leakage of INT0 and LOCK as inputs. T7 minimum specification improved: Power Supply Current: 10 MHz 16 MHZ Was: 24 ns 15 ns Is: T1 - 11 ns T1 - 11 ns Last Rev. -004 -004 Description Deleted corresponding graph of open drain voltage vs. output current. Regraphed data in three graphs instead of two.
2.5 Test Load Circuit (pg. 13) 2.7 DC Characteristics (pg. 14)
-001 -001
NOTES: Page numbers refer to 80960SB data sheet number 272207-001.
33
80960SB
The sections significantly changed between revisions -003 and -004 of the 80960SA/SB Data Sheet were: Section DC Characteristics Last Rev. -003 Description Operating temperature for PLCC package changed: WAS: IS: TCASE = 0C to +100C TCASE = 0C to +85C
The test program has not changed. Table 7. QFP Package, Thermal Resistance -- C/Watt -003 Corrected QFP Package Thermal Resistance values: for JC at 0 ft./min. for JA at 0 ft./min. airflow: airflow: WAS: 4 /W WAS: 45.7 /W IS: 11 /W IS: 54 /W Corrected PLCC Package Thermal Resistance values: for JA: at 50 ft./min. airflow WAS: IS: for JC: WAS: IS: Table 9. 80960SA and 80960SB QFP Pinout -- In Pin Order -003 NA 31 at 100 ft./min. airflow WAS: IS: NA 28.5
Table 8. PLCC Package, Thermal Resistance -- C/Watt
-003
at 0 ft./min. airflow 13 11
at 50-1000 ft./min. airflow WAS: IS: NA 11
Signal A12 incorrectly shown as Pin 28; is now correctly shown as Pin 38. Note added to clarify No Connect Pins.
34

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