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Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
FEATURES
* Dual device * Low threshold voltage * Fast switching * Logic level compatible * Surface mount package
PHN203
SYMBOL
d1 d1 d2 d2
QUICK REFERENCE DATA
VDS = 25 V ID = 6.3 A RDS(ON) 30 m (VGS = 10 V) RDS(ON) 55 m (VGS = 4.5 V)
s1 g1 s2 g2
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHN203 is supplied in the SOT96-1 (SO8) surface mounting package.
PINNING
PIN 1 2 3 4 5,6 7,8 DESCRIPTION source 1 gate 1 source 2 gate 2 drain 2 drain 1
SOT96-1
8 7 6 5
pin 1 index
1
2
3
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Repetitive peak drain-source voltage Continuous drain-source voltage Drain-gate voltage Gate-source voltage Drain current per MOSFET1 Drain current per MOSFET (both MOSFETs conducting)1 Drain current per MOSFET (pulse peak value) Total power dissipation (either or both MOSFETs conducting)1 Storage & operating temperature CONDITIONS Tj = 25 C to 150C RGS = 20 k Ta = 25 C Ta = 70 C Ta = 25 C Ta = 70 C Ta = 25 C Ta = 25 C Ta = 70 C MIN. - 55 MAX. 25 25 25 20 6.3 5 4.4 3.5 25 2 1.3 150 UNIT V V V V A A A A A W W C
1 Surface mounted on FR4 board, t 10 sec January 1999 1 Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-a Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient CONDITIONS Surface mounted on FR4 board, t 10 sec; either or both MOSFETs conducting Surface mounted on FR4 board; either or both MOSFETs conducting TYP. 150 MAX. 62.5 -
PHN203
UNIT K/W K/W
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy (per MOSFET) Non-repetitive avalanche current (per MOSFET) CONDITIONS Unclamped inductive load, IAS = 6.3 A; tp = 0.2 ms; Tj prior to avalanche = 25C; VDD 15 V; RGS = 50 ; VGS = 10 V MIN. MAX. 20 6.3 UNIT mJ A
ELECTRICAL CHARACTERISTICS
Tj= 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IDSS IGSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 10 A; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VGS = 10 V; ID = 4 A VGS = 4.5 V; ID = 2 A VGS = 10 V; ID = 4 A; Tj = 150C Forward transconductance VDS = 20 V; ID = 4 A Zero gate voltage drain VDS = 20 V; VGS = 0 V; current VDS = 20 V; VGS = 0 V; Tj = 150C Gate source leakage current VGS = 20 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 4 A; VDD = 20 V; VGS = 10 V MIN. 25 22.5 1 0.4 5 TYP. MAX. UNIT 2 27 40 43 9.7 60 0.1 10 20 1.9 6.1 8 11 31 17 2.5 5 611 260 137 2.8 3.2 30 55 51 100 10 100 V V V V V m m m S nA A nA nC nC nC ns ns ns ns nH nH pF pF pF
VDD = 20 V; RD = 18 ; VGS = 10 V; RG = 6 Resistive load Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz
January 1999
2
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source diode current (per MOSFET) Pulsed source diode current (per MOSFET) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Ta = 25 C MIN. IF = 1.25 A; VGS = 0 V IF = 1.25 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V -
PHN203
TYP. MAX. UNIT 0.75 35 24 2.85 25 1 A A V ns nC
Normalised Power Dissipation, PD (%)
120 100
100
Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID
PHN203 tp = 10 us 100 us 1 ms 10 ms
10 80 60 40 20 0 0 25 50 75 100 125 150 0.01 0.1 1 10 Drain-Source Voltage, VDS (V) Ambient Temperature, Ta (C) 0.1 1
100 ms
10 s
100
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ta)
Fig.3. Safe operating area. Ta = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Drain Current, ID (%)
120 100 80 60 40
100
Peak Pulsed Drain Current, IDM (A) D = 0.5
PHN203
10
0.2 0.1 0.05 0.02 single pulse P D tp D = tp/T
1
0.1 20 T 0 0 25 50 75 100 125 150 Ambient Temperature, Ta (C) 0.01 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ta); conditions: VGS 4.5 V
Fig.4. Transient thermal impedance; Zth j-a = f(t); parameter D = tp/T
January 1999
3
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
PHN203
Drain Current, ID (A) 10 9 8 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Drain-Source Voltage, VDS (V) 10V VGS = 5 V Tj = 25 C
PHN203 3.6 V 3.4 V
3.2 V 3V 2.8 V 2.6 V 1.8 2
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transconductance, gfs (S) VDS > ID X RDS(ON)
PHN203
Tj = 25 C 150 C
0
1
2
3
4 5 6 7 Drain current, ID (A)
8
9
10
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
a
Drain-Source On Resistance, RDS(on) (Ohms) 0.5 2.6V 2.8V 3V 3.2 V 3.4V 3.6V
PHN203 Tj = 25 C
2
SOT223 30V Trench
Normalised RDS(ON) = f(Tj)
0.4
1.5
0.3
1
0.2
0.1
0.5
10V VGS =5 V
0 0 1 2 3 4 5 6 Drain Current, ID (A) 7 8 9 10
0 -50
0
50 Tj / C
100
150
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
VGS(TO) / V 4
Drain current, ID (A) 10 9 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 150 C VDS > ID X RDS(ON)
PHN203
3
max. typ.
2
Tj = 25 C
1
min.
4.5
5
0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics. ID = f(VGS)
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
January 1999
4
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
PHN203
1E-01
Sub-Threshold Conduction
10 9
Source-Drain Diode Current, IF (A) VGS = 0 V
PHN203
1E-02 min typ max
8 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 150 C Tj = 25 C
1E-03
1E-04
1E-05
1E-06
0
1
2
3
4
5
Drain-Source Voltage, VSDS (V)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A) PHN203 25 C
Capacitances, Ciss, Coss, Crss (pF) 10000
PHN203
10
Tj prior to avalanche =125 C
1000 Ciss
VDS tp ID
Coss Crss 100 0.1 1 10 Drain-Source Voltage, VDS (V) 100 1 1E-06
1E-05
1E-04 Avalanche time, tp (s)
1E-03
1E-02
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load
Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 4A Tj = 25 C VDD = 20 V
PHN203
5
10 15 20 Gate charge, QG (nC)
25
30
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
January 1999
5
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PHN203
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-05-22
Fig.16. SOT96 surface mounting package.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8".
January 1999
6
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHN203
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
January 1999
7
Rev 1.000

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