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FUJITSU SEMICONDUCTOR DATA SHEET
AE1E
MEMORY
CMOS
8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM
MB81N643289-50/-60
CMOS 8-BANK x 262,144-WORD x 32 BIT Fast Cycle Random Access Memory (FCRAM) with Double Data Rate s DESCRIPTION
The Fujitsu MB81N643289 is a CMOS Fast Cycle Random Access Memory (FCRAM) containing 67,108,864 memory cells accessible in an 32-bit format. The MB81N643289 features a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81N643289 is designed to reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints. The MB81N643289 uses Double Data Rate (DDR) where data bandwidth is twice of fast speed compared with regular SDRAMs. The MB81N643289 is designed using Fujitsu advanced FCRAM Core Technology. The MB81N643289 is ideally suited for Digital Visual System, High Performance Graphic Adapters, Hardware Accelerators, Buffers, and other applications where large memory density and high effective bandwidth are required and where a simple interface is needed. The MB81N643289 adopts new I/O interface circuitry, 2.5 V CMOS Source Termination I/O interface, which is capable of extremely fast data transfer of quality under point to point bus environment.
s PRODUCT LINE
Parameter Clock Frequency Burst Mode Cycle Time Random Address Cycle Time DQS Access Time From Clock Operating Current Power Down Current Notice : FCRAM is a trademark of Fujitsu Limited, Japan. CL = 3 CL = 2 CL = 3 CL = 2 MB81N643289 -50 200 MHz max 133 MHz max 2.5 ns min 3.75 ns min 30 ns min 0.1*tCK + 0.2 ns max 450 mA max 35 mA max -60 167 MHz max 111 MHz max 3.0 ns min 4.5 ns min 36 ns min 0.1*tCK + 0.2 ns max 385 mA max
1
MB81N643289-50/-60 Preliminary (AE1E)
s FEATURES
Double Data Rate Bi-directional Data Strobe Signal Eight bank operation Burst read/write operation Programmable, burst length, and CAS latency * Write latency (Write command to data input) = CAS latency -1 * * * * * Byte write control by DM0 to DM3 Page Close Power Down Mode Distributed Auto-refresh cycle in 8 s 2.5 V CMOS Source Termination I/O for all signals * VDD: +2.5V Supply 0.2V tolerance * VDDQ: +2.5V Supply 0.2V tolerance * * * *
s PACKAGE
Plastic TSOP(II) Package
(FPT-86P-M01) (Normal Bend)
Package and Ordering Information
- 86-pin plastic (400 mil) TSOP-II, order as MB81N643289-xxFN
2
MB81N643289-50/-60 Preliminary (AE1E)
s PIN ASSIGNMENTS AND DESCRIPTIONS
86-Pin TSOP(II) (TOP VIEW)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 DQS0 VDD DM0 WE CAS RAS CS BA2 BA0 BA1 A10/AC A0 A1 A2 DM2 VDD DQS2 DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 DQS1 VSS DM1 VREF CLK CLK PD A9 A8 A7 A6 A5 A4 A3 DM3 VSS DQS3 DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
Pin Number 1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85
Symbol VDD, VDDQ VSS, VSSQ DQ0 to DQ31 Supply Voltage Ground Data I/O
Function
* * * * * * * *
Byte 0 : DQ0 to DQ7 Byte 1 : DQ8 to DQ15 Byte 2 : DQ16 to DQ23 Byte 3 : DQ24 to DQ31 DQS0 : for DQ0 to DQ7 DQS1 : for DQ8 to DQ15 DQS2 : for DQ16 to DQ23 DQS3 : for DQ24 to DQ31
14, 30, 57, 73
DQS0 to DQS3
Data Strobe
16, 28, 59, 71 17 18 19 20 21, 22, 23 24 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 67 68 69 70
DM0 to DM3 WE CAS RAS CS BA2, BA1, BA0 AC A0 to A10 PD CLK CLK VREF
Input Mask Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select (Bank Address) Auto Close Enable Address Input Power Down Clock Input Clock Input Input Reference Voltage * Row: A0 to A10 * Column: A0 to A6
3
MB81N643289-50/-60 Preliminary (AE1E)
s BLOCK DIAGRAM
Fig. 1 - MB81N643289 BLOCK DIAGRAM
CLK CLK PD Bank-7
. . . .
CLOCK BUFFER
To each block
Enable
..
Bank-1 Bank-0 RAS
CS RAS CAS WE AC
CONTROL SIGNAL LATCH COMMAND DECODER
CAS
WE
DRAM
MODE REGISTER
CORE (2048 x 128 x 32)
11 A0 to A10
ROW ADDRESS
DM0 to DM3
COLUMN ADDRESS COUNTER I/O DATA BUFFER/ REGISTER & DQS GENERATOR
..
BA0,BA1,BA2
.
ADDRESS BUFFER/ REGISTER
7
COLUMN ADDRESS I/O
DQ0 to DQ31 DQS0 to DQS3
32
DLL
Clock Buffer
VDD VREF VSS / VSSQ
VDDQ, VSSQ
4
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE
COMMAND TRUTH TABLE
Function Device Deselect No Operation Reserved Read Read with Auto-close Write Write with Auto-close Bank Active (RAS) Page Close Single Bank Page Close All Banks *5 *5 *5 *5 *6 *7 *7 Notes *4 *4 Symbol PD DESL NOP -- RD RDA WR WRA ACTV PC PCA MRS/ EMRS H H H H H H H H H H H
Note *1 Note *2, and *3
CS RAS CAS WE AC BA2-0 A10 H L L L L L L L L L L X H H H H H H L L L L X H H L L L L H H H L X H L H H L L H L L L X X X L H L H X L H L X X X V V V V V V X V X X X X X X X V X X L A9 X X X X X X X V X X V A8-7 A6-0 X X X X X X X V X X V X X X V V V V V V V V
Mode Register Set/ *7,*8,*9 Extended Mode Register Set Notes: *1. *2. *3. *4. *5. *6. *7. *8. *9.
V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance. All commands are assumed to be valid state transitions. All inputs for command are latched on the rising edge of clock(CLK). NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions. RD, RDA, WR and WRA commands should only be issued after the corresponding bank has been activated (ACTV command). Refer to STATE DIAGRAM in page 18. ACTV command should only be issued after corresponding bank has been page closed by PC or PCA command. Either PC or PCA command and MRS or EMRS command are required after power up. MRS or EMRS command should only be issued after all banks have been page closed (PC or PCA command), and DQs are in Hi-Z. Refer to STATE DIAGRAM. Refer to MODE REGISTER TABLE.
5
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (continued)
DM TRUTH TABLE (Effective during Write mode)
PD Function Data Mask for DQ0 to DQ7 Data Mask for DQ8 to DQ15 Data Mask for DQ16 to DQ23 Data Mask for DQ24 to DQ31 Command (n - 1) MASK0 MASK1 MASK2 MASK3 H H H H (n) X X X X H X X X X H X X X X H X X X X H DM0 DM1 DM2 DM3
PD TRUTH TABLE
Current State Idle Idle Selfrefresh Selfrefresh Idle Power Down Power Down Function Auto-refresh Self-refresh Entry Self-refresh Continue Self-refresh Exit Power Down Entry Power Down Continue Power Down Exit *12 Notes *10 *10 *11 Command REF SELF -- SELFX PDEN -- PDEX PD (n-1) (n) H H L L L H H L L L H L L H H L L L H H CS RAS CAS WE L L X L H L H X L H L L X H X H X X H X L L X H X H X X H X H H X H X H X X H X AC X X X X X X X X X X BA0-2 A10-0 DQ0-31 X X X X X X X X X X X X X X X X X X X X -- Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Notes:*10. The REF and SELF commands should only be issued after all banks have been precharged (PC or PCA command). In case of SELF command, it should also be issued after the last read data have been appeared on DQ. Refer to STATE DIAGRAM. *11. PD must bring to Low level together with REF command. *12. The PDEN command should only be issued after the last read data have been appeared on DQ and after the lWPL is satisfied from last write data input.
6
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (continued)
OPERATION COMMAND TABLE (Applicable to single bank)
Current State Idle CS H L L L L L L L L L Bank Active H L L L L L L L L L RAS CAS X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L WE X H L H L H L L H L X H L H L H L L H L Address X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE Command DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS NOP NOP Illegal Illegal Illegal Bank Active after lRCD NOP NOP Auto-refresh or Self-refresh Mode Register / Extended Mode Register Set (Idle after lRSC) NOP NOP Illegal Begin Read; Determine AC Begin Write; Determine AC Illegal Page Close Page Close Illegal Illegal *14 *15 *14 *16 *16 *14 *15 *15 Function
Note *13
Notes
7
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (Continued)
OPERATION COMMAND TABLE (Continued)
Current State Read CS H L L L L L L L L L Write H L L L L L L L L L RAS CAS X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L WE X H L H L H L L H L X H L H L H L L H L Address X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE Command DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS Function NOP (Continue Burst to End -> Bank Active) NOP (Continue Burst to End -> Bank Active) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal NOP (Continue Burst to End -> Bank Active) NOP (Continue Burst to End -> Bank Active) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal *14 *15 *14 *15 Notes
8
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (Continued)
OPERATION COMMAND TABLE (Continued)
Current State Read With Auto-Close CS H L L L L L L L L L Write with Auto-Close H L L L L L L L L L RAS CAS X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L WE X H L H L H L L H L X H L H L H L L H L Address X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE Command DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS Function NOP (Continue Burst to End -> Bank Idle) NOP (Continue Burst to End -> Bank Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal NOP (Continue Burst to End -> Bank Idle) NOP (Continue Burst to End -> Bank Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal *17 *17 *15 *15 *17 *17 *15 *15 Notes
9
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (Continued)
OPERATION COMMAND TABLE (Continued)
Current State Page Close CS H L L L L L L L L L Bank Activating H L L L L L L L L L RAS CAS X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L WE X H L H L H L L H L X H L H L H L L H L Address X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE Command DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS Function NOP (Idle after tPCL) NOP (Idle after tPCL) Illegal Illegal Illegal Illegal NOP NOP Illegal Illegal NOP (Bank Active after lRCD) NOP (Bank Active after lRCD) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal *15 *15 *15 *15 *15 *15 *15 *15 *14 Notes
10
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (Continued)
OPERATION COMMAND TABLE (Continued)
Current State Write Recovering CS H L L L L L L L L L Write Recovering with AutoClose H L L L L L L L L L Refreshing H L L L L RAS CAS X H H H H L L L L L X H H H H L L L L L X H H L L X H H L L H H H L L X H H L L H H H L L X H L H L WE X H L H L H L L H L X H L H L H L L H L X X X X X Address X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE X X -- BA, CA, AC BA, CA, AC BA, RA BA, AC BA, AC X MODE X X X X X Command DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS DESL NOP -- RD/RDA WR/WRA ACTV PC PCA REF/SELF MRS/EMRS DESL NOP RD/RDA/ WR/WRA ACTV/ PC/PCA REF/SELF/ MRS/EMRS Function NOP (Bank Active after lWRL) NOP (Bank Active after lWRL) Illegal Illegal New Write; Determine AC Illegal Illegal Illegal Illegal Illegal NOP (Idle after lWAL) NOP (Idle after lWAL) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal NOP (Idle after lREFC) NOP (Idle after lREFC) Illegal Illegal Illegal *17 *17 *15 *15 *15 Notes
11
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (Continued)
OPERATION COMMAND TABLE (Continued)
Current State Mode Register Setting CS H L L L RAS CAS X H H H X H H L WE X H L X Address X X -- X Command DESL NOP -- RD/RDA/ WR/WRA Function NOP (Idle after lRSC) NOP (Idle after lRSC) Illegal Illegal Notes
L
L
X
X
X
ACTV/PC/PCA/ REF/SELF/ Illegal MRS/EMRS
Abbreviations: RA = Row Address BA = Bank Address CA = Column Address AC = Auto Close Notes:*13. All entries assume the PD was High during the proceeding clock cycle and the current clock cycle. *14. Entry may affect other banks. *15. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. *16. Illegal if any bank is not idle. *17. Entry may legal specified by BA if applicable AC specification are satisfied.
12
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (Continued)
COMMAND TRUTH TABLE FOR PD
Current State Selfrefresh PD CS (n-1) H L L L L L L Selfrefresh Recovery L H H H H H H Power Down H L L L L L L (n) X H H H H H L X H H H H H L X H H H H H L X H L L L L X X H L L L L X X H L L L L X X X H H H L X X X H H H L X X X H H H L X X X H H L X X X X H H L X X X X H H L X X X X H L X X X X X H L X X X X X H L X X X X X X X X X X X X X X X X X X X X X X X X Invalid Exit Self-refresh (Idle after lLOCK) Exit Self-refresh (Idle after lLOCK) Illegal Illegal Illegal NOP (Maintain Self-refresh) Invalid Idle after lLOCK Idle after lLOCK Illegal Illegal Illegal Illegal Invalid Exit Power Down (Idle after tPDE) Exit Power Down (Idle after tPDE) Illegal Illegal Illegal NOP (Maintain Power Down Mode) RAS CAS WE Address Function Notes
13
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (continued)
COMMAND TRUTH TABLE FOR PD (continued)
Current State All Banks Idle PD CS (n-1) H H H H H H H H L Bank Active H H L L (n) H L L L L L L L X H L H L X H L L L L L L X X X X X X X H H H L L L X X X X X X X H H L H L L X X X X X X X H L X X H L X X X X X X X X X X X X X X X X X X Refer to the Command Truth Table. Power Down Entry Power Down Entry Illegal Illegal Illegal Self-refresh Entry Illegal Invalid Refer to the Command Truth Table. Illegal Invalid Invalid *18 *18 RAS CAS WE Address Function Notes
14
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTION TRUTH TABLE (continued)
COMMAND TRUTH TABLE FOR PD (continued)
Current State Read, Write, Write Page Closing PD CS (n-1) H H L L Any State Other Than Listed Above L H H H H H H Refreshing H H L L H (n) H L H L X H L H L L L L L L H H X X X X X X X X H L L L L X X X X X X X X X X X X H H H L X X X X X X X X X X X X H H L X X X X X X X X X X X X X H L X X X X X X X X X X X X X X X X X X X X X Refer to the Command Truth Table. Illegal Invalid Invalid Invalid Refer to the Command Truth Table. Illegal Refer to the Command Truth Table. Illegal Illegal Illegal Illegal Illegal Invalid Invalid Refer to the Command Truth Table. *19 RAS CAS WE Address Function Notes
*18. PDEN and SELF command should only be issued after the last read data have been appeared on DQ. *19. The Clock Suspend mode is not supported on this device and it is illegal if PD is brought to Low during the Burst Read or Write mode.
15
MB81N643289-50/-60 Preliminary (AE1E)
s STATE DIAGRAM
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
ACTV SELF lRSC
*5 *4, 5
WRA
MRS
RDA
PCA
First command MRS ACTV RD
*4, 5
lRSC
lRSC
*3 *3
lRSC lRCD lCCD lRCD
*3
lRSC tRAS
*3
lRSC
lRCDW
*2
lRCDW
*2, 3
tRAS
*3
lCCD
lRWL
lRWL
lRPL
*3
lRPL
*3
RDA WR
lRDA
lRDA
*3 *3
lRDA
*3
lRDA
*3
lRDA
REF
*3 *5
WR
RD
PC
Second command (same bank)
*1
lRDA
lWRL
*5
lWRL
lCCD
lCCD
lWPL
*3
lWPL
*5
WRA PC PCA REF SELFX Notes: *1. *2. *3. *4. *5.
lWAL
*4, 5
lWAL tPCL
*4
lWAL 1 1 tREFC lLOCK
lWAL
*3
lWAL
*5
lWAL
*4, 5
tPCL tPCAL tREFC lLOCK
1 1 tREFC lLOCK
tPCL tPCAL tREFC lLOCK
tPCL
*4
tPCAL tREFC lLOCK
tPCAL tREFC lLOCK
Assume PCA command does not affect any operation on the other banks. Assume no I/O conflict. tRAS must be satisfied. Assume all outputs are in High-Z state. Assume all other banks are in idle state. Illegal Command
16
MB81N643289-50/-60 Preliminary (AE1E)
s STATE DIAGRAM (continued)
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION
ACTV SELF lRSC
*6 *4, 6
WRA
MRS
RDA
PCA
First command MRS ACTV RD
*9
lRSC
lRSC
*5 *10 *3, 10 *2, 10 *2, 10
lRSC 1 1
*8
lRSC tRAS
*3
lRSC
lRRD
*5
1
*2
1
*2, 8
1 1
*2
1
*6 *5
lCBD
*4
lCBD
*3
lRWL
*2
lRWL lRWL
*3
lRPL lRDA
*3
RDA WR
lRDA
1
*5
lCBD lWRD
*5
lCBD
*3
lRWL lCBD lCBD
*2, 10
1 1 1 1 1 tREFC lLOCK
lRDA
REF
*6
WR
RD
PC
Second command (other bank)
*7
*7
*7
*7
*8
*1, 8
lRDA
1
*6
lWRD
*3
lCBD lCBD
*2, 10
lWPL
*6
WRA PC PCA REF SELFX Notes: *1. *2. *3. *4. *5. *6. *7. *8. *9.
lWAL
*6
1
*5
lWRD
*10
lWRD
*3, 10
lWAL
*3
lWAL
*6
lWAL
*4, 6
tPCL tPCAL tREFC lLOCK
1 tPCAL tREFC lLOCK
1
1
1
1
1 1 tREFC lLOCK
tPCL tPCAL tREFC lLOCK
tPCL
*4
tPCAL tREFC lLOCK
Assume PCA command does not affect any operation on the other bank(s). Assume no I/O conflict. tRAS must be satisfied. Assume all outputs are in High-Z state. Assume applicable bank is in idle state. Assume all other banks are in idle state. Assume the other bank(s) is in active state and lRCD or lRCDW is satisfied. Assume the other bank(s) is in active state and tRAS is satisfied. Second command have to follow the minimum clock latency or delay time of single bank operation in other bank (second command is asserted.) *10. Assume other banks are not in RD/RDA/WR/WRA state. Illegal Command.
17
MB81N643289-50/-60 Preliminary (AE1E)
s STATE DIAGRAM (continued)
Fig. 2 - STATE DIAGRAM (Simplified for Single Bank Operation)
POWER DOWN
PDEN
SELF
SELF REFRESH
PDEX IDLE (Standby) MRS
SELFX
REF
MODE REGISTER
AUTO REFRESH
ACTV WRA
PC or PCA
RDA
WRITE PAGE CLOSE WRA RDA
READ PAGE CLOSE
ACTIVE WR RD
WRITE PAGE OPEN
READ PAGE OPEN
DEFINITION OF ALLOWS Command Input Automatic Return
18
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION
DDR, Double Data Rate Function
The regular SDRAM read and write cycle have only used the rising edge of external clock input. When clock signal goes to High from Low at the read mode, the read out data will be available at every rising clock edge after the specified latency up to burst length. The MB81N643289 DDR FCRAM features a twice of data transfer rate within a same clock period by transferring data at every rising and falling clock edge. Refer to Figure 3 in Page 24.
FCRAMTM
The MB81N643289 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
CLOCK (CLK, CLK)
The MB81N643289 adopts differential clock scheme. CLK is a master clock and its rising edge is used to latch all command and address inputs. CLK is a complementary clock input. The MB81N643289 implements Delay Locked Loop (DLL) circuit. This internal DLL tracks the signal cross point between CLK and CLK and generate some clock cycle delay for the output buffer control at Read mode. The internal DLL circuit requires some Lock-on time for the stable delay time generation. In order to stabilize the delay, a constant stable clock input for lLOCK period is required during the Power-up initialization and a constant stable clock input for lLOCK period is also required after Self-refresh exit as specified lLOCK prior to the any command.
POWER DOWN (PD)
PD is a synchronous input signal and enables power down mode. When all banks are in idle state, PD controls Power Down (PD) and Self-refresh mode. The PD and Self-refresh is entered when PD is brought to Low and exited when it returns to High. During the Power Down and Self-refresh mode, both CLK and CLK are disabled after specified time. PD does not have a Clock Suspend function unlike CKE pin of regular SDRAMs, and it is illegal to bring PD into Low if any read or write operation is being performed. For the detail, refer to Timing Diagrams. It is recommended to maintain PD to be Low until VDD gets in the specified operating range in order to assure the power-up initialization.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, all command signals are negated but internal operation such as burst cycle will not be suspended.
COMMAND INPUTS (RAS, CAS and WE)
As well as regular SDRAMs, each combination of RAS, CAS and WE input in conjunction with CS input at a rising edge of the CLK determines FCRAM operation. Refer to FUNCTION TRUTH TABLE in page 5.
19
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION (continued)
BANK ADDRESS (BA0 to BA2)
The MB81N643289 has eight internal banks and each bank is organized as 256K words by 32-bit. Bank selection by BA occurs at Bank Active command (ACTV) followed by read (RD or RDA), write (WR or WRA), and Page Close(PC) command.
ADDRESS INPUTS (A0 to A10)
Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix within each bank. A total of twenty address input signals are required to decode such a matrix. The MB81N643289 adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially latched as well as three bank addresses and the remainder of seven Column addresses are then latched by a Column address strobe command of either a read command (RD or RDA) or write command (WR or WRA).
DATA STROBE (DQS0 to DQS3)
DQS0 to DQS3 are bi-directional signal and represent byte 0 to byte 3, respectively. During Read operation, DQS0 to DQS3 provides the read data strobe signal that is intended to use input data strobe signal at the receiver circuit of the controller(s). It turns Low before first data is coming out and toggle High to Low or Low to High till end of burst read. Refer to Figure 3 for the timing example. The CAS Latency is specified to the first Low to High transition of these DQS0 to DQS3 output. During the write operation, DQS0 to DQS3 are used to latch write data and Data Mask signals. As well as the behavior of read data strobe, the first rising edge of DQS0 to DQS3 input latches first input data and following falling edge of DQS0 to DQS3 signal latches second input data. This sequence shall be continued till end of burst count. Therefore, DQS0 to DQS3 must be provided from controller that drives write data. Note that DQS0 to DQS3 input signal should not be tristated from High at the end of write mode.
DATA INPUTS AND OUTPUTS (DQ0 to DQ31)
Input data is latched by DQS0 to DQS3 input signal and written into memory. After the (CL-1) clock cycle from the Write command, data input is started from the rising edge of DQS. Output data is obtained together with DQS0 to DQS3 output signals at programmed read CAS latency. The polarity of the output data is identical to that of the input. Data is valid after DQS0 to DQS3 output signal transitions (tQSQ) as specified in Data Valid Time (tQSQV).
WRITE DATA MASK (DM0 to DM3)
DM0 to DM3 are active High enable inputs and represent byte 0 to byte 3 respectively. DM0 to DM3 have a data input mask function, and are also sampled by DQS0 to DQS3 input signal together with input data. During write cycle, DM0 to DM3 provide byte mask function. When DMx = High is latched by a DQS0 to DQS3 signal edge, data input at the same edge of DQS0 to DQS3 is masked. During read cycle, the DM0 to DM3 inactive and does not have any effect on read operation. Refer to DM TRUTH TABLE in page 6.
20
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION (continued)
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access and MB81N643289 read and write operations are burst oriented. The burst mode is implemented by keeping the same Row address and by automatic strobing Column address in every single clock edge till programmed burst length(BL). Access time of burst mode is specified as tAC. The internal column address counter operation is determined by a mode register which defines burst type(BT) and burst count length(BL) of 2, 4 or 8 bits of boundary. The burst type is sequential only. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to the least significant address(= 0). If the first access of column address is even (0), the next address will be odd (1), or vice-versa. Burst Length 2 Starting Column Address A2 A1 A0 XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 Sequential Mode 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
21
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION (continued)
PAGE CLOSE AND PAGE CLOSE OPTION (PC, PCA)
The DDR FCRAM memory core is the same as conventional DRAMs', requiring Page close and refresh operations. Page close rewrites the bit line and to reset the internal Row address line and is executed by the Page close operation (PC or PCA). With the Page close operation, DDR SDRAM will automatically be in standby state after specified precharge time (tPCL). The Page closed bank is selected by combination of AC and bank address (BA) when Page close command is issued. If AC = High, all banks are Page closed regardless of BA (PCA command). If AC = Low, a bank to be selected by BA is Page closed (PC command). The auto-pageclose enters Page close mode at the end of burst mode of read or write without Page close command issue. This auto-pageclose is entered by AC = High when a Read (RD) or Write (WR) command is issued. Refer to FUNCTION TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The MB81N643289 Auto-refresh command (REF) automatically generates Bank Active and Page close command internally. All banks of SDRAM should be Page closed prior to the Auto-refresh command. The Auto-refresh command should also be issued within every 8 s period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh operation until cancelled by SELFX. The Self-refresh mode is entered by applying an Auto-refresh command in conjunction with PD = Low (SELF). Once MB81N643289 enters the self-refresh mode, all inputs except for PD can be either logic high or low level state and outputs will be in a High-Z state. During Self-refresh mode, PD = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ. Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit Self-refresh mode, PD must bring to High for at least 2 clock cycles together with NOP condition. Refer to Timing Diagram for the detail procedure. It is recommended to issue at least one Auto-refresh command just after the tRC period to avoid the violation of refresh period. WARNING:A stable clock for lLOCK period with a constant duty cycle must be supplied prior to applying any command to insure the DLL is locked against the latest device conditions. Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted both before the self-refresh entry and after the self-refresh exit.
22
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION (continued)
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields; Burst Length, Burst Type, CAS Latency, and Test Mode Entry (This Test Mode Entry must not be used.) Refer to MODE REGISTER TABLE in page 25. The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power). MRS command should only be issued on condition that all banks are in idle state and all DQS are in High-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field at power-up initialization. Refer to POWER-UP INITIALIZATION below. Note: The Extended Mode Register Set command (EMRS) and its DLL Enable function of EMRS field is only used at power-on sequence.
POWER-UP INITIALIZATION
The MB81N643289 internal condition at and after power-up will be undefined. Since MB81N643289 adopts the method for two power supplies, which has two different power supply pins for internal core and I/O, it is required to follow the following Power On Sequence to execute read or write operation. 1. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins and attempt to maintain all input signals to be Low state (or at least PD to be Low state). 2. Apply VDD voltage to all VDDQ pins before or at the same time as VREF. 3. Apply VREF. 4. Start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200s. 5. After the minimum of 200s stable power and clock, apply NOP condition and take PD to be High state. 6. Issue Page Close All Banks (PCA) command or Page Close Single Bank (PC) command to every banks. 7. Issue EMRS to enable DLL, DE = Low. 8. Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lLOCK*1 period is required to lock the DLL. 9. Apply minimum of two Auto-refresh command (REF).*2 10. Program the mode register by Mode Register Set command (MRS) with DR = Low.*2 Notes: *1. The lLOCK depends on operating clock period. The lLOCK is counted from "DLL Reset" at step-8 to any command input at step-10. *2. The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle (REF).
POWER-DOWN
The MB81N643289 uses multiple power supply voltage. It is required to follow the reversed sequence of above Power On Sequence. 1. Take all input signals to be VSS or High-Z. 2. Deapply VDDQ. 3. Deapply VDD after or at the same time as VDDQ.
23
MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION (continued)
Fig. 3 - SDRAM READ TIMING EXAMPLE (@ CL=2 & BL=2)
CLK (external)
t0
t1
t2
t3
t4
Command
RD
Stored by CLK input DATA
Hi-Z Q1 Q2
Output in every rising CLK edge
< DDR SDRAM >
t0 CLK CLK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4
Command
RD
Stored by CLK input DQS
Hi-Z Low High
DQS signal transition occurs at the same time as data bus.
DATA
Hi-Z Q1 Q2
Output in every cross point of clock input
24
MB81N643289-50/-60 Preliminary (AE1E)
s MODE REGISTER TABLE
MODE REGISTER SET
ADDRESS REGISTER BA2 0*1 BA1 0*1 BA0 0*1 A10 0 A9 1*2 A8 DR A7 TE A6 - A4 CL A3 BT A2 - A0 BL
A6 0 0 0 1 1 1 1
A5 0 1 1 0 0 1 1
A4 X 0 1 0 1 0 1
CAS Latency (CL) Reserved 2 *5 3*
5
A2 0 0 0 0 1
A1 0 0 1 1 X
A0 0 1 0 1 X
Burst Length (BL) Reserved 2 4 8 Reserved
Reserved Reserved Reserved Reserved
A7 0 1 A8 0 1
Test Mode Entry (TE) Normal Operation Test Mode (Used for Supplier Test Mode) DLL RESET (DR) Normal Operation RESET DLL
A3 0 1 Reserved
Burst Type (BT) Sequential (Wrap round, Binary up)
EXTENDED MODE REGISTER SET (Note *4)
ADDRESS EXTENDED MODE REGISTER BA2 0*3 BA1 0*3 BA0 1*3 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DE
RESERVED *4
A0 0 1
DLL Enable (DE) DLL Enable DLL Disable
Notes: *1. *2. *3. *4. *5.
A combination of BA2 = BA1 = BA0 = 0 (Low) selects standard Mode Register. This field must be set as 1. A combination of BA1-2 = 0 and BA0 = 1 (High) selects Extended Mode Register. The RESERVED field must be set as 0. Write latency (WL) = CL-1
25
MB81N643289-50/-60 Preliminary (AE1E)
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VDD, VDDQ VIN, VOUT IOUT PD TSTG Value -0.5 to +3.6 -0.5 to +3.6 50 2.0 -55 to +125 Unit V V mA W C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter Notes Symbol VDD Supply Voltage VDDQ VSS, VSSQ Input Reference Voltage Single Ended DC Input High Level Single Ended DC Input Low Level Single Ended AC Input High Level Single Ended AC Input Low Level Differential DC Level Input Voltage Differential DC Level Differential Input Voltage Differential AC Level Differential Input Voltage Differential AC Level Input Cross Point Voltage Differential Input Signal Offset Voltage Ambient Temperature *4 *1 *2 *3 VREF VIH(DC) VIL(DC) VIH(AC) VIL(AC) VIN(DC) VSWING(DC) VSWING(AC) VX(AC) VISO(AC) TA Min. 2.3 VDD 0 VDDQ/2 *98% (1.15V min) VREF + 0.25 -0.1 VREF + 0.35 -0.1 -0.1 0.50 0.70 VDDQ/2 - 0.2 VDDQ/2 - 0.2 0 Typ. 2.5 VDD 0 VDDQ/2 -- -- -- -- -- -- -- VDDQ/2 VDDQ/2 -- Max. 2.7 VDD 0 VDDQ/2 *102% (1.35V max) VDDQ + 0.1 VREF - 0.25 VDDQ + 0.1 VREF - 0.35 VDDQ + 0.1 VDDQ + 0.2 VDDQ + 0.2 VDDQ/2 + 0.2 VDDQ/2 + 0.2 70 Unit V V V V V V V V V V V V V C
26
MB81N643289-50/-60 Preliminary (AE1E)
s RECOMMENDED OPERATING CONDITIONS (Continued)
Notes:
VDD + 1V 50% of pulse amplitude VIH VIHmin VIL Pulse width 4 ns VIH VILmax VIL 50% of pulse amplitude -1.0V Pulse width 4 ns
*1. Overshoot limit: VIH (max) = VDD + 1V for pulse width <= 4 ns acceptable, pulse width measured at 50% of pulse amplitude.
*2. Undershoot limit: VIL (min) = VSS -1.0V for pulse width <= 4 ns acceptable, pulse width measured at 50% of pulse amplitude.
*3. VREF is expected to track variations in the DC level of VDDQ of the transmitting device. Peak-to-Peak noise level on VREF may not exceed +/- 2% of the supplied DC value. *4. VISO means {VIN(CLK) + VIN(CLK)} / 2. Refer to Differential Input Signal Definition. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
Differential Input Signal Definition
Fig. 4 - Differential Input Signal Offset Voltage (For Clock Input)
CLK
VX
CLK VSS |VSWING|
VSWING(AC)
0V Differential VISO VISO (min.) VSS VISO (max.)
s CAPACITANCE
(TA = 25C, f = 1 MHz) Parameter Input Capacitance, Address & Control Input Capacitance, CLK & CLK Input Capacitance, DM0 to DM3 I/O Capacitance Symbol CIN1 CIN2 CIN3 CI/O Min. 2.5 2.5 4.0 4.0 Typ. -- -- -- -- Max. 3.5 3.5 5.5 5.5 Unit pF pF pF pF 27
MB81N643289-50/-60 Preliminary (AE1E)
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1,*2,*3
Parameter Output Minimum Source DC Current Output Minimum Sink DC Current Input Leakage Current (any input) Output Leakage Current VREF Current MB81N643289-50 Operating Current (Average Power Supply Current) MB81N643289-60 IDD1S *4 *4 Symbol IOH(DC) IOL(DC) ILI ILO IREF Burst Length = 2 tCK = min, tRC = min for BL = 2 One bank active, Address change up to 3 times during tRC (min) 0 V < VIN < VIL (max), VIH (min) < VIN < VDD PD = VIH, tCK = min All banks idle, NOP commands only, Input signals (except to CMD) are changed one time during 20 ns 0 V < VIN < VIL (max), VIH (min) < VIN < VDD PD = VIL, tCK = min All banks idle, 0 V < VIN < VDD PD = VIH, tCK = min All banks Active, NOP commands only, Input signals (except to CMD) are changed one time during 20 ns 0 V < VIN < VIL (max), VIH (min) < VIN < VDD Condition VDDQ = 2.3V for min, 2.7V for max VOH = VDDQ-0.2V VDDQ = 2.3V for min, 2.7V for max VOL = +0.2V 0 V < VIN < VDD; All other pins not under test = 0 V 0 V < VIN < VDD; Data out disabled Value Min. -4.0 4.0 -10 -10 -10 Max. -6.8 6.8 10 10 10 450 -- 385 mA Unit mA mA A A A
MB81N643289-50 Standby Current MB81N643289-60 IDD2N
85 -- 75 mA
Power Down Current
IDD2P
--
35
mA
Active Standby Current (Power Supply Current)
MB81N643289-50 IDD3N MB81N643289-60
235 -- 200 mA
(Continued)
28
MB81N643289-50/-60 Preliminary (AE1E)
(Continued)
Parameter Symbol Condition Burst Length = 4, CAS Latency = 3, All bank active, Gapples data, tCK = min, 0 V < VIN < VIL (max), VIH (min) < VIN < VDD Burst Length = 4, CAS Latency = 3, All bank active, Gapless data, tCK = min, 0 V < VIN < VIL (max), VIH (min) < VIN < VDD Auto-refresh; tCK = min, tREFC = min 0 V < VIN < VIL (max), VIH (min) < VIN < VDD Self-refresh; PD = VIL, 0 V < VIN < VDD Value Min. Max. 510 -- 430 mA Unit
MB81N643289-50 Bust Read Current (Average Power Supply Current) IDD4R MB81N643289-60
MB81N643289-50 Bust Write Current (Average Power Supply Current) IDD4W MB81N643289-60 MB81N643289-50 IDD5 MB81N643289-60 IDD6
595 -- 505 320 -- 270 -- 5 mA mA mA
Auto-refresh Current (Average Power Supply Current)
Self-refresh Current (Average Power Supply Current)
Notes: *1. All voltages referenced to VSS. *2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure. *3. IDD depends on the output termination or load conditions, clock cycle rate, and number of address and command change within certain period. The specified values are obtained with the output open. *4. Refer to output characteristics for the detail.
29
MB81N643289-50/-60 Preliminary (AE1E)
s DC CHARACTERISTICS (Continued)
OUTPUT CHARACTERISTICS
Fig. 5 - Pull-down Characteristics
60 50 40
Min
VOL (V)
Current(mA) Min 0 11.1 21.6 31.1 39.2 44.6 46.4 N/A Max 0 11.3 22.1 32.3 41.6 49.9 56.3 55.8
Max
0 0.4
Current(mA)
0.8 1.2 1.6 2.0
30 20 10 0
2.4 2.8
0
0.2
0.4 0.6 0.8
1.0
1.2
1.4 1.6 1.8 VOL (V)
2.0 2.2
2.4
2.6 2.8
Fig. 6 - Pull-up Characteristics 0 -10 -20 Current(mA) -30 -40 -50 -60 -70
VDDVOH (V) 0 0.4 0.8 1.2
Current(mA) Min 0 -10.5 -20.1 -28.6 -35.2 -38.7 -40.9 N/A Max 0 -11.0 -21.6 -31.8 -41.6 -50.7 -59.0 -60.4
Min Max
1.6 2.0 2.4 2.8
0
0.2
0.4 0.6 0.8
1.0
1.2
1.4 1.6 1.8 VDD - VOH (V)
2.0 2.2
2.4
2.6 2.8
30
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.) Note *1,*2,*3 AC PARAMETERS (CAS LATENCY DEPENDENT)
Parameter Symbol CL = 3 CL = 2 MB81N643289-50 MB81N643289-60 Min. 5.0 7.5 Max. 9.0 10.5 Min. 6.0 9.0 Max. 10.5 10.5 Unit
Clock Period
tCK
ns
AC PARAMETERS (ABSOLUTE BALES)
Parameter Input Setup Time (Except for DQS, DM and DQs) Input Hold Time (Except for DQS, DM and DQs) Data Input Setup Time Data Input Hold Time DQS First Input Setup Time (Input Preamble Setup Time) Input Transition Time Power Down Exit and Self-refresh Exit Time Notes *4 *4 *5 *5 *4 *6 *4 Symbol tIS tIH tDS tDH tDSPRES tT tPDE MB81N643289-50 MB81N643289-60 Min. 1.0 1.0 0.6 0.6 0 0.1 3.0 Max. -- -- -- -- -- 0.8 -- Min. 1.2 1.2 0.7 0.7 0 0.1 3.6 Max. -- -- -- -- -- 0.9 -- Unit ns ns ns ns ns ns ns
BASE VALUES FOR CLOCK COUNT/LATENCY (Note *7)
Parameter Random Cycle Time Active to Page Close Time Page Close Single Bank to Active Page Close All Bank to Active Auto-refresh Cycle Time Auto-refresh Interval Time between Refresh Pause Time after Power-on Notes Symbol tRC tRAS tPCL tPCAL tREFC tREFI tREF tPAUSE MB81N643289-50 Min. Max. 30 -- 20 55000 10 -- 20 -- 60 -- -- 8.0 -- 32 200 -- MB81N643289-60 Min. Max. 36 -- 24 55000 12 -- 24 -- 72 -- -- 8.0 -- 32 200 -- Unit ns ns ns ns ns s ms s
*8 *8 *8 *9
31
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
AC PARAMETERS (FREQUENCY DEPENDANT) Note *10
Parameter Clock High Time Clock Low Time DQS Low to High Input Transition Setup Time from CLK DQS First Low Input Hold Time (Input Preamble Hold Time) DQS First Low Input Pulse Width (Input Preamble Pulse Width) DQS Last Low Input Hold Time (Input Postamble Hold Time) DQ, DQS, DM Input Pulse Width DQS Input Falling Edge to Clock Setup Time DQS Input Falling Edge to Clock Hold Time QS Access Time from Clock Data Access Time from CLK Data Output Valid Time DQS Output in Low-Z (Output Preamble Setup Time) DQS First Low Output Hold Time (Output Preamble Hold Time) DQS Last Low Output Hold Time (Output Postamble Hold Time) DQS Last Low Output in High-Z from CLK to CLK QS Pulse Width Data Output Valid Time from DQS Data Output skew from DQS DQ Output in Low-Z DQ Output in High-Z *5 *4, *12 *4, *13 *4, *12 *4 *4, *13 *4, *13 *4 *4 Notes *4 *4 *4, *11 *4 Symbol tCH tCL tDQSS tDSPREH tDSPRE tDSPST tDIPW tDSS tDSH tCKQS tAC tOH tQSLZ tQSPRE tQSPST tQSHZ tQSP tQSQV tQSQ tLZ tHZ Min. 0.45 * tCK 0.45 * tCK (CL - 1 - 0.25) * tCK 0.25 * tCK 0.4 * tCK 0.4 * tCK 0.35 * tCK 0.2 * tCK (1.5 ns min) 0.2 * tCK (1.5 ns min) - 0.1 * tCK - 0.2 - 0.1 * tCK - 0.2 - 0.1 * tCK - 0.2 - 0.1 * tCK - 0.2 0.9 * tCK - 0.2 0.4 * tCK - 0.2 -- 0.4 * tCK - 0.2 0.4 * tCK - 0.4 - 0.1 * tCK - 0.1 * tCK - 0.2 - 0.1 * tCK - 0.2 Max. -- -- (CL - 1 + 0.25) * tCK -- 0.6 * tCK 0.6 * tCK -- -- -- 0.1 * tCK + 0.2 0.1 * tCK + 0.2 0.1 * tCK + 0.2 -- 1.1 * tCK + 0.2 0.6 * tCK + 0.2 0.1 * tCK + 0.2 -- -- 0.1 * tCK -- 0.1 * tCK + 0.2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
32
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
EXAMPLE OF FREQUENCY DEPENDANT AC PARAMETERS (@ Minimum tCK)
Parameter Clock High Time Clock Low Time DQS Low to High Input Transition Setup Time from CLK CL=2 tDQSS CL=3 tDSPREH tDSPRE tDSPST tDIPW tDSS tDSH tCKQS tAC tOH tQSLZ tQSPRE tQSPST tQSHZ tQSP tQSQV tQSQ tLZ tHZ 8.8 11.3 10.5 13.5 13.2 16.9 15.8 20.3 18.4 1.3 2.0 2.0 1.8 1.5 1.5 -- 3.0 3.0 -- -- -- 1.5 2.4 2.4 2.1 1.5 1.5 -- 3.6 3.6 -- -- -- 1.9 3.0 3.0 2.7 1.5 1.5 -- 4.5 4.5 -- -- -- 2.3 3.6 3.6 3.2 1.8 1.8 -- 5.4 5.4 -- -- -- 2.7 4.2 4.2 3.7 2.1 2.1 -1.3 -1.3 -1.3 -1.3 9.3 4.0 -- 4.0 3.8 -1.1 -1.3 -1.3 23.7 -- 6.3 6.3 -- -- -- 1.3 1.3 1.3 -- 11.8 6.5 1.3 -- -- 1.1 -- 1.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol tCH tCL tCK = 5ns tCK = 6ns tCK = 7.5ns tCK = 9ns tCK = 10.5ns Unit ns ns ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 2.3 2.3 3.8 -- -- 6.3 2.7 2.7 4.5 -- -- 7.5 3.4 3.4 5.7 -- -- 9.4 4.1 4.1 -- -- 4.8 4.8 7.9 -- -- 13.2
6.8 11.3
DQS First Low Input Hold Time (Input Preamble Hold Time) DQS First Low Input Pulse Width (Input Preamble Pulse Width) DQS Last Low Input Hold Time (Input Postamble Hold Time) DQ, DQS, DM Input Pulse Width DQS Input Falling Edge to Clock Setup Time DQS Input Falling Edge to Clock Hold Time QS Access Time from Clock Data Access Time from CLK Data Output Valid Time DQS Output in Low-Z (Output Preamble Setup Time) DQS First Low Output Hold Time (Output Preamble Hold Time) DQS Last Low Output Hold Time (Output Postamble Hold Time) DQS Last Low Output in High-Z from CLK to CLK QS Pulse Width Data Output Valid Time from DQS Data Output skew from DQS DQ Output in Low-Z DQ Output in High-Z
-0.7 0.7 -0.8 0.8 -1.0 1.0 -1.1 1.1 -0.7 0.7 -0.8 0.8 -1.0 1.0 -1.1 1.1 -0.7 0.7 -0.8 0.8 -1.0 1.0 -1.1 1.1 -0.7 4.3 1.8 -- 1.8 1.6 -- 5.7 3.2 0.7 -- -- -0.8 5.2 2.2 -- 2.2 2.0 -- 6.8 3.8 0.8 -- -- -1.0 6.6 2.8 -- 2.8 2.6 -- 8.5 4.7 1.0 -- -- -1.1 --
7.9 10.1 3.4 -- 3.4 3.2 5.6 1.1 -- --
-0.5 0.5 -0.6 0.6 -0.8 0.8 -0.9 0.9 -0.7 -- -0.8 -- -1.0 -- -1.1 --
-0.7 0.7 -0.8 0.8 -1.0 1.0 -1.1 1.1
33
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
MINIMUM LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Parameter RAS (ACT) to CAS (Read) Delay (minimum) (Applicable to same bank)
Symbol lRCD lRCDW lWRD lRDA lWAL lRPL lWPL lCCD lCBD lRWL lWRL lRSC lPDEX lRRD lPD lLOCK
CL = 3 CL = 2 CL = 3 RAS (ACT) to CAS (Write) Delay (minimum) (Applicable to same bank) CL = 2 CL = 3 Write Command to Read Command Delay Time (Applicable to other bank in page open) CL = 2 CL = 3 Read with Auto-close to Next Command Input Delay (Applicable to same bank) CL = 2 CL = 3 Write with Auto-close Command to Next Command Input Delay (Applicable to same bank) CL = 2 CL = 3 Read to Page Close Command Delay (Applicable to same bank) CL = 2 CL = 3 Write to Page Close Command Delay (Applicable to same bank) CL = 2 CL = 3 CAS to CAS Delay (Applicable to same bank) CL = 2 CL = 3 CAS to CAS Bank Delay (Applicable to other bank) CL = 2 CL = 3 Read Command to Write Command Lead Time (Applicable to any bank in page open) CL = 2 CL = 3 Write Command to Read Command Lead time (Applicable to same bank) CL = 2 CL = 3 Mode Register Set Cycle Time CL = 2 CL = 3 Power Down Exit to Next Command Input Delay (Minimum) CL = 2 CL = 3 Active Command to Next Active (Applicable to other bank) CL = 2 CL = 3 PD Low to Command/Address Input Inactive CL = 2 tCK < 7.5 ns Clock Lock-on Time *14 7.5 to tCK(max)
BL = 2 3 2 1 1 2 2 3 3 7 6 1 1 5 4 1 1 1 1 3 3 5 4 2 2 2 2 1 1 1 1 400 630
BL = 4 3 2 1 1 3 3 4 4 8 7 2 2 6 5 2 2 2 2 4 4 6 5 2 2 2 2 1 1 1 1 400 630
BL = 8 3 2 1 1 5 5 6 6 10 9 4 4 8 7 4 4 4 4 6 6 8 7 2 2 2 2 1 1 1 1 400 630
Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
34
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure and stable clock input with constant clock period and with 50% duty cycle. *2. Access Times assume input slew rate of 1ns/volt between VREF+0.35V to VREF-0.35V, where VREF is VDDQ/2, with 1 resistor and 1 capacitor load conditions. Refer to AC TEST LOAD CIRCUIT in page 36. *3. VREF = 1.25V is a typical reference level for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max) unless otherwise noted. Refer to AC TEST CONDITIONS in page 36. *4. This parameter is measured from the cross point of CLK and CLK input. *5. This parameter is measured from signal transition point of DQS input crossing VREF level. *6. tT is defined as the transition time between VIH (AC)(min) and VIL (AC)(max). *7. All base values are measured from the cross point of the rising edge of CLK and falling edge of CLK at the command input to the cross point of same clock input condition for the next command input. All clock counts (= latency) are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). Clock > Base Value Clock Period (Round off a whole number)
*8. Total of 4096 REF command must be issued within tREF(max). tREFC is a reference value for distributed refresh and specifies the time between one REF command to next REF command except for a condition where PD = L during Self-Refresh mode. *9. Specified when the clock input is started on the condition of the stable supply voltage. *10. Frequency dependent AC parameters are scalable by actual clock period (tCK) and affected by an abrupt change of duty cycle, jitters on clock input, TA and level of VDD and VDDQ. The internal DLL circuit can adjust delay time to change and following level change of VDD and VDDQ, (change rate of TA < 0.1 C / 20 ns, change rate of VDD and VDDQ < 1 mV / 10 ns. If change rate is bigger than these value, frequency dependent AC parameters affected by jitters causing by these change.) *11. More than 2 signal edge of DQS0-3 should not be input within 1 clock (tCK) cycle. *12. Low-Z (Low Impecdnce State) is specified and measured at VDD / 2 +/- 200 mV from standby state. *13. tHZ are specified where output buffer is no longer driven. *14. Clock period must satisfy specified tCK and it must be stable. Applicable also if device operating conditions such as supply voltages, case temperature, and/or clock frequency (tCK difference must be 0.2 ns and under) is changed during any operation.
35
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Fig. 7 - EXAMPLE OF AC TEST LOAD CIRCUIT (2.5 V CMOS Source Termination)
R = 50 Output
VDDQ/2
CL = 20 pF
Note: By adding appropriate correlation factors to the test conditions, tAC and tOH measured when the Output is coupled to the Output Load Circuit are within specifications.
AC TEST CONDITIONS
Parameters Single-end Input Input High Level Input Low Level Input Reference Level Input Slew Rate Differential Input (CLK and CLK) Input Reference Level Input Level Input Slew Rate Vr VSWING SLEW Vx(AC) 0.7 1.0 V V V/ns VIH VIL VREF SLEW VREF+0.35 VREF-0.35 VDDQ/2 1.0 V V V V/ns Symbol Value Unit
VX means the actual cross point between CLK and CLK input.
36
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Fig. 8 - AC TIMING of CLK & CLK
tCK CLK
VX VSWING(AC)
tCL
tOH
CLK
Note: Reference level for AC timings of clock are the cross point of CLK and CLK as specified in VX.
Fig. 9 - AC TIMING of Command Input & Address
tCK CLK
VX
CLK tIS Input (Controls & Addresses) tIH
VIH (AC) Input Valid VREF VIL (AC)
Note: The cross point of CLK and CLK (VX) is used for command and address input. The reference level of single ended input is VREF.
Fig. 10 - AC TIMING of Write Mode (Data Strobe, Write Data and Data Mask Input)
tCK CLK CLK tIS Input (Controls & Addresses) tIH
VIH (AC) Write Command VREF VIL (AC)
tCK
tDSS tDQSS tDIPW tDIPW
tDSH tDIPW tDSPST
VREF
tDQSS tDSPRES tDSPREH tDSPRE
VIL
DQS Input (@BL=4)
VREF
tDS Input (Data&DM)
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Input Valid
Input Valid
Input Valid
Input Valid
tDIPW
37
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Fig. 11 - AC TIMING of Read Mode (Clock to DQS Output Delay Time)
tCK CLK CLK tQSLZ
(min)
tCK
VX
tCKQS
(min)
tCKQS
(min)
tCKQS
(min)
tCKQS
(min)
tQSHZ tCKQS
(max)
tQSPRE DQS Output (@BL=4)
Hi-Z VIL
tCKQS
(max)
tCKQS
(max)
tCKQS
(max)
tQSP
tQSP
tQSP tQSPST
Note: DQS Access time (tQSCK) is measured from the cross point of clock (VX) and VREF. The end of tQSPST and tQSHZ specification is defined at where output buffer is no longer driven.
Fig. 12 - AC TIMING of Read Mode (Clock to Data Output Delay Time)
tCK CLK CLK tAC
(min)
tCK
VX
tAC
(min)
tAC
(min)
tAC
(min)
tOH
(min)
tLZ
(min)
tOH tAC
(max) (max)
tAC
(max)
tAC
(max)
tAC
(max)
DQ Data Output (@BL=4)
Hi-Z
tHZ
(max)
VIH VIL
Note: Access time (tAC) is measured from the cross point of clock (VX) and VREF. The end of tHZ specification is defined at where output buffer is no longer driven.
Fig. 13 - AC TIMING of Read Mode (DQS Output to Data Output Delay Time)
DQS Output (@BL=4) tQSQ
(min)
VREF
tQSQ
(min)
tQSQ
(min)
tQSQ
(min)
tQSQ DQ Data Output (@BL=4)
(max)
tQSQ
(max)
tQSQ
(max)
tQSQ
(max)
Hi-Z
VIH VIL
tQSQV
tQSQV
tQSQV
tQSQV
Note: DQS Output Edge to Data Output Edge Skew Time (tQSQ) is measured from VDDQ/2 to VDDQ/2.
38
MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Fig. 14 - AC TIMING, PULSE WIDTH
CLK CLK
VX VX
tRC, tRAS, tPCAL, tREF, tREFI, tREFC, tPAUSE
Input (Controls & Addresses)
Command
Command
Note: All parameters listed above are measured from the cross point at rising edge of the CLK and falling edge of CLK of one command input to next command input.
Fig. 15 - AC TIMING of Power Down Mode
tRC (min), tREF (max)
PD
VREF tPDE lPDEX (min)
CLK CLK
lPD
Command
NOP
PDEN
NOP
Don't Care
PDEX
NOP
ACTV
Note: Minimum 2 clock cycles is required for complete power down on clock buffer.
Fig. 16 - AC TIMING of Self-refresh Mode
tREFC (min)*2
PD
VREF tIS tPDE lLOCK (min)
CLK CLK
Note *1 lPD
Command
NOP
SELF
NOP
Don't Care
NOP
NOP
ACTV
Note: 1. Minimum 2 clock cycles is required for complete power down on clock buffer. 2 PD must maintain High level and clock must be provided during the lLOCK period. lLOCK must be satisfied before any command input.
39
MB81N643289-50/-60 Preliminary (AE1E)
s TIMING DIAGRAMS
TIMING DIAGRAM - 1 : PAGE MODE READ (Timing assumes Same Bank Access)
CLK CLK lRCD Command
ACTV NOP RD
lCCD
RD RD
lRPL
PC
tPCL
NOP ACTV NOP RDA NOP
tRAS DQ (Output) @CL = 3 DQS (Output) @CL = 3
Hi-Z
Q1 Q2 Q1 Q2 Q1 Q2
CL CL CL Hi-Z
DQ (Output) @CL = 2 DQS (Output) @CL = 2
Hi-Z
Q1 Q2 Q1 Q2 Q1 Q2
CL CL CL Hi-Z
Notes: 1. lRCD :Latency of ACTV to Read command input delay. 2. lCCD :Latency of CAS to CAS delay (Page cycle time). 3. lRPL :Latency of Read command to Page Close lead time. 4. tPCL :Page Close to next command lead time.
40
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 2 : RANDOM READ WITH AUTO-CLOSE (Timing assumes CL=3, Same Bank Access)
CLK CLK lRCD Command
ACTV NOP RDA
lRDA
NOP ACTV NOP RDA NOP ACTV NOP
DQ (Output) @BL = 2 DQS (Output) @BL = 2
Hi-Z
Q1 Q2
Q1 Q2
CL Hi-Z
CL
lRCD Command
ACTV NOP RDA
lRDA
NOP ACTV NOP RDA NOP ACTV NOP
DQ (Output) @BL = 4 DQS (Output) @BL = 4
Hi-Z
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
CL Hi-Z
CL
lRCD Command
ACTV NOP RDA
lRDA
NOP ACTV NOP RDA NOP
DQ (Output) @BL = 8 DQS (Output) @BL = 8
Hi-Z
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q1 Q2 Q3 Q4
CL Hi-Z
CL
Note: lRDA : Latency of Read with Auto Close command.
41
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 3 : RANDOM WRITE (Timing assumes CL=3, BL=4, Same Bank Access)
CLK CLK lRCDW Command
ACTV WR
lWPL
NOP PC
tPCL
NOP ACTV NOP
WL (= CL-1)
DQ (Output)
Hi-Z
D1 D2 D3 D4
tDQSS DQS (Output)
Hi-Z
Notes: 1 2
lRCDW : Letency of ACTV to Write command input delay is minimum 1 clock. lWPL : Latency of Write command to Auto Close command lead time.
TIMING DIAGRAM - 4 : RANDOM WRITE WITH AUTO-CLOSE (Timing assumes CL=3, BL=4, Same Bank Access)
CLK CLK lRCDW Command
ACTV WRA
lWAL
NOP ACTV NOP
WL (= CL-1)
DQ (Output)
Hi-Z
D1 D2 D3 D4
tDQSS DQS (Output)
Hi-Z
Note: lWAL : Latency Write with Auto Close command to next Active command lead time.
42
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 5 : PAGE MODE WRITE (Timing assumes CL=3, BL=4, Same Bank Access)
CLK CLK lRCDW Command
ACTV WR
lCCD
NOP WRA
lWAL
NOP ACTV NOP
DQ (Output)
Hi-Z
D1 D2 D3 D4 D1 D2 D3 D4
WL WL
DQS (Output)
Hi-Z
TIMING DIAGRAM - 6 : PAGE MODE WRITE (Timing assumes CL=3, BL=2, Same Bank Access)
CLK CLK lRCDW Command
ACTV
lCCD
WR
lWPL
NOP PC
tPCL
NOP ACTV NOP
WR
DQ (Output)
Hi-Z
D1 D2 D1 D2
WL WL
DQS (Output)
Hi-Z
43
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 7 : RANDOM READ (Timing assumes CL=3, BL=4, Multiple Bank Access)
CLK CLK
lRCD lRDA
RDAa NOP RDAb NOP
lRCD
ACTVa ACTVb NOP RDAa NOP
Command
ACTVa ACTVb NOP
lRRD
lCBD
DQ (Output)
Hi-Z
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
CL (Bank b) CL (Bank a) CL (Bank a)
DQS (Output)
Hi-Z
Notes: 1 2
lCBD : Latency of CAS to CAS Bank Delay lRRD : Latency of Active command to next Active command.
TIMING DIAGRAM - 8 : RANDOM READ (Timing assume CL=3, BL=4, Multiple Bank Access)
CLK CLK
lRCD lRDA
RDa NOP RDb NOP RDa NOP RDb NOP PCa
tPCL
NOP ACVTa PCb
Command
ACTVa ACTVb NOP
lRRD
lCBD
DQ (Output)
Hi-Z
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CL (Bank b) CL (Bank a) CL (Bank b) CL (Bank a)
DQS (Output)
Hi-Z
44
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 9 : RANDOM WRITE (Timing assumes CL=3, BL=4, Multiple Bank Access)
CLK CLK
lWAL
Command
ACTVa ACTVb NOP
WRAa NOP
WRAb
NOP
ACTVa ACTVb NOP
NOP
lRRD
lCBD
DQ (Output)
Hi-Z
D1 D2 D3 D4 D1 D2 D3 D4
WL (Bank b) WL (Bank a)
DQS (Output)
Hi-Z
TIMING DIAGRAM - 10 : RANDOM WRITE (Timing assumes CL=2, BL=4, Multiple Bank Access)
CLK CLK
lWPL tPCL
NOP PCa NOP ACTVa PCb NOP
Command
ACTVa ACTVb NOP
WRa
NOP
WRb
lRRD
lCBD
DQ (Output)
Hi-Z
D1 D2 D3 D4 D1 D2 D3 D4
WL (Bank b) WL (Bank a)
DQS (Output)
Hi-Z
45
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 11 : RANDOM READ / WRITE (Timing assumes CL=2, BL=2, Same Bank Access)
CLK CLK
lRCD lRDA
RDA NOP ACTV NOP WR_ NOP
Command
ACTV
NOP
CL Hi-Z
WL
DQ
Q1
Q2
D1
D2
DQS
Hi-Z
TIMING DIAGRAM - 12 : RANDOM READ / WRITE (Timing assumes CL=2, BL=4, Same Bank Access)
CLK CLK
lWAL
Command
ACTV
NOP
WRA
NOP
ACTV
NOP
RD_
WL Hi-Z
DQ
D1
D2
D3
D4
DQS
Hi-Z
46
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 13 : PAGE MODE READ / WRITE (Timing assumes CL=3, BL=4, Same Bank Access)
CLK CLK
lRCD lRWL
RD NOP WR
lWRL
NOP RD NOP
Command
ACTV
NOP
DQ
Hi-Z
Q1 Q2 Q3 Q4
D1 D2 D3 D4
CL
WL
DQS
Hi-Z
Notes: 1. lRWL : Letency of Read to Write command. 2. lWRL : Latency of Read to Write command in same bank.
TIMING DIAGRAM - 14 : PAGE MODE READ / WRITE (Timing assumes CL=3, BL=4, Multiple Bank Access)
CLK CLK
lRCD lRWL
RDa NOP WRb
lWRD
NOP RDa NOP PCb PCa
Command
ACTVa ACTVb NOP
DQ
Hi-Z
Q1 Q2 Q3 Q4
D1 D2 D3 D4
Q1 Q2 Q3 Q4
CL (Bank a)
WL (Bank b)
CL (Bank a)
DQS
Hi-Z
Notes: 1. lWRD : Latency of Write to Read command in different bank. 2. Data Strobe Input must be applied after or before output of DQS is in High-Z.
47
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 15 : PAGE MODE READ / WRITE (Timing assumes CL=3, BL=4, Multiple Bank Access)
CLK CLK
lRCD lWRD
WRa NOP RDb
lRPL
NOP PCA
tPCAL
NOP ACTV NOP
Command
ACTVa ACTVb NOP
DQ
Hi-Z
D1 D2 D3 D4
Q1 Q2 Q3 Q4
WL (Bank a)
CL (Bank b)
DQS
Hi-Z
TIMING DIAGRAM - 16 : AUTO-REFRESH (Timing assumes CL=2, BL=2)
CLK CLK
lRDA tREFC
REF NOP Any
Command
ACTV
NOP
RDA
NOP
DQ
Hi-Z
Q1
Q2
DQS
Hi-Z
Note: Refresh command can be issued all banks has been closed.
48
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 17 : SELF-REFRESH (Timing assumes CL=2)
CLK CLK
tPDE
PD
lLOCK
Command
NOP
SELF
NOP
Don't Care
SELFX
NOP
Any
DQ
Hi-Z
TIMING DIAGRAM - 18 : POWER DOWN (Timing assumes any CL)
CLK CLK
tPDE
PD
lPDEX
Command
NOP
PDEN
NOP
PDEX
NOP
Any
NOP
DQ
Hi-Z
Note: lPDEX : Latency of Power Down Exit to next command input delay. tREF must be satisfied for burst refresh and tAREF must be satisfied for distributed refresh.
49
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 19 : MODE REGISTER SET (Timing assumes any CL and frequency)
CLK CLK
lRSC
Command
NOP
MRS
NOP
Any
NOP
Note: lRSC : Latency of Mode Register Set to next command lead time.
50
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 20 : POWER-UP INITIALIZATION
VDD VDDQ VREF
tCK tCH tCL llock
CLK CLK
PD
VREF
tPCAL tIS Command tIH
PCA
lRSC
lRSC
tPCL
tREF
tREFC
NOP
EMRS
MRS
PC
REF
REF
MRS
ACT
A0 to A9
DE
DR,
CL,BL
RA
A10
L
L
L
RA
BA0
H
L
L
BA
BA1,BA2
L
L
L
BA
DQ
Hi-Z
Hi-Z
DQS
51
MB81N643289-50/-60 Preliminary (AE1E)
s SCITT TEST MODE
ABOUT SCITT
SCITT (Static Component Interconnection Test Technology) is an XNOR circuit based test technology that is used for testing interconnection between SDRAM and SDRAM controller on the printed circuit boards. SCITT provides inexpensive board level test mode in combination with boundary-scan. The basic idea is simple, consider all output of SDRAM as output of XNOR circuit and each output pin has a unique mapping on the input of SDRAM. The ideal schematic block diagram is as shown below.
SDRAM Controller
C
Boundary Scan
TEST Control
xAddress Bus
SDRAM CORE XNOR
ASIC
Data Bus
TEST Control : CAS, CS, PD xAddress Bus : A0 to A10, BA0 to BA2, RAS, DM0 to DM3, CLK, CLK, WE Data Bus : DQ0 to DQ31, DQS0 to DQS3
It is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short faults.
52
MB81N643289-50/-60 Preliminary (AE1E)
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge command in POWER-UP INITIALIZATION. Once Precharge command is issued to SDRAM, it never get back to SCITT Test Mode during regular operation for the purpose of a fail-safe way in get in and out of test mode. 1. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins and attempt to maintain all input signals to be Low state (or at least PD to be Low state). 2. Apply VDD voltage to all VDDQ pins before or at the same time as VREF. 3. Apply VREF. 4. Maintain stable power for a minimum of 100s. 5. Enter SCITT test mode. 6. Execute SCITT test. 7. Exit from SCITT mode. It is required to follow Power On Sequence to execute read or write operation. 8. Start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200s. 9. After the minimum of 200s stable power and clock, apply NOP condition and take PD to be High state. 10.Issue Page Close All Banks (PCA) command or Page Close Single Bank (PC) command to every banks. 11.Issue EMRS to enable DLL, DE = Low. 12.Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lLOCK*1 period is required to lock the DLL. 13.Apply minimum of two Auto-refresh command (REF).*2 14.Program the mode register by Mode Register Set command (MRS) with DR = Low.*2 The 5,6,7 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to POWERUP INITIALIZATION). Notes: *1. The lLOCK depends on operating clock period. The lLOCK is counted from "DLL Reset" at step-8 to any command input at step-10. *2. The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
COMMAND TRUTH TABLE Note *1
Control CAS SCITT mode entry HL *2 SCITT mode exit SCITT mode output enable *4 Notes: *1. *2. *3. *4. *5. LH *3 L CS L H *5 L PD L L *5 H WE X X V RAS X X V Input A0 to A10, BA0 to BA2 X X V DM0 to DM3 X X V CLK, CLK X X V Output DQ0 to DQ31 X X V DQS0 to DQS3 X X V
L = Logic Low, H = Logic High, V = Valid, X = either L or H The SCITT mode entry command assumes the first CAS falling edge with CS and PD = L after power on. The SCITT mode exit command assumes the first CAS rising edge after the test mode entry. Refer the test code table. CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
53
MB81N643289-50/-60 Preliminary (AE1E)
TEST CODE TABLE
DQ0 to DQ31 and DQS0 to DQS3 output data is static and is determined by following logic during the SCITT mode operation.
DQ0 = RAS xnor A0 DQ1 = RAS xnor A1 DQ2 = RAS xnor A2 DQ3 = RAS xnor A3 DQ4 = RAS xnor A4 DQ5 = RAS xnor A5 DQ6 = RAS xnor A6 DQ7 = RAS xnor A7 DQ8 = RAS xnor A8 DQ9 = RAS xnor A9 DQ10 = RAS xnor A10 DQ11 = RAS xnor BA1 DQ12 = RAS xnor BA0 DQ13 = RAS xnor BA2 DQ14 = RAS xnor DM0 DQ15 = RAS xnor DM1 DQ16 = RAS xnor DM2 DQ17 = RAS xnor DM3 DQ18 = RAS xnor CLK DQ19 = RAS xnor CLK DQ20 = RAS xnor WE DQ21 = A0 xnor A1 DQ22 = A0 xnor A2 DQ23 = A0 xnor A3 DQ24 = A0 xnor A4 DQ25 = A0 xnor A5 DQ26 = A0 xnor A6 DQ27 = A0 xnor A7 DQ28 = A0 xnor A8 DQ29 = A0 xnor A9 DQ30 = A0 xnor A10 DQ31 = A0 xnor BA0 DQS0 = A0 xnor BA1 DQS1 = A0 xnor BA2 DQS2 = A0 xnor DM0 DQS3 = A0 xnor DM1
* EXAMPLE OF TEST CODE TABLE
Input bus Output bus RAS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 BA1 BA2 DM0 DM1 DM2 DM3 CLK CLK WE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS0 DQS1 DQS2 DQS3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 H L L H H H H H H H H H H H H H H H H H H H H L L H H H H H H H H H H H H H H H H H H H H H H L H L H H H H H H H H H H H H H H H H H H H L H L H H H H H H H H H H H H H H H H H H H H H L H H L H H H H H H H H H H H H H H H H H H L H H L H H H H H H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H H H H H H L H H L H H H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H H H H L H L H H H H H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H H H H H H L L H H H H H H H H H H H H H H H H H H H H L H H H L L H H H H H H H H H H H H H H H H H H H H L L H H H H H H H H H H H H H H H H H H H H H H L H L H H H H H H H H H H H H H H H H H H H L H L H H H H H H H H H H H H H H H H H H H H H L H H L H H H H H H H H H H H H H H H H H H L H H L H H H H H H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H L H H H H H H
0 = input Low, 1 = input High, L = output Low, H = output High
54
MB81N643289-50/-60 Preliminary (AE1E)
AC SPECIFICATION
Parameter tTS tTH tEPD tTLZ tTHZ tTCA tTIA tTOH tETD tTIH Description Test mode entry set up time Test mode entry hold time Test mode exit to power on sequence delay time Test mode output in Low-Z time Test mode output in High-Z time Test mode access time from control signals (output enable & chip select) Test mode Input access time Test mode Output Hold time Test mode entry to test delay time Test mode input hold time Minimum 10 10 10 0 0 -- -- 0 10 30 Maximum -- -- -- -- 20 40 20 -- -- -- Units ns ns ns ns ns ns ns ns ns ns
TIMING DIAGRAMS
TIMING DIAGRAM - 1 : POWER-UP TIMING DIAGRAM
*2 VDD 100s Pause Time Test Mode Entry Point CS
PD
CAS
*3
*1
Notes: *1. SCITT is enabled if CS = L, PD = L, CAS = L at just power on. *2. All output buffers maintains in High-Z state regardless of the state of control signals as long as the above timing is maintained. *3. CAS must not be brought from High to Low.
55
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence and normal operation VCC Pause 100s tTS tTH Test Mode tEPD
CAS
HL
CS
L
PD
L *3 *2 Entry
*2. PC or PCA commands must not be asserted. Test mode is disable by those commands. *3. Outputs must be disabled by CS = H or PD = L before Exit.
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, PD pins will have some problems.
56
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 3 : OUTPUT CONTROL (1)
VDD
Entry CAS must not brought from High to Low
CAS DQ turn to Low-Z at CS=L and PD=H CS DQ turn to High-Z at CS=H
PD High-Z
DQ0 to DQ31 DQS0 to DQS3 Memory device output buffer status
High-Z Time (a)
tTLZ
Low-Z Time (b)
tTHZ
High-Z Time (c)
This is not bus line level
TIMING DIAGRAM - 4 : OUTPUT CONTROL (2)
VDD
Entry CAS must not brought from High to Low
CAS DQ turn to Low-Z at CS=L and PD=H CS DQ turn to High-Z at PD=L PD High-Z
DQ0 to DQ31 DQS0 to DQS3 Memory device output buffer status
High-Z Time (a)
tTLZ
Low-Z Time (b)
tTHZ
High-Z Time (c)
This is not bus line level
57
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 5 : TEST TIMING (1)
Test mode Entry Command tETD CAS Test mode Entry Under test
CS PD
DQ becomes Low-Z at CS=L and PD=H
A0 tTCA Under Check Pins A1 tTIA A2 tTOH DQ0 to DQ31 DQS0 to DQS3 tTLZ Valid tTOH Valid Valid tTIA tTIA
58
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 6 : TEST TIMING (2)
Test mode Entry CAS L Test mode Exit
Under test
CS-#1
L H Changed under test devices Tested #1 device Tested #2 device
CS-#2
PD tTIH tTIH tTIH tTCA tTLZ Under Check Pins tTHZ A1 tTIA A2 tTOH DQ0 to DQ31 DQS0 to DQS3 Valid tTOH Valid Valid tTOH Valid Valid tTIA tTIA tTIA tTIA
A0
59
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM - 7 : TEST TIMING (3)
Test mode Entry CAS L Test mode Exit
Under test
CS-#1
L H Changed under test devices Tested #1 device Tested #2 device
CS-#2
PD tTIH tTIH tTHZ tTIH
A0 tTCA A1 tTIA A2 tTOH DQ0 to DQ31 DQS0 to DQS3 Valid tTOH Valid Valid tTOH Valid Valid tTIA tTIA tTLZ tTIA tTIA
Under Check Pins
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MB81N643289-50/-60 Preliminary (AE1E)
s PACKAGE DIMENSIONS
86-pin plastic TSOP (II) (FPT-86P-M01)
86 44
Details of "A" part
0.25(.010)
INDEX 0~8 0.45/0.75 (.018/.030)
LEAD No.
1
43
* 22.220.10(.875.004) 0.22 0.04 +.002 .009 .002
+0.05
11.760.20(.463.008) 1.20(.047)MAX
(Mounting height)
0.10(.004)
M
10.160.10(.400.004)
0.145 0.03 +.002 .006 .001
+0.05
0.50(.020)TYP
0.10(.004) 21.00(.827)REF
0.100.05 (.004.002) (STAND OFF)
"A"
C
1996 FUJITSU LIMITED F86001S-1C-1
Dimensions in mm (inches)
61
MB81N643289-50/-60 Preliminary (AE1E)
MEMO
62
MB81N643289-50/-60 Preliminary (AE1E)
MEMO
63
MB81N643289-50/-60 Preliminary (AE1E)
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3753 Fax: (044) 754-3332 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and office equipment industrial, communications, and measurement equipment, personal or household devices, etc.). IMPORTANT NOTE: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high lives of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. There is a slight risk of failure with all semiconductor devices. You must protect against injury, damage to loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If the products described in this document represent goods or technologies subject to restrictions based on the Foreign Exchange and Foreign Trade Control Low, you must obtain permission to export these products.
F0003 (c) FUJITSU LIMITED Printed in Japan
64

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