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| PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER FEATURES * Two LVDS outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.41ps (typical) * Full 3.3V or 2.5V supply modes * -40C to 85C ambient operating temperature GENERAL DESCRIPTION The ICS844002I-01 is a 2 output LVDS Synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from ICS. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The ICS844002I-01 uses ICS' 3 rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ether net jitter requirements. The ICS844002I-01 is packaged in a small 20-pin TSSOP package. ICS FREQUENCY SELECT FUNCTION TABLE M Divider Value 25 25 25 Not Used N Divider Value 4 5 10 Output Frequency (MHz) (25MHz Reference) 156.5 125 62.5 Not Used PIN ASSIGNMENT nc VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 nQ1 GND VDD nXTAL_SEL TEST_CLK XTAL_IN XTAL_OUT F_SEL1 F_SEL1 F_SEL0 0 0 1 1 0 1 0 1 ICS844002I-01 BLOCK DIAGRAM F_SEL[1:0] Pulldown nPLL_SEL Pulldown TEST_CLK Pulldown 25MHz 2 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View Q0 1 1 XTAL_IN OSC XTAL_OUT nXTAL_SEL Pulldown 0 Phase Detector VCO 625MHz (w/25MHz Reference) F_SEL[1:0] 0 0 /4 0 1 /5 1 0 /10 11 not used nQ0 0 Q1 nQ1 M = 25 (fixed) MR Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844002AGI-01 www.icst.com/products/hiperclocks.html 1 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1, 7 2, 20 3, 4 5 Name nc VDDO Q0, nQ0 MR Type Unused Power Ouput Input Description No connect. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Power supply ground. Differential output pair. LVDS interface levels. 6 8 9, 11 10, 16 12, 13 14 15 17 18, 19 nPLL_SEL VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN TEST_CLK nXTAL_SEL GND nQ1, Q1 Input Power Input Power Input Input Input Power Output NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k 844002AGI-01 www.icst.com/products/hiperclocks.html 2 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER 4.6V -0.5V to VCC + 0.5V 10mA 15mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 TBD TBD TBD Maximum 3.465 3.465 3.465 Units V V V mA mA mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 TBD TBD TBD Maximum 2.625 2.625 2.625 Units V V V mA mA mA TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465 or 2.5V VDD = 3.465V or 2.5V, VIN = 0V -150 Minimum Typical 2 1.7 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A IIL A 844002AGI-01 www.icst.com/products/hiperclocks.html 3 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 40 1.4 50 Maximum Units mV mV V mV TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 40 1.2 50 Maximum Units mV mV V mV TABLE 4. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. 22.4 Test Conditions Minimum Typical 25 Maximum 27.2 50 7 1 Units MHz pF mW Fundamental 844002AGI-01 www.icst.com/products/hiperclocks.html 4 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 TBD 156.25MHz, (1.875MHz - 20MHz) 0.41 0.44 0.47 450 125MHz, (1.875MHz - 20MHz) 62.5MHz,(1.875MHz - 20MHz) 20% to 80% Typical Maximum 170 136 68 Units MHz MHz MH z ps ps ps ps ps % TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time tsk(o) tjit(O) tR / tF odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time 125MHz, (1.875MHz - 20MHz) 62.5MHz,(1.875MHz - 20MHz) tR / tF 20% to 80% Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 TBD 0.41 0.44 0.47 480 Typical Maximum 170 136 68 Units MHz MHz MH z ps ps ps ps ps % tsk(o) tjit(O) odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. 844002AGI-01 www.icst.com/products/hiperclocks.html 5 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION Qx 3.3V5% POWER SUPPLY + Float GND - SCOPE 2.5V5% POWER SUPPLY + Float GND - Qx SCOPE LVDS nQx LVDS nQx 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT nQx 80% Qx nQy Qy tsk(o) 80% VSW I N G Clock Outputs 20% tR tF 20% OUTPUT SKEW PROPAGATION DELAY Phase Noise Plot Noise Power nQ0, nQ1 Q0, Q1 t PW t PERIOD Phase Noise Mask odc = f1 Offset Frequency f2 t PW t PERIOD x 100% RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER 844002AGI-01 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 6 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER VDD VDD out out DC Input LVDS 100 VOD/ VOD out DC Input LVDS out VOS/ VOS DIFFERENTIAL OUTPUT VOLTAGE SETUP OFFSET VOLTAGE SETUP 844002AGI-01 www.icst.com/products/hiperclocks.html 7 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA. 3.3V or 2.5V VDD .01F V DDA .01F 10F 10 FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS844002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 844002AGI-01 www.icst.com/products/hiperclocks.html 8 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near 3.3V or 2.5V VDD LVDS R1 100 + - FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844002AGI-01 www.icst.com/products/hiperclocks.html 9 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP JA by Velocity (Meters per Second) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS844002I-01 is: 2914 844002AGI-01 www.icst.com/products/hiperclocks.html 10 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER 20 LEAD TSSOP PACKAGE OUTLINE - G SUFFIX FOR TABLE 7. PACKAGE DIMENSIONS SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX Reference Document: JEDEC Publication 95, MO-153 844002AGI-01 www.icst.com/products/hiperclocks.html 11 REV. A JUNE 14, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844002I-01 FEMTOCLOCKSTMCRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number ICS844002AGI-01 ICS844002AGI-01T Marking ICS44002AI01 ICS44002AI01 Package 20 Lead TSSOP 20 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C The aforementioned trademark, HiPerClockSTM and FEMTOCLOCKSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844002AGI-01 www.icst.com/products/hiperclocks.html 12 REV. A JUNE 14, 2005 |
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