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PRELIMINARY
CY7C1011
128K x 16 Static RAM
Features
* High speed -- tAA = 15 ns * Low active power -- 1150 mW (max.) * Low CMOS standby power (L version) -- 40 mW (max.) * 2.0V Data Retention (4 mW at 2.0V retention) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011 is available in a standard 44-pin TSOP II package with center power and ground (revolutionary) pinout.
Functional Description
The CY7C1011 is a high-performance CMOS static RAM organized as 131,072 words by 16 bits. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable
Logic Block Diagram
INPUT BUFFER
Pin Configuration
TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A0 A1 A2 A3 A4 A5 A6 A7 A8
256K x 16 ARRAY 1024 x 4096
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER
BHE WE CE OE BLE
1011-1
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
1011-2
ROW DECODER
Selection Guide
7C1011-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Com'l 15 230 8 7C1011-20 20 220 8 7C1011-25 25 200 8
Cypress Semiconductor Corporation
A9 A10 A 11 A 12 A 13 A14 A15 A16
SENSE AMPS
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 November 19, 1998
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V Range Commercial Ambient Temperature[2] 0C to +70C
CY7C1011
DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA
Operating Range
VCC 5V 0.5
Electrical Characteristics Over the Operating Range
7C1011-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 Com'l Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -1 -1 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 230 40 2.2 -0.5 -1 -1 Max. 7C1011-20 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 220 40 2.2 -0.5 -1 -1 Max. 7C1011-25 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 200 40 Max. Unit V V V V A A mA mA
ISB2
8
8
8
mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 255 R1 481 R1 481 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND 3ns 3.0V 90% 10% 90% 10% 3 ns ALL INPUT PULSES
1011-3 1011-4
THEVENIN EQUIVALENT 167 1.73V OUTPUT
2
PRELIMINARY
Switching Characteristics[4] Over the Operating Range
7C1011-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z
[5] [5, 6]
CY7C1011
7C1011-20 Min. 20 Max.
7C1011-25 Min. 25 Max. Unit ns 25 3 25 10 0 10 5 10 0 25 10 0 10 25 15 15 0 0 15 10 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 15 ns ns
Description
Min. 15
Max.
15 3 15 7 0 7 3 7 0 15 7 0 7 15 12 12 0 0 12 8 0 3 7 12 13 20 13 13 0 0 13 9 0 3 0 0 3 0 3
20 20 8 8 8 20 8 8
OE HIGH to High Z
CE LOW to Low Z[5] CE HIGH to High Z[5, 6] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z CYCLE[7,8] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[5] WE LOW to High Z
[5, 6]
8
Byte Enable to End of Write
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
3
PRELIMINARY
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current Com'l VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC Conditions[10] Min. 2.0 2
CY7C1011
Max.
Unit V mA
tCDR[3] tR[9]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
1011-5
VDR > 2V
3.0V tR
Switching Waveforms
Read Cycle No. 1
[11, 12]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1011-6
Notes: 9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 12. WE is HIGH for read cycle.
4
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE V CC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD tHZOE
[12, 13]
CY7C1011
HIGH IMPEDANCE
DATA OUT
IICC CC 50% IISB SB
1011-7
Write Cycle No. 1 (CE Controlled)
[14, 15]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD
tHA
1011-8
Notes: 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
CY7C1011
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATAI/O tHD
tHA
1011-9
Write Cycle No.3 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
1011-10
6
PRELIMINARY
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8-I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Power Down Read All bits Read Lower bits only Read Upper bits only Write All bits Write Lower bits only Write Upper bits only Selected, Outputs Disabled Mode
CY7C1011
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 15 20 25 Ordering Code CY7C1011-15VC CY7C1011-20VC CY7C1011-25ZC Package Name Z44 Z44 Z44 Package Type 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II Operating Range Commercial
Document #: 38-00744
Package Diagram
44-Pin TSOP II Z44
51-85087-A
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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