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PI6C185-02B
Precision 1-7 Clock Buffer
Features
High speed: 140 MHz Low noise non-inverting 1-7 buffer Supports up to three SDRAM DIMMs Low skew (<250ps) between any two output clocks I2C Serial Configuration interface Multiple Vdd, Vss pins for noise reduction 3.3V power supply voltage 16-pin TSSOP (L) and QSOP (Q) packages
Description
The PI6C185-02B, a high-speed low-noise 1-7 non-inverting buffer, is designed for SDRAM clock buffer applications. It is intended to be used with the PI6C10X clock generator for Intel Architecture-based Mobile systems. At power up, all SDRAM outputs are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the seven output drivers. Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips.
Block Diagram
SDRAM0
Pin Configuration
SDRAM1
BUF_IN SDRAM2
SDRAM3
Vdd SDRAM0 SDRAM1 Vss BUF_IN SDRAM2 Vdd SDATA
1 2 3 4 5 6 7 8
16-Pin L,Q
16 15 14 13 12 11 10 9
SDRAM6 SDRAM5 Vss Vdd SDRAM4 SDRAM3 Vss SCLK
SDRAM6
SDATA SCLOCK
I2C I/O
1
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PI6C185-02B Precision 1-7 Clock Buffer
Pin Description
Pin 2,3,6,11,12,15,16 5 8 9 1,7,13 4,10,14 Signal SDRAM [0...6] BUF_IN SDATA SCLK VDD VSS Type I I I/O I Power Ground Qty. 7 1 1 1 3 3 D e s cription Buffered Clock O utputs Clock Buffer Input Serial Data for I2C interface Serial Clock for I2C interface 3.3V Power Supply Ground
PI6C185-02B I2C Address Assignment
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W 0
PI6C185-02 Serial Configuration Map
Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 6 3 2 SDRAM2
D e s cription
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 16 15 12 11 SDRAM6 SDRAM5
D e s cription
NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) SDRAM1 SDRAM0 NC (Initialize to 0) NC (Initialize to 0)
NC (Initialize to 0) NC (Initialize to 0) SDRAM4 SDRAM3 NC (Initialize to 0) NC (Initialize to 0)
Note: Inactive means outputs are held LOWand are disabled from switching
2
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PI6C185-02B Precision 1-7 Clock Buffer
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C185-02B, a slave receiver device, cannot be read back. Sub addressing is not supported. To change one of the control bytes, all preceding bytes must be sent. Every byte put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers, SDATA changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a "start" condition; a LOW to HIGH transition on SDATA while SCLK is HIGH is a "stop" condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device's own address is detected, PI6C185-02B generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (0D2H), two more bytes must be sent: 1. "Command Code" byte &2. "Byte Count" byte. Although the data bits on these two bytes are "don't care," they must be sent and acknowledged.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Note: Storage Temperature ..................................... -65C to +150C Stresses greater than those listed under MAXIMUM RATINGS Ambient Temperature with Power Applied ....... -0C to +70C may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other 3.3V Supply Voltage to Ground Potential ....... -0.5V to +4.6V conditions above those indicated in the operational sections of DC Input Voltage ............................................. -0.5V to +4.6V this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Supply Current (VDD = +3.465V, Cload = max)
Symbol IDD IDD IDD Parame te r Supply Current Supply Current Supply Current Te s t Condition BUF_IN = 0 MHz BUF_IN = 66.66 MHz BUF_IN = 100.0 MHz M in. Typ. M ax. 3 TBD mA Units
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PI6C185-02B Precision 1-7 Clock Buffer
DC Operating Specifications (VDD = +3.3V 5%, TA = 0C -70C)
Symbol Input Voltage VIH VIL IIL Input High Voltage Input Low Voltage Input Leakage Current 0 < VIN < VDD VDD 2.0 VSS 0.3 -5 VDD +0.3 0.8 +5 V A Parame te r Condition M in. M ax. Units
VDD = 3.3V 5% VOH VOL Output High Voltage Output Low Voltage IOH = 1mA IOL = 1mA 2.4 0.4 V
CIN COUT LPIN TA
Input Pin Capacitance Output pins Capacitance Pin Inductance Ambient Temperature No Airflow 0
5 6 7 70
pF nH C
SDRAM Clock Buffer Operating Specification
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRHSDRAM tFHSDRAM Parame te r Pull- up current Pull- up current Pull- down current Pull- down current Output rise edge rate SDRAM only Output fall edge rate SDRAM only Condition VOUT = 2.0V VOUT = 3.135V VOUT = 1.0V VOUT = 0.4V 3.3V 5% @0.4V- 2.4V 3.3V 5% @2.4V- 0.4V 1.5 1.5 40 38 4 4 V/ns M in. Typ. M ax. Units 40 36 mA
AC Timing
Symbol tSDKP tSDKH tSDKL tSDRISE tSDFALL tPLH tPHL tPZL,tPZH tPLZ,tPHZ Duty Cycle tSDSKW Parame te r SDRAM CLK period SDRAM CLK high time SDRAM CLK low time SDRAM CLK rise time SDRAM CLK fall time SDRAM Buffer LH prop delay SDRAM Buffer HL prop delay SDRAM Buffer Enable delay SDRAM Buffer Disable delay Measured at 1.5V SDRAM Output to Output Skew 66 M Hz M in. 15.0 5.6 5.3 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.5 5.5 8.0 8.0 55 250 M ax. 15.5 100 M Hz M in. 10.0 3.3 3.1 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.5 5.5 8.0 8.0 55 250 M ax. 10.5 133 M Hz M in. 7.5 1.0 1.0 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.5 5.5 8.0 8.0 55 250 % ps
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M ax. 7.8
Units
ns
V/ns
ns
4
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Output Buffer Test Point
PI6C185-02B Precision 1-7 Clock Buffer
1 2
Test Load
tSDKP tSDKH
3 4
tSDKL
3.3V Clocking Interface (TTL)
2.4 1.5 0.4
5 6
tSDRISE
tSDFALL
Input Waveform tplh Output Waveform
1.5V
1.5V
tphl
7 8 9 10 11 12 13 14 15
1.5V
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock SDRAM M in Load M ax Load 15 20 Units pF Note s SDRAM DIMM Specification
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
Design Guidelines to Reduce EMI
1. Place RS series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of "vias" of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
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PI6C185-02B Precision 1-7 Clock Buffer
PI6C185-02B
100/66 MHz Clock from Chipset
SDRAM
7
RS CL
SDRAM DIMM Spec.
Figure 2. Design Guidelines
16-Pin TSSOP (L) Package
16
16-Pin QSOP (Q) Package
16
.150 .157
.169 .177 4.3 4.5
3.81 3.99 .015 x 45 0.38
1
1 .193 .201 4.9 5.1 .047 max. 1.20 SEATING PLANE 0.45 .018 0.75 .030 .252 BSC 6.4 .004 .008 0.09 0.20
.189 .197 4.80 5.00
.007 .010 0.41 .016 1.27 .050 .228 .244 5.79 6.19 SEATING PLANE .004 0.101 .010 0.254
0.178 0.254
.008 0.203 REF
.053 1.35 .069 1.75
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
.025 BSC 0.635
.008 .012 0.203 0.305
X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Ordering Information
P/N
PI6C185- 02BL PI6C185- 02BQ
D e s cription
TSSO P Package Q SO P Package
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS8469 05/03/00

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