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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
FEATURES
* 6 LVPECL outputs * Crystal oscillator interface * Output frequency: 75MHz or 150MHz * Crystal input frequency: 25MHz * Cycle-to-cycle jitter: 20ps (typical) * RMS phase jitter at 150MHz, using a 25MHz crystal (899.8KHz to 20MHz): TBD * Phase noise: Offset 100Hz ............... 1KHz ............... 10KHz ............... 100KHz ............... Noise Power TBD TBD TBD TBD
GENERAL DESCRIPTION
The ICS84326 is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout Buffer designed for Serial HiPerClockSTM Attached SCSI applications and is a member of the HiperClockS family of High Performance Clock Solutions from ICS. Using a 25MHz crystal, the 6 LVPECL outputs can be set for either 75MHz or 150MHz using the frequency select pins. The low jitter/low phase noise characteristics make it an ideal clock source for use in Serial Attached SCSI applications or for other applications which require a 75MHz or 150MHz reference clock.
,&6
FUNCTION TABLE
Inputs MR 1 0 0 F_SEL X 0 1 Output Frequency F_OUT LOW 75MHz 150MHz
* Full 3.3V or 3.3V core, 2.5V supply mode * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCO F_SEL nc MR XTAL1 XTAL2 nc VCCA VCC PLL_SEL VEE VCCO
XTAL1
OSC
XTAL2
0 1
6 Output Divider
PLL
/ 6 /
Q0:Q5 nQ0:nQ5
Feedback Divider
ICS84326
24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View
MR PLL_SEL F_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
Type Output Output Output Output Output Output Power Power Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output supply pins. Core supply pin. Negative supply pin. Selects between the PLL and crystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. Analog supply pin. No connect. Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low, and the inver ted Pulldown outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pullup Output frequency select pin. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 24 16 14 15 17 18, 22 19, 20 21 23 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 Q5, nQ5 VCCO VCC VEE PLL_SEL VCCA nc XTAL2, XTAL1 MR F_SEL Input Power Unused Input Input Input Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 50C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 140 20 Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current PLL_SEL, MR, F_SEL PLL_SEL, MR, F_SEL MR PLL_SEL, F_SEL MR PLL_SEL, F_SEL Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 140 20 Maximum 3.465 3.465 2.625 Units V V V mA mA
TABLE 3D. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current
TABLE 3E. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current PLL_SEL, MR, F_SEL PLL_SEL, MR, F_SEL MR PLL_SEL, F_SEL MR PLL_SEL, F_SEL Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
TABLE 3F. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pf parallel resonant crystal. Test Conditions Minimum Typical Fundamental 25 70 7 MHz pF Maximum Units
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
Test Conditions Minimum 75 20 TBD 50 20% to 80% 200 50 1 700 Typical Maximum 150 Units MHz ps ps ps ps % ms
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 2 Period Jitter, RMS Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle
tjit(cc) tjit(per) tsk(o)
tR / t F odc
tLOCK PLL Lock Time See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 2 Period Jitter, RMS Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 200 50 1 Test Conditions Minimum 75 20 TBD 35 700 Typical Maximum 150 Units MHz ps ps ps ps % ms
tjit(cc) tjit(per) tsk(o)
tR / tF odc
tLOCK PLL Lock Time See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO = 2V 2.8V 2V
Qx
SCOPE
VCC, V CCA
Qx VCCO
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE = -1.3V 0.165V
VEE = -0.5V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
VOH
nQx Qx
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VREF VOL
nQy Qy
tsk(o)
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
OUTPUT SKEW
PERIOD JITTER
nQ0:nQ5
80%
Q0:Q5
80% V
SW I N G
20%
20% t
R
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
nQ0:nQ5 Q0:Q5
Pulse Width t
PERIOD
odc =
t PW t PERIOD
odc & tPERIOD
84326AM
tcycle n+1
Clock Outputs t
F
OUTPUT RISE/FALL TIME
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84326 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 20 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10 F 20
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for 3.3V LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V Zo = 50 FOUT FIN 5 2 Zo Zo = 50 5 2 Zo
Zo = 50 50 50 VCC - 2V
FOUT
FIN
Zo = 50 3 2 Zo 3 2 Zo
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 2A. LVPECL OUTPUT TERMINATION
84326AM
RTT
FIGURE 2B. LVPECL OUTPUT TERMINATION
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V 2.5V 2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driver R2 62.5 R4 62.5 R3 250
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V 2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driver R1 50 R2 50
R3 18
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V 2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driver R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
CRYSTAL INPUT INTERFACE
The ICS84326 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 25MHz, 18pF
19 C1 18pF 25MHz X1 20 C2 22pF
XTAL2
XTAL1 ICS84326
Figure 4. CRYSTAL INPUt INTERFACE
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of using an ICS84326. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 is 22pF and 18pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL=0, therefore, the output frequency is 150MHz. It is recommended to
VCC
have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VCCA pin as possible.
VCC R7 24 VCCA 22p C11 0.1u C16 10u C1 X1 25MHz,18pF C2 18p
R4 1K
VCC 13 14 15 16 17 18 19 20 21 22 23 24 R6 1K
U1 Zo = 50 VCCO VEE PLL_SEL VCC VCCA nc XTAL2 XTAL1 MR nc F_SEL VCCO nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 12 11 10 9 8 7 6 5 4 3 2 1 Zo = 50 + R2 50 R1 50
R5 1K
R3 50
ICS84326
(U1,13)
VCC
(U1,16) C5 0.1u
(U1,24) C3 0.1u
VCC=3.3V
C6 0.1u
FIGURE 5A. ICS84326 SCHEMATIC EXAMPLE
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ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
* The differential 50 output traces should have the same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C5, C6 and C3, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 20 (XTAL1) and 19 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
C6
GND VCC
C5 C1 R7
Signals
C11
C16
VIA
X1
C2
C3
U1
ICS84326
Pin1
50 Ohm Traces
FIGURE 5B. ICS84326 P.C. BOARD LAYOUT EXAMPLE
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REV. A MARCH 10, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84326. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS84326 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power_MAX (3.465V, with all outputs switching) = 485mW + 181mW = 666mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.666W * 43C/W = 98.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
24-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 50C/W
200
43C/W
500
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 1.0V (V
CCO_MAX
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 50C/W
200
43C/W
500
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84326 is: 2804
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ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 24 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
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ICS84326
CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
Marking ICS84326AM ICS84326AM Package 24 Lead SOIC 24 Lead SOIC on Tape and Reel Count 30 per tube 1000 Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS84326AM ICS84326AMT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84326AM
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