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INTEGRATED CIRCUITS
74ALVCH16843 18-bit bus-interface D-type latch (3-State)
Product specification IC24 Data Handbook 1998 Aug 04
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
FEATURES
* Wide supply voltage range of 1.2V to 3.6V * Complies with JEDEC standard no. 8-1A. * CMOS low power consumption * Direct interface with TTL levels * Current drive 24 mA at 3.0 V * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
1CLR 1OE 1Q0 GND 1Q1 1Q2 VCC 1Q3 1Q4 1Q5 GND 1Q6 1Q7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1LE 1PRE 1D0 GND 1D1 1D2 VCC 1D3 1D4 1D5 GND 1D6 1D7 1D8 2D0 2D1 2D2 GND 2D3 2D4 2D5 VCC 2D6 2D7 GND 2D8 2PRE 2LE
* All data inputs have bus hold * Output drive capability 50 transmission lines @ 85C
DESCRIPTION
The 74ALVCH16843 has two 9-bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
1Q8 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2OE 2CLR
SH00143
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf 2.5ns PARAMETER SYMBOL Propagation delay nDn to nQn tPHL/tPLH Propagation delay nLE to nQn CI Input capacitance CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF transparent mode Output enabled Output disabled Clocked mode Output enabled Output disabled TYPICAL 2.2 2.1 2.3 2.0 5.0 17 3 19 9 UNIT ns ns pF
CPD
Power dissipation capacitance per buffer dissi ation ca acitance er
VI = GND to VCC1
pF F
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II 1998 Aug 04 TEMPERATURE RANGE -40C to +85C 2 OUTSIDE NORTH AMERICA 74ALVCH16843 DGG NORTH AMERICA ACH16843 DGG DRAWING NUMBER SOT364-1
853-2108 019833
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
PIN DESCRIPTION
PIN NUMBER 1 2 55 56 54, 52, 51, 49, 48, 47, 45, 44, 43 3, 5, 6, 8, 9, 10, 12, 13, 14 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 27 28 29 30 42, 41, 40, 38, 37, 36, 34, 33, 31 15, 16, 17, 19, 20, 21, 23, 24, 26 SYMBOL 1CLR 1OE 1PRE 1LE 1D0 to 1D8 1Q0 to 1Q8 GND VCC 2OE 2CLR 2LE 2PRE 2D0 to 2D8 2Q0 to 2Q8 NAME AND FUNCTION Clear input (active LOW) Output enable input (active LOW) Preset input (active LOW) Latch enable input (active HIGH) Data inputs Data outputs Ground (0V) Positive supply voltage Output enable input (active LOW) Clear input (active LOW) Latch enable input (active HIGH) Preset input (active LOW) Data inputs Data outputs
LOGIC SYMBOL
1 55 2 56
1CLR 1PRE 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2CLR 2PRE
1OE
1LE 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31
2OE
2LE
28
30
27
29
FUNCTION TABLE
INPUTS nPRE L H H H H X H L X Z = = = = nCLR X L H H H X nOE L L L L L H LE X X H H H H DX X X L H X X OUTPUT Q H L L H Q0 Z
SH00144
HIGH voltage level LOW voltage level Don't care High impedance "off" state
1998 Aug 04
3
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
LOGIC DIAGRAM
nD0
LOGIC SYMBOL (IEEE/IEC)
1OE 2 EN4 S2 R3 C1 EN8 S6 R7 C5 1D 2, 3, 4 3 5 6 8 9 10 12 13 14 5D 6, 7, 8 15 16 17 19 20 21 23 24 26 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
1PRE 56 1CLR D CLR P DRE LE 1
1LE 56 2OE 27 2PRE 30 2CLR 28 2LE 29 1D0 54 1D1 52
nCLR nPRE
nLE
1D2 51 1D3 49
nOE
1D4 48 1D5 47 nQ0 1D6 45 1D7 44 1D8 43
SH00146
BUS HOLD CIRCUIT
VCC
2D0 42 2D1 41 2D2 40 2D3 38 2D4 37 2D5 36 2D6 34 2D7 33
Data Input
To internal circuit
2D8 31
SH00145
SW00044
1998 Aug 04
4
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) DC Input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V CONDITIONS MIN 2.3 3.0 0 0 -40 0 0 MAX 2.7 V 3.6 VCC VCC +85 20 10 V V C ns/V UNIT
VCC
VI VO Tamb tr, tf
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC in ut voltage input DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic medium-shrink (SSOP) -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 11.3 mW/K above +55C derate linearly with 8 mW/K VI t0 For control pins2 For data inputs2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +4.6 -0.5 to VCC +0.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 850 600 V mA V mA mA C mW UNIT V mA
NOTE: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Aug 04
5
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = -100A 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = -6mA VO OH HIGH level output voltage VCC = 2.3V; VI = VIH or VIL; IO = -12mA VCC = 2.7V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = 6mA VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ ICC ICC IBHL2 IBHH2 IBHLO2 IBHHO2 Input leakage current g 3-State output OFF-state current Quiescent supply current Additional quiescent supply current Bus hold LOW sustaining current Bus hold HIGH sustaining current Bus hold LOW overdrive current Bus hold HIGH overdrive current VCC = 2 3 to 3 6V; 2.3 3.6V; VI = VCC or GND VCC = 2.3 to 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 VCC = 2.3V to 3.6V; VI = VCC - 0.6V; IO = 0 VCC = 2.3V; VI = 0.7V VCC = 3.0V; VI = 0.8V VCC = 2.3V; VI = 1.7V VCC = 3.0V; VI = 2.0V VCC = 3.6V VCC = 3.6V 45 75 -45 -75 500 -500 -175 VCC*0.2 02 VCC*0.3 VCC*0.6 VCC*0.5 VCC*0.6 VCC*1.0 1.7 2.0 TYP1 1.2 V 1.5 1.2 1.5 VCC VCC*0.08 VCC*0.26 VCC*0.14 VCC*0.09 VCC*0.28 GND 0.07 0.15 0.14 0.27 0.1 0.1 0.2 150 - 150 0.20 0 20 0.40 0.70 0.40 0.55 5 10 40 750 A A A A A A A A V V V V 0.7 V 0.8 MAX UNIT
VIL
NOTES: 1. All typical values are at Tamb = 25C. 2. Valid for data inputs of bus hold parts.
1998 Aug 04
6
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE
GND = 0V; tr = tf 2.0ns; CL = 30pF SYMBOL LIMITS PARAMETER Propagation delay nDn to nQn Propagation delay nLE to nQn Propagation delay nPRE to nQn Propagation delay nCLR to nQn tPZH/tPZL tPHZ/tPLZ tSU th tW 3-State output enable time nOE to nQn 3-State output disable time nOE to nQn Set-up time nDn to nLE Hold time nDn to nLE nLE pulse width HIGH nPRE pulse width LOW nCLR pulse width LOW tREM Recovery time nPRE to nLE Recovery time nCLR to nLE WAVEFORM MIN 1, 6 2, 6 1, 6 1, 6 5, 6 5, 6 3, 6 3, 6 2, 6 4, 6 4, 6 4, 6 4, 6 1.0 1.0 1.0 1.0 1.0 1.1 0.5 0.9 1.5 1.5 1.5 0.5 0.5 VCC = 2.3 to 2.7V TYP1 2.2 2.3 2.5 2.5 2.8 2.2 -0.1 0.5 0.5 0.5 0.5 1.1 1.0 MAX 4.3 4.6 ns 4.8 4.8 5.8 4.3 - - - - - - - ns ns ns ns ns ns UNIT
tPHL/tPLH
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V; tr = tf 2.5ns; CL = 50pF SYMBOL LIMITS PARAMETER Propagation delay nDn to nQn Propagation delay nLE to nQn Propagation delay nPRE to nQn Propagation delay nCLR to nQn tPZH/tPZL tPHZ/tPLZ tSU th tW 3-State output enable time nOE to nQn 3-State output disable time nOE to nQn Set-up time nDn to nLE Hold time nDn to nLE nLE pulse width HIGH nPRE pulse width LOW nCLR pulse width LOW tREM Recovery time nPRE to nLE Recovery time nCLR to nLE WAVEFORM VCC = 3.3 0.3V MIN 1, 6 2, 6 1, 6 1, 6 5, 6 5, 6 3, 6 3, 6 2, 6 4, 6 4, 6 4, 6 4, 6 1.0 1.0 1.0 1.0 1.0 1.3 0.5 0.9 1.5 1.5 1.5 1.0 0.8 TYP1, 2 2.1 2.0 2.2 2.3 2.5 2.6 0.0 0.5 0.5 0.5 0.5 0.4 0.2 MAX 3.5 3.5 3.8 3.9 4.4 4.0 - - - - - - - MIN 1.0 1.0 1.0 1.0 1.0 1.3 0.5 0.9 1.5 1.5 1.5 0.8 0.6 LIMITS VCC = 2.7V TYP1 2.3 2.1 2.6 2.5 3.0 2.8 -0.3 0.5 0.5 0.6 0.5 -0.2 -0.4 MAX 4.0 3.9 ns 4.5 4.3 5.3 4.4 - - - - - - - ns ns ns ns ns ns UNIT
tPHL/tPLH
NOTES: 1. All typical values are measured Tamb = 25C. 2. Typical value is measured at VCC = 3.3V
1998 Aug 04
7
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
VM = 0.5 V VX = VOL + 0.15V VY = VOH -0.15V VOL and VOH are the typical output voltage drop that occur with the output load. V =V CC I
Dn INPUT
GND
LE INPUT
GND
AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND VCC = 2.7V RANGE
VM = 1.5 V VX = VOL + 0.3V VY = VOH -0.3V VOL and VOH are the typical output voltage drop that occur with the output load. V = 2.7V I
CLR, Dn VI VM PRE GND tPHL VOH Qn OUTPUT VOL VM tPLH
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 3. Data set-up and hold times for the Dn input to the LE input
CLR, PRE GND
SH00147
Waveform 1. Data input (Dn) to output (Qn), clear input (CLR) to output (Qn) and preset input (PRE) to output (Qn) propagation delay
Waveform 4. Clear (CLR) and preset (PRE) pulse width, the clear (CLR) and preset (PRE) to latch (LE) removal time
VI LE INPUT GND VM tW VM
nOE INPUT GND
tPHL
VOH Qn OUTPUT VOL VM
tPLH
tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VX VM tPZL
SH00150
VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled VY VM tPZH
Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delay
1998 Aug 04
8
EEE E EEEEEEEEEE EEE E EEEEEEEEEE EEE EEEEEEEE EEE
VI VM th th tSU tSU VI VM
AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND VCC < 2.3V RANGE
SH00149
VI VM
tW(L) VI LE GND
tREM
VM
SH00148
VI VM
SH00137
Waveform 5. 3-State enable and disable times
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
TEST CIRCUIT
VCC S1 2 * VCC Open GND
VI PULSE GENERATOR RT D.U.T.
VO
RL = 500
CL
RL = 500
Test Circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC
GND
VCC < 2.7V 2.7-3.6V
VI VCC 2.7V
SV00906
Waveform 6. Load circuitry for switching times
1998 Aug 04
9
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Aug 04
10
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
NOTES
1998 Aug 04
11
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 07-98 9397-750-04562
Philips Semiconductors
1998 Aug 04 12

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