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LH1562
LH1562
DESCRIPTION
The LH1562 is a 240-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The LH1562 is good both as a segment driver and a common driver, and it can create a low power consuming, highresolution LCD.
240-output LCD Segment/Common Driver IC
* Available in a single mode (240-bit shift register) or in a dual mode (120-bit shift register x 2) q Y1/Y240 Single mode w Y240/Y1 Single mode e Y1/Y120, Y121/Y240 Dual mode r Y240/Y121, Y120/Y1 Dual mode The above 4 shift directions are pin-selectable * Shift register circuits are reset when active
PIN CONNECTIONS
269-PIN TCP
Y1 1 Y2 Y3
FEATURES
* * * * * * Number of LCD drive outputs : 240 Supply voltage for LCD drive : +15.0 to +42.0 V Supply voltage for the logic system : +2.5 to +5.5 V Low power consumption Low output impedance Package : 269-pin TCP (Tape Carrier Package)
TOP VIEW
(Segment mode) * Shift clock frequency - 20 MHz (MAX.) : VDD = +5.00.5 V - 15 MHz (MAX.) : VDD = +3.0 to +4.5 V - 12 MHz (MAX.) : VDD = +2.5 to +3.0 V * Adopts a data bus system * 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin * Automatic transfer function of an enable signal * Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data * Line latch circuits are reset when active (Common mode) * Shift clock frequency : 4 MHz (MAX.) * Built-in 240-bit bi-directional shift register (divisible into 120 bits x 2)
Y238 Y239 Y240 240
269 V0R V12R V43R V5R VSS TEST2 TEST1 MD L/R FR EIO1 LP DISPOFF XCK DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 EIO2 S/C VDD V5L V43L V12L 241 V0L
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
CHIP SURFACE
LH1562
PIN DESCRIPTION
PIN NO. 1 to 240 241, 269 242, 268 243, 267 244, 266 245 246 247, 259 248 to 254 255 256 257 258 260 261 262 263, 264 265 SYMBOL Y1-Y240 V0L, V0R V12L, V12R V43L, V43R V5L, V5R VDD S/C EIO2, EIO1 DI0-DI6 DI7 XCK LP FR L/R MD TEST1, TEST2 VSS I/O O - - - - - I I/O I I I I I I I I I - DESCRIPTION LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for logic system (+2.5 to +5.5 V) Segment mode/common mode selection Input/output for chip selection at segment mode/ Shift data input/output for shift register at common mode Display data input at segment mode Display data input at segment mode/Dual mode data input at common mode Clock input for taking display data at segment mode Control input for output of non-select level Latch pulse input for display data at segment mode/ Shift clock input for shift register at common mode AC-converting signal input for LCD drive waveform Input for selecting the reading direction of display data at segment mode/ Input for selecting the shift direction of shift register at common mode Mode selection input Test mode selection input Ground (0 V)
BLOCK DIAGRAM
V0R 269 FR 260 257 EIO1 259 EIO2 247 LEVEL SHIFTER V12R 268 V43R 267 V5R 266 Y1 1 Y2 2 Y239 239 Y240 240 244 V5L 240-BIT 4-LEVEL DRIVER 243 V43L
240
ACTIVE CONTROL
240-BIT LEVEL SHIFTER
240
242 V12L 241 V0L
16 16 16
240-BIT LINE LATCH/SHIFT REGISTER
16 16 16
LP 258 XCK 256 L/R 261 MD 262 S/C 246
CONTROL LOGIC
8
8 BITS x 2 DATA LATCH
DATA CONTROL
SP CONVERSION & DATA CONTROL (4 to 8 or 8 to 8)
TEST CIRCUIT
248 DI0
249 DI1
250 DI2
251 DI3
252 DI4
253 DI5
254 DI6
255 DI7
263 TEST1
264 TEST2
245 VDD
265 VSS
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LH1562
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK FUNCTION In case of segment mode, controls the selection or non-selection of the chip. Following an LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time. In case of segment mode, selects the state of the data latch which reads in the data bus Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. In case of segment mode, latches the data on the data bus. The latch state of each LCD Data Latch drive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. In case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. Level Shifter 4-Level Driver The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the driver block. Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 levels (V0, V12, V43, or V5) based on the S/C, FR and signals. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output Control Logic from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip is non-selected. In case of common mode, controls the direction of data shift. The circuit for testing. During normal operation, it isn't activated.
Active Control
SP Conversion & Data Control
Line Latch/ Shift Register
Test Circuit
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LH1562
INPUT/OUTPUT CIRCUITS
VDD
I
To Internal Circuit
VSS (0 V)
Applicable pins L/R, S/C, DI6-DI0, , LP, FR, MD
Fig. 1 Input Circuit (1)
VDD
I Control Signal VSS (0 V) VSS (0 V)
To Internal Circuit
Applicable pins DI7, XCK
Fig. 2 Input Circuit (2)
VDD
I VDD VSS (0 V) VSS (0 V)
To Internal Circuit
Applicable pins TEST1, TEST2
Fig. 3 Input Circuit (3)
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LH1562
VDD
To Internal Circuit Control Signal VSS (0 V) VSS (0 V) VDD Output Signal I
O Control Signal VSS (0 V)
Applicable pins EIO1, EIO2
Fig. 4 Input/Output Circuit
V0
V0
V12
Control Signal 1
Control Signal 2
O
Control Signal 3
Control Signal 4
VSS (0 V)
V43
VSS (0 V)
V5
Applicable pins Y1-Y240
Fig. 5 LCD Drive Output Circuit
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LH1562
FUNCTIONAL DESCRIPTION Pin Functions
(Segment mode)
SYMBOL VDD VSS V0L, V0R V12L, V12R V43L, V43R V5L, V5R FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage * Normally use the bias voltages set by a resistor divider. * Ensure that voltages are set such that VSS V5 < V43 < V12 < V0. * ViL and ViR (i = 0, 12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. Input pins for display data * In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. DI7-DI0 Connect DI7-DI4 to VSS or VDD. * In 8-bit parallel input mode, input data into the 8 pins, DI7-DI0. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data * Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data * When set to VSS level "L", data is read sequentially from Y240 to Y1. * When set to VDD level "H", data is read sequentially from Y1 to Y240. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * When set to VSS level "L", the LCD drive output pins (Y1-Y240) are set to level V5. * When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of . When the function is canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
XCK LP
L/R
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LH1562
SYMBOL FUNCTION AC signal input pin for LCD drive waveform * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and FR controls the LCD drive circuit. * Normally it inputs a frame inversion signal. * The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin * When set to VSS level "L", 8-bit parallel input mode is set. MD * When set to VDD level "H", 4-bit parallel input mode is set. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Segment mode/common mode selection pin * When set to VDD level "H", segment mode is set. Input/output pins for chip selection * When L/R input is at VSS level "L", EIO1 is set for output, and EIO2 is set for input. EIO1, EIO2 * When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output. * During output, set to "H" while LP* is "H" and after 240 bits of data have been read, set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H". * During input, the chip is selected while EI is set to "L" after the LP signal is input. The chip is non-selected after 240 bits of data have been read. TEST1 TEST2 Test mode selection pins * During normal operation, fix to VSS level "L". LCD drive output pins Y1-Y240 * Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
S/C
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LH1562
(Common mode)
SYMBOL VDD VSS V0L, V0R V12L, V12R V43L, V43R V5L, V5R FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage * Normally use the bias voltages set by a resistor divider. * ViL and ViR (i = * Ensure that voltages are set such that VSS V5 < V43 < V12 < V0. 0, 12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. Shift data input/output pin for bi-directional shift register * Output pin when L/R is at VSS level "L", input pin when L/R is at VDD level "H". EIO1 * When L/R = H, EIO1 is used as input pin, it will be pulled down. * When L/R = L, EIO1 is used as output pin, it won't be pulled down. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Shift data input/output pin for bi-directional shift register * Input pin when L/R is at VSS level "L", output pin when L/R is at VDD level "H". EIO2 * When L/R = L, EIO2 is used as input pin, it will be pulled down. * When L/R = H, EIO2 is used as output pin, it won't be pulled down. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Shift clock pulse input pin for bi-directional shift register * Data is shifted at the falling edge of the clock pulse. Input pin for selecting the shift direction of bi-directional shift register * Data is shifted from Y240 to Y1 when set to VSS level "L", and data is shifted from Y1 to L/R Y240 when set to VDD level "H". * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * When set to VSS level "L", the LCD drive output pins (Y1-Y240) are set to level V5. * When set to "L", the contents of the shift register are reset to not reading data. When the data is read at the next falling edge of the LP. At that time, if function is canceled, the driver outputs non-select level (V12 or V43), and the shift removal time does
LP
not correspond to what is shown in AC characteristics, the shift data is not read correctly. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
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LH1562
SYMBOL FUNCTION AC signal input pin for LCD drive waveform * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and FR controls the LCD drive circuit. * Normally it inputs a frame inversion signal. * The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin * When set to VSS level "L", single mode operation is selected; when set to VDD level "H", MD dual mode operation is selected. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Dual mode data input pin * According to the data shift direction of the data shift register, data can be input starting DI7 from the 121st bit. When the chip is used in dual mode, DI7 will be pulled down. When the chip is used in single mode, DI7 won't be pulled down. * Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. S/C DI6-DI0 XCK TEST1 TEST2 Segment mode/common mode selection pin * When set to VSS level "L", common mode is set. Not used * Connect DI6-DI0 to VSS or VDD, avoiding floating. Not used * XCK is pulled down in common mode, so connect to VSS or open. Test mode selection pins * During normal operation, fix to VSS level "L". LCD drive output pins * Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and output. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Y1-Y240
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LH1562
Functional Operations
TRUTH TABLE (Segment Mode)
FR L L H H X LATCH DATA L H L H X H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240) V43 V5 V12 V0 V5
(Common Mode)
FR L L H H X LATCH DATA L H L H X H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240) V43 V0 V12 V5 V5
NOTES :
* VSS V5 < V43 < V12 < V0, L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care * "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin.
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LH1562
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (Segment Mode ) (a) 4-bit Parallel Input Mode
MD L/R DATA NUMBER INPUT 60 CLOCK 59 CLOCK 58 CLOCK Y1 Y5 Y9 DI0 DI1 Y2 Y6 Y10 Output Input DI2 Y3 Y7 Y11 DI3 Y4 Y8 Y12 DI0 Y240 Y236 Y232 DI1 Y239 Y235 Y231 Input Output DI2 Y238 Y234 Y230 DI3 Y237 Y233 Y229 EIO1 EIO2 OF CLOCKS 3 CLOCK 2 CLOCK 1 CLOCK Y229 Y233 Y237 Y230 Y234 Y238 Y231 Y235 Y239 Y232 Y236 Y240 Y12 Y8 Y4 Y11 Y7 Y3 Y10 Y6 Y2 Y9 Y5 Y1
H
L
H
H
(b) 8-bit Parallel Input Mode
MD L/R DATA NUMBER INPUT 30 CLOCK 29 CLOCK 28 CLOCK Y1 Y9 Y17 DI0 DI1 Y2 Y10 Y18 DI2 Y3 Y11 Y19 DI3 Y4 Y12 Y20 Output Input DI4 Y5 Y13 Y21 DI5 Y6 Y14 Y22 DI6 Y7 Y15 Y23 DI7 Y8 Y16 Y24 DI0 Y240 Y232 Y224 DI1 Y239 Y231 Y223 DI2 Y238 Y230 Y222 DI3 Y237 Y229 Y221 Input Output DI4 Y236 Y228 Y220 DI5 Y235 Y227 Y219 DI6 Y234 Y226 Y218 DI7 Y233 Y225 Y217 EIO1 EIO2 OF CLOCKS 3 CLOCK 2 CLOCK 1 CLOCK Y217 Y225 Y233 Y218 Y226 Y234 Y219 Y227 Y235 Y220 Y228 Y236 Y221 Y229 Y237 Y222 Y230 Y238 Y223 Y231 Y239 Y224 Y232 Y240 Y24 Y16 Y8 Y23 Y15 Y7 Y22 Y14 Y6 Y21 Y13 Y5 Y20 Y12 Y4 Y19 Y11 Y3 Y18 Y10 Y2 Y17 Y9 Y1
L
L
L
H
(Common Mode )
MD L (Single) H (Dual) L/R L H L H DATA TRANSFER DIRECTION Y240 / Y1 / Y240 Y1 Y240 / Y121 Y120 / Y1 / Y120 Y1 Y121 / Y240 EIO1 Output Input Output Input EIO2 Input Output Input Output DI7 X X Input Input
NOTES :
* L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care * "Don't care" should be fixed to "H" or "L", avoiding floating.
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LH1562
CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS (a) When L/R = "L"
Top data Data flow Y240 EIO2 Y1 EIO1 L/R XCK XCK DI7 -DI0 LP MD LP MD FR FR Y240 EIO2 Y1 EIO1 L/R DI7 -DI0 XCK LP MD FR Y240 EIO2 Y1 EIO1 L/R DI7 -DI0 LP EIO2 Y240 XCK Last data
XCK LP MD FR DI7-DI0 8
VSS
(b) When L/R = "H"
VDD 8
DI7-DI0 FR MD LP XCK DI7 -DI0 DI7 -DI0 XCK
XCK
DI7 -DI0 L/R EIO1 Y1
FR
MD
LP
FR
MD
LP
L/R VSS EIO1 Y1 EIO2 Y240 Data flow Top data
L/R EIO1 Y1 EIO2 Y240
FR MD
Last data
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LH1562
TIMING CHART OF 4-DEVICE CASCADE CONNECTION OF SEGMENT DRIVERS
FR
LP
XCK
TOP DATA DI7-DI0 n* 1 2 device A EI (device A) EO (device A) EO (device B) EO (device C) n* 1 2 device B n* 1 2 device C n* 1 2 device D
LAST DATA n* 1 2
H L
* n = 60 in 4-bit parallel input mode. n = 30 in 8-bit parallel input mode.
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LH1562
CONNECTION EXAMPLES FOR PLURAL COMMON DRIVERS (a) Single Mode (L/R = "L")
First Last
Y240 DISPOFF DI EIO2 L/R MD DI7 LP
Y1 EIO1 FR
Y240 DISPOFF EIO2 L/R MD DI7 LP
Y1 EIO1 FR
Y240 DISPOFF DI7 EIO2 L/R MD MD DI7 LP
Y1 EIO1 FR EIO2 Y240 Last LP
LP VSS (VDD) VSS VSS DISPOFF FR
(b) Single Mode (L/R = "H")
FR DISPOFF VDD VSS VSS (VDD) LP DISPOFF L/R DI7 FR MD LP DISPOFF FR EIO1 Y1 DISPOFF L/R MD L/R FR DI7 LP
DI
EIO1 Y1
EIO2 Y240
EIO1 Y1
EIO2 Y240
First
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LH1562
(c) Dual Mode (L/R = "L")
First 1 Last 1 First 2 Last 2
Y240 DISPOFF DI1 EIO2 L/R MD DI7 LP
Y1 EIO1 FR
Y240 EIO2
Y121 Y120 DISPOFF
Y1 EIO1 FR
Y240 DISPOFF DI7 EIO2 L/R MD MD DI7 LP
Y1 EIO1 FR EIO2 Y240 LP
LP DI2 VSS (VDD) VDD VSS DISPOFF FR
(d) Dual Mode (L/R = "H")
FR DISPOFF VDD VSS VSS (VDD) DI2 LP FR EIO1 Y1 DISPOFF DISPOFF L/R DISPOFF L/R MD MD L/R FR DI7 DI7 FR LP LP EIO2 Y240
DI1
EIO1 Y1
EIO2 Y240
EIO1 Y1
Y120 Y121
First 1
Last 1 First 2
L/R
MD
DI7
LP
Last 2
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LH1562
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows. o When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power. o It is advisable to connect the serial resistor (50 to 100 $) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on function. After that, cancel the function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level V5 on function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here.
VDD
VDD VSS VDD VSS V0
V0 VSS
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LH1562
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage (1) SYMBOL VDD V0 Supply voltage (2) V12 V43 V5 Input voltage Storage temperature VI TSTG APPLICABLE PINS VDD V0L, V0R V12L, V12R V43L, V43R V5L, V5R DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, , TEST1, TEST2 -45 to +125 C RATING -0.3 to +7.0 -0.3 to +45.0 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to VDD + 0.3 UNIT V V V V V V 1, 2 NOTE
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to VSS (0 V).
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage (1) Supply voltage (2) Operating temperature SYMBOL VDD V0 TOPR APPLICABLE PINS VDD V0L, V0R MIN. +2.5 +15.0 -20 TYP. MAX. +5.5 +42.0 +85 UNIT V V C NOTE 1, 2
NOTES :
1. The applicable voltage on any pin with respect to VSS (0 V). 2. Ensure that voltages are set such that VSS V5 < V43 < V12 < V0.
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LH1562
ELECTRICAL CHARACTERISTICS DC Characteristics
(Segment Mode)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current ILIH Output resistance Standby current Supply current (1) (Non-selection) Supply current (2) (Selection) Supply current (3) RON ISTB IDD1 IDD2 I0 VI = VDD |VON| = 0.5 V V0 = 40 V V0 = 30 V V0 = 20 V VSS VDD VDD V0L, V0R Y1-Y240
(VSS = V5 = 0 V, VDD = +2.5 to +5.5 V, V0 = +15.0 to +42.0 V, TOPR = -20 to +85 C)
SYMBOL CONDITIONS VIL VIH VOL VOH ILIL IOL = +0.4 mA IOH = -0.4 mA VI = VSS APPLICABLE PINS DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, EIO1, EIO2 DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, 1.0 1.5 2.0 MIN. TYP. MAX. 0.2VDD 0.8VDD +0.4 VDD - 0.4 -10.0 +10.0 1.5 2.0 2.5 75.0 2.0 12.0 1.5 A mA mA mA 1 2 3 4 k$ UNIT V V V V A A NOTE
NOTES :
1. VDD = +5.0 V, V0 = +42.0 V, VI = VSS. 2. VDD = +5.0 V, V0 = +42.0 V, fXCK = 20 MHz, no-load, EI = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +5.0 V, V0 = +42.0 V, fXCK = 20 MHz, no-load, EI = VSS. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +5.0 V, V0 = +42.0 V, fXCK = 20 MHz, fLP = 41.6 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode).
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LH1562
(Common Mode)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage
(VSS = V5 = 0 V, VDD = +2.5 to +5.5 V, V0 = +15.0 to +42.0 V, TOPR = -20 to +85 C)
SYMBOL CONDITIONS VIL VIH VOL VOH ILIL IOL = +0.4 mA IOH = -0.4 mA VI = VSS APPLICABLE PINS DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, EIO1, EIO2 DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, ILIH VI = VDD VI = VDD |VON| = 0.5 V V0 = 40 V V0 = 30 V V0 = 20 V VSS VDD V0L, V0R Y1-Y240 DI6-DI0, LP, L/R, FR, MD, S/C, DI7, XCK, EIO1, EIO2 1.0 1.5 2.0 +10.0 100.0 1.5 2.0 2.5 75.0 120.0 240.0 A A A 1 2 2 k$ A A -10.0 A 0.8VDD +0.4 VDD - 0.4 V V V MIN. TYP. MAX. 0.2VDD UNIT V NOTE
Input leakage current
Input pull-down current Output resistance Standby current Supply current (1) Supply current (2)
IPD
RON ISTB IDD I0
NOTES :
1. VDD = +5.0 V, V0 = +42.0 V, VI = VSS 2. VDD = +5.0 V, V0 = +42.0 V, fLP = 41.6 kHz, fFR = 80 Hz, 1/480 duty operation, no-load.
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LH1562
AC Characteristics
(Segment Mode 1) (VSS = V5 = 0 V, VDD = +5.00.5 V, V0 = +15.0 to +42.0 V, TOPR = -20 to +85 C)
SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tS tR tF tSD tWDL tD tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 30 1.2 1.2 CONDITIONS tR, tF 10 ns MIN. 50 15 15 10 12 15 0 30 25 25 10 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s 2 2 NOTE 1 PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time removal time "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3)
NOTES :
1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
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LH1562
(Segment Mode 2) (VSS = V5 = 0 V, VDD = +3.0 to +4.5 V, V0 = +15.0 to +42.0 V, TOPR = -20 to +85 C)
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time removal time "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tS tR tF tSD tWDL tD tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 41 1.2 1.2 CONDITIONS tR, tF 10 ns MIN. 66 23 23 15 23 30 0 50 30 30 15 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s 2 2 NOTE 1
NOTES :
1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
21
LH1562
(Segment Mode 3) (VSS = V5 = 0 V, VDD = +2.5 to +3.0 V, V0 = +15.0 to +42.0 V, TOPR = -20 to +85 C)
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time removal time "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tS tR tF tSD tWDL tD tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 57 1.2 1.2 CONDITIONS tR, tF 10 ns MIN. 82 28 28 20 23 30 0 65 30 30 15 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s 2 2 NOTE 1
NOTES :
1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
22
LH1562
Timing Chart of Segment Mode
tWLPH LP tLD tLS XCK tR tWCK DI7-DI0 LAST DATA tWDL tSD tF tDS TOP DATA tDH tSL tLH tWCKH tWCKL
Fig. 6 Timing Characteristics (1)
LP XCK EI EO 1 tS 2 n*
tD
* n = 60 in 4-bit parallel input mode. n = 30 in 8-bit parallel input mode.
Fig. 7 Timing Characteristics (2)
23
LH1562
FR tPD1
LP tPD2
tPD3
Y1-Y240
Fig. 8 Timing Characteristics (3)
(Common Mode)
(VSS = V5 = 0 V, VDD = +2.5 to +5.5 V, V0 = +15.0 to +42.0 V, TOPR = -20 to +85 C)
SYMBOL tWLP tWLPH tSU tH tR tF tSD tWDL tDL tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 200 1.2 1.2 CONDITIONS tR, tF 20 ns VDD = +5.00.5 V VDD = +2.5 to +4.5 V MIN. 250 15 30 30 50 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns s ns s s
PARAMETER Shift clock period Shift clock "H" pulse width Data setup time Data hold time Input signal rise time Input signal fall time removal time "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3)
24
LH1562
Timing Chart of Common Mode
tWLP LP tR tWLPH tSU tF tH
EIO2 tDL EIO1 tWDL tSD
FR tPD1
LP tPD2
tPD3
Y1-Y240
[L/R = "L"]
25
VEE LH1562 x 2 EIO1 MD Y1-Y240 S/C FR LP L/R DI7- DISP DI0 OFF EIO2 XCK COM1 COM2
50-100 $
V0
R
V1 R V2 (n - 4) R V3 R V4 R V5
1 920 x 480 DOT MATRIX LCD PANEL
EIO1 MD Y1-Y240 S/C 8 / SEG2 SEG1 COM479 COM480 Y1-Y240 LP L/R DI7- DISP DI0 OFF EIO2 XCK FR
VDD
SYSTEM CONFIGURATION EXAMPLE
VSS
(Case of 1/n bias)
SEG1920 SEG1919
26
FR LP DISP OFF XCK 6 / 6 / EIO1 MD S/C L/R DI7DI0 EIO2 8 /
Y1-Y240
Y1-Y240
Y1-Y240
YD FR LP
XCK EIO1 MD FR S/C LP L/R DISP DI7DI0 OFF XCK EIO2 EIO1 MD FR S/C LP L/R DISP DI7DI0 OFF XCK EIO2 EIO1 MD FR S/C LP L/R DISP DI7OFF DI0 XCK EIO2
Controller
XD7-XD0
LH1562 x 8
LH1562
LH1562F1
Film center Device center 18.8 (SL) (Resin area) 17.8 (SL) 0.8 (SL) 16.00.02
PACKAGES
NC V0L V0L V12L V43L V5L NC VDD S/C EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 XCK DISPOFF LP EIO1 FR L/R MD TEST1 VSS V5R V43R V12R V0R V0R NC 0.7 (SL) 0.2MAX. Pattern side
0.02
1.35MAX. Total
O2 (Good device hole) 1.2 (SL) 33-0.25 [0.5] P0.5
0.02
11.50.7
0.75 Backside
MAX.
[4.15 (E.L.)]
3.075 3.03
2.45
0.7
Sprocket center
UPILEX is a trademark of UBE INDUSTRIES, LTD..
[10.5 (E.L.)] Chip center 4.30.05 [6.35 (E.L.)]
2.525 (Resin area)
MAX.
2.2250.25 (SR)
27
Solder resist area 17.150.02 (Pitch 0.07, 240 leads + dummy 6 leads) 17.550.02 DUMMY Y1 DUMMY DUMMY DUMMY Y240 DUMMY DUMMY
0.2380.02
0.2380.02
o Tape Specification
Tape width Tape type Perforation pitch 35 mm Wide 3 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 SLP 18 m Epoxy resin (Unit : mm)
PACKAGES FOR LCD DRIVERS
LH1562F4
Film center Device center
1.35 0.9 (SL) 27.7 (SL) 25.250.7 44.00.09 1.35 (SL) 1.35 (SL) 18.4 P0.80 x (17 - 1) = 12.80.04 W0.400.02 4.0 0.5 15.0 (SL) DUMMY V0L V0L V12L V43L V5L DUMMY VDD S/C EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 0.5 DI7 XCK DISPOFF LP EIO1 FR L/R MD TEST1 VSS DUMMY V5R V43R V12R V0R V0R DUMMY 0.3MAX. Pattern side 18.4 P0.80 x (17 - 1) = 12.80.04 W0.400.02 15.0 (SL) 0.75MAX. Backside 1.2MAX. Total 27.7 (SL) 0.9 (SL)
63.950.12 [56.0 (E.L)]
1.75
2.05
1.75 2.75 O2.0 (Good device hole) 0.3 0.4 2.7 (SR) 2-O1.8 (Cu hole) 5.2 MAX. (Resin area) 2-O2.2 (PI) 2-O2.4 (SR) Flexible slits 2-O3.0 (Cu) 2-O3.6 (SR) 18.84 MAX.(Resin area) 1.9810.05 4.750.05 0.10.02
0.3 0.10.02 0.10.02 0.40.02
3.0 (SL)
0.10.02 0.10.02 0.40.02 Sprocket center
[0.4]
8.60.7
[6.5 (E.L.)]
Chip center 0.10.02 0.10.02 1.33 0.3 0.3 0.40.02
3.0 5.0 (SL) 4.0 (SL) 9.0 (SL) 6.33 6.58 8.58 10.58 +0.25 12.18 -0.30 (SR)
14.280.05 14.430.05 14.580.05 [15.93 (E.L.)] [22.43 (E.L.)]
28
0.3 26.93 (SL) P0.21 x (121 - 1) = 25.20.06 W0.110 0.3 2.33 53.560.012 27.23 27.4 (SR) 55.06 (Backside PI coating) [56.0 E.L.)] 26.93 (SL) 27.23 27.4 (SR)
Y120 Y119 Y122 Y121 Y2 Y1 DUMMY
0.10.02 1.9810.05 0.3 0.10.02 0.2 Both side polyimide coating 0.10.02 0.2 0.4
[0.4]
1.0 (SL) 1.0 (SL) 1.0 (SL) P0.21 x (121 - 1) = 25.20.06 W0.110
DUMMY Y240 Y239
[3.75TYP. (3.5MIN.)]
o Tape Specification
Tape width Tape type Perforation pitch 70 mm Wide 6 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 USLP 18 m Polyimide SSF
PACKAGES FOR LCD DRIVERS

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