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 EDGE693 500 MHz Monolithic Dual Pin Electronics Driver
EDGE HIGH-PERFORMANCE PRODUCTS Description
The EDGE693 is a dual pin electronics driver solution manufactured in a high-performance, complementary bipolar process. In Automatic Test Equipment (ATE) applications, the EDGE693 offers two pin drivers suitable for drive-only channels in memory testers, as well as for bidirectional channels in memory, VLSI, and mixed- signal test systems. Each driver is completely isolated from the other. There are separate data, enable, slew rate adjust, high and low levels; as well as power supply inputs for each driver. The driver output slew rate is adjustable from 3 V/ns to 1 V/ns, allowing the matching of edges from channel-tochannel, as well as slowing down edges for noise sensitive applications. Each driver is capable of driving 9 V signals over a 12 V range, in addition to going into a high impedance state. The EDGE693 can generate ECL signals up to 500 MHz and 3V signals in excess of 300 MHz. Combining two independent drivers into a 28-pin PLCC package offers a highly integrated solution appropriate where speed and density are at a premium.
Applications
* * Memory Test Equipment Instrumentation
Functional Block Diagram
SLEWADJA
VCCA GNDA VEEA
DRVENA DRVENA* DRIVER A DHIA EN DOUTA
Features
* * * * * * >2.5 V/ns Driver Slew Rates Adjustable Driver Slew Rates HiZ Capability 12 V Output Range 9 V Output Swings 28-Pin PLCC with an Internal Heat Spreader
DHIA* DVHA DVLA BIAS DRVENB DRVENB* DRIVER B DHIB EN DHIB* DVHB DVLB DOUTB
SLEWADJB
VCCB GNDB VEEB
Revision 1 / August 4, 2000
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description
Pin Name Driver DRVENA, DRVENA* DRVENB, DRVENB* DHIA, DHIA* DHIB, DHIB* DOUTA DOUTB DVLA, DVHA DVLB, DVHB DVLCAPA, DVHCAPA DVLCAPB, DVHCAPB SLEWADJA SLEWADJB BIAS Power VEEA, VEEB VCCA, VCCB GNDA, GNDB Test Pins THERMAL DIODE
Pin #
Description
25, 24 5, 6 27, 28 3, 2 18 12 22, 23 8, 7 16, 21 14, 9 20 10 1
Wide voltage differential input pins that determine whether the driver (A and B respectively) is forcing a voltage or placed in a high impedance state. Wide voltage differential input pins that force one of two programmable levels (DVH or DVL) at the driver (A and B respectively) output. Driver A and driver B outputs. Buffereed analog inputs that program the low and high output levels for driver A and driver B. Analog pins. 0.01 F capacitor to ground should be connected to each pin. Analog current inputs that adjust the rise and fall slew rates of driver A and driver B. Analog input. A positive current into this node sets the internal bias level for driver A and driver B.
17, 13 19, 11 26, 4
Negative power supply for driver A and driver B. Positive power supply for driver A and driver B. Device ground for driver A and driver B.
15
Thermal monitor output used to track the die junction temperature.
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description (continued)
28-Pin PLCC
SLEWADJA 20
DVHCAPA
DRVENA*
DRVENA
25
24
23
22
21
GNDA DHIA DHIA* BIAS DHIB* DHIB GNDB
26 27 28 1 2 3 4
10 11 5 6 7 8 9
19
VCCA
DVHA
DVLA
18 17 16 15 14 13 12
DOUTA VEEA DVLCAPA THERMAL DIODE DVLCAPB VEEB DOUTB
DRVENB
DRVENB*
DVHCAPB
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SLEWADJB
VCCB
DVHB
DVLB
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description
Introduction The driver circuit will force the DOUT output to one of three states: 1. 2. 3. DVH (driver high voltage level) DVL (driver low voltage level) High Impedance (Hi Z). Driver Levels DVH and DVL are high-input impedance voltage controlled inputs that establish the driver logical high and low levels respectively. Slew Rate Adjustment The driver rising and falling slew rates are adjustable from 3.0 V/ns to 1 V/ns. The SLEWADJ signals are current controlled inputs that vary the rising and falling edge slew rates. An input current of 2.0 mA translates to a slew rate of 3.0 V/ns. An input current of 0.8 mA forces a 1 V/ns edge (see Figure 1).
Both driver digital control inputs (DHI/DHI*, DRVEN/ DRVEN*) are wide-voltage differential inputs capable of receiving ECL, TTL, and CMOS signals. Single-ended operation is achievable by generating the proper threshold levels for the inverting inputs. Drive Enable The drive enable (DRVEN/DRVEN*) inputs control whether the driver is forcing a voltage or is placed in a high-impedance state. If DRVEN is more positive than DRVEN*, the output will force either DVL or DVH, depending on the driver data inputs. When DRVEN is more negative than DRVEN*, the output is set to highimpedance, independent of the driver data inputs. Driver Data The driver data inputs (DHI/DHI*) determine whether the driver output is high or low. If DHI is more positive than DHI*, the output will force DVH when the driver is enabled. If DHI is more negative than DHI*, the output will force DVL when the driver is enabled. Table 1 summarizes the functionality of the driver enable and driver data pins.
DRVEN, DRVEN* DRVEN > DRVEN* DRVEN > DRVEN* DRVEN < DRVEN* DHI, DHI* DHI > DHI* DHI < DHI* X DOUT DVH DVL HiZ
Slew Rate (V/ns)
2.5
1.0
0.8
2.0
SLEWADJ (mA) (BIAS = 1.5 mA)
Figure 1. Slew Rate Control
Notice that the driver A slew rate and driver B slew rate are independent. However, the rising and falling edge slew rates on each driver track each other and are not independent (see Figure 2).
a
b
a. SLEWADJ = 2.0 mA, Rising SR = Falling SR = 2.5V/ns. b. SLEWADJ = 0.8 mA, Rising SR = Falling SR = 1.0V/ns.
Table 1. DRVEN and DHI Pin Functionality
Figure 2. Output Slew Rate Adjustability
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
For system level flexibility, the SLEWADJ input is designed to allow a voltage DAC, a current DAC, or a resistor to a fixed voltage as possible slew rate control mechanisms (see Figure 3).
SLEWADJ
DVLCAP / DVHCAP These two analog nodes are brought out to better stabilize the high and low driver levels. Much like placing decoupling capacitors on the DVL and DVH input pins, the DVLCAP and DVHCAP pins require a fixed .01 F chip capacitor (with good high frequency characteristics) to ground (see Figure 5). A tight layout with minimum etch is recommended.
EDGE693
1.5K
Rise/Fall Adjust Current
DVLCAP .01 F
DVHCAP .01 F
Figure 3. SLEWADJ Inputs Figure 5. DVLCAP and DVHCAP
Driver Bias Thermal Monitor The BIAS pin is an analog current input that requires a 1.2 mA fixed reference current for the driver. Several circuit configurations are usable to satisfy this requirement, the most simple being a fixed resistor to a fixed power supply, typically VCC (see Figure 4). Looking into the BIAS node shows a .7 V voltage source with a 1.5 KW impedance, so the equation to select the fixed resistor is: (VCC - .7) / (R + 1.5) = 1.2 mA The EDGE693 includes an on-chip thermal monitor accessible through the THERMAL DIODE pin. This node connects to 5 diodes in series to VEE (see Figure 6) and may be used to accurately measure the junction temperature at any time.
Thermal Diode
Bias Current
Alternatively, a current DAC could be used to either program the BIAS current or to perform subtle adjustments in the fixed value.
VCC
EDGE693
VEE
Temperature coefficient = -10 mV/ C
Figure 6. Thermal Diode String
1.2 mA R Bias
A bias current of 100 A is injected into this node, and the measured voltage corresponds to a specific junction temperature with the following equation: TJ(C) = {(VTHERMAL DIODE - VEE) / 5 - .7} / (-.00208).
Figure 4. Bias Current Generation
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS Application Information
Thermal Information
Parameter Thermal Resistance Junction to Case Junction to Air Still Air 50 LFPM 400 LFPM Symbol JC JA JA JA Min Typ Max Units
oC/W
13
49 36 26
oC/W oC/W oC/W
Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device mounted either in the test socket or on the printed circuit board. Thermal resistance measurements are taken with device soldered to PCB.
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS Package Information
28 Pin PLCC Package JA = 75 to 80C / W
PIN Descriptions
Pin #1 Pin #1 Ident 0.045 x 45o [1.143]
Pin #1
0.485 - 0.495 [12.32 - 12.57] SQ 0.450 - 0.456 [11.43 - 11.58] SQ
0.300 REF [7.62]
0.050 [1.27] TYP
.045 x 45 [1.14]
o
0.165 - 0.180 [4.19 - 4.57]
0.026 - 0.032 [0.661 - 0.812]
0.390 - 0430 [9.91 - 10.92]
0.026 - 0.032 [0.661 - 0.812]
0.090 - 0.120 [2.29 - 3.04]
Notes: (unless otherwise specified) 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .XXX 0.005 [0.127]. 3. PLCC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers.
2000 Semtech Corp.
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS Recommended Operating Conditions
Parameter Positive Power Supply Negative Power Supply Total Analog Supply Analog Inputs Driver High Level Driver Low Level Driver Bias Driver A Slew Rate Adjust Driver B Slew Rate Adjust Ambient Operating Temperature Junction Temperature Symbol VCC VEE VCC - VEE DVH DVL BIAS SLEWADJA SLEWADJB TA TJ Min 10.5 -8.0 14.7 VEE + 3.5 VEE + 2.9 1.5 0.8 0.8 0 +25 2.5 2.5 +70 +125 Typ Max 12.5 -4.2 19.0 VCC - 2.9 VCC - 3.5 Units V V V V V mA mA mA
oC oC
Absolute Maximum Ratings
Parameter VCC (Relative to GND) VEE (Relative to GND Total Power Supply Digital Input Voltages Differential Digital Input Voltages Analog Voltages Analog Input Currents Driver Bias Slew Rate Adjust Driver Output Current (Static) Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) Symbol VCC VEE VCC - VEE DRVEN, DRVEN* DHI, DHI* DRVEN - DRVEN* DHI - DHI* DOUT, DVL, DVH BIAS SLEWADJA SLEWADJB DOUT TA TS TJ TSOL VEE -5.5 VEE 0 0 0 -50 -55 -65 Min 0 -10.0 Typ Max +14.0 0 +19.0 +7.0 +5.5 VCC 2.5 3.0 3.0 +50 +125 +150 +150 260 Units V V V V V V mA mA mA
mA oC oC oC oC
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2000 Semtech Corp. 8 www.semtech.com
EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS DC Characteristics
Parameter Analog Input Current DVH, DVL Bias Input Adjustment Inputs SLEWADJ Input Resistance SLEWADJ Current Range Driver Circuit Output Voltage Range Output Voltage Swing Max Static Output Current: DOUT >= -2V DOUT < -2V Max Dynamic Output Current DOUT Leakage Current (Note 1) DOUT >= -2V DOUT < -2V Driver High Accuracy Offset (Note 1) Gain (Note 2) Linearity (Note 3) Driver Low Accuracy Offset (Note 1) Gain (Note 2) Linearity (Note 3) Offset Voltage Temperature Coefficient Driver Output Impedance Driver PSRR Digital Inputs DRVEN, DRVEN*, DHI, DHI* Input Current Input Voltage Range Differential Input Swing Power Supply Current Positive Supply Negative Supply VDOUT Vswing IDOUT IDOUT Symbol Min Typ Max Units
IIN BIAS
-50 1.5 1.5 0.9 VEE + 3.5 0.25 -35 -20 -100 -1 -3 -90 -95 -15 -65 .99 1
+50
A mA K mA V V mA mA mA A A mV V/V mV
2.0 VCC - 3.5 9.0 +35 +35 +100 1 3 -40 1.0 +15
ILEAK ILEAK DVH - DOUT DVH / DOUT DVL - DOUT
DVH - DOUT DVH / DOUT DVL - DOUT DOUT TC ZOUT PSRR
-75 -95 -15
-50 .99 1 1
-25 1.0 +15
mV V/V mV mV/oC
1.0 20
3.0
4.5
dB
IIN VRNG VDIFF ICC IEE
-900 -2.0 0.25 140 -140
+900 +5.5 +4.0 160
A V V mA mA
-160
Note 1: Note 2:
Note 3:
The offset voltage is defined as the difference between the measured driver output at DOUT under no load conditions versus the programmed voltage (DVH or DVL) when forced to -1.0 V. The driver gain is defined as the change in driver output voltage (DOUT) divided by the change in programmed input voltage (DVH or DVL). Measurements are taken at -1.0 V and +4.0 V programmed inputs with the output under no-load conditions. Linearity error is defined as the maximum deviation between the theoretical driver output voltage (predicted by the straight line determined by the offset and gain) and the actual measured output voltage under no load conditions.
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS AC Characteristics
Parameter Driver Circuit Tpd from DHI to DOUT (Note 1) Tpd from DRVEN to DOUT HiZ (Note 2) Tpd from DRVEN to DOUT Active (Note 2) DOUT Rise/Fall Times (Note 3) ECL, 20% - 80% 3V, 10% - 90% 5V, 10% - 90% 8V, 10% - 90% Slew Rate Sensitivity to RADJ or FADJ Toggle Rate (Note 4) Output Capacitance in HiZ Minimum Pulse Width (Note 5) ECL 3V 5V 7V Tr/Tf Tr/Tf Tr/Tf Tr/Tf SR/IADJ Fmax Cout Tpd 1.5 1.5 1.5 0.6 1.2 1.8 2.75 .938 500 2.0 1.0 2.0 2.7 3.5 ns ns ns ns ns ns ns V/ns/mA MHz pF ns ns ns ns Symbol Min Typ Max Units
The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least two minutes while maintaining the normal operating environment. (IBIAS = 1.2 mA, SLEWADJ = 2.5 mA) Note 1: Note 2: Tpd is measured from crossover point of DHI and DHI* to the 50% point in the output. DVL equals 0 V and DVH equals +3 V. Specification condition: DVL equals -1 V and DVH equals +1 V. Output is terminated to GND by 100 . Tpd is measured from the crossover point of DRVEN and DRVEN* to the point where a 10-percent change in output voltage occurs. The driver load is an 18 cm 50 transmission line terminated with 1K in parallel with 3 pF. ECL output conditions. Signal reaches 100% of programmed value. The output pulse width is measured at the 50-percent points. Output reaches 100% of programmed value.
Note 3: Note 4: Note 5:
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EDGE693
EDGE HIGH-PERFORMANCE PRODUCTS Ordering Information
Model Number E693AHJ
Package 28-Pin PLCC (with Internal Heat Spreader)
EVM693AHJ
EDGE693 Evaluation Module
Contact Information
Semtech Corporation Edge High-Performance Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633
2000 Semtech Corp. 11 www.semtech.com


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