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QL5032 - QuickPCITM
33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM last updated 12/2/99
DEVICE HIGHLIGHTS Device Highlights
High Performance PCI Controller
s 32-bit / 33 MHz PCI Master/Target s Zero-wait state PCI Master provides 132 MB/s transfer rates s Programmable back-end interface to optional local processor s Independent PCI bus (33 MHz) and local bus
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(up to 160 MHz) clocks
s Fully customizable PCI Configuration Space s Configurable FIFOs with depths up to 256 s Reference design with driver code (Win 95/98/Win 2000/
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s PCI v2.2 compliant s Supports Type 0 Configuration Cycles in Target mode s 3.3V, 5V Tolerant PCI signaling supports Universal
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PCI Adapter designs
s 3.3V CMOS in 208-pin PQFP and 256-pin PBGA s Supports endian conversions s Unlimited/Continuous Burst Transfers Supported
FIGURE 1. QL5032 Diagram
Architecture Overview ARCHITECTURE OVERVIEW
The QL5032 device in the QuickLogic QuickPCI ESP (Embedded Standard Product) family provides a complete and customizable PCI interface solution combined with 37,000 system gates of programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MB/s). The programmable logic portion of the device contains 390 QuickLogic Logic Cells, and 14 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs. The QL5032 device meets PCI 2.2 electrical and timing specifications and has been fully hardwaretested. This device also supports the Win'98 and PC'98 standards. The QL5032 device features 3.3volt operation with multi-volt compatible I/Os. Thus it can easily operate in 3-volt systems and is fully compatible with 3.3V,5V or Universal PCI card development.
Extendable PCI Functionality
s Support for Configuration Space from 0x40 to 0x3FF s Multi-Function, Expanded Capabilities, & Expansion ROM capa-
ble
s Power management, Compact PCI, hot-swap/hot-plug
compatible
s PCI v2.2 Power Management Spec compatible s PCI v2.2 Vital Product Data (VPD) configuration support s Programmable Interrupt Generator s I2O support with local processor s Mailbox register support
Programmable Logic
s 37K system gates / 390 Logic Cells s 16,128 RAM bits, up to 154 I/O pins s 250 MHz 16-bit counters, 275 MHz Datapaths, 160 MHz FIFOs s All back-end interface and glue-logic can be implemented on chip s 7 64-deep FIFOs or 3 128-deep FIFOs or a single 256-deep
FIFO or a combination that requires 14 or less QuickLogic RAM Modules
s (3) 32-bit busses interface between the PCI Controller and the
Programmable Logic
Rev B
QL5032 - QuickPCITM
PCI CONTROLLER
The PCI Controller is a 32-bit/33 MHz PCI 2.2 Compliant Master/Target Controller. It is capable of infinite length Master Write and Read transactions at zero wait state (132 MBytes/second). The Master will never insert wait states during transfers, so data should be supplied or received by FIFOs, which can be configured in the programmable region of the device. The Master Controller will most often be operated by a DMA Controller in the programmable region of the device. A DMA Controller reference design is available. The Target interface offers full PCI Configuration Space and flexible target addressing. Any number of 32-bit BARs may be configured, as either memory or I/O space. All required and options PCI 2.2 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is provided. The interface ports are divided into a set of ports for master transactions and a set for target transactions. The Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable logic region of the device. Since these functions are not timing critical, leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. Reference DMA controller, Configuration Space, and Address Decoding blocks are included so that the design cycle can be minimized.
PCI Controller
DMA MASTER/TARGET CONTROL DMA Master/Target Control
The customizable DMA controller included with the QuickWorks design software contains the following features:
s s s s
Configurable DMA count size for reads and writes (up to 30-bits) Configurable DMA burst size for PCI (including unlimited/continuous burst) Programmable Arbitration between DMA Read & Write transactions DMA Registers may be mapped to any area of Target Memory Space
-
Read Address (32-bit register) - Write Address (32-bit register) - Read Length (16-bit register) / Write Length (16-bit register) - Control and Status (32-bit register, includes 8 bit Burst Length)
s
DMA Registers are available to the local design or the PCI bus Programmable Interrupt Control to signal end of transfer or other event
s
CONFIGURABLE FIFOS
FIFOs may be created with the Ram/FIFO wizard in the QuickWorks tools. The figure below shows the graphical interface used to create these FIFOs. FIFOs may be designed up to 256 deep. With 14 RAM cells available in the QL5032, that allows for up to 7 FIFOs at 64 deep (36 wide), 3 FIFOs at 128 deep (36 wide), or 1 FIFO at 256 deep (36 wide).
Configurable FIFOs
CONFIGURATION SPACE Configuration Space and Address Decode AND ADDRESS DECODE
The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back-end logic. It also allows the user to implement any subset of the PCI commands supported by the QL5032. QuickLogic provides a reference Address Register/Counter and Command Decode block.
FIGURE 2. Graphical Interface to create FIFO
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Preliminary
QL5032 - QuickPCITM
PCI InterfaceSymbol PCI Interface Symbol
The figure below shows the interface symbol you would use in your schematic design in order to attach the local interface programmable logic design to the PCI core. If you were designing with a top-level Verilog or VHDL file, then you would use a structural instantiation of this PCI32 block, instead of a graphical symbol.
PCI32 PCI Pads AD[31:0] CBEN[3:0] FRAMEN IRDYN TRDYN DEVSELN STOPN PAR PERRN SERRN REQN INTAN PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCI_DEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 Usr_WrReq Usr_Write Cfg_Write Usr_Addr_WrData[31:0] Usr_CBE[3:0] Usr_Adr_Valid Usr_Adr_Inc Usr_Last_Cycle_D1 Usr_TRDYN Usr_STOPN Usr_Devsel Cfg_PERR_Det Cfg_SERR_Sig Cfg_MstPERR_Det Master Mst_WrData_Rdy Mst_WrBurst_Done Mst_RdData[31:0] Mst_RdData_Valid Mst_RdBurst_Done Mst_Xfer_D1 Mst_Last_Cycle Mst_REQN Mst_IRDYN Mst_Tabort_Det Mst_TTO_Det
CLK RSTN IDSEL GNTN
PCI Signals
Usr_RdData[31:0] Usr_Select Usr_Stop Usr_Interrupt Usr_Rdy Usr_MstRdAd_Sel Usr_MstWrAd_Sel Usr_RdDecode Usr_WrDecode Cfg_RdData[31:0] Cfg_LatCnt[7:0] Cfg_CmdReg6 Cfg_CmdReg8 Mst_WrMode Mst_WrData[31:0] Mst_WrData_Valid Mst_WrAd[31:0] Mst_RdMode Mst_RdAd[31:0] Mst_RdCmd[1:0] Mst_One_Read Mst_Two_Reads Mst_Burst_Req Mst_LatCntEn
Target
FIGURE 3. PCI Interface Symbol
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QL5032 - QuickPCITM
PCI Master Interface
The internal signals used to interface with the PCI controller in the QL5032 are listed below, along with a description of each signal. The direction of the signal indicates if it is an input provided by the local interface (i) or an output provided by the PCI controller (o). Signals that end with the character `N' should be considered activelow (for example, Mst_IRDYN
Mst_WrAd[31:0] I Address for master DMA writes. This address must be treated as valid from the beginning of a DMA burst write until the DMA write operation is complete. It must be incremented (by 4) each time data is transferred on the PCI bus, since only DWORD (4 byte) transfers are supported. Address for master DMA reads. This address must be treated as valid from the beginning of a DMA burst read until the DMA read operation is complete. It must be incremented (by 4) each time data is transferred on the PCI bus, since only DWORD (4 byte) transfers are supported. DMA state machine in "write" mode. This must be asserted at the beginning of a Master Transfer, and must be held until the Master Transfer completed (Mst_WrBurst_Done). DMA state machine in "read" mode. This must be asserted at the beginning of a Master Transfer, and must be held until the Master Transfer completed (Mst_RdBurst_Done). Request use of the PCI bus. This signal should be held from when the DMA controller is ready to provide the first data, until the transfer is complete (Mst_WrBurst Done or Mst_RdBurst_Done). This signals to the PCI core that one data transfer remains in the burst. This signal must be asserted when only one DWORD remains to be transferred on the PCI bus. Two or less data transfers remain in the burst. This signal must be asserted when two or less DWORDs remain to be transferred on the PCI bus. Data for master DMA writes (to PCI bus). Data valid on Mst_WrData[31:0]. Data receive acknowledge for Mst_WrData[31:0]. This serves as a POP control for a FIFO which provides data to the PCI core. Master write pipeline is empty, which indicates that the Write burst transaction is completed. Data for master DMA reads (from PCI bus). Data valid on Mst_RdData[31:0]. This serves as a PUSH control for a FIFO that receives data from the PCI core. Master read pipeline is empty, which indicates that Read burst transaction is completed. Type of PCI read command to be used for DMA reads: 00 or 01 = Memory Read 10 = Memory Read Line 11 = Memory Read Multiple Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch). For full PCI compliance, this port should be always set to 1. Data was transferred on the previous PCI clock. Useful for updating DMA transfer counts on DMA Read operations. Active during the last data transfer of a PCI master transaction. The PCI REQN signal generated by this device as PCI master. Not usually used in the back-end design. The PCI IRDYN signal generated by this device as PCI master. Not usually used in the back-end design. Target abort detected during master transaction. This is normally an error condition to be handled in the DMA controller. Target timeout detected (no response from target). This is normally an error condition to be handled in the DMA controller.
PCI Master Interface
Mst_RdAd[31:0]
I
Mst_WrMode
I
Mst_RdMode
I
Mst_Burst_Req
I
Mst_One_Read Mst_Two_Reads Mst_WrData[31:0] Mst_WrData_Valid Mst_WrData_Rdy Mst_WrBurst_Done Mst_RdData[31:0] Mst_RdData_Valid Mst_RdBurst_Done Mst_RdCmd[1:0]
I I I I O O O O O I
Mst_LatCntEn Mst_Xfer_D1 Mst_Last_Cycle Mst_REQN Mst_IRDYN Mst_Tabort_Det Mst_TTO_Det
I O O O O O O
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Preliminary
QL5032 - QuickPCITM
PCI Target Interface
Usr_Addr_WrData[31:0] O Target address and data from target writes. During all target accesses, the address will be presented on Usr_Addr_WrData[31:0] and simultaneously, Usr_Adr_Valid will be active. During target write transactions, this port will present write data to the PCI configuration space or user logic. PCI command and byte enables. During target accesses, the PCI command will be presented on Usr_CBE[3:0] and simultaneously, Usr_Adr_Valid will be active. During target read or write transactions, this port will present active-low byte-enables to the PCI configuration space or user logic. Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this address belongs to the device's memory space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal will be low, indicating that data (not an address) is present on Usr_Addr_WrData[31:0]. Indicates that the target address should be incremented, because the previous data transfer has completed. During burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented (by 4) for subsequent data transfers. This signal will be active for the duration of a target write transaction, and may be used by back-end logic to turn on outputenables for transmitting the data off-chip. Active when a "user read" command has been decoded from the Usr_CBE[3:0] bus. This command may be mapped from any of the PCI "read" commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. Active when a "user write" command has been decoded from the Usr_CBE[3:0] bus. This command may be mapped from any of the PCI "write" commands, such as Memory Write or I/O Write. The address on Usr_Addr_WrData[31:0] has been decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h). Write enable for data on Usr_Addr_WrData[31:0] during PCI writes. Write enable for data on Usr_Addr_WrData[31:0] during PCI configuration write transactions. Data from the PCI configuration registers, required to be presented during PCI configuration reads. Data from the back-end user logic (and/or DMA configuration registers), required to be presented during PCI reads.
PCI Target Interface
Usr_CBE[3:0]
O
Usr_Adr_Valid
O
Usr_Adr_Inc
O
Usr_WrReq
O
Usr_RdDecode
I
Usr_WrDecode
I
Usr_Select
I
Usr_Write Cfg_Write Cfg_RdData[31:0] Usr_RdData[31:0]
O O I I
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QL5032 - QuickPCITM
PCI Target Interface (Continued)
Cfg_RdData[31:0] Usr_RdData[31:0] Cfg_CmdReg8 Cfg_CmdReg6 Cfg_LatCnt[7:0] Usr_MstRdAd_Sel I I I I I Data from the PCI configuration registers, required to be presented during PCI configuration reads. Data from the back-end user logic (and/or DMA configuration registers), required to be presented during PCI reads. Bits 6 and 8 from the Command Register in the PCI configuration space (offset 04h). 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch). Used when a target read operation should return the value set on the Mst_RdAd[31:0] pins. This select pin saves on logic which would otherwise need to be used to multiplex Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Used when a target read operation should return the value set on the Mst_WrAd[31:0] pins. This select pin saves on logic which would otherwise need to be used to multiplex Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set in the PCI configuration space (offset 04h). System error asserted on the PCI bus. When this signal is active, the Signalled System Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). Data parity error detected on the PCI bus by the master. When this signal is active, bit 8 of the Status Register must be set in the PCI configuration space (offset 04h). Copy of the TRDYN signal as driven by the PCI target interface. Copy of the STOPN signal as driven by the PCI target interface. Inverted copy of the DEVSELN signal as driven by the PCI target interface. Last transfer in a PCI transaction is occurring. Used to delay (add wait states to) a PCI transaction when the back end needs additional time. Subject to PCI latency restrictions. Used to prematurely stop a PCI target access on the next PCI clock. Used to signal an interrupt on the PCI bus.
Usr_MstWrAd_Sel
I
Cfg_PERR_Det Cfg_SERR_Sig
O O
Cfg_MstPERR_Det
O
Usr_TRDYN Usr_STOPN Usr_Devsel Usr_Last_Cycle_D1 Usr_Rdy Usr_Stop Usr_Interrupt
O O O O I I I
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Preliminary
QL5032 - QuickPCITM
PCI Internal Signals
PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCI_DEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 O O O O O O O O PCI clock. PCI reset signal. Copy of the IRDYN signal from the PCI bus, delayed by one clock. Copy of the FRAMEN signal from the PCI bus, delayed by one clock. Copy of the DEVSELN signal from the PCI bus, delayed by one clock. Copy of the TRDYN signal from the PCI bus, delayed by one clock. Copy of the STOPN signal from the PCI bus, delayed by one clock. Copy of the IDSEL signal from the PCI bus, delayed by one clock.
PCI Internal Signals
RAM Module Features RAM Module Features
The QL5032 device has fourteen 1,152-bit RAM modules, for a total of 16,128 RAM bits. Using two "mode" pins, designers can configure each module into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 blocks. See the figure below. The blocks are also easily cascadable to increase their effective width or depth. The RAM modules are "dual-ported", with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. This approach allows up to 512-deep configurations as large as 28 bits wide in the QL5032 device. A similar technique can be used to create depths greater than 512 words. In this case address signals higher than the eighth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
RAM Module
MODE[1:0] WA[a:0] WD[w:0] ASYNCRD RA[a:0] RD[w:0]
WE WCLK
RE RCLK
FIGURE 4. RAM Module
Address Buses [a:0] 64x18 128x9 256x4 512x2 [5:0] [6:0] [7:0] [8:0]
Data Buses [w:0] [17:0] [8:0] >@ [1:0]
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QL5032 - QuickPCITM
JTAG Support
JTAG Support
QuickWorksDesign Software
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for the QL5032 device. Six pins are dedicated to JTAG and programming functions on each QL5032 device, and are unavailable for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. A sixth pin, STM, is used only for programming.
Third Party Design Entry & Synthesis
Schematic Verilog
SCS Tools
VHDL/
Turbo HDL Editor
Mixed-Mode Design
SynplifyHDL Synthesi Simulator Third Party Simulation Quick ool T /QuicChi: Optimize, Place, Route Silos III VeriBest
Development ToolSupport Development Tool Support
Software support for the QL5032 device is available through the QuickWorks(R) development package. This turnkey PC-based QuickWorks(R) package, shown in Figure 5, provides a complete ESP software solution with design entry, logic synthesis, place and route, and simulation. QuickWorks(R) includes VHDL, Verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated Synplicity Synplify LiteTM tool, specially tuned to take advantage of the QL5032 architecture. QuickWorks also provides functional and timing simulation for guaranteed timing and source-level debugging. The UNIX-based QuickToolsTM and PC-based QuickWorks-LiteTM packages are a subset of QuickWorks(R) and provide a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickToolsTM and QuickWorks-LiteTM read EDIF netlists and provide support for all QuickLogic devices. QuickToolsTM and QuickWorks-LiteTM also support a wide range of third-party modeling and simulation tools. In addition, the PC-based package combines all the features of QuickWorks-LiteTM with the SCS schematic capture environment, providing a low-cost design entry and compilation solution.
FIGURE 5. QuickWorks(R) Tool Suite
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Preliminary
QL5032 - QuickPCITM
Pin Type Descriptions
The QL5032 Device Pins are indicated in the table below. These are pins on the device, some of which connect to the PCI bus, and others that are programmable as user IO.
Pin Type Descriptions
Type IN OUT T/S S/T/S
Description Input. A standard input-only signal Totem pole output. A standard active output driver Tri-state. A bi-directional, tri-state input/output pin Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the PCI system central resource to sustain the inactive state once the active driver has released the signal. Open Drain. Allows multiple devices to share this pin as a wired-or.
Pin/Bus Name VCC VCCIO
Type IN IN
Function Supply pin. Tie to 3.3V supply. Supply pin for I/O. Set to 3.3V for 3.3V I/O, 5V for 5.0V compliant I/O Ground pin. Tie to GND on the PCB. Programmable Input/Output/TriState/Bi-directional Pin. Programmable Global Network or Input-only pin. Tie to VCC or GND if unused. Programmable Array Network or Input-only pin. Tie to VCC or GND if unused. Reserved by QuickLogic for future PCB. JTAG Data In/Ram Init. Serial Data In. Tie to VCC if unused. Connect to Serial EPROM data for RAM init. JTAG Data Out/Ram Init Clock. Leave unconnected if unused. Connect to Serial EPROM clock for RAM init. JTAG Clock. Tie to GND if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset/RAM Init. Reset Out. Tie to GND if unused. Connect to Serial EPROM reset for RAM init. QuickLogic Reserved pin. Tie to GND on the PCB.
GND I/O GLCK/I
IN T/S IN
ACLK/I
IN
O/D
RSVRD TDI/RSI*
IN IN
TDO/ RCO*
OUT
TCK TMS TRSTB/ RRO* STM
IN IN IN
IN
* See QuickNote 65 on the QuickLogic web site for information on RAM initialization.
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QL5032 - QuickPCITM
QL5032 External Device Pins
Pin/Bus Name
AD[31:0] CBEN[3:0]
QL5032 External Device Pins
Type
T/S T/S
Function
PCI Address and Data: 32 bit multiplexed address/data bus. PCI Bus Command and Byte Enables: Multiplexed bus which contains byte enables for AD[31:0] or the Bus Command during the address phase of a PCI transaction. PCI Parity: Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after address or data phases. Master drives PAR on address cycles and PCI writes. The Target drives PAR on PCI reads. PCI Cycle Frame: Driven active by current PCI Master during a PCI transaction. Driven low to indicate the address cycle, driven high at the end of the transaction. PCI Device Select. Driven by a Target that has decoded a valid base address. PCI System Clock Input. PCI System Reset Input PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) wishes to use the bus. A point to point signal between the PCI Device and the System Arbiter. PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access to the PCI bus by the Arbiter. A point to point signal between the PCI device and the System Arbiter. PCI Data Parity Error. Driven active by the initiator or target two clock cycles after a data parity error is detected on the AD and C/BE# busses. PCI System Error: Driven active when an address cycle parity error, data parity error during a special cycle, or other catastrophic error is detected. PCI Initialization Device Select. Use to select a specific PCI Agent during System Initialization. PCI Initiator Ready. Indicates the Initiator's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Target Ready. Indicates the Target's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Stop. Used by a PCI Target to end a burst transaction. Interrupt A. Asynchronous Active-Low Interrupt Request.
PAR
T/S
FRAMEN
S/T/S
DEVSELN CLK RSTN REQN
S/T/S IN IN T/S
GNTN
IN
PERRN
S/T/S
SERRN
O/D
IDSEL IRDYN
IN S/T/S
TRDYN
S/T/S
STOPN INTAN
S/T/S O/D
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Preliminary
QL5032 - QuickPCITM
PIN #157
PIN #1
QuickPCI QL5032-33APQ208C
PIN # 53
FIGURE 6. 208-pin PQFP
PIN # 105
PIN A1 CORNER
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
Bottom View
N P R T U V W Y
FIGURE 7. 256-pin PBGA
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QL5032 - QuickPCITM
QL5032 - 208 PQFP QL5032-208 PQFP Pinout Table Pinout Table
QL5032 256-PBGA Pinout Table
PQ208 Function PQ208 Function PQ208 Function PQ208 Function PQ208 Function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND INTAN RSTN ACLK/I VCC GCLK/I CLK VCC GNTN REQN AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24] VCC CBEN[3
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
GND IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] CBEN[2] TDI FRAMEN IRDYN TRDYN DEVSELN GND STOPN VCC I/O I/O PERRN I/O SERRN PAR CBEN[1] AD[15] AD[14] AD[13] AD[12] GND AD[11] AD[10] AD[9] AD[8] GND CBEN[0] AD[7] AD[6] AD[5] VCCIO AD[4]
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
AD[3] AD[2] AD[1] AD[0] I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O I/O I/O
169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O
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Preliminary
QL5032 - QuickPCITM
QL5032 256-PBGA Pinout Table
PB256 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 Function PB256 Function PB256 Function PB256 Function PB256 Function PB256 Function GND C4 I/O E19 I/O L2 ACLK/I T17 I/O V20 I/O I/O C5 I/O E20 I/O L3 RSTN T18 I/O W1 I/O I/O C6 I/O F1 I/O L4 GCLK/I T19 NC W2 I/O I/O C7 I/O F2 I/O L17 VCC T20 I/O W3 TDI I/O C8 I/O F3 I/O L18 I/O U1 I/O W4 GNTN I/O C9 VCCIO F4 VCC L19 I/O U2 I/O W5 AD[27] I/O C10 I/O F17 VCC L20 I/O U3 I/O W6 CBEN[3] I/O C11 I/O F18 NC M1 I/O U4 GND W7 AD[21] I/O C12 I/O F19 I/O M2 I/O U5 AD[26] W8 AD[20] I/O C13 I/O F20 I/O M3 I/O U6 VCC W9 CBEN[2] I/O C14 I/O G1 I/O M4 NC U7 AD[22] W10 DEVSELN I/O C15 I/O G2 NC M17 NC U8 GND W11 PERRN I/O C16 I/O G3 I/O M18 I/O U9 FRAMEN W12 CBEN[1] I/O C17 I/O G4 I/O M19 I/O U10 VCC W13 PAR I/O C18 I/O G17 I/O M20 I/O U11 I/O W14 AD[10] I/O C19 I/O G18 I/O N1 I/O U12 I/O W15 AD[9] I/O C20 I/O G19 NC N2 I/O U13 GND W16 AD[5] I/O D1 I/O G20 I/O N3 I/O U14 AD[11] W17 AD[1] TCK D2 I/O H1 I/O N4 GND U15 VCC W18 AD[0] I/O D3 I/O H2 I/O N17 GND U16 AD[4] W19 I/O TDO D4 GND H3 I/O N18 I/O U17 GND W20 TRSTB I/O D5 I/O H4 GND N19 I/O U18 I/O Y1 INTAN I/O D6 VCC H17 GND N20 I/O U19 I/O Y2 NC I/O D7 I/O H18 I/O P1 I/O U20 I/O Y3 REQN I/O D8 GND H19 I/O P2 I/O V1 I/O Y4 AD[31] I/O D9 I/O H20 I/O P3 I/O V2 NC Y5 AD[29] I/O D10 I/O J1 I/O P4 I/O V3 I/O Y6 AD[25] I/O D11 VCC J2 I/O P17 I/O V4 AD[30] Y7 AD[23] I/O D12 I/O J3 NC P18 I/O V5 AD[28] Y8 AD[19] I/O D13 GND J4 I/O P19 NC V6 AD[24] Y9 AD[17] I/O D14 I/O J17 NC P20 I/O V7 IDSEL Y10 IRDYN I/O D15 VCC J18 I/O R1 NC V8 AD[18] Y11 I/O I/O D16 I/O J19 I/O R2 I/O V9 AD[16] Y12 SERRN I/O D17 GND J20 GCLK / I R3 I/O V10 TRDYN Y13 AD[14] I/O D18 I/O K1 I/O R4 VCC V11 STOPN Y14 AD[12] I/O D19 I/O K2 I/O R17 VCC V12 VCCIO Y15 AD[8] NC D20 I/O K3 I/O R18 I/O V13 AD[15] Y16 AD[7] STM E1 NC K4 VCC R19 I/O V14 AD[13] Y17 AD[3] NC E2 I/O K17 GCLK/I R20 I/O V15 CBEN[0] Y18 I/O I/O E3 I/O K18 ACLK/I T1 NC V16 AD[6] Y19 I/O I/O E4 I/O K19 GCLK/I T2 I/O V17 AD[2] Y20 NC I/O I/O E17 E18 I/O I/O K20 L1 NC CLK T3 T4 I/O NC V18 V19 I/O TMS
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QL5032 - QuickPCITM
Absolute Maximum Ratings
DC Input Current ........................... .... 20 mA ESD Pad Protection........................ .... 2000V Storage Temperature...............-65C to +150C Lead Temperature ................... ...... .......300C
VCC Voltage ........... ............ -0.5 to 4.6V VCCIO Voltage ........ ............ -0.5 to 7.0V Input Voltage ........... -0.5 to VCCIO+0.5V Latch-up Immunity ................ .... 200mA
Operating Range
Sym bol VCC VCC IO TA K Param eter Supply Voltage I/O Input Tolerance Voltage Am bient Tem perature Delay Factor -A Speed G rade Industrial M in M ax 3.0 3.6 3.0 5.5 -40 85 0.43 0.95 Com m ercial M in M ax 3.0 3.6 3.0 5.25 0 70 0.46 0.93 U nit V V C
DC Characteristics
Symbol VIH VIL VOH VOL II IOZ CI IOS ICC ICCIO Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [1] Output Short Circuit Current [2] D.C. Supply Current [3] D.C. Supply Current on VCCIO Conditions Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 A IOL = 16 mA 0.45 V IOL = 1.5 mA 0.1VCC V A VI = VCCIO or GND -10 10 A VI = VCCIO or GND -10 10 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 2 mA A 0 100
Notes: [1] Capacitance is sample tested only. [2] Only one output at a time. Duration should not exceed 30 seconds. [3] For -A commercial grade device only. Maximum ICC is 3 mA for all industrial grade devices. For AC conditions, contact QuickLogic Customer Engineering.
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Preliminary
QL5032 - QuickPCITM
AC CHARACTERISTICS at VCC = 3.3V, TA = 25C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.8 0.0 0.8 1.6 1.6 1.4 1.2 1.9 1.8 Propagation Delays (ns) Fanout [4] 2 3 4 1.7 2.0 2.3 1.8 1.8 1.8 0.0 0.0 0.0 1.1 1.4 1.7 1.6 1.6 1.6 1.6 1.6 1.6 1.7 2.0 2.3 1.5 1.8 2.1 1.9 1.9 1.9 1.8 1.8 1.8
8 3.5 1.8 0.0 2.9 1.6 1.6 3.5 3.3 1.9 1.8
RAM Cell Synchronous Write Timing
Propagation Delays (ns) Fanout [4] 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 5.3 5.6 5.9
Symbol TSWA THWA TSWD THWD TSWE THWE TWCRD Notes:
Parameter WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA) [4] 1 1.0 0.0 1.0 0.0 1.0 0.0 5.0
8 1.0 0.0 1.0 0.0 1.0 0.0 7.1
[4] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the Appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [5] These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL5032 - QuickPCITM
RAM Cell Synchronous Read Timing
Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 4.3 4.6 4.9
Symbol TSRA THRA TSRE THRE TRCRD
Parameter RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD [5] 1 1.0 0.0 1.0 0.0 4.0
8 1.0 0.0 1.0 0.0 6.1
RAM Cell Asynchronous Read Timing
Symbol RPDRD Parameter RA to RD [5] 1 3.0 Propagation Delays (ns) Fanout 2 3 4 3.3 3.6 3.9
8 5.1
Input-Only Cells
Symbol TIN TINI TISU TIH TlCLK TlRST TlESU TlEH Parameter
1
Propagation Delays (ns) Fanout [5]
2 3 4 8 12 24
High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time
1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0
1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0
1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0
1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0
2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0
2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0
4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
Clock Cells
Symbols tACK tGCKP tGCKB Parameter 1 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1.2 0.7 0.8 2 1.2 0.7 0.8 Propagation Delays (ns) Loads per Half Column [6] 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 12 1.7 0.7 1.3 15 1.8 0.7 1.4
Notes: [6] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column.
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Preliminary
QL5032 - QuickPCITM
I/O Cell Input Delays
Symbol
tI/O TISU TIH TlOCLK TlORST TlESU TlEH
Parameter
1 Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time
Propagation Delays (ns) Fanout [5]
2 3 4 8 10
1.3 3.1 0.0 0.7 0.6 2.3 0.0
1.6 3.1 0.0 1.0 0.9 2.3 0.0
1.8 3.1 0.0 1.2 1.1 2.3 0.0
2.1 3.1 0.0 1.5 1.4 2.3 0.0
3.1 3.1 0.0 2.5 2.4 2.3 0.0
3.6 3.1 0.0 3.0 2.9 2.3 0.0
I/O Cell Output Delays
Symbol
TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ
Parameter
30 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8]
Propagation Delays (ns) Output Load Capacitance (pF)
50 75 100 150
2.1 2.2 1.2 1.6 2.0 1.2
2.5 2.6 1.7 2.0
3.1 3.2 2.2 2.6
3.6 3.7 2.8 3.1
4.7 4.8 3.9 4.2
Notes:
[7] The following loads are used for tPXZ:
tPHZ 1K 5 pF 1K tPLZ 5 pF
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