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19-3559; Rev 0; 1/05
KIT ATION EVALU E AILABL AV
Integrated L1-Band GPS Receiver
General Description Features
Supports All Popular Handset Reference Frequencies Up to 26MHz 4.7dB Cascaded Noise Figure 80dB Cascaded Gain Tolerates -90dBm In-Band Jammer Tolerates +13dBm CDMA Out-of-Band Jammer at Device Input Integrated Synthesizer and VCO Integrated 2- or 3-Bit ADC 50dB IF AGC Range Small 28-Pin Thin QFN Package SPITM Control Interface Clock Output for Baseband Processor
SPI is a trademark of Motorola, Inc.
MAX2741
The MAX2741 L1-band GPS receiver IC offers a highperformance, compact solution for mobile handsets, PDAs, and automotive applications. Total voltage gain of 80dB and a 4.7dB cascaded noise figure can provide receiver sensitivity for applications requiring -185dBW for indoor tracking solutions. This dual-conversion receiver downconverts the 1575.42MHz GPS signal to a 37.38MHz first IF, and then a 3.78MHz second IF. An integrated 2- or 3-bit ADC (1bit SIGN, 1- or 2-bit MAG selectable) samples the second IF and outputs the digitized signals to the baseband processor. The integrated synthesizer offers the flexibility in frequency planning to allow a single board design to be employed for reference frequencies from 2MHz to 26MHz. The integrated reference oscillator allows either TCXO or crystal operation. The receiver runs from a 2.7V to 3.0V supply, and draws only 30mA when active. It is offered in a 28-pin thin QFN package, and is specified for -40C to +85C at 3V.
28THIN Q PIN
FN
Ordering Information
PART MAX2741ETI TEMP RANGE -40C to +85C PIN-PACKAGE 28 Thin QFN
IFOUT+
IFOUT-
IFIN+
VCC6
IFIN-
N.C.
Telematics (Vehicle and Asset Tracking, Inventory Management) Automotive Security Emergency Response Systems Emergency Road-Side Assistance Location-Based Services/Internet (PDAs) Digital Cameras/Camcorders Recreational Handhelds/Walkie-Talkies Geographical Information Systems (GIS) Consumer Electronics (Location-Based Games) Precision Timing
VCC4 VCC2 N.C. VCC1
28
27
26
25
24
23
22
1
33.6MHz
MAX2741
N.C.
In-Vehicle Navigation Systems (IVNS)
FILT
SCLK
CS
SDI
XTAL
________________________________________________________________ Maxim Integrated Products
REFCLK
SHDN
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
5.
0m
mx5
.0 m
m
Applications
Pin Configuration/ Functional Diagram
21
SDO
2 LNA 1612.8MHz 4 90 /2 0 /96 /16128 P.D. 200kHz
VCO 3225.6MHz
20
N.C.
RFIN
3
19
VCC5
ADC
18
GPSIF0
VCC3
5
/R /192 16.8MHz MUX
17
GPSIF1
6
16
GPSIF2
GND
7
SPI INTERFACE
REF OSC 11 12 13 14
15
GPSCLK
8
9
10
1
Integrated L1-Band GPS Receiver MAX2741
ABSOLUTE MAXIMUM RATINGS
VCC Pins to GND ...................................................-0.3V to +3.3V VCC Pins to Each Other .........................................-0.3V to +0.3V FILT to GND................................................-0.3V to (VCC + 0.3V) CMOS Inputs to GND (SHDN, SCLK, CS, SDI).................................................+0.3V to (VCC + 0.3V) CMOS Outputs to GND (CLKOUT, GPSIF_, SDO).........................................-0.3V to (VCC + 0.3V) RFIN to GND...............................................-0.3V to (VCC + 0.3V) First IF Filter I/O to GND (IFOUT, IFIN).....-0.3V to (VCC + 0.3V) Crystal Inputs to GND (XTAL, REFCLK).....-0.3V to (VCC + 0.3V) Maximum RF Input Power...................................................0dBm Continuous Power Dissipation (TA = +85C) 28-Pin Thin QFN (derate 20.8mW/C above +70C) .1000mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(Operating conditions (unless otherwise specified): VCC = 2.7V to 3.0V; REFCLK driven with 10MHz sinusoid, 1.2VP-P; registers set according to mode; no RF input signal; digital baseband outputs left open; TA = -40C to +85C. Typical values are measured at VCC = 2.75V, TA = +25C.)
PARAMETER Supply Voltage Supply Current Input-Logic High Threshold Input-Logic Low Threshold Input-Logic High/Low Current Output-Logic High Output-Logic Low ILOAD = 100A ILOAD = 100A -10 VCC 0.3 0.3 Normal operation (TA = +25C) Standby (V SHDN = VIL, SYNTH:D8 = 0) VCC 0.1 0.1 +10 CONDITIONS MIN 2.7 30 0.7 TYP MAX 3.0 42 UNITS V mA V V A V V
AC ELECTRICAL CHARACTERISTICS
(Operating conditions (unless otherwise specified): VCC = 2.7V to 3.0V for TA = -40C to +85C; REFCLK driven at 10MHz sinusoid, 1.2VP-P; registers set according to mode; using the Typical Application Circuit; CW RF signal at 1575.42MHz. Typical values are measured at VCC = 2.75V, TA = +25C.)
PARAMETER 1st CONVERSION STAGE (RF TO 1st IF) RF Frequency RF Conversion Gain Noise Figure Input IP3 RF Image Rejection LO Leakage at RF L1-band (Note 1) Mid-gain (CONFIG1:D4-D0 = 10000) (Note 2) (Notes 3, 4) LO to RFIN pin 20 15 1575.42 21 4.7 -30 35 -90 32 MHz dB dB dBm dB dBm CONDITIONS MIN TYP MAX UNITS
2
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Integrated L1-Band GPS Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(Operating conditions (unless otherwise specified): VCC = 2.7V to 3.0V for TA = -40C to +85C; REFCLK driven at 10MHz sinusoid, 1.2VP-P; registers set according to mode; using the Typical Application Circuit; CW RF signal at 1575.42MHz. Typical values are measured at VCC = 2.75V, TA = +25C.)
PARAMETER 2nd CONVERSION STAGE (1st IF TO ADC INPUT) 1st IF Frequency Conversion Gain Input IP3 Noise Figure IF Output Port Admittance IF Input Port Admittance LPF -3dB Corner Frequency SYNTHESIZER ICP_OH ICP_OL Closed-Loop Phase Noise Comparison Spurs Reference Oscillator Frequency REF Input Voltage Level VCO Coarse Tune Range DIGITAL I/O SPI Clock Frequency 1 MHz PLL charge-pump source current PLL charge-pump sink current At 1kHz offset At 200kHz offset Sinusoid (Note 1) Sinusoid (Note 1) Programmable (CONFIG1:D7 to D5 = 000 to 111) (Note 1) 2 0.6 240 75 -100 -55 -44 10 26 2.2 A A dBc/Hz dBc/Hz MHz VP-P MHz At IFOUT Max gain (CONFIG1:D4-D0 = 11111) (Note 1) Min gain (CONFIG1:D4-D0 = 00000) (Note 1) 1st conversion (Note 5) Max gain (CONFIG1:D4-D0 = 11111) Real Imaginary Real Imaginary (SYNTH:D13-D10 = 1111) (SYNTH:D13-D10 = 0000) 48 37.38 61 10 -36 12 0.40 1.5 0.40 0.15 2.9 7.7 74 MHz dB dB dBm dB mS pF mS pF MHz CONDITIONS MIN TYP MAX UNITS
MAX2741
Note 1: Note 2: Note 3: Note 4: Note 5:
Production tested for +25C and +85C, guaranteed by design and characterization for -40C. Test tones at 1575.8MHz and 1576.8MHz at -60dBm/tone. Guaranteed by design and characterization. Image frequency is 1575.42MHz + 2(fIF) = 1650.18MHz Test tones at 37.38MHz and 36.88MHz at -50dBm/tone.
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3
Integrated L1-Band GPS Receiver MAX2741
Pin Description
PIN 1 2, 20, 22, 23 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 24 25 26 27 28 Exposed NAME VCC1 N.C. RFIN VCC2 VCC3 VCC4 GND FILT SCLK CS SDI SHDN XTAL REFCLK GPSCLK GPSIF2 GPSIF1 GPSIF0 VCC5 SDO IFINIFIN+ IFOUTIFOUT+ VCC6 GND Reserved. Make no connections to this pin. LNA Input. Connect to GPS antenna through a bandpass filter. This input requires an external matching network to match to 50. AC-couple to this pin. VCO Supply Connection. External RF bypass capacitor to ground required. CML Supply Connection. External RF bypass capacitor to ground required. Digital Logic and PLL Supply Connection. External RF bypass capacitor to digital ground required. Ground. Connect to PC board digital ground plane. PLL Loop Filter Connection. This is the output of the phase detector's charge pump. Use the recommended filter on EV kit for optimal phase noise and lock time. SPI Clock Input (CMOS) SPI Chip-Select Input (CMOS, Active Low) SPI Data Input (CMOS) Full IC Power-Down. This shutdown pin disables the on-chip oscillator and the rest of the IC. To keep the oscillator running, use the software shutdown (SYNTH:D8); (CMOS, active high). Crystal Oscillator Feedback Capacitor Connection Reference Clock Input for PLL. Drive with 1.2VP-P when using TCXO module. GPS Clock Output to Baseband. This is the clock used by the ADC to sample the GPS data (CMOS). Sampled IF Output, Bit 2 (CMOS). See Table 5. Sampled IF Output, Bit 1 (CMOS). See Table 5. Sampled IF Output, Bit 0 (CMOS). See Table 5. IF Supply Connection. External RF bypass capacitor to ground required. SPI Data Output (CMOS) 1st IF Input (Inverting). Connect this 2.5k differentially terminated input to the 1st IF filter's (-) output. 1st IF Input (Noninverting). Connect this 2.5k differentially terminated input to the 1st IF filter's (+) output. 1st IF Output (Inverting). Connect this 2.4k differential output to the 1st IF filter's (-) input. 1st IF Output (Noninverting). Connect this 2.4k differential output to the 1st IF filter's (+) input. RF Image-Reject Mixer Supply. External RF bypass capacitor to ground required. RF Ground. Ultra-low inductance connection to ground. Place several vias to PC board ground plane. FUNCTION LNA Supply Connection. External RF bypass capacitor to ground required.
4
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Integrated L1-Band GPS Receiver
Detailed Description
The MAX2741 GPS offers a high-performance superheterodyne receiver solution for low-power mobile devices, with the benefit of using the system's existing clock reference. This receiver is ideal for integration into mobile phone handsets using common reference frequencies such as 10.0, 13.0, 14.4, 19.2, 20.0, and 26.0MHz. The only external components required are the GPS RF filter, an IF filter (typically designed from inexpensive discretes), a three-component PLL loop filter, and a few other resistors and capacitors. The MAX2741 integrates the reference oscillator core, the VCO and its tank, the synthesizer, a 1- to 3-bit ADC, and all signal path blocks except for the 1st IF filter. The typical application area for the receiver is less than 2cm2. DC offset compensation at the ADC input is performed by an on-chip 4-bit DAC. This compensates for any DC error introduced by transistor mismatch in the differential stage driving the ADC input, allowing the downconverted GPS signal's DC level to be centered within the threshold voltages of the ADC.
MAX2741
ADC
The on-chip ADC samples the down-converted GPS signal at the 2nd IF (3.78MHz). Sampled output is provided in either 2-bit (1-bit magnitude, 1-bit sign) or 3-bit (2-bit magnitude, 1-bit sign) formats, as determined by the ADC mode configuration bit (CONFIG1:D15); see Table 5 for details. The ADC sample clock (system GPS clock) is derived either directly from the reference clock (SYNTH:D9 = 1), or from an RFLO divide-by-96 block to provide a 16.8MHz sample clock (SYNTH:D9 = 0). The clock is available to the baseband processor at GPSCLK (pin 15). The sampled ADC data bits are available on pins 16, 17, and 18 (GPSIF2, GPSIF1, and GPSIF0). The functionality of the pins is different in each mode (2-bit vs. 3-bit)--see Table 5 in determining the interface connection for the application circuit.
RF/1st Conversion Stage (Front-End)
The MAX2741 RF front-end LNA and mixer are the most important in the signal path. This stage sets the noise figure for the receiver, defining the sensitivity, and mixes the 1575.42MHz L1-band GPS signal down to a 1st IF of 37.38MHz. The LNA itself has an NF of approximately 1.5dB; the cascaded NF of the front-end (including the mixer) is approximately 4.7dB, and the cascaded gain is typically 21dB. The image-reject mixer is set up for a high-side injected RFLO (1612.80MHz), and offers typically better than 30dB rejection of the image noise (1650.18MHz). The -30dBm input 3rd-order intercept (IIP3) of the RF strip, in conjunction with the GPS IF filter, provides excellent out-of-band interferer immunity. The 1st IF outputs (IFOUT) are internally biased to approximately 2V, and have a differential source impedance of approximately 2.5k. The IF filter can be implemented as a discrete L/C filter, or as a monolithic SAW or ceramic if one is available.
Synthesizer
The MAX2741 integrates an integer-N synthesizer; all blocks except the loop filter are on-chip. The reference can be either a crystal (driven by the internal oscillator), or a TCXO module. The oscillator provides a 5pF load to the crystal. A TCXO module should provide a swing in the 0.6VP-P to 2.2VP-P range. The reference divider (/R) is programmable (SYNTH: D7-D0), and can accommodate reference frequencies up to 26MHz. The reference divider needs to be set so the comparison frequency (fCOMP) at the frequency/ phase detector is 200kHz. The VCO runs at twice the frequency of the RFLO; the RFLO is therefore generated from the VCO using a quadrature divide-by-2 block. The RF LO is fCOMP x 8064 (typically 1612.80MHz), and the 1st IF LO is fCOMP x 168 (typically 33.6MHz); the RF and IF LO division ratios are not adjustable. This configuration allows for the use of reference frequencies common to GSM, CDMA, TDMA, TD-SCDMA, and UMTS handsets: 9.6MHz (R = 48), 13.0MHz (R = 65), 14.4MHz (R = 72), 19.2MHz (R = 96), 26.0MHz (R = 130), etc.
IF/2nd Conversion Stage
The 2nd conversion stage consists of an active mixer, a variable-gain amplifier (VGA), and a tunable lowpass filter. The IF mixer is configured for low-side LO injection for a 2nd IF of 3.78MHz. Total gain in this stage is 62dB, and the VGA offers 51dB of gain adjustment. The VGA is typically controlled by the baseband IC through the SPI interface to optimize the signal swing for digitization by the ADC. The on-chip lowpass filter has an adjustable cutoff frequency, programmable from 2.9MHz to 7.7MHz in 16 steps. This LPF further reduces out-of-band noise and band-limits the signal to the ADC, ensuring that the sampling process does not generate alias components.
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5
Integrated L1-Band GPS Receiver MAX2741
SPI Bus, Address and Bit Assignments
VCC4 GND
MAX2741
6 7 8
FILT
9
SCLK
22nF 100pF 36k
Figure 1. Recommended 3rd-Order PLL Filter
The VCO offers a bank of tuning capacitors that can be latched in/out to adjust the center frequency. Because the system does not require any RF LO frequency change (i.e., changing channels), the VCO varactor tuning gain is very low by design, which means the tuning range of the VCO is narrow. The coarse-tune capacitors in the tank circuit allow the system to adjust the VCO center frequency as needed to guarantee that the synthesizer can lock. In practice, process and temperature effects on VCO centering are negligible, and a coarsetune setting of 110 (CONFIG:D7 to D5) will center the VCO tuning range correctly in virtually all cases. To aid in bench and prototype testing, the PFD offers out-of-lockhigh and out-of-lock-low indicators, available in the SPI STATUS register (STATUS:D9 to D8). Use these flags to determine if the VCO tuning range needs to be adjusted higher or lower in the case where the PLL cannot lock. The PLL filter is the only external block of the synthesizer. The typical filter is a classic C-R-C two-pole shunt network on the tune line. Low phase noise is preferred at the expense of longer PLL settling times, so a low 10kHz to 20kHz loop bandwidth is used. The recommended PLL 10kHz filter implementation, with charge pump set to 200A (CONFIG1:D10 = 1), is shown in Figure 1. The system/GPS clock is derived either directly from the reference oscillator, or synthesized from the RFLO (see the ADC section). This clock is used as the sampling clock for the on-chip ADC, and is seen at pin 15, GPSCLK.
An SPI-compatible serial interface is used to program the MAX2741 for configuring the different operating modes. In addition, data can be read out of the MAX2741 for status and diagnostic use. The serial interface is controlled by four signals: SCLK (serial clock), CS (chip-select), SDI (data input), and SDO (data output). The control of the PLL, AGC, test, offset management, and block selection is performed through the SPI bus from the baseband controller. A 20-bit word, with the MSB (D15) being sent first, is clocked into a serial shift register when the chip-select signal is asserted low. The SPI bus has four control lines: serial clock (SCLK), chip-select (CS), data in (SDI), and data out (SDO). Enable SDO functionality by setting the digital test bus bits: CONFIG1:D9 to D8 = 01. The timing of the interface signals is shown in Figure 2 and Table 1 along with typical values for setup and hold time requirements. For best performance, the SPI bus should be configured during the startup initialization and then left with the optimum values in the registers. Any changes to the ADC and VGA bits during GPS signal processing may cause glitches and corrupt the analog signal path. Reading from the SPI bus does not interrupt GPS operation.
CS tSETUPD SCLK tHDATA SDI LSB
tSETUPSS tEND
tPERIOD MSB
Figure 2. SPI Timing Diagram
Table 1. SPI Timing Requirements
SYMBOL tSETUPD tPERIOD tHDATA tSETUPSS tEND PARAMETER Data to SCLK setup SCLK period Data hold to SCLK CS to SCLK disable Falling SCLK to CS inactive TYP VALUE 20 100 20 20 20 UNITS ns ns ns ns ns
6
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SYNTH
CONFIG 2
CONFIG 1
REGISTER NAME
REGISTER NAME
D15
D15
Reserved Reserved Reserved Reserved Reserved D10 Reserved D9 Out-of-Lock (High) Reserved Reserved Reserved Reserved Reserved Analog Test Mode Select Analog Test Mode Select Analog Test Mode Select Analog Test Mode Select Analog Test Mode Select 0 Digital Test Bus Mode Select (LSB) VCO Coarse Tuning Range (MSB) VCO Coarse Tuning Range VCO Coarse Tuning Range (LSB) AGC Gain (MSB) AGC Gain AGC Gain AGC Gain AGC Gain (LSB) 0 D8 Out-of-Lock (Low) DATA D7 XTAL Clock Selected D6 Parity D5 Reserved D4 LPF Autocalibrate End D3 LPF Autotune (MSB) D2 LPF Autotune D1 LPF Autotune D0 LPF Autotune (LSB) 0 1 1 Digital Test Bus Mode Select (MSB) Reserved Double ChargePump Current Reserved ADC Offset Control (SIGN) LPF Tuning Word LPF Tuning Word (LSB) XTAL Clock Select Standby PLL Ref Div Ratio (MSB) PLL Ref Div Ratio PLL Ref Div Ratio PLL Ref Div Ratio PLL Ref Div Ratio PLL Ref Div Ratio PLL Ref Div Ratio PLL Ref Div Ratio (LSB) 0 D12 D11 D12 D11 Reserved ADC Offset Control (MSB) LPF Tuning Word Drive VCO High ADC Offset Control LPF Tuning Word (MSB) D14 D13 D14 D13 Drive VCO Low ADC Offset Control (LSB) LPF Autotune Initiate
Table 3. Register Address and Data Bit Assigments (Read)
Table 2. Register Address and Data Bit Assigments (Write)
STATUS Reset CMOS ADC Mode Reserved D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA 1 1 1 0 1 0
MAX2741
_______________________________________________________________________________________
ADDRESS ADDRESS A3 A2 A1 A0 A3 A2 A1 A0 1 0 1 0
Integrated L1-Band GPS Receiver
7
Integrated L1-Band GPS Receiver MAX2741
Detailed Register Definitions
Table 4. Detailed Register Definition for Write Address 0100: SYNTH
DATA BIT D15 D14 D13-D10 D9 D8 D7-D0 DEFAULT 1 1 0100 1 0 01100000 Reserved LPF Autotune Initiate: I = Initiate autotune, 0 = Manual tuning. LPF Tuning Word: 0000 ~ 7.7MHz, 1111 ~ 2.9MHz. XTAL Clock Select: 1 = External reference, 0 = Synthesized 16.8MHz. Standby: 0 = Normal operating mode, 1 = Standby (oscillator remains active), but only if D9 = 1. Reference Division Ratio. Default 19.2MHz external reference (R = 96dec). R = fREF / 200kHz. DESCRIPTION
Table 5. Detailed Register Definition for Write Address 0101: CONFIG 1
DATA BIT D15 D14-D11 D10 D9 to D8 D7 to D5 D4-D0 DEFAULT 1 0000 0 00 001 11111 DESCRIPTION ADC Mode. Select 1 for 1-bit magnitude and sign, select 0 for 2-bit magnitude and sign. 1: GPSIF2 = sign, GPSIF1 = magnitude, GPSIF0 = X 0: GPSIF2 = MSB magnitude, GPSIF1 = LSB magnitude, GPSIF0 = sign ADC Offset Control (approx 4mV/step): D14 = LSB, D12 = MSB, D11 = sign. Double Charge-Pump Current: 0 = 100A, 1 = 200A. Digital Test Bus Mode Select. See Table 9 for test-mode descriptions. VCO Coarse Tuning Range. 000 = Lowest frequency, 111 = Highest frequency. AGC Gain. Digital control of the AGC amplifier in the 2nd IF section. 00000 => min gain, 11111 => max gain (linear gain ~2.5dB per unit SPI word).
Table 6. Detailed Register Definition for Write Address 0110: CONFIG 2
DATA BIT D15 D14 D13 D12-D7 D6 to D5 D4-D0 DEFAULT 1 1 1 100000 11 11111 DESCRIPTION Reset CMOS: 0 = Hold CMOS dividers in reset and PFD is tri-stated, 1 = Inactive. Drive VCO Low: 0 = Active, forces VCO to lowest frequency. N.B. do not activate both D14 and D13 at the same time. Drive VCO High: 0 = Active, forces VCO to highest frequency. N.B. do not activate both D14 and D13 at the same time. Reserved Must be programmed to 11 Analog Test Mode Select: Reserved
8
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Integrated L1-Band GPS Receiver MAX2741
Table 7. Detailed Register Definition for Read Address 0111: STATUS
DATA BIT D15-D10 D9 D8 D7 D6 D5 D4 D3-D0 DEFAULT XXXXXX X X 1 X X X XXXX Reserved Out-of-Lock (High Frequency): 1 = PLL is out of lock, VCO free-running at its highest frequency, 0 = Locked. Out-of-Lock (Low Frequency): 1 = PLL is out of lock, VCO free-running at its lowest frequency, 0 = Locked high. XTAL Clock Selected: 1 = Synthesized 16.8MHz reference, 0 = External clock. Parity: 1 = Even, 0 = Odd. Reserved LPF Autotune End: 0 = Autotune run ended; 1 = Calibrating or manual tuning. LPF Autotune: 0000 ~ 7.7MHz; 1111 = 2.9MHz. DESCRIPTION
Applications Information
Fundamentally, the only application areas that require careful consideration are the LNA input match and the 1st IF filter. Of course, proper supply bypassing, grounding, and layout is required for reliable performance from any RF circuit.
Table 8. MAX2741 S11
FREQ (MHz) 1100 1200 1300 1400 1500 1550 1560 1570 1575 1580 1590 1600 1650 1700 1800 1900 2000 S11 (MAG) 0.874 0.867 0.859 0.842 0.821 0.809 0.806 0.804 0.803 0.801 0.799 0.796 0.783 0.768 0.739 0.708 0.677 S11 () -50.9 -56.1 -61.5 -66.9 -72.3 -74.9 -75.4 -75.9 -76.2 -76.4 -77.0 -77.5 -80.0 -82.5 -87.4 -92.3 -96.8
LNA Input Matching
Input matching is critical for optimum noise figure and system sensitivity. Optimum source impedance (as seen from the LNA input) for lowest noise figure is 29 + j47. Remember that optimum noise match and optimum gain match (return loss) do not occur simultaneously, so a good application circuit will sacrifice gain slightly in favor of reduced noise figure. Gain and noise circles are provided in Figure 3; S11 tabular data is provided in Table 8.
G = Gmax - 1dB NF = NFmin + 0.2dB
1st IF Interface and Filtering
The typical application uses a 37.38MHz 1st IF, and employs an IF filter. The order of the filter should be tailored to suit the application--stand-alone GPS receivers will not require the channel-selection and stopband attenuation of GPS receivers that are integrated into other wireless handsets. Be sure that the filter topology provides DC-blocking for the IF I/O ports.
Figure 3. Gain and Noise Circles for MAX2741 LNA Input _______________________________________________________________________________________ 9
Integrated L1-Band GPS Receiver MAX2741
Typical Interface Diagram
IFOUT+ IFOUTIFIN+ VCC6 IFINN.C.
28
VCC1 N.C. RFIN VCC2 VCC3 VCC4 GND
27
26
25
24
23
N.C.
22
SDO N.C. VCC5 GPSIF0 GPSIF1 GPSIF2 GPSCLK BASEBAND IC SDO SD1 CS SCLK GPSIF0 GPSIF1 GPSIF2 GPSCLK REFCLK
1 2 3 4 5 6 7
21 20 19
MAX2741
18 17 16 15
8
FILT SCLK
9
10
CS
11
SDI
12
SHDN
13
XTAL
14
REFCLK
Interface Summary
All I/O connections are DC-coupled. Supply voltages as specified in the electrical specifications.
RF I/O CONNECTION RFIN I/O CONNECTION IFOUT+ IFOUTIFIN+ IFINI/O CONNECTION SCLK CS SDI SDO SHDN GPSCLK GPSIF0 GPSIF1 GPSIF2 I/O CONNECTION FILT XTAL REFCLK CMOS Input CMOS Input CMOS Input CMOS Output CMOS Input CMOS Output CMOS Output CMOS Output CMOS Output SYNTHESIZER RECEIVER PLL Phase-Detector Charge-Pump Crystal Oscillator Feedback External TCXO or Crystal EXTERNAL COMPONENTS PLL Loop Filter Feedback Capacitors Analog (also connected to REFCLK input to MAC) LNA Input IF RECEIVER 1st IF Output from Mixer (+) 1st IF Output from Mixer (-) 1st IF Input (+) 1st IF Input (-) BASEBAND RECEIVER CMOS Output CMOS Output CMOS Output CMOS Input CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input BB IC/MAC IF FILTER IF BPF Input, 2.5k Differential IF BPF Input, 2.5k Differential IF BPF Input, 2.5k Differential IF BPF Input, 2.5k Differential RECEIVER RF BPF Output RF BPF
10
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Integrated L1-Band GPS Receiver MAX2741
Typical Application Circuit
VCC 680pF 5.6pF 680pF
39pF
470H
470H
39pF
100pF
22pF
680pF
5.6pF
680pF
IFOUT+
IFOUT-
IFIN+
VCC6
IFIN-
N.C.
28
27
26
25
24
23
VCC 100pF 22pF
VCC1
1
33.6MHz
N.C.
22
MAX2741
21
SDO
SPI DATA OUT TO BASEBAND PROCESSOR
N.C. 100pF GPS RF INPUT FROM GPS BPF VCC 100pF VCC 1nF VCC 100nF 100pF GND 100pF VCC4 22pF VCC3 2.2pF VCC2 6.2nH
2 LNA 1612.8MHz 4 90 /2 0 /96 /16128 P.D. 5 200kHz
VCO 3225.6MHz
20
N.C.
RFIN
3
19
VCC5 100pF 1nF
VCC
ADC
18
GPSIF0
/R /192 16.8MHz MUX
17
GPSIF1 GPS DATA AND CLOCK TO BASEBAND PROCESSOR
6
16
GPSIF2
7
SPI INTERFACE
REF OSC 11 12
SHDN
15
GPSCLK
8
FILT SCLK
9
10
CS
13
XTAL
14
REFCLK 220pF
22nF 100pF 36k
SPI CLOCK AND DATA INTO BASEBAND PROCESSOR H/W SHUTDOWN LINE FROM BASEBAND PROCESSOR
SDI
SYSTEM TCXO (2MHz TO 26MHz)
Table 9. Digital Test-Mode-Select Description
MODE 3 2 1 0 REGISTER SETTING CONFIG1:D9 to D8 11 10 01 00 DIGITAL OUTPUT FUNCTION GPSIF2 SIGN M COUNTER CHARGE PUMP UP CML CLOCK GPSIF1 LSB R COUNTER CHARGE PUMP DOWN CALIBRATE LPF END GPSIF0 MSB HANDSHAKE STATUS SDO XTL CLOCK SELECTED
Digital Test Bus
The digital test bus (DTB) is provided to allow for easy bench analysis of the digital workings of the receiver.
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11
Integrated L1-Band GPS Receiver MAX2741
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
XXXXX
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
1
2
COMMON DIMENSIONS PKG. 20L 5x5 28L 5x5 32L 5x5 16L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 -
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** **
NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
** SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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