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| IC66LV10016AL Document Title 16M-BIT (1M-WORD BY 16-BIT) Low Power Pseudo SRAM Revision History Revision No 0A History Initial Draft Draft Date February 05,2004 Remark Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 1 IC66LV10016AL 16M-BIT (1M-WORD BY 16-BIT) Low-Power Pseudo SRAM FEATURES * Organization : 1M x 16 * Power Supply Voltage : 2.7~3.3V * Three state output and TTL Compatible DESCRIPTION The IC66LV10016AL is a family of low voltage, low power 16Mbit static RAM organized as 1M-words by 16-bit, designed with Pseudo SRAM technology, fabricated with CMOS process technology. The IC66LV10016AL is designed specifically for low-power applications such as mobile cellular phones, personal digital assistants and other battery-operated products. The operation modes are determined by a combination of the device control inputs CE , ZZ, LB , UB , WE and OE . Each mode is summarized in the function table. A write operation is executed whenever the low level WE overlaps with the low level LB and/or UB and the low level CE and the high level ZZ. The address (A0~A19) must be set up before the write cycle and must be stable during entire cycle. A read operation is executed by setting WE at a high level and OE at a low level while LB and/or UB and CE are in an active state, ZZ is in a inactive state. When setting LB at the high level and other controls are in an active stage, upper-byte is selected for read and write operations, and lower-byte is not selected. When setting UB at a high level and other pins are in an active stage, lower-byte is selected and upper-byte is not. When setting LB and UB at a high level or CE and ZZ at a high level or ZZ at a low level, the chip is in a non-select mode. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips. When OE is at a high level, the output stage is in a highimpedance state. * Package Type : 48-FBGA-6.00x8.00 mm2 * Address Acess Time : 70ns PART NAME TABLE & KEY SPEC SUMMARY Product Family Operating Operating Voltage Speed Temperature (VCC/VCCQ) 2.7-3.3V 70ns Deep powe down Standby Operating PKG Type (IZZ,Max) (ISB2,Max) (Icc2,Max) 25A 70A 20mA 48-TFBGA IC66LV10016AL-70B Extended (-25-85C) ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit VCC VSS Row Addresses Row select Memory array I/O1~I/O8 Data Cont I/O Circuit Column select I/O9~I/O16 Data Cont Data Cont Column Addresses CE OE WE UB LB ZZ Control Logic Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 3 IC66LV10016AL PIN CONFIGURATIONS (TOP VIEW) 2 34 5 OE UB A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O2 I/O4 I/O5 I/O6 WE A11 Pin 6 ZZ I/O1 I/O3 VCC VSS I/O7 I/O8 NC Function Address input Data input / output Low power modes Chip select input Write enable input Output enable input Upper Byte (I/O9 ~ 16) Lower Byte (I/O1 ~ 8) Power supply Ground supply No connection 1 A B C D E F G H LB I/O9 A0~A19 I/O1 ~ I/O16 ZZ CE WE OE UB LB VCC VSS NC I/O10 I/O11 VSS I/O12 VCC I/O13 I/O15 I/O14 I/O16 A19 A8 A18 48-TFBGA FUNCTION TABLE CE H X(1) L L L L L L L L ZZ H L H H H H H H H H OE X (1) WE X (1) LB X (1) UB X (1) I/O1-8 High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9-16 High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Output disabled Output disabled Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write Power Standby Deep Power Down Mode Active Active Active Active Active Active Active Active X(1) H X (1) X(1) H H H H H L L L X(1) X(1) H L H L L H L X(1) X(1) H H L L H L L L L L H H H Notes: 1. X means don't-care.(Must be low or hight state) 4 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL ABSOLUTE MAXIMUM RATINGS Symbol VIN,VOUT Vcc PD TSTG Toper Parameter Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage Temperature Operating Temperature Ratings -0.2 to Vcc+0.3 -0.2 to 3.6 1.0 -65 to 150 -25 to 85 Unit V V W C C Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS Symbol VCC VIH VIL ILI ILO VOL VOH Parameter (1) Conditions Min 2.7 Vcc-0.3 -0.3(3) -1 -1 Max 3.3 Vcc+0.3(2) 0.3 1 1 0.3 Units V V V A A V V Supply Voltage Input High Voltage Input Low Voltage Input Leakage current VIN=Vss to Vcc Output Leakage current VOUT=Vss to Vcc Output Disable Output low Voltage Output high Voltage IOL=0.5mA IOH=-0.5mA Vcc-0.3 Notes: 1. Toper=-25 to 85C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width 20ns 3. Undershoot : -1.0V in case of pulse width 20ns 4. Overshoot and undershoot are sampled, not 100% tested. POWER CONSUMPTION CHARACTERISTICS Symbol ICC1 Parameter Vcc operating supply current Vcc Dynamic operation supply current TTL Standby Current ( TTL inputs ) CMOS Standby Current ( CMOS inputs ) Deep power down mode Conditions Cycle time=1s,100% duty IOUT=0mA,CE0.2V,ZZ=VIH, VIN0.2V or VINVcc-0.2V Cycle time=tRCmin,100% duty IOUT=0mA,CE=VIL,ZZ=VIH, VIN=VIL or VIH CE=VIH,ZZ=VIH, Other inputs=VIL or VIH CEVcc-0.2V,ZZVcc-0.2V, VIN0.2V or VINVcc-0.2V ZZ0.2V, VIN0.2V or VINVcc-0.2V Min -- Max 3 Units mA ICC2 -- 20 mA ISB1 ISB2 IZZ -- -- -- 0.3 70 25 mA A A CAPACITANCE Symbol CIN CIO Parameter Input Capacitance Output Capacitance Test Condition VIN=0V VIO=0V Min Max 8 10 Notes pF pF 5 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Parameter Input pulse level Input rise and fall time Input and output reference voltage Output loads AC CHARATERISTICS READ CYCLE Symbol tRC tAA tOHA tACE tDOE tBA tASO tASC tAHC tLZCE tLZB tLZOE tHZCE tHZB tHZOE WRITE CYCLE Symbol tWC tSCE tSA tAW tASC tAHC tPWE tPWB tHA tSD tHD Parameter Min Write Cycle Time CE to Write End Address Setup Time Address Setup Time to Write End Address set up to CE Low Address hold time from OE High WE Pulse Width LB, UB to End of Write Address Hold from Write End Data Setup to Write End Data Hold from Write End 70 60 0 60 0 0 40 60 0 30 0 -70 Max 32K -- -- -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns Parameter Min Read Cycle Time Address Access time Output Hold Time CE Access Time OE Access Time UB, LB Access Time Address set up to OE Low Address set up to CE Low Address hold time from OE High CE to Low-Z Output UB, LB to Low-Z Output OE to Low-Z Output CE to High- Z Output UB, LB to High- Z Output OE to High-Z Output 70 -- 5 -- -- -- -5 0 0 0 0 0 -- -- -- -70 Max 32K 70 -- 70 40 25 -- -- -- -- -- -- 15 15 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Value 0.3 to Vcc-0.3V 5ns 0.5VCC CL=50pF+1TTL 50pF 1 TTL tCP CE High Pulse width 30 -- ns 6 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL Power Down Cycle( Ta = -25~85 oC) Symbol tSSP tSHP TC2LP tHPD Parameter CE High set up time for Power Down entry CE High hold time before Power Down exit ZZ Low pulse width CE High hold time after Power Down exit Min 0 0 30 300 Max -- -- -- -- Units ns ns ns s Power Up Timing Requirement( Ta = -25~85 oC) Symbol tSHU tHPU Parameter CE ZZ set up time after Power Up Standby hold time after Power Up Min 0 300 Max -- -- Units ns s Data Retention Timing Requirement( Ta = -25~85 oC) Symbol tBAH tCSH Parameter A2 to A19 hold time during active CE hold time for A2 to A19 fix Min 0 300 Max -- -- Units ns s Address Skew Timing Requirement( Ta = -25~85 oC) Symbol tSKEW Parameter Maximum address skew Min -- Max 10 Units ns Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 7 IC66LV10016AL Standby Mode State machines Power on CE=VIH Wait 200s Initial State CE=VIL , ZZ=VIH Active Mode CE=VIL ZZ=VIH CE=VIH ZZ=VIH ZZ=VIL Standby Mode ZZ=VIH DPD Mode CE=VIH ZZ=VIL CE=VIL ZZ=VIH Standby Mode Characteristics Mode Standby DPD Mode Memory Cell Data Valid Invalid Standby Current(A) 70 25(IZZ) Wait Time(S) 0 300 8 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL READ CYCLE tRC Address tAA tACE tOHA CE tASC tBA tAHC tHZCE UB,LB tASO tDOE tHZB OE tLZOE tLZB tLZCE tHZOE Data Out ZZ and WE must be H level for entire read cycle WRITE CYCLE (WE Control) tWC Address tAW tSCE CE tPWB UB,LB tHA tSA tPWE WE tSD tHD Data In ZZ and OE must be H level for entire read cycle Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 9 IC66LV10016AL WRITE CYCLE (LB UB Control) tWC Address tAW tSCE tAHC CE tASC tSA tPWB tHA UB,LB tPWE WE tSD tHD Data In ZZ and OE must be H level for entire read cycle STANDBY Address tCP CE tAHC tASC Active Standby Active 10 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL Power Down Mode Entry / Exit CE tSHP tC2LP tHPD ZZ tSSP Power Up CE tSHU tHPU ZZ VCC VCC(min) Data Retention(1) tBAH Address (A19-A2) CE This applies for both read and write Data Retention(2) tCSH Address (A19-A2) No Change CE This applies for both read and write Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 11 IC66LV10016AL Address Skew(1) A0-A19 tRC / tWC tSKEN CE tSKEN is from first address change to last address change Address Skew(2) A0-A19 tRC / tWC tSKEN CE tSKEN is from first address change to last address change Address Skew(2) A0-A19 tSKEN CE tSKEN is from first address change to last address change 12 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL ORDERING INFORMATION Temperature Range: -25C to +85C Order Part No. IC66LV10016AL-70B Speed (ns) 70 Package 6*8mm TFBGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 13 |
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