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| Features * PowerPC(R) Single Issue Integer Core * Precise Exception Model * Extensive System Development Support - On-chip Watchpoints and Breakpoints - Program Flow Tracking - On-chip Emulation (Once) Development Interface High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power) Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O) MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with Book 1 of the PowerPC Architecture Definition) with 32 x 32-bit Fixed Point Registers - Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch, without Conditional Execution - 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU - Instruction and Data Caches are Two-way, Set Associative, Physical Address, 4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line Granularity - MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs - MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB; 16 Virtual Address Spaces and 8 Protection Groups - Advanced On-chip Emulation Debug Mode Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit) 32 Address Lines Fully Static Design VCC = +3.3V 5% fmax = 66 MHz (80 MHz (TBC)) Military Temperature Range: -55C < TC < +125C PD = 0.75 W Typical at 66 MHz * * * * 32-bit Quad Integrated Power QUICCTM Communication Controller TSPC860 * * * * * * * Description The TSPC860 PowerPC QUad Integrated Communication Controller (Power QUICCTM) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications and networking systems. The Power QUICC (pronounced "quick") can be described as a PowerPC-based derivative of the TS68EN360 (QUICCTM). The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and data caches. The communications processor module (CPM) of the TS68EN360 QUICC has been enhanced with the addition of a Two-wire Interface (TWI) compatible with protocols such as I2C. Moderate to high digital signal processing (DSP) functionality has been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories (DRAMs). Overall system functionality is completed with the addition of a PCMCIA socket controller supporting up to two sockets and a real-time clock. PBGA 357 ZP suffix Rev. 2129A-HIREL-08/02 1 Screening/Quality This product will be manufactured in full compliance with: * According to Atmel Standards The TSPC860 is functionally composed of three major blocks: * * * A 32-bit PowerPC Core with MMUs and Caches A System Interface Unit A Communications Processor Module General Description Figure 1. Block Diagram View of the TSPC860 4 or 16 KB I-Cache SYSTEM INTERFACE UNIT Memory Controller Unified Bus Bus Interface Unit Embedded PowerPC Core Instruction Bus I-MMU 4 or 8 KB D-Cache System Functions Real Time Clock PCMCIA Interface Load/store BUS 4 Timers D-MMU Parallel I/O Baud Rate Generators Parallel Interface Port Interrupt Controller Dual-Port RAM 16 Serial DMA and Virtual IDMA 32-bit RISC Controller and Program ROM MAC Timer SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI TWI Time Slot Assigner Serial Interface 2 TSPC860 2129A-HIREL-08/02 TSPC860 Main Features The Following is a List of the TSPC860's Important Features: * * * * * * * * Fully Static Design Four Major Power Saving Modes 357 OMPAC Ball Grid Array Packaging (Plastic) 32-bit Address and Data Busses Flexible Memory Management 4-Kbyte Physical Address, Two-way, Set-associative Data Cache 4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache Eight-bank Memory Controller - - - * - - - - - - - - * - - - - - - Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals Byte Write Enables and Selectable Parity Generation 32-bit Address Decodes With Bit Masks Clock Synthesizer Power Management Reset Controller PowerPC Decrementer And Time Base Real-time Clock Register Periodic Interrupt Timer Hardware Bus Monitor and Software Watchdog Timer IEEE 1149.1 JTAG Test Access Port Embedded 32-bit RISC Controller Architecture for Flexible I/O Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual DMA Channel Controller Continuous Mode Transmission And Reception On All Serial Channels Serial DMA Channels For Reception And Transmission On All Serial Channels I/O registers with Open-drain and Interrupt Capability Memory-memory and Memory-I/O Transfers with Virtual DMA Functionality System Interface Unit Communications Processor Module 3 2129A-HIREL-08/02 - Protocols Supported by ROM or Downloadable Microcode and Include, but Limited to, the Digital Portion of: - Ethernet/IEEE 802.3 CS/CDMA - HDLC2/SDLC and HDLC bus - Apple Talk - Signaling System #7 (RAM Microcode Only) - Universal Asynchronous Receiver Transmitter (UART) - Synchronous UART - Binary Synchronous (BiSync) Communications - Totally Transparent - Totally Transparent with CRC - Profibus (RAM Microcode Option) - Asynchronous HDLC - DDCMP - V.14 (RAM Microcode Option) - X.21 (RAM Microcode Option) - V.32bis Datapump Filters - IrDA Serial Infrared - Basis Rate ISDN (BRI) in Conjunction with SMC Channels - Primary Rate ISDN (MH Version Only) Four Hardware Serial Communications Controller Channels Supporting the Protocols Two Hardware Serial Management Channels - Management for BRI Devices as General Circuit Interface Controller Multiplexed Channels - Low-speed UART operation Hardware Serial Peripheral Interfaces Two-wire Interface (TWI) Time-slot Assigner Port Supports Centronics Interfaces and Chip-to-chip Four Independent Baud Rate Generators and Four Input Clock Pins for Supplying Clocks to SMC and SCC Serial Channels Four Independent 16-bit timers Which Can Be Interconnected as Two 32-bit Timers - - - - - - - - 4 TSPC860 2129A-HIREL-08/02 TSPC860 Pin Assignment Plastic Ball Grid Array Figure 2. Pin Assignment: Top View W PD10 PD8 PD3 IRQ7 D0 D4 D1 D2 D3 D5 VDDL D6 D7 D29 DP2 CLKOUT IPA3 V PD14 PD13 PD9 PD6 M_Tx_EN IRQ0 D13 D27 D10 D14 D18 D20 D24 D28 DP1 DP3 DP0 N/C VSSSYN1 U PA0 PA1 PB14 PD15 PC5 PC4 PD4 PD11 PD5 PD7 IRQ1 D8 D23 D17 D11 D9 D16 D15 D19 D22 D21 D25 D26 D31 D30 IPA6 IPA5 IPA0 IPA4 IPA1 IPA2 IPA7 N/C VSSSYN T VDDH D12 VDDH XFC VDDSYN PC6 PA2 PB15 PD12 R VDDH WAIT_B WAIT_A PORESET KAPWR P PA4 PB17 PA3 VDDL GND GND VDDL RSTCONF SRESET XTAL N HRESET TEXP EXTCLK EXTAL M PB19 PA5 PB18 PB16 PA7 PC8 PA6 PC7 MODCK2 BADDR28 BADDR29 VDDL L PB22 PC9 PA8 PB20 OP0 AS OP1 MODCK1 K PC10 PA9 PB23 PB21 GND BADDR30 IPB6 ALEA IRQ4 J PC11 PB24 PA10 PB25 IPB5 IPB1 IPB2 ALEB H VDDL M_MDIO TDI TCK M_COL IRQ2 IPB0 IPB7 G TRST TMS TDO PA11 GND VDDH GND VDDH BR IRQ6 IPB4 IPB3 F PB26 PC12 PA12 VDDL VDDL TS IRQ3 BURST E PB27 PC13 PA13 PB29 CS3 BI BG BB D PB28 PC14 PA14 PC15 A8 N/C N/C A15 A19 A25 A18 BSA0 GPLA0 N/C CS6 CS2 GPLA5 BDIP TEA C PB30 PA15 PB31 A3 A9 A12 A16 A20 A24 A26 TSIZ1 BSA1 WE0 GPLA1 GPLA3 CS7 CS0 TA GPLA4 B A0 A1 A4 A6 A10 A13 A17 A21 A23 A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 CE1A WR GPLB4 A A2 19 18 A5 17 A7 16 A11 15 A14 14 A27 13 A29 12 A30 11 A28 10 A31 9 VDDL BSA2 8 7 WE1 6 WE3 5 CS4 4 CE2A 3 CS1 2 1 Signal Descriptions This section describes the signals on the TSPC860. 5 2129A-HIREL-08/02 Figure 3. TSPC860 External Signals 6 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 4. TSPC860 Signals and Pin Numbers (Part 1) 7 2129A-HIREL-08/02 Figure 5. TSPC860 Signals and Pin Numbers (Part 2) 8 TSPC860 2129A-HIREL-08/02 TSPC860 System Bus Signals The TSPC860 system bus consists of all signals that interface with the external bus. Many of these signals perform different functions, depending on how the user assigns them. The following input and output signals are identified by their abbreviation. Each signal's pin number can be found in Figure 4 and Figure 5. Table 1. Signal Descriptions Name A(0-31) Reset Hi-Z Number See Figure 2 Type Bidirectional Three-state Description Address Bus -- Provides the address for the current bus cycle. A0 is the most-significant signal. The bus is output when an internal master starts a transaction on the external bus. The bus is input when an external master starts a transaction on the bus. Transfer Size 0 -- When accessing a slave in the external bus, used (together with TSIZ1) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. TSIZ0 is an input when an external master starts a bus transaction. Register -- When an internal master initiates an access to a slave controlled by the PCMCIA interface, REG is output to indicate which space in the PCMCIA card is accessed. Transfer Size 1 -- Used (with TSIZ0) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. The TSPC860 drives TSIZ1 when it is bus master. TSIZ1 is input when an external master starts a bus transaction. Read/Write -- Driven by the bus master to indicate the direction of the bus's data transfer. A logic one indicates a read from a slave device and a logic zero indicates a write to a slave device. The TSPC860 drives this signal when it is bus master. Input when an external master initiates a transaction on the bus. Burst Transaction -- Driven by the bus master to indicate that the current initiated transfer is a burst. The TSPC860 drives this signal when it is bus master. This signal is input when an external master initiates a transaction on the bus. Burst Data in Progress -- When accessing a slave device in the external bus, the master on the bus asserts this signal to indicate that the data beat in front of the current one is the one requested by the master. BDIP is negated before the expected last data beat of the burst transfer. General-Purpose Line B5-Used by the memory controller when UPMB takes control of the slave access. Transfer Start -- Asserted by the bus master to indicate the start of a bus cycle that transfers data to or from a slave device. Driven by the master only when it has gained the ownership of the bus. Every master should negate this signal before the bus relinquish. TS requires the use of an external pull-up resistor. The TSPC860 samples TS when it is not the external bus master to allow the memory controller/PCMCIA interface to control the accessed slave device. It indicates that an external synchronous master initiated a transaction. TSIZ0 REG Hi-Z B9 Bidirectional Three-state TSIZ1 Hi-Z C9 Bidirectional Three-state RD/WR Hi-Z B2 Bidirectional Three-state BURST Hi-Z F1 Bidirectional Three-state BDIP GPL_B5 See Section "Signal States During Hardware Reset" on page 28 Hi-Z D2 Bidirectional Three-state TS F3 Bidirectional Active Pull-up 9 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name TA Reset Hi-Z Number C2 Type Bidirectional Active Pull-up Description Transfer Acknowledge -- Indicates that the slave device addressed in the current transaction accepted data sent by the master (write) or has driven the data bus with valid data (read). This is an output when the PCMCIA interface or memory controller controls the transaction. The only exception occurs when the memory controller controls the slave access by means of the GPCM and the corresponding option register is instructed to wait for an external assertion of TA. Every slave device should negate TA after a transaction ends and immediately three-state it to avoid bus contention if a new transfer is initiated addressing other slave devices. TA requires the use of an external pull-up resistor. Transfer Error Acknowledge -- Indicates that a bus error occurred in the current transaction. The TSPC860 asserts TEA when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. Asserting TEA terminates the bus cycle, thus ignoring the state of TA. TEA requires the use of an external pull-up resistor. Burst Inhibit -- Indicates that the slave device addressed in the current burst transaction cannot support burst transfers. It acts as an output when the PCMCIA interface or the memory controller takes control of the transaction. BI requires the use of an external pull-up resistor. Reservation -- The TSPC860 outputs this three-state signal in conjunction with the address bus to indicate that the core initiated a transfer as a result of a stwcx. or lwarx. Interrupt Request 2 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Kill Reservation -- This input is used as a part of the memory reservation protocol, when the TSPC860 initiated a transaction as the result of a stwcx. instruction. Retry -- This input is used by a slave device to indicate it cannot accept the transaction. The TSPC860 must relinquish mastership and reinitiate the transaction after winning in the bus arbitration. Interrupt Request 4 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal that is sent to the interrupt controller is the logical AND of this line (if defined as IRQ4) and DP1/IRQ4 (if defined as IRQ4). SPKROUT -- Digital audio wave form output to be driven to the system speaker. Cancel Reservation -- This input is used as a part of the storage reservation protocol. Interrupt Request 3 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of CR/IRQ3 (if defined as IRQ3) and DP0/IRQ3 if defined as IRQ3. TEA Hi-Z D1 Open-drain BI Hi-Z E3 Bidirectional Active Pull-up RSV IRQ2 See Section "Signal States During Hardware Reset" on page 28 See Section "Signal States During Hardware Reset" on page 28 H3 Bidirectional Three-state KR/RETRY IRQ4 SPKROUT K1 Bidirectional Three-state CR IRQ3 Hi-Z F2 Input 10 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name D(0-31) Reset Hi-Z (Pulled Low if RSTCONF pulled down) Hi-Z Number See Figure 2 Type Bidirectional Three-state Description Data Bus -- This bidirectional three-state bus provides the generalpurpose data path between the TSPC860 and all other devices. The 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers. D0 is the MSB of the data bus. Data Parity 0 -- Provides parity generation and checking for D(0-7) for transfers to a slave device initiated by the TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves sitting on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 3 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of DP0/IRQ3 (if defined as IRQ3) and CR/IRQ3 (if defined as IRQ3). Data Parity 1 -- Provides parity generation and checking for D(8-15) for transfers to a slave device initiated by the TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 4 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of this line (if defined as IRQ4) and KR/IRQ4/SPKROUT (if defined as IRQ4). Data Parity 2 -- Provides parity generation and checking for D(1623) for transfers to a slave device initiated by the TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 5 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Data Parity 3 -- Provides parity generation and checking for D(2431) for transfers to a slave device initiated by the TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 6 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of this line (if defined as IRQ6) and the FRZ/IRQ6 (if defined as IRQ6). Bus Request -- Asserted low when a possible master is requesting ownership of the bus. When the TSPC860 is configured to work with the internal arbiter, this signal is configured as an input. When the TSPC860 is configured to work with an external arbiter, this signal is configured as an output and asserted every time a new transaction is intended to be initiated (no parking on the bus). DP0 IRQ3 V3 Bidirectional Three-state DP1 IRQ4 Hi-Z V5 Bidirectional Three-state DP2 IRQ5 Hi-Z W4 Bidirectional Three-state DP3 IRQ6 Hi-Z V4 Bidirectional Three-state BR Hi-Z G4 Bidirectional 11 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name BG Reset Hi-Z Number E2 Type Bidirectional Description Bus Grant -- Asserted low when the arbiter of the external bus grants the bus to a specific device. When the TSPC860 is configured to work with the internal arbiter, BG is configured as an output and asserted every time the external master asserts BR and its priority request is higher than any internal sources requiring a bus transfer. However, when the TSPC860 is configured to work with an external arbiter, BG is an input. Bus Busy -- Asserted low by a master to show that it owns the bus. The TSPC860 asserts BB after the arbiter grants it bus ownership and BB is negated. Freeze -- Output asserted to indicate that the core is in debug mode. Interrupt Request 6 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of FRZ/IRQ6 (if defined as IRQ6) and DP3/IRQ6 (if defined as IRQ6). Interrupt Request 0 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Interrupt Request 1 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Interrupt Request 7 -- One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Chip Select -- These outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. CS0 can be configured to be the global chip-select for the boot device. Chip Select 6 -- This output enables a peripheral or memory device at a programmed address if defined appropriately in the BR6 and OR6 in the memory controller. Card Enable 1 Slot B -- This output enables even byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. Chip Select 7 -- This output enables a peripheral or memory device at a programmed address if defined appropriately in the BR7 and OR7 in the memory controller. Card Enable 2 Slot B -- This output enables odd byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. BB Hi-Z E1 Bidirectional Active Pull-up Bidirectional FRZ IRQ6 See Section "Signal States During Hardware Reset" on page 28 Hi-Z G3 IRQ0 V14 Input IRQ1 Hi-Z U14 Input IRQ7 Hi-Z W15 Input CS(0-5) High C3, A2, D4, E4, A4, B4 D5 Output CS6 CE1_B High Output CS7 CE2_B High C4 Output 12 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name WE0 BS_B0 IORD Reset High Number C7 Type Output Description Write Enable 0 -- Output asserted when a write access to an external slave controlled by the GPCM is initiated by the TSPC860. WE0 is asserted if D(0-7) contains valid data to be stored by the slave device. Byte Select 0 on UPMB -- Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, the line is only asserted if D(0-7) contains valid data. IO Device Read -- Output asserted when the TSPC860 starts a read access to a region controlled by the PCMCIA interface. Asserted only for accesses to a PC card I/O space. Write Enable 1 -- Output asserted when the TSPC860 initiates a write access to an external slave controlled by the GPCM. WE1 is asserted if D(8-15) contains valid data to be stored by the slave device. Byte Select 1 on UPMB -- Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, the line is only asserted if D(8-15) contains valid data. I/O Device Write -- This output is asserted when the TSPC860 initiates a write access to a region controlled by the PCMCIA interface. IOWR is asserted only if the access is to a PC card I/O space. Write Enable 2 -- Output asserted when the TSPC860 starts a write access to an external slave controlled by the GPCM. WE2 is asserted if D(16-23) contains valid data to be stored by the slave device. Byte Select 2 on UPMB -- Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, BS_B2 is asserted only D(16-23) contains valid data. PCMCIA Output Enable -- Output asserted when the TSPC860 initiates a read access to a memory region under the control of the PCMCIA interface. Write Enable 3 -- Output asserted when the TSPC860 initiates a write access to an external slave controlled by the GPCM. WE3 is asserted if D(24-31) contains valid data to be stored by the slave device. Byte Select 3 on UPMB -- Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, BS_B3 is asserted only if D(24-31) contains valid data. PCMCIA Write Enable -- Output asserted when the TSPC860 initiates a write access to a memory region under control of the PCMCIA interface. Byte Select 0 to 3 on UPMA -- Outputs asserted under requirement of the UPMB, as programmed by the user. For read or writes, asserted only if their corresponding data lanes contain valid data: BS_A0 for D(0-7), BS_A1 for D(8-15), BS_A2 for D(16-23), BS_A3 for D(24-31) WE1 BS_B1 IOWR High A6 Output WE2 BS_B2 PCOE High B6 Output WE3 BS_B3 PCWE High A5 Output BS_A(0-3) High D8, C8, A7, B8 Output 13 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name GPL_A0 GPL_B0 Reset High Number D7 Type Output Description General-Purpose Line 0 on UPMA -- This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by the UPMA. General-Purpose Line 0 on UPMB -- This output reflects the value specified in the UPMB when an external transfer to a slave is controlled by the UPMB. Output Enable -- Output asserted when the TSPC860 initiates a read access to an external slave controlled by the GPCM. General-Purpose Line 1 on UPMA -- This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. General-Purpose Line 1 on UPMB -- This output reflects the value specified in the UPMB when an external transfer to a slave is controlled by UPMB. General-Purpose Line 2 and 3 on UPMA -- These outputs reflect the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. General-Purpose Line 2 and 3 on UPMB -- These outputs reflect the value specified in the UPMB when an external transfer to a slave is controlled by UPMB. Chip Select 2 and 3 -- These outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. The double drive capability for CS2 and CS3 is independently defined for each signal in the SIUMCR. User Programmable Machine Wait A -- This input is sampled as defined by the user when an access to an external slave is controlled by the UPMA. General-Purpose Line 4 on UPMA -- This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. User Programmable Machine Wait B -- This input is sampled as defined by the user when an access to an external slave is controlled by the UPMB. General-Purpose Line 4 on UPMB -- This output reflects the value specified in the UPMB when an external transfer to a slave is controlled by UPMB. General-Purpose Line 5 on UPMA -- This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. This signal can also be controlled by the UPMB. Power on Reset -- When asserted, this input causes the TSPC860 to enter the power-on reset state. Reset Configuration -- The TSPC860 samples this input while HRESET is asserted. If RSTCONF is asserted, the configuration mode is sampled in the form of the hard reset configuration word driven on the data bus. When RSTCONF is negated, the TSPC860 uses the default configuration mode. Note that the initial base address of internal registers is determined in this sequence. Hard Reset -- Asserting this open drain signal puts the TSPC860 in hard reset state. OE GPL_A1 GPL_B1 High C6 Output GPL_A(2-3) GPL_B(2-3) CS(2-3) High B5, C5 Output UPWAITA GPL_A4 Hi-Z C1 Bidirectional UPWAITB GPL_B4 Hi-Z B1 Bidirectional GPL_A5 High D3 Output PORESET RSTCONF Hi-Z Hi-Z R2 P3 Input Input HRESET Low N4 Open-drain 14 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name SRESET XTAL EXTAL XFC CLKOUT Reset Low Analog Driving Hi-Z Analog Driving High until SPLL locked, then oscillating Hi-Z High Low Number P2 P1 N1 T2 W3 Type Open-drain Analog Output Analog Input (3.3V only) Analog Input Output Description Soft Reset -- Asserting this open drain line puts the TSPC860 in soft reset state. This output is one of the connections to an external crystal for the internal oscillator circuitry. This line is one of the connections to an external crystal for the internal oscillator circuitry. External Filter Capacitance -- This input is the connection pin for an external capacitor filter for the PLL circuitry. Clock Out -- This output is the clock system frequency. EXTCLK TEXP ALE_A N2 N3 K2 Input (3.3V only) Output Output External Clock -- This input is the external input clock from an external source. Timer Expired -- This output reflects the status of PLPRCR[TEXPS]. Address Latch Enable A -- This output is asserted when TSPC860 initiates an access to a region under the control of the PCMCIA interface to socket A. Card Enable 1 Slot A -- This output enables even byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface. Card Enable 2 Slot A -- This output enables odd byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface. Wait Slot A -- This input, if asserted low, causes a delay in the completion of a transaction on the PCMCIA controlled Slot A. Wait Slot B -- This input, if asserted low, causes a delay in the completion of a transaction on the PCMCIA controlled Slot B. Input Port A 0-1 -- The TSPC860 monitors these inputs that are reflected in the PIPR and PSCR of the PCMCIA interface. Input Port A 2 -- The TSPC860 monitors these inputs; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. I/O Device A is 16-Bits Ports Size -- The TSPC860 monitors this input when a transaction under the control of the PCMCIA interface is initiated to an I/O region in socket A of the PCMCIA space. Input Port A 3-7 -- The TSPC860 monitors these inputs; their values and changes are reported in the PIPR and PSCR of the PCMCIA interface. CE1_A High B3 Output CE2_A High A3 Output WAIT_A WAIT_B IP_A(0-1) IP_A2 IOIS16_A Hi-Z Hi-Z Hi-Z Hi-Z R3 R4 T5, T4 U3 Input Input Input Input IP_A(3-7) Hi-Z W2, U4, U5, T6, T3 Input 15 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name ALE_B DSCK/AT1 Reset See Section "Signal States During Hardware Reset" on page 28 Number J1 Type Bidirectional Three-state Description Address Latch Enable B -- This output is asserted when the TSPC860 initiates an access to a region under the control of the PCMCIA socket B interface. Development Serial Clock -- This input is the clock for the debug port interface. Address Type 1 -- The TSPC860 drives this bidirectional three-state line when it initiates a transaction on the external bus. When the transaction is initiated by the core, it indicates if the transfer is for user or supervisor state. This signal is not used for transactions initiated by external masters. Input Port B 0-1 -- The TSPC860 senses these inputs; their values and changes are reported in the PIPR and PSCR of the PCMCIA interface. Instruction Watchpoint 0-1 -- These outputs report the detection of an instruction watchpoint in the program flow executed by the core. Visible History Buffer Flushes Status -- The TSPC860 outputs VFLS(0-1) when program instruction flow tracking is required. They report the number of instructions flushed from the history buffer in the core. Input Port B 2 -- The TSPC860 senses this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. I/O Device B is 16- Bits Port Size -- The TSPC860 monitors this input when a PCMCIA interface transaction is initiated to an I/O region in socket B in the PCMCIA space. Address Type 2 -- The TSPC860 drives this bidirectional three-state signal when it initiates a transaction on the external bus. If the core initiates the transaction, it indicates if the transfer is instruction or data. This signal is not used for transactions initiated by external masters. Input Port B 3 -- The TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Instruction Watchpoint 2 -- This output reports the detection of an instruction watchpoint in the program flow executed by the core. Visible Instruction Queue Flush Status -- The TSPC860 outputs VF2 with VF0/VF1 when instruction flow tracking is required. VFn reports the number of instructions flushed from the instruction queue in the core. Input Port B 4 -- The TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Load/Store Watchpoint 0 -- This output reports the detection of a data watchpoint in the program flow executed by the core. Visible Instruction Queue Flushes Status -- The TSPC860 outputs VF0 with VF1/VF2 when instruction flow tracking is required. VFn reports the number of instructions flushed from the instruction queue in the core. IP_B(0-1) IWP(0-1) VFLS(0-1) See Section "Signal States During Hardware Reset" on page 28 H2, J3 Bidirectional IP_B2 IOIS16_B AT2 Hi-Z J2 Bidirectional Three-state IP_B3 IWP2 VF2 See Section "Signal States During Hardware Reset" on page 28 G1 Bidirectional IP_B4 LWP0 VF0 Hi-Z G2 Bidirectional 16 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name IP_B5 LWP1 VF1 Reset Hi-Z Number J4 Type Bidirectional Description Input Port B 5 -- The TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Load/Store Watchpoint 1 -- This output reports the detection of a data watchpoint in the program flow executed by the core. Visible Instruction Queue Flushes Status -- The TSPC860 outputs VF1 with VF0 and VF2 when instruction flow tracking is required. VFn reports the number of instructions flushed from the instruction queue in the core. Input Port B 6 -- The TSPC860 senses this input and its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Development Serial Data Input -- Data input for the debug port interface. Address Type 0 -- The TSPC860 drives this bidirectional three-state line when it initiates a transaction on the external bus. If high (1), the transaction is the CPM. If low (0), the transaction initiator is the CPU. This signal is not used for transactions initiated by external masters. Input Port B 7 -- The TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Program Trace -- To allow program flow tracking, the TSPC860 asserts this output to indicate an instruction fetch is taking place. Address Type 3 -- The TSPC860 drives the bidirectional three-state signal when it starts a transaction on the external bus. When the core initiates a transfer, AT3 indicates whether it is a reservation for a data transfer or a program trace indication for an instruction fetch. This signal is not used for transactions initiated by external masters. Output Port 0-1 -- The TSPC860 generates these outputs as a result of a write to the PGCRA register in the PCMCIA interface. Output Port 2 -- This output is generated by the TSPC860 as a result of a write to the PGCRB register in the PCMCIA interface. Mode Clock 1 -- Input sampled when PORESET is negated to configure PLL/clock mode. Special Transfer Start -- The TSPC860 drives this output to indicate the start of an external bus transfer or of an internal transaction in show-cycle mode. Output Port 3 -- This output is generated by the TSPC860 as a result of a write to the PGCRB register in the PCMCIA interface. Mode Clock 2 -- This input is sampled at the PORESET negation to configure the PLL/clock mode of operation. Development Serial Data Output -- Output data from the debug port interface. IP_B6 DSDI AT0 Hi-Z K3 Bidirectional Three-state IP_B7 PTR AT3 Hi-Z H1 Bidirectional Three-state OP(0-1) OP2 MODCK1 STS Low Hi-Z L4, L2 L1 Output Bidirectional OP3 MODCK2 DSDO Hi-Z M4 Bidirectional 17 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name BADDR30 REG Reset Hi-Z Number K4 Type Output Description Burst Address 30 -- This output duplicates the value of A30 when the following is true: * An internal master in the TSPC860 initiates a transaction on the external bus. * An asynchronous external master initiates a transaction. * A synchronous external master initiates a single beat transaction. The memory controller uses BADDR30 to increment the address lines that connect to memory devices when a synchronous external master or an internal master initiates a burst transfer. Register -- When an internal master initiates an access to a slave under control of the PCMCIA interface, this signal duplicates the value of TSIZ0/REG. When an external master initiates an access, REG is output by the PCMCIA interface (if it must handle the transfer) to indicate the space in the PCMCIA card being accessed. Burst Address -- Outputs that duplicate A(28-29) values when one of the following occurs: * An internal master in the TSPC860 initiates a transaction on the external bus. * An asynchronous external master initiates a transaction. * A synchronous external master initiates a single beat transaction. The memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer. Address Strobe -- Input driven by an external asynchronous master to indicate a valid address on A(0-31). The TSPC860 memory controller synchronizes AS and controls the memory device addressed under its control. General-Purpose I/O Port A Bit 15 -- Bit 15 of the general-purpose I/O port A. RXD1 -- Receive data input for SCC1. General-Purpose I/O Port A Bit 14 -- Bit 14 of the general-purpose I/O port A. TXD1 -- Transmit data output for SCC1. TXD1 has an open-drain capability. General-Purpose I/O Port A Bit 13 -- Bit 13 of the general-purpose I/O port A. RXD2 -- Receive data input for SCC2. General-Purpose I/O Port A Bit 12 -- Bit 12 of the general-purpose I/O port A. TXD2 -- Transmit data output for SCC2. TXD2 has an open-drain capability. General-Purpose I/O Port A Bit 11 -- Bit 11 of the general-purpose I/O port A. L1TXDB -- Transmit data output for the serial interface TDM port B. L1TXDB has an open-drain capability. General-Purpose I/O Port A Bit 10 -- Bit 10 of the general-purpose I/O port A. L1RXDB -- Receive data input for the serial interface TDM port B. BADDR(2829) Hi-Z M3 M2 Output AS Hi-Z L3 Input PA[15] RXD1 PA[14] TXD1 Hi-Z C18 Bidirectional D17 Bidirectional (Optional: Open-drain) Bidirectional PA[13] RXD2 PA[12] TXD2 E17 F17 Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional PA[11] L1TXDB G16 PA[10] L1RXDB J17 18 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name PA[9] L1TXDA Reset Number K18 Type Bidirectional (Optional: Open-drain) Bidirectional Description General-Purpose I/O Port A Bit 11 -- Bit 9 of the general-purpose I/O port A. L1TXDA -- Transmit data output for the serial interface TDM port A. L1TXDA has an open-drain capability. General-Purpose I/O Port A Bit 8 -- Bit 8 of the general-purpose I/O port A. L1RXDA -- Receive data input for the serial interface TDM port A. General-Purpose I/O Port A Bit 7 -- Bit 7 of the general-purpose I/O port A. CLK1 -- One of eight clock inputs that can be used to clock SCCs and SMCs. TIN1 -- Timer 1 external clock. L1RCLKA -- Receive clock for the serial interface TDM port A. BRGO1 -- Output clock of BRG1. General-Purpose I/O Port A Bit 6 -- Bit 6 of the general-purpose I/O port A. CLK2 -- One of eight clock inputs that can be used to clock SCCs and SMCs. TOUT1 -- Timer 1 output. BRGCLK1 -- One of two external clock inputs of the BRGs. General-Purpose I/O Port A Bit 5 -- Bit 5 of the general-purpose I/O port A. CLK3 -- One of eight clock inputs that can be used to clock SCCs and SMCs. TIN2 -- Timer 2 external clock input. L1TCLKA -- Transmit clock for the serial interface TDM port A. BRGO2 -- Output clock of BRG2. General-Purpose I/O Port A Bit 4 -- Bit 4 of the general-purpose I/O port A. CLK4 -- One of eight clock inputs that can be used to clock SCCs and SMCs. TOUT2 -- Timer 2 output. General-Purpose I/O Port A Bit 3 -- Bit 3 of the general-purpose I/O port A. CLK5 -- One of eight clock inputs that can be used to clock SCCs and SMCs. TIN3 -- Timer 3 external clock input. BRGO3 -- Output clock of BRG3. General-Purpose I/O Port A Bit 2 -- Bit 2 of the general-purpose I/O port A. CLK6 -- One of eight clock inputs that can be used to clock the SCCs and SMCs. TOUT3 -- Timer 3 output. L1RCLKB -- Receive clock for the serial interface TDM port B. BRGCLK2 -- One of the two external clock inputs of the BRGs. PA[8] L1RXDA PA[7] CLK1 TIN1 L1RCLKA BRGO1 L17 M19 Bidirectional PA[6] CLK2 TOUT1 BRGCLK1 M17 Bidirectional PA[5] CLK3 TIN2 L1TCLKA BRGO2 N18 Bidirectional PA[4] CLK4 TOUT2 Hi-Z P19 Bidirectional PA[3] CLK5 TIN3 BRGO3 P17 Bidirectional PA[2] CLK6 TOUT3 L1RCLKB BRGCLK2 R18 Bidirectional 19 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name PA[1] CLK7 TIN4 BRGO4 Reset Number T19 Type Bidirectional Description General-Purpose I/O Port A Bit 1 -- Bit 1 of the general-purpose I/O port A. CLK7 -- One of eight clock inputs that can be used to clock SCCs and SMCs. TIN4 -- Timer 4 external clock input. BRGO4 -- BRG4 output clock. General-Purpose I/O Port A Bit 0 -- Bit 0 of the general-purpose I/O port A. CLK8 -- One of eight clock inputs that can be used to clock SCCs and SMCs. TOUT4 -- Timer 4 output. L1TCLKB -- Transmit clock for the serial interface TDM port B. General-Purpose I/O Port B Bit 31 -- Bit 31 of the general-purpose I/O port B. SPISEL -- SPI slave select input. REJECT1 -- SCC1 CAM interface reject pin. General-Purpose I/O Port B Bit 30 -- Bit 30 of the general-purpose I/O port B. SPICLK -- SPI output clock when it is configured as a master or SPI input clock when it is configured as a slave. RSTRT2 -- SCC2 serial CAM interface output signal that marks the start of a frame. General-Purpose I/O Port B Bit 29 -- Bit 29 of the general-purpose I/O port B. SPIMOSI -- SPI output data when it is configured as a master or SPI input data when it is configured as a slave. General-Purpose I/O Port B Bit 28 -- Bit 29 of the general-purpose I/O port B. SPIMISO -- SPI input data when the TSPC860 is a master; SPI output data when it is a slave. BRGO4 -- BRG4 output clock. General-Purpose I/O Port B Bit 27 -- Bit 27 of the general-purpose I/O port B. I2CSDA -- TWI serial data pin. Bidirectional; should be configured as an open-drain output. BRGO1 -- BRG1 output clock. General-Purpose I/O Port B Bit 26 -- Bit 26 of the general-purpose I/O port B. I2CSCL -- TWI serial clock pin. Bidirectional; should be configured as an open-drain output. BRGO2 -- BRG2 output clock. General-Purpose I/O Port B Bit 25 -- Bit 25 of the general-purpose I/O port B. SMTXD1 -- SMC1 transmit data output. General-Purpose I/O Port B Bit 24 -- Bit 24 of the general-purpose I/O port B. SMRXD1 -- SMC1 receive data input. PA[0] CLK8 TOUT4 L1TCLKB U19 Bidirectional PB[31] SPISEL REJECT1 PB[30] SPICLK RSTRT2 C17 Bidirectional (Optional: Open-drain) C19 Bidirectional (Optional: Open-drain) PB[29] SPIMOSI E16 Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) PB[28] SPIMISO BRGO4 D19 PB[27] I2CSDA BRGO1 Hi-Z E19 Bidirectional (Optional: Open-drain) PB[26] I2CSCL BRGO2 F19 Bidirectional (Optional: Open-drain) PB[25] SMTXD1 PB[24] SMRXD1 J16 Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) J18 20 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name PB[23] SMSYN1 SDACK1 Reset Number K17 Type Bidirectional (Optional: Open-drain) Description General-Purpose I/O Port B Bit 23 -- Bit 23 of the general-purpose I/O port B. SMSYN1 -- SMC1 external sync input. SDACK1 -- SDMA acknowledge 1 output that is used as a peripheral interface signal for IDMA emulation, or as a CAM interface signal for Ethernet. General-Purpose I/O Port B Bit 22 -- Bit 22 of the general-purpose I/O port B. SMSYN2 -- SMC2 external sync input. SDACK2 -- SDMA acknowledge 2 output that is used as a peripheral interface signal for IDMA emulation, or as a CAM interface signal for Ethernet. General-Purpose I/O Port B Bit 21 -- Bit 21 of the general-purpose I/O port B. SMTXD2 -- SMC2 transmit data output. L1CLKOB -- Clock output from the serial interface TDM port B. General-Purpose I/O Port B Bit 20 -- Bit 20 of the general-purpose I/O port B. SMRXD2 -- SMC2 receive data input. L1CLKOA -- Clock output from the serial interface TDM port A. General-Purpose I/O Port B Bit 19 -- Bit 19 of the general-purpose I/O port B. RTS1 -- Request to send modem line for SCC1. L1ST1 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port B Bit 18 -- Bit 18 of the general-purpose I/O port B. RTS2 -- Request to send modem line for SCC2. L1ST2 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port B Bit 17 -- Bit 17 of the general-purpose I/O port B. L1RQB -- D -- channel request signal for the serial interface TDM port B. L1ST3 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port B Bit 16 -- Bit 16 of the general-purpose I/O port B. L1RQA -- D-channel request signal for the serial interface TDM port A. L1ST4 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port B Bit 15 -- Bit 15 of the general-purpose I/O port B. BRGO3 -- BRG3 output clock. PB[22] SMSYN2 SDACK2 L19 Bidirectional (Optional: Open-drain) PB[21] SMTXD2 L1CLKOB PB[20] SMRXD2 L1CLKOA PB[19] RTS1 L1ST1 K16 Bidirectional (Optional: Open-drain) L16 Bidirectional (Optional: Open-drain) N19 Bidirectional (Optional: Open-drain) PB[18] RTS2 L1ST2 N17 Bidirectional (Optional: Open-drain) PB[17] L1RQB L1ST3 Hi-Z P18 Bidirectional (Optional: Open-drain) PB[16] L1RQA L1ST4 N16 Bidirectional (Optional: Open-drain) PB[15] BRGO3 R17 Bidirectional 21 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name PB[14] RSTRT1 Reset Number U18 Type Bidirectional Description General-Purpose I/O Port B Bit 14 -- Bit 14 of the general-purpose I/O port B. RSTRT1 -- SCC1 serial CAM interface outputs that marks the start of a frame. General-Purpose I/O Port C Bit 15 -- Bit 15 of the general-purpose I/O port C. DREQ0 -- IDMA channel 0 request input. RTS1 -- Request to send modem line for SCC1. L1ST1 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port C Bit 14 -- Bit 14 of the general-purpose I/O port C. DREQ1 -- IDMA channel 1 request input. RTS2 -- Request to send modem line for SCC2. L1ST2 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port C Bit 13 -- Bit 13 of the general-purpose I/O port C. L1RQB -- D-channel request signal for the serial interface TDM port B. L1ST3 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port C Bit 12 -- Bit 12 of the general-purpose I/O port C. L1RQA -- D-channel request signal for the serial interface TDM port A. L1ST4 -- One of four output strobes that can be generated by the serial interface. General-Purpose I/O Port C Bit 11 -- Bit 11 of the general-purpose I/O port C. CTS1 -- Clear to send modem line for SCC1. General-Purpose I/O Port C Bit 10 -- Bit 10 of the general-purpose I/O port C. CD1 -- Carrier detect modem line for SCC1. TGATE1 -- Timer 1/timer 2 gate signal. General-Purpose I/O Port C Bit 9 -- Bit 9 of the general-purpose I/O port C. CTS2 -- Clear to send modem line for SCC2. General-Purpose I/O Port C Bit 8 -- Bit 8 of the general-purpose I/O port C. CD2 -- Carrier detect modem line for SCC2. TGATE2 -- Timer 3/timer 4 gate signal. PC[15] DREQ0 RTS1 L1ST1 D16 Bidirectional PC[14] DREQ1 RTS2 L1ST2 D18 Bidirectional PC[13] L1RQB L1ST3 E18 Bidirectional PC[12] L1RQA L1ST4 F18 Bidirectional PC[11] CTS1 PC[10] CD1 TGATE1 PC[9] CTS2 PC[8] CD2 TGATE2 Hi-Z J19 Bidirectional K19 Bidirectional L18 Bidirectional M18 Bidirectional 22 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name PC[7] CTS3 L1TSYNCB SDACK2 Reset Number M16 Type Bidirectional Description General-Purpose I/O Port C Bit 7 -- Bit 7 of the general-purpose I/O port C. CTS3 -- Clear to send modem line for SCC3. L1TSYNCB -- Transmit sync input for the serial interface TDM port B. SDACK2 -- SDMA acknowledge 2 output that is used as a peripheral interface signal for IDMA emulation or as a CAM interface signal for Ethernet. General-Purpose I/O Port C Bit 6 -- Bit 6 of the general-purpose I/O port C. CD3 -- Carrier detect modem line for SCC3. L1RSYNCB -- Receive sync input for the serial interface TDM port B. General-Purpose I/O Port C Bit 5 -- Bit 5 of the general-purpose I/O port C. CTS4 -- Clear to send modem line for SCC4. L1TSYNCA -- Transmit sync input for the serial interface TDM port A. SDACK1 -- SDMA acknowledge 1output that is used as a peripheral interface signal for IDMA emulation or as a CAM interface signal for Ethernet. General-Purpose I/O Port C Bit 4 -- Bit 4 of the general-purpose I/O port C. CD4 -- Carrier detect modem line for SCC4. L1RSYNCA -- Receive sync input for the serial interface TDM port A. General-Purpose I/O Port D Bit 15 -- Bit 15 of the general-purpose I/O port D. L1TSYNCA -- Input transmit data sync signal to the TDM channel A. General-Purpose I/O Port D Bit 14 -- Bit 14 of the general-purpose I/O port D. L1RSYNCA -- Input receive data sync signal to the TDM channel A. General-Purpose I/O Port D Bit 13 -- Bit 13 of the general-purpose I/O port D. L1TSYNCB -- Input transmit data sync signal to the TDM channel B. General-Purpose I/O Port D Bit 12 -- Bit 12 of the general-purpose I/O port D. L1RSYNCB -- Input receive data sync signal to the TDM channel B. General-Purpose I/O Port D Bit 11 -- Bit 11 of the general-purpose I/O port D. RXD3 -- Receive data for serial channel 3. General-Purpose I/O Port D Bit 10 -- Bit 10 of the general-purpose I/O port D. TXD3 -- Transmit data for serial channel 3. General-Purpose I/O Port D Bit 9 -- Bit 9 of the general-purpose I/O port D. RXD4 -- Receive data for serial channel 4. PC[6] CD3 L1RSYNCB R19 Bidirectional PC[5] CTS4 L1TSYNCA SDACK1 T18 Bidirectional PC[4] CD4 L1RSYNCA T17 Bidirectional PD[15] L1TSYNCA PD[14] L1RSYNCA PD[13] L1TSYNCB PD[12] L1RSYNCB PD[11] RXD3 PD[10] TXD3 PD[9] RXD4 Hi-Z U17 Bidirectional V19 Bidirectional V18 Bidirectional R16 Bidirectional T16 Bidirectional W18 Bidirectional V17 Bidirectional 23 2129A-HIREL-08/02 Table 1. Signal Descriptions (Continued) Name PD[8] TXD4 PD[7] RTS3 Reset Number W17 Type Bidirectional Description General-Purpose I/O Port D Bit 8 -- Bit 8 of the general-purpose I/O port D. TXD4 -- Transmit data for serial channel 4. General-Purpose I/O Port D Bit 7 -- Bit 7 of the general-purpose I/O port D. RTS3 -- Active low request to send output indicates that SCC3 is ready to transmit data. General-Purpose I/O Port D Bit 6 -- Bit 6 of the general-purpose I/O port D. RTS4 -- Active low request to send output indicates that SCC4 is ready to transmit data. General-Purpose I/O Port D Bit 5 -- Bit 5 of the general-purpose I/O port D. REJECT2 -- This input to SCC2 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. General-Purpose I/O Port D Bit 4 -- Bit 4 of the general-purpose I/O port D. REJECT3 -- This input to SCC3 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. General-Purpose I/O Port D Bit 3 -- Bit 3 of the general-purpose I/O port D. REJECT4 -- This input to SCC4 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. Provides clock to scan chain logic or for the development port logic. Should be tied to Vcc if JTAG or development port are not used. Controls the scan chain test mode operations. Should be tied to power through a pull-up resistor if unused. Input serial data for either the scan chain logic or the development port and determines the operating mode of the development port at reset. Output serial data for either the scan chain logic or for the development port. T15 Bidirectional PD[6] RTS4 V16 Bidirectional PD[5] REJECT2 U15 Bidirectional PD[4] REJECT3 U16 Bidirectional PD[3] REJECT4 W16 Bidirectional TCK DSCK TMS TDI DSDI TDO DSDO Hi-Z (Pulled up on rev 0 to rev A.3) Pulled up Pulled up (HiZ on rev 0 to rev A.3) Low H16 Input G18 H17 Input Input G17 Output 24 TSPC860 2129A-HIREL-08/02 TSPC860 Table 1. Signal Descriptions (Continued) Name TRST Reset Pulled up Number G19 Type Input Description Reset for the scan chain logic. If JTAG is not used, connect TRST to ground. If JTAG is used, connect TRST to PORESET. In case PORESET logic is powered by the keep-alive power supply (KAPWR), connect TRST to PORESET through a diode (anode connected to TRST and cathode to PORESET). Spare signals -- Not used on current chip revisions. Leave unconnected. VDDL -- Power supply of the internal logic. VDDH -- Power supply of the I/O buffers and certain parts of the clock control. VDDSYN -- Power supply of the PLL circuitry. KAPWR -- Power supply of the internal OSCM, RTC, PIT, DEC, and TB. VSS -- Ground for circuits, except for the PLL circuitry. VSSSYN, VSSSYN1 -- Ground for the PLL circuitry. SPARE[1-4] Power Supply Hi-Z B7, H18, V15, H4 See Figure 4 No-connect Power Active Pull-up Buffers Active pull-up buffers are a special variety of bidirectional three-state buffer with the following properties: * * When enabled as an output and driving low, they behave as normal output drivers (that is, the pin is constantly driven low). When enabled as an output and driving high, drive high until an internal detection circuit determines that the output has reached the logic high threshold and then stop driving (that is, the pin switches to high-impedance). When disabled as an output or functioning as an input, it should not be driven. * Due to the behavior of the buffer when being driven high, a pull-up resistor is required externally to function as a `bus keep' for these shared signals in periods when no drivers are active and to keep the buffer from oscillating when the buffer is driving high, because if the voltage ever dips below the logic high threshold while the buffer is enabled as an output, the buffer will reactivate. Further, external logic must not attempt to drive these signals low while active pull-up buffers are enabled as outputs, because the buffers will reactivate and drive high, resulting in a buffer fight and possible damage to the TSPC860, to the system, or to both. Figure 6 compares three-state buffers and active pull-up buffers graphically in general terms. It makes no implication as to which edges trigger which events for any particular signal. 25 2129A-HIREL-08/02 Figure 6. Three-State Buffers and Active Pull-Up Buffers 3 Three-state buffer 1 2 1 Drive high on one edge 2 Switch to Hi-Z on later edge 3 Pull-up resistor maintains logic high state 3 Active pull-up buffer 12 4 5 1 Drive high on one edge 2 Switch to Hi-Z when threshold voltage (Voh+margin) is reached 3 Pull-up resistor maintains logic high state 4 Disable buffer as output 5 Pull-up resistor maintains logic high state; other driver can drive signal Note: Events 1 and 4 can be in quick succession. Table 2 summarizes when active pull-up drivers are enabled as outputs. Table 2. Active Pull-Up Resistors Enabled as Outputs Signal TS, BB BI TA Description When the TSPC860 is the external bus master throughout the entire bus cycle. When the TSPC860's memory controller responds to the access on the external bus, throughout the entire bus cycle. When the TSPC860's memory controller responds to the access on the external bus, then: * For chip-selects controlled by the GPCM set for external TA, the TSPC860's TA buffer is not enabled as an output. * For chip-selects controlled by the GPCM set to terminate in n wait-states, TA is enabled as an output on cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction. External logic can drive TA at any point before this, thus terminating the cycle early. [For example, assume the GPCM is programmed to drive TA after 15 cycles. If external logic drives TA before 14 clocks have elapsed then the TA will be accepted by the TSPC860 as a cycle termination.] * For chip-selects controlled by the UPM, the TA buffer is enabled as an output throughout the entire bus cycle. The purpose of active pull-up buffers is to allow access to zero wait-state logic that drives a shared signal on the clock cycle immediately following a cycle in which the signal is driven by the TSPC860. In other words, it eliminates the need for a bus turnaround cycle. Internal Pull-up and Pull- The TMS and TRST pins have internal pull-up resistors. TSPC860 devices from Rev 0 to Rev A.3 (masks xE64C and xF84C) have an internal pull-up resistor on TCK/DSCK down Resistors but no internal pull-up resistor on TDI/DSDI. This was corrected on Rev B and later; on these chips, the internal pull-up resistor was removed from TCK/DSCK and an internal pull-up resistor was added to TDI/DSDI. If RSTCONF is pulled down, during hardware reset (initiated by HRESET or PORESET), the data bus D[0-31] is pulled down with internal pull-down resistors. These internal pull-down resistors are to provide a logic-zero default for these pins when programming the hard reset configuration word. These internal pull-down resistors are disconnected after HRESET is negated. No other pins have internal pull-ups or pull-downs. 26 TSPC860 2129A-HIREL-08/02 TSPC860 Resistance values for internal pull-up and pull-down resistors are not specified because their values may vary due to process variations and shrinks in die size, and they are not tested. Typical values are on the order of 5 K but can vary by approximately a factor of 2. Recommended Basic Pin Connections Reset Configuration Some external pin configuration is determined at reset by the hard reset configuration word. Thus, some decisions as to system configuration (for example, location of BDM pins) should be made before required application of pull-up and pull-down resistors can be determined. RSTCONF should be grounded if the hard reset configuration word is used to configure the TSPC860 or should be connected to VCC if the default configuration is used. Pull-up resistors may not be used on D[0-31] to set the hard reset configuration word, as the values of the internal pull-down resistors are not specified or guaranteed. To change a data bus signal from its default logic low state during reset, actively drive that signal high. MODCK[1-2] must be used to determine the default clocking mode for the TSPC860. After hardware reset, the MODCK[1-2] pins change function and become outputs. Thus, if these alternate functions are also desired, then the MODCK[1-2] configuration should be set with three-state drivers that turn off after HRESET is negated; however, if MODCK[1-2] pins' alternate output functions are not used in the system, they can be configured with pull-up and pull-down resistors. Signals with open-drain buffers and active pull-up buffers (HRESET, SRESET, TEA, TS, TA, BI, and BB) must have external pull-up resistors. These signals include the following: Some other input signals do not absolutely require a pull-up resistor, as they may be actively driven by external logic. However, if they are not used externally, or if the external logic connected to them is not always actively driving, they may need external pullup resistors to hold them negated. These signals include the following: * * * * * * * PORESET AS CR/IRQ3 KR/RETRY/IRQ4/SPKROUT (if configured as KR/RETRY or IRQ4) Any IRQx (if configured as IRQx) BR (if the TSPC860's internal bus arbiter is used) BG (if an external bus arbiter is used) 27 2129A-HIREL-08/02 JTAG and Debug Ports TCK/DSCK or ALE_B/DSCK/AT1 (depending on the configuration of the DSCK function) should be connected to ground through a pull-down resistor to disable Debug Mode as a default. When required, a debug mode controller tool externally drives this signal high actively to put the TSPC860 into debug mode. Two pins need special attention, depending on the version of TSPC860 used. * * For TSPC860 rev B and later, TDI/DSDI should be pulled up to VCC to keep it from oscillating when unused. For TSPC860 rev A.3 and earlier, TCK/DSCK should be connected to ground if it is configured for its DSCK function, as stated above. However, for these versions of the TSPC860, the pull-down resistor must be strong (for example, 1 k to overcome the internal pull-up resistor. To allow application of any version of processor, perform both of the above actions. Unused Inputs In general, pull-up resistors should be used on any unused inputs to keep them from oscillating. For example, if PCMCIA is not used, the PCMCIA input pins (WAIT_A, WAIT_B, IP_A[0-8], IP_B[0-8]) should have external pull-up resistors. However, unused pins of port A, B, C, or D can be configured as outputs, and, if they are configured as outputs they do not require external terminations. Unused outputs can be left unterminated. During hardware reset (HRESET or PORESET), the signals of the TSPC860 behave as follows: * * * The bus signals are high-impedance. The port I/O signals are configured as inputs, and are therefore high-impedance. The memory controller signals are driven to their inactive state. Unused Outputs Signal States During Hardware Reset However, some signal functions are determined by the reset configuration. When HRESET is asserted, these signals immediately begin functioning as determined by the reset configuration and are either high-impedance or are drive to their inactive state accordingly. The behavior of these signals is shown in Table 12. Table 3. Signal States during Hardware Reset Signal BDIP/GPL_B5 RSV/IRQ2 KR/RETRY/IRQ4/SPKROUT FRZ/IRQ6 ALE_B/DSCK/AT1 IP_B[0-1]/IWP[0-1]/VFLS[0-1] Behavior BDIP: high impedance GPL_B5: high RSV: high IRQ2: high impedance KR/RETRY/IRQ4: high impedance SPKROUT: low FRZ: low IRQ6: high impedance ALE_B: low DSCK/AT1: high impedance IP_B[0-1]: high impedance IWP[0-1]: high VFLS[0-1]: low 28 TSPC860 2129A-HIREL-08/02 TSPC860 Table 3. Signal States during Hardware Reset (Continued) Signal IP_B3/IWP2/VF2 Behavior IP_B3: high impedance IWP2: high VF2: low IP_B4: high impedance LWP0: high VF0: low IP_B5: high impedance LWP1: high; VF1: low IP_B4/LWP0/VF0 IP_B5/LWP1/VF1 Scope Applicable Documents Requirements General Design and Construction Terminal Connections Lead Material and Finish Package This drawing describes the specific requirements for the microcontroller TSPC860, in compliance with MIL-STD-883 class Q or Atmel standard screening. 1. MIL-STD-883: Test methods and procedures for electronics. 2. MIL-PRF-38535 appendix A: General specifications for microcircuits. The microcircuits are in accordance with the applicable documents and as specified herein. The terminal connections shall be as shown in the general description. Lead material and finish shall be as specified on page 87. The macrocircuits are packaged in 357-lead Plastic Ball Grid Array (BGA) packages. The precise case outlines are described at the end of the specification. 29 2129A-HIREL-08/02 Absolute Maximum Ratings Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Table 4. Absolute Maximum Rating for the TSPC860 Parameter I/O Supply Voltage Internal Supply Voltage Backup Supply Voltage PLL Supply Voltage Input Voltage Storage Temperature Range Symbol VDDH VDDL KAPWR VDDSYN VIN TSTG Min -0.3 -0.3 -0.3 -0.3 -0.3 -55 Max 4.0 4.0 4.0 4.0 5.8 +150 Unit V V V V V C Table 5. Thermal Characteristics Rating Junction to Ambient (1) Environnement Natural Convection Single layer board (1s) Four layer board (2s2p) Air Flow (200 ft/min) Single layer board (1s) Four layer board (2s2p) Symbol RJA (2) (3) Rev A 31 20 26 16 8 5 1 2 Rev B, C, D 40 25 32 21 15 7 2 3 Unit C/W RJMA RJMA RJMA RJB RJC Junction to Board Junction to Case (4) (5) (6) Junction to Package Top Natural Convection Air Flow (20 ft/min) JT Notes: 1. Junction temperature is a function on on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simlated value from the junction to the exposed pas without contact resistance. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 30 TSPC860 2129A-HIREL-08/02 TSPC860 Table 6. Power Dissipation (PD)(3) Die Revision A.3 and Previous Frequency 25 40 50 B.1 and C.1 33 50 66 D.3 and D.4 (1:1 Mode) D.3 and D.4 (2:1 Mode) Note: 50 66 66 80 Typical(1) 450 700 870 375 575 750 656 TBD 722 851 Maximum(2) 550 850 1050 TBD TBD TBD 735 TBD 762 909 Unit mW mW mW mW mW mW mW mW mW mW 1. Typical power dissipation is measured at 3.3V. 2. Maximum power dissipation is measured at 3.65V. 3. Values in Table 6 represent VDDL-based power dissipation and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry. 31 2129A-HIREL-08/02 Electrical Characteristics General Requirements DC Electrical Specifications Table 7. DC Electrical Specification VCC = 3.3 5% VDC, GND = 0 VDC, -55C Tc 125C Characteristic Operating Voltage Symbol VDDH, VDDL, KAPWR, VDDSYN KAPWR (powerdown mode) KAPWR (all other operating modes) Input High Voltage (all inputs except EXTAL and EXTCLK) Input Low Voltage EXTAL, EXTCLK Input High Voltage Input Leakage Current, VIN = 5.5V (Except TMS, TRST, DSCK and DSDI pins) Input Leakage Current, VIN = 3.6V (Except TMS, TRST, DSCK and DSDI pins) Input Leakage Current, VIN = 0V (Except TMS, TRST, DSCK and DSDI pins) Output High Voltage, IOH = -2.0 mA, VDDH = 3.0V Except XTAL, XFC, and Open drain pins VIH VIL VIHC IIN IIN IIN VOH Min 3.135 Max 3.465 Unit V All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below. 2.0 3.6 V VDDH - 0.4 VDDH V 2.0 GND 0.7 * (VCC) 2.4 5.5 0.8 VCC + 0.3 100 10 10 - V V V A A A V 32 TSPC860 2129A-HIREL-08/02 TSPC860 Table 7. DC Electrical Specification (Continued) VCC = 3.3 5% VDC, GND = 0 VDC, -55C Tc 125C Characteristic Output Low Voltage IOL = 2.0 mA IOL = 3.2 mA CLKOUT A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, L1TCLKB/TOUT4/CLK8/PA0, RRJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/sdack1/PB23, SMSYN2/sdack2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19, L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11, TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, CTS3/SDACK2/L1TSYNCB/PC7, CD3/L1RSYNCB/PC6, CTS4/SDACK1/L1TSYNCA/PC5, CD4/L1RSYNCA/PC4, PD15/L1TSYNCA, PD14/L1RSYNCA, PD13/L1TSYNCB, PD12/L1RSYNCB, PD11/RXD3, PD10/TXD3, PD9/RXD4, PD8/TXD4, PD5/RRJCT2, PD6/RTS4, PD7/RTS3, PD4/RRJCT3, PD3 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30) TXD1/PA14, TXD2/PA12 TS, TA, TEA, BI, BB, HRESET, SRESET Cin 20 pF Symbol VOL Min Max 0.5 Unit V IOL = 5.3 mA IOL = 7.0 mA IOL = 8.9 mA Input Capacitance 33 2129A-HIREL-08/02 AC Electrical Specifications Control Timing Figure 7. AC Electrical Specifications Control Timing Diagram 2.0V 2.0V 0.8V A B 2.0V 2.0V 0.8V 0.8V CLKOUT OUTPUTS 0.8V A B 2.0V OUTPUTS 0.8V 2.0V 0.8V C D 2.0V 2.0V 0.8V C D 2.0V 0.8V INPUTS 0.8V INPUTS 2.0V 0.8V A. Maxi mu m Output Delay Speci ficat ion B. Minim um Out put Hold Tim e C. Minim um input Setup Tim e Specification D. Minim um input Hold Tim e Specification The timing for the TSPC860 bus shown assumes a 50 pF load for maximum delays and a 0 pF load for minimum delays. For loads other than 50 pF, maximum delays can be derated by 1 ns per 10 pF. 34 TSPC860 2129A-HIREL-08/02 TSPC860 Table 8. Bus Operation Timings 33 MHz Num B1 B1a B1b B1c B1d B1e B1f B1g B1h B2 B3 B4 B5 B7 B7a B7b B8 B8a B8b B9 Characteristic CLKOUT Period EXTCLK to CLKOUT Phase Skew (EXTCLK > 15 MHz and MF 2) EXTCLK to CLKOUT Phase Skew (EXTCLK > 10 MHz and MF < 10) CLKOUT Phase Jitter (EXTCLK > 15 MHz and MF 2)(1) CLKOUT Phase Jitter CLKOUT Frequency Jitter (MF < 10) CLKOUT Frequency Jitter (10 < MF < 500) CLKOUT Frequency Jitter (MF > 500) Frequency Jitter on EXTCLK(2) CLKOUT pulse width low CLKOUT width high CLKOUT rise time(3) CLKOUT fall time (3) 40 MHz Min 25 -0.90 -2.30 -0.60 -2 - - - - 10 10 - - 6.25 6.25 6.25 6.25 6.25 6.25 6.25 Max 30.30 0.90 2.30 0.60 2 0.50 2 3 0.50 - - 4 4 - - - 13 13 13 13 50 MHz Min 20 -0.90 -2.30 -0.60 -2 - - - - 8 8 - - 5 5 5 5 5 5 5 Max 30.30 0.90 2.30 0.60 2 0.50 2 3 0.50 - - 4 4 - - - 11.75 11.75 11.75 11.75 66 MHz Unit Min 15.15 -0.90 -2.30 -0.60 -2 - - - - 6.06 6.06 - - 3.80 3.80 3.80 3.80 3.80 3.80 3.80 Max 30.30 0.90 2.30 0.60 2 0.50 2 3 0.50 - - 4 4 - - - 10.04 10.04 10.04 10.04 ns ns ns ns ns % % % % ns ns ns ns ns ns ns ns ns ns ns Min 30.30 -0.90 -2.30 -0.60 -2 - - - - 12.12 12.12 - - 7.58 7.58 7.58 7.58 7.58 7.58 7.58 Max 30.30 0.90 2.30 0.60 2 0.50 2 3 0.50 - - 4 4 - - - 14.33 14.33 14.33 14.33 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) Invalid CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR Invalid CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2), IWP(0:2), LWP(0:1), STS Invalid(4) CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) valid CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR valid CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS valid(4) CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, AT(0:3), PTR High Z CLKOUT to TS, BB assertion CLKOUT to TA, BI assertion (when driven by the Memory Controller or PCMCIA I/F) CLKOUT to TS, BB negation CLKOUT to TA, BI negation (when driven by the Memory Controller or PCMCIA interface) CLKOUT to TS, BB High Z B11 B11a B12 B12a B13 7.58 2.50 7.58 2.50 7.58 13.58 9.25 14.33 11 21.58 6.25 2.50 6.25 2.50 6.25 12.25 9.25 13 11 20.25 5 2.50 5 2.50 5 11 9.25 11.75 11 19 3.80 2.50 3.80 2.50 3.80 11.29 9.75 8.54 9 14.04 ns ns ns ns ns 35 2129A-HIREL-08/02 Table 8. Bus Operation Timings (Continued) 33 MHz Num B13a B14 B15 B16 B16a B16b B17 B17a B18 B19 B20 B21 B22 B22a B22b B22c B23 Characteristic CLKOUT to TA, BI High Z (when driven by the Memory Controller or PCMCIA interface) CLKOUT to TEA assertion CLKOUT to TEA High Z TA, BI valid to CLKOUT (Setup Time) TEA, KR, RETRY, CR valid to CLKOUT (Setup Time) BB, BG, BR, valid to CLKOUT (setup time)(5) CLKOUT to TA, TEA, BI, BB, BG, BR valid (Hold Time) CLKOUT to KR, RETRY, CR valid (Hold Time) D(0:31), DP(0:3) valid to CLKOUT Rising Edge (Setup Time)(6) CLKOUT Rising Edge to D(0:31), DP(0:3) valid (Hold Time)(6) D(0:31), DP(0:3) valid to CLKOUT Falling Edge (Setup Time)(7) CLKOUT Falling Edge to D(0:31), DP(0:3) valid (Hold Time)(7) CLKOUT Rising Edge to CS asserted -GPCM- ACS = 00 CLKOUT Falling Edge to CS asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 0 CLKOUT Falling Edge to CS asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 0 CLKOUT Falling Edge to CS asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 1 CLKOUT Rising Edge to CS negated -GPCM- Read Access, -GPCM- write access, ACS = `00', TRLX = `0' & CSNT = `0' A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 10, TRLX = 0 A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 11, TRLX = 0 CLKOUT Rising Edge to OE, WE(0:3) asserted CLKOUT Rising Edge to OE negated A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 10, TRLX = 1 A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 11, TRLX = 1 Min 2.50 2.50 2.50 9.75 10 8.50 1 2 6 1 4 2 7.58 - 7.58 10.86 2 Max 15 10 15 - - - - - - - - - 14.33 8 14.33 17.99 8 40 MHz Min 2.50 2.50 2.50 9.75 10 8.50 1 2 6 1 4 2 6.25 - 6.25 8.88 2 Max 15 10 15 - - - - - - - - - 13 8 13 16 8 50 MHz Min 2.50 2.50 2.50 9.75 10 8.50 1 2 6 1 4 2 5 - 5 7 2 Max 15 10 15 - - - - - - - - - 11.75 8 11.75 14.13 8 66 MHz Unit Min 2.50 2.50 2.50 6 4.50 4 2 2 6 2 4 2 3.80 - 3.80 5.18 2 Max 15 9 15 - - - - - - - - - 10.04 8 10.54 12.31 2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns B24 B24a B25 B26 B27 B27a 5.58 13.15 - 2 35.88 43.45 - - 9 9 - - 4.25 10.5 - 2 29.25 35.50 - - 9 9 - - 3 8 - 2 23 28 - - 9 9 - - 1.79 5.58 - 2 16.94 20.73 - - 9 9 - - ns ns ns ns ns ns 36 TSPC860 2129A-HIREL-08/02 TSPC860 Table 8. Bus Operation Timings (Continued) 33 MHz Num B28 B28a Characteristic CLKOUT rising edge to WE(0:3) negated GPCM write access CSNT = 0 CLKOUT falling Edge to WE(0:3) negated -GPCM- write access TRLX = 0, CSNT = 1, EBDF = 0 CLKOUT falling edge to CS negated -GPCM- write access TRLX = `0', CSNT = `1', ACS = 11, EBDF = 0 CLKOUT Falling Edge to WE(0:3) negated -GPCM- write access TRLX = `0', CSNT = `1' write access TRLX = 0, CSNT = 1, EBDF = 1 CLKOUT Falling Edge to CS negated -GPCM- write access TRLX = `0', CSNT = `1', ACS = 10, or ACS = `11', EBDF = 1 WE (0:3) negated to DP (0:3) High-Z -GPCM- write access, CSNT = 0, EBDF = 0 WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = 1', EBDF = 0 CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, ACS = `00', TRLX = `0' & CSNT = `0' CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = `1', ACS = `11,', EBDF = 0 WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `1', CSNT = `1', EBDF = 0 CS negated to D (0:31), DP(0:3) High Z -GPCM- write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = `1', EBDF = 1 CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = `1', ACS = `10' or ACS = '11', EBDF = 1 WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `1', CSNT = `1', EBDF = 1 CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `1', CSNT = `1', ACS = `10' or ACS = '11 ', EBDF = 1 CS, WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access(8) Min - 7.58 Max 9 14.33 40 MHz Min - 6.25 Max 9 13 50 MHz Min - 5 Max 9 11.75 66 MHz Unit Min - 3.8 Max 9 10.54 ns ns B28b - 14.33 - 13 - 11.75 - 10.54 ns B28c 10.86 17.99 8.88 16 7 14.13 5.18 12.31 ns B28d - 17.99 - 16 - 14.13 - 12.31 ns B29 B29a 5.58 13.15 - - 4.25 10.5 - - 3 8 - - 1.79 5.58 - - ns ns B29b 5.58 - 4.25 - 3 - 1.79 - ns B29c 13.15 - 10.5 - 8 - 5.58 - ns B29d 43.45 - 35.5 - 28 -- 20.73 - ns B29e 43.45 - 35.5 - 28 - 29.73 - ns B29f 8.86 - 6.8 - 5 - 3.48 - ns B29g 8.86 - 6.8 - 5 - 3.48 - ns B29h 38.67 - 31.38 - 24.50 - 17.83 - ns B29i 38.67 - 31.38 - 24.50 - 17.83 - ns B30 5.58 - 4.25 - 3 - 1.79 - 37 2129A-HIREL-08/02 Table 8. Bus Operation Timings (Continued) 33 MHz Num B30a Characteristic WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '0', CSNT = '1'. CS negated to A(0:31) invalid GPCM write access, TRLX = '0', CSNT = '1', ACS = 10, ACS = 11, EBDF = 0 WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '1', CSNT = '1'. CS negated to A(0:31) invalid -GPCM- write access, TRLX = '1', CSNT = '1', ACS = 10, ACS = '1 1', EBDF = 0 WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '0', CSNT = '1'. CS negated to A(0:31) invalid -GPCM- write access, TRLX = '0', CSNT = '1', ACS = 10, ACS = '11', EBDF = 1 WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '1', CSNT = '1'. CS negated to A(0:31) invalid -GPCM- write access, TRLX = '1', CSNT = '1', ACS = 10,ACS = '11', EBDF = 1 CLKOUT Falling Edge to CS valid - as requested by control bit CST4 in the corresponding word in the UPM CLKOUT Falling Edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM CLKOUT Rising Edge to CS valid - as requested by control bit CST2 in the corresponding word in the UPM CLKOUT Rising Edge to CS valid - as requested by control bit CST3 in the corresponding word in the UPM CLKOUT Falling Edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM, EBDF = 1 CLKOUT Falling Edge to BS valid - as requested by control bit BST4 in the corresponding word in the UPM CLKOUT Falling Edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 Min 13.15 Max - 40 MHz Min 10.50 Max - 50 MHz Min 8 Max - 66 MHz Unit Min 5.58 Max - ns B30b 43.45 - 35.50 - 28 - 20.73 - ns B30c 8.36 - 6.38 - 4.50 - 2.68 - ns B30d 38.67 - 31.38 - 24.50 - 17.83 - ns B31 1.5 6 1.50 6 1.50 6 1.50 6 ns B31a 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns B31b 1.50 8 1.50 8 1.50 8 1.50 8 ns B31c 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns B31d 13.26 17.99 11.28 16 9.40 14.13 7.58 12.31 ns B32 1.50 6 1.50 6 1.50 6 1.50 6 ns B32a 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns 38 TSPC860 2129A-HIREL-08/02 TSPC860 Table 8. Bus Operation Timings (Continued) 33 MHz Num B32b Characteristic CLKOUT Rising Edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM CLKOUT Rising Edge to BS valid - as requested by control bit BST3 in the corresponding word in the UPM CLKOUT Falling Edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 CLKOUT Falling Edge to GPL valid - as requested by control bit GxT4 in the corresponding word in the UPM CLKOUT Rising Edge to GPL valid - as requested by control bit GxT3 in the corresponding word in the UPM A(0:31), BADDR(28:30), and D(0:31) to CS valid as requested by control bit CST4 in the corresponding word in the UPM A(0:31), BADDR(28:30), and D(0:31) to CS valid as requested by control bit CST1 in the corresponding word in the UPM A(0:31), BADDR(28:30), and D(0:31) to CS valid as requested by control bit CST2 in the corresponding word in the UPM A(0:31), BADDR(28:30), and D(0:31) to BS valid as requested by control bit BST4 in the corresponding word in the UPM A(0:31), BADDR(28:30), and D(0:31) to BS valid as requested by control bit BST1 in the corresponding word in the UPM A(0:31), BADDR(28:30), and D(0:31) to BS valid as requested by control bit BST2 in the corresponding word in the UPM A(0:31), BADDR(28:30), and D(0:31) to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM UPWAIT valid to CLKOUT Falling Edge(9) CLKOUT Falling Edge to UPWAIT valid AS valid to CLKOUT Rising Edge(10) A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT Rising Edge. (9) 40 MHz Min 1.50 Max 8 50 MHz Min 1.50 Max 8 66 MHz Unit Min 1.50 Max 8 ns Min 1.50 Max 8 B32c 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns B32d 13.26 17.99 11.28 16 9.40 14.13 7.58 12.31 ns B33 1.50 6 1.50 6 1.50 6 1.50 6 ns B33a 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns B34 5.58 - 4.25 - 3 - 1.79 - ns B34a 13.15 - 10.50 - 8 - 5.58 - ns B34b 20.73 - 16.75 - 13 - 9.36 - ns B35 5.58 - 4.25 - 3 - 1.79 - ns B35a 13.15 - 10.50 - 8 - 5.58 - ns B35b 20.73 - 16.75 - 13 - 9.36 - ns B36 5.58 - 4.25 - 3 - 1.79 - ns B37 B38 B39 B40 6 1 7 7 - - - - 6 1 7 7 - - - - 6 1 7 7 - - - - 6 1 7 7 - - - - ns ns ns ns 39 2129A-HIREL-08/02 Table 8. Bus Operation Timings (Continued) 33 MHz Num B41 B42 B43 Notes: Characteristic TS valid to CLKOUT Rising Edge (SetUp Time). CLKOUT Rising Edge to TS Valid (Hold Time). Min 7 2 Max - - 40 MHz Min 7 2 Max - - 50 MHz Min 7 2 Max - - 66 MHz Unit Min 7 2 Max - - ns ns AS negation to Memory Controller Signals - TBD - TBD - TBD - TBD ns Negation 1. Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value. 2. If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e. it does not stay at an extreme value for a long time) then the maximum allowed jitter on EXTAL can be up to 2% 3. The timings specified in B4 and B5 are based on full strength clock. 4. The timing for BR output is relevant when the PC860 is selected to work with the external bus arbiter. The timing for BG output is relevant when the PC860 is selected to work with internal bus arbiter. 5. The timing required for BR input is relevant when the TSPC860 is selected to work with internal bus arbiter. The timing for BG input is relevant when the TSPC860 is selected to work with internal bus arbiter. 6. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. 7. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the Memory Controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the cases where data is latched on the falling edge of CLKOUT). 8. The timing B30 refers to CS when ACS = 00 and to WE (0:3) when CSNT = 0 9. The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 22. 10. The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 25. Figure 8. External Clock Timing CLKOUT B1 B1 B4 B5 B3 B2 40 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 9. Synchronous Output Signals Timing CLKOUT B8 B7 Output Signals B8a B7a Output Signals B8b B7b Output Signals B9 B9 Figure 10. Synchronous Active Pull-up and Open Drain Output Signals Timing CLKOUT B13 B11 TS, BB B13a B11a TA, BI B14 B15 TEA B12a B12 41 2129A-HIREL-08/02 Figure 11. Synchronous Input Signals Timing CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure 12. Input Data Timing in Normal Case CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure 13. Input Data Timing when controlled by UPM in the Memory Controller CLKOUT TA B20 B21 D[0:31], DP[0:3] 42 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 14. External Bus Read Timing (GPCM Controlled - ACS = `00') CLKOUT B11 TS B8 A[0:31] B22 CSx B25 OE B28 WE[0:3] B18 D[0:31], DP[0:3] B19 B26 B23 B12 Figure 15. External Bus Read Timing (GPCM Controlled - TRLX = `0' ACS = `10') CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B24 OE B18 D[0:31], DP[0:3] B19 B25 B26 43 2129A-HIREL-08/02 Figure 16. External Bus Read Timing (GPCM Controlled - TRLX = `0' ACS = `11') CLKOUT B11 TS B8 A[0:31] B22c B22b B12 B23 CSx B24a B25 B26 OE B18 D[0:31], DP[0:3] B19 Figure 17. External Bus Read Timing (GPCM Controlled - TRLX = `1', ACS = `10', ACS = `11') CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B27 OE B27a B22b B22c B26 B18 B19 D[0:31], DP[0:3] 44 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 18. External Bus Write Timing (GPCM controlled - TRLX = `0', CSNT = `0') CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B9 B29b B12 B30 B23 B28 B29 Figure 19. External Bus Write Timing (GPCM controlled - TRLX = `0', CSNT = `1') CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28a B28c B29a B29f B29c B29g B28b B28d B30a B30c B12 B23 B9 45 2129A-HIREL-08/02 Figure 20. External Bus Write Timing (GPCM controlled - TRLX = `1', CSNT = `1') CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28a B28c B29d B29h B29e B29i B28b B28d B30b B30d B12 B23 B29b B9 46 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 21. External Bus Timing (UPM Controlled Signals) CLKOUT B8 A[0:31] B31a B31d B31c B31b B31 CSx B34 B34a B34b B32a B32d B32c B32b B32 BS_A[0:3], BS_B[0:3] B35 B36 B35a B35b B33a B33 GPL_A[0:5], GPL_B[0:5] Figure 22. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] 47 2129A-HIREL-08/02 Figure 23. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 24. Synchronous External Master Access Timing - GPCM handled ACS = `00' CLKOUT B41 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx B42 48 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 25. Asynchronous External Master Memory Access Timing (GPCM Controlled - ACS = '00') CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 26. Asynchronous External Master - Control Signals Negation Time AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Table 9. Interrupt Timing(2) All Frequencies Num I39 I40 I41 I42 I43 Notes: Characteristic (1) Min 6 2 3 3 4XTCLOCKOUT Max Unit ns ns ns ns IRQx Valid to CLKOUT Rising Edge (Set Up Time) IRQx Hold Time After CLKOUT IRQx Pulse Width Low IRQx Pulse Width High IRQx Edge to Edge Time - - - - - - 1. The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. 2. The timings I41, I42 and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the TSPC860 is able to support. Figure 27. Interrupt Detection Timing for External Level Sensitive Lines CLKOUT I39 I40 IRQx 49 2129A-HIREL-08/02 Figure 28. Interrupt Detection Timing for External Edge Sensitive Lines CLKOUT I41 IRQx I43 I43 I42 Table 10. PCMCIA Timing 33 MHz Num P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 Notes: Characteristic A(0:31), REG valid to PCMCIA Strobe asserted(1) A(0:31), REG valid to ALE negation(1) CLKOUT to REG valid CLKOUT to REG Invalid CLKOUT to CE1, CE2 asserted CLKOUT to CE1, CE2 negated CLKOUT to PCOE, IORD, PCWE, IOWR assert time CLKOUT to PCOE, IORD, PCWE, IOWR negate time CLKOUT to ALE assert time CLKOUT to ALE negate time PCWE, IOWR negated to D(0:31) invalid (1) 50 MHz Min 16.75 23 6.25 7.25 6.25 6.25 Max 50 MHz Min 13 18 5 6 5 5 Max 66 MHz Min 9.36 13.15 3.79 4.84 3.79 3.79 Max Unit ns ns ns ns Min 20.73 28.30 7.58 8.58 7.58 7.58 Max - - 15.58 - - 14.25 - - 13 - - 11.84 - 15.58 15.58 11 - 14.25 14.25 11 - 13 13 - 11.84 11.84 ns ns ns 2 7.58 11 15.58 15.58 2 6.25 11 14.25 14.25 5 13 13 3.79 11.04 11.84 ns ns ns ns ns - 5.58 8 - 4.25 8 2 - 3 8 2 - 1.79 8 2 - - - - - - - - - - - - WAITA and WAITB valid to CLKOUT rising edge(1) 2 CLKOUT rising edge to WAITA and WAITB invalid(1) 1. PSST = 1. Otherwise add PSST times cycle time. 2. PSHT = 1. Otherwise add PSHT times cycle time. These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. 50 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 29. PCMCIA Access Cycles Timing External Bus Read CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCOE, IORD P52 ALE B18 D[0:31] B19 P53 P52 P51 P49 P45 P47 51 2129A-HIREL-08/02 Figure 30. PCMCIA Access Cycles Timing External Bus Write CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCOE, IOWR P52 ALE B18 D[0:31] B19 P53 P52 P51 P54 P49 P45 P47 Figure 31. PCMCIA Wait Signals Detection Timing CLKOUT P55 P56 WAITx Table 11. PCMCIA Port Timing 33 MHz Num P57 P58 P59 P60 Note: Characteristic CLKOUT to OPx Valid HRESET negated to OPx drive(1) IP_Xx valid to CLKOUT Rising Edge CLKOUT Rising Edge to IP_Xx invalid 1. OP2 and OP3 only. Min Max 19 40 MHz Min Max 19 50 MHz Min Max 19 66 MHz Min Max 19 Unit ns ns ns ns - 25.73 5 1 - 21.75 5 1 - 18 5 1 - 14.36 5 1 - - - - - - - - - - - - 52 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 32. PCMCIA Output Port Timing CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 33. PCMCIA Input Port Timing CLKOUT P59 P60 Input Signals Table 12. Debug Port Timing All Frequencies Num P61 P62 P63 P64 P65 P66 P67 Characteristic DSCK Cycle Time DSCK Clock Pulse Width DSCK Rise and Fall Times DSDI Input Data Setup Time DSDI Data Hold Time DSCK Low to DSDO Data Valid DSCK Low to DSDO Invalid Min 3xTCLOCKOUT 1.25xTCLOCKOUT 0 8 5 0 0 Max Unit - - 3 - - ns ns ns ns ns - - 15 2 53 2129A-HIREL-08/02 Figure 34. Debug Port Clock Input Timing CLKOUT P59 P60 Input Signals Figure 35. Debug Port Timings DSCK D64 D65 DSDI D66 D67 DSDO 54 TSPC860 2129A-HIREL-08/02 TSPC860 Table 13. RESET Timing 33 MHz Num R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 Characteristic CLKOUT to HRESET high impedance CLKOUT to SRESET high impedance RSTCONF pulse width Min Max 20 20 40 MHz Min Max 20 20 50 MHz Min Max 20 20 66 MHz Min Max 20 20 - Unit ns ns ns - - 515.15 - - 425 - - 340 - - 257.58 - - - - - - 25 25 25 - - - - - - 25 25 25 - Configuration Data to HRESET rising edge set up time Configuration Data to RSTCONF rising edge set up time Configuration Data hold time after RSTCONF negation Configuration Data hold time after HRESET negation HRESET and RSTCONF asserted to Data out drive RSTCONF negated to Data out high impedance. CLKOUT of last rising edge before chip tristates HRESET to Data out high impedance. DSDI, DSCK set up DSDI, DSCK hold time SRESET negated to CLKOUT rising edge for DSDI and DSCK sample - 504.55 350 0 0 - - - - 425 350 0 0 - - - - - - - - 25 25 25 - 350 350 0 0 - - - - 277.27 350 0 0 - - - - - - - - 25 25 25 - ns ns ns ns ns ns ns R80 R81 R82 90.91 0 242.42 - - - 75 0 200 - - - 60 0 160 - - - 45.45 0 121.21 - - - ns ns ns Figure 36. Reset Timing - Configuration from Data Bus HRESET R71 R76 RSTCONF R73 R74 D[0:31] (IN) R75 55 2129A-HIREL-08/02 Figure 37. Reset Timing - TSPC860 Data Bus Weak Drive during Configuration CLKOUT R69 HRESET R79 RSTCONF R77 D[0:31] (OUT) (Weak) R78 Figure 38. Reset Timing - Debug Port Configuration IEEE 1149.1 Electrical Specifications CLKOUT R70 R82 SRESET R80 R81 DSCK, DSDI R80 R81 56 TSPC860 2129A-HIREL-08/02 TSPC860 Table 14. JTAG Timing All Frequencies Num J82 J83 J84 J85 J86 J87 J88 J90 J91 J92 J93 J94 J95 J96 Characteristic TCK Cycle Time TCK Clock Pulse Width Measured at 1.5V TCK Rise and Fall Times TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO Data Invalid TRST Assert Time TRST Setup Time to TCK Low TCK Falling Edge to Output Valid TCK Falling Edge to Output Valid out of High Impedance TCK Falling Edge to Output High Impedance Boundary Scan Input Valid to TCK Rising Edge TCK Rising Edge to Boundary Scan Input Invalid 50 50 0 100 40 50 50 50 Min 100 40 0 5 25 27 10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 39. JTAG Test Clock Input Timing TCK J82 J82 J84 J83 J83 J84 Figure 40. JTAG - Test Access Port Timing Diagram TCK J85 J86 TMS, TDI J87 J88 TDO J89 57 2129A-HIREL-08/02 Figure 41. JTAG - TRST Timing Diagram TCK J91 J90 TRST Figure 42. Boundary Scan (JTAG) Timing Diagram TCK J92 Output Signals J93 Output Signals J95 Output Signals J96 J94 CPM Electrical Characteristics PIP/PIO AC Electrical Specifications Table 15. PIP/PIO Timing All Frequencies Num 21 22 23 24 25 26 27 28 29 30 31 Note: Characteristic Data-In Setup Time to STBI Low Data-In Hold Time to STBI High STBI Pulse Width STBO Pulse Width Data-Out Setup Time to STBO Low Data-Out Hold Time from STBO High STBI Low to STBO Low (Rx Interlock) STBI Low to STBO High (Tx Interlock) Data-In Setup Time to Clock Low Data-In Hold Time from Clock Low Clock High to Data-Out Valid (CPU Writes Data, Control, or Direction) 1. t3 = Specification 23 Min 0 2.5 - t3 1.5 1 clk - 5 ns 2 5 - 2 15 7.5 - (1) Max - - - - - - 2 - - - 25 Unit ns clk clk ns clk clk clk clk ns ns ns 58 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 43. PIP RX (Interlock Mode) Timing Diagram 21 DATA IN 22 23 STBI 27 STBO 24 Figure 44. PIP TX (Interlock Mode) Timing Diagram 25 DATA OUT 24 26 STBO (OUTPUT) 28 23 STBI (IN PUT) 59 2129A-HIREL-08/02 Figure 45. PIP RX (Pulse Mode) Timing Diagram 21 DATA IN 22 23 STBI (IN PUT) 24 STBO (OUTPUT) Figure 46. PIP TX (Pulse Mode) Timing Diagram 25 DATA OUT 26 24 STBO (OUTPUT) 23 STBI (IN PUT) 60 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 47. Parallel I/O Data-in/Data-out Timing Diagram CLKO 29 30 DATA IN 31 DATA OUT IDMA Controller AC Electrical Specifications All Frequencies Num 40 41 42 43 44 45 46 Note: Characteristic DREQ Setup Time to Clock High DREQ Hold Time from Clock High SDACK Assertion Delay from Clock High SDACK Negation Delay from Clock Low SDACK Negation Delay from TA Low SDACK Negation Delay from Clock High TA Assertion to Falling Edge of the Clock Setup Time(1) 1. Applies to external TA. Min 7 3 - - - - 7 Max - - 12 12 20 15 - Unit ns ns ns ns ns ns ns Figure 48. IDMA External Requests Timing Diagram CLKO (OUTPUT) 41 DREQ (IN PUT) 40 61 2129A-HIREL-08/02 Figure 49. SDACK Timing Diagram - Peripheral Write, TA Sampled Low at the Falling Edge of the Clock CLKO (OUTPUT) TS (OUTPUT) RD / WR (OUTPUT) 42 DAT A 46 TA (OUTPUT) 43 SDACK Figure 50. SDACK Timing Diagram - Peripheral Write, TA Sampled High at the Falling Edge of the Clock CLKO (OUTPUT) TS (OUTPUT) RD / WR (OUTPUT) 42 DAT A 44 TA (OUTPUT) SDACK 62 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 51. SDACK Timing Diagram - Peripheral Read CLKO (OUTPUT) TS (OUTPUT) RD / WR (OUTPUT) 42 DAT A 45 TA (OUTPUT) SDACK Baud Rate Generator AC Electrical Specifications All Frequencies Num 50 51 52 Characteristic BRGO Rise and Fall Time BRGO Duty Cycle BRGO Cycle Min - 40 40 Max 10 60 - Unit ns % ns Figure 52. Baud Rate Generator Timing Diagram 50 BRGOx 51 52 51 50 63 2129A-HIREL-08/02 Timer AC Electrical Specifications All Frequencies Num 61 62 63 64 65 Characteristic TIN/TGATE Rise and Fall Time TIN/TGATE Low Time TIN/TGATE High Time TIN/TGATE Cycle Time CLKO High to TOUT Valid Min 10 1 2 3 3 Max - - - - 25 Unit ns clk clk clk ns Figure 53. CPM General-Purpose Timers Timing Diagram 60 CLKO 61 TI N / TGATE (IN PUT) 61 TOUT (OUTPUT) 65 63 62 64 64 TSPC860 2129A-HIREL-08/02 TSPC860 Serial Interface AC Electrical Specifications All Frequencies Num 70 71 71A 72 73 74 75 76 77 78 78A 79 80 80A 81 82 83 83A 84 85 86 87 88 Notes: 1. 2. 3. 4. Characteristic L1RCLK, L1TCLK Frequency (DSC = 0)(1)(3) L1RCLK, L1TCLK Width Low (DSC = 0) (3) (2) Min - P+10 P+10 - 20 35 - 17 13 10 10 10 10 (4) Max SYNCCLK/2.5 Unit MHz ns L1RCLK, L1TCLK Width High (DSC = 0) - 15 - - 15 - - 45 45 45 55 55 42 16 or SYNCCLK/2 - - 30 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns L1TCLK ns ns ns L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time) L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time) L1RSYNC, L1TSYNC Rise/Fall Time L1RXD Valid to L1CLK Edge (L1RXD Setup Time) L1CLK Edge to L1RXD Invalid (L1RXD Hold Time) L1CLK Edge to L1ST(1-4) Valid L1SYNC Valid to L1ST(1-4) Valid(4) L1CLK Edge to L1ST(1-4) Invalid L1CLK Edge to L1TXD Valid L1TSYNC Valid to L1TXD Valid 10 0 - P+10 (2) L1CLK Edge to L1TXD High Impedance L1RCLK, L1TCLK Frequency (DSC = 1) L1RCLK, L1TCLK Width Low (DSC = 1) L1RCLK, L1TCLK Width High (DSC = 1) P+10 - 1 42 42 L1CLK Edge to L1CLKO Valid (DSC = 1) L1RQ Valid Before Falling Edge of L1TSYNC(4) L1GR Setup Time L1GR Hold Time (3) L1CLK Edge to L1SYNC Valid - 0 (FSD = 00, CNT = 0000, BYT = 0, DSC = 0) The ratio SyncCLK/L1RCLK must be greater than 2.5/1. Where P = 1/CLKO1. Thus for a 25 MHz CLKO1 rate, P = 40 ns. These specs are valid for IDL mode only. The strobes and Txd on the first bit of the frame becomes valid after L1CLK edge or L1SYNC, whichever is later. 65 2129A-HIREL-08/02 Figure 54. SI Receive Timing Diagram With Normal Clocking (DSC = 0) 71A 71 L 1RCLK (FE=0, CE=0) (IN PUT) 72 L 1RCLK (FE=1, CE=1) (IN PUT) 75 L 1RSYNC (IN PUT) 73 74 L1RXD (IN PUT) 76 L1ST(1--4) (OUTPUT) 78 79 77 BIT 0 70 RFSD=1 66 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 55. SI Receive Timing with Double-Speed Clocking (DSC = 1) L 1RCLK (FE=0, CE=0) (IN PUT) 72 L 1RCLK (FE=1, CE=1) (IN PUT) 82 83a 75 L 1RSYNC (IN PUT) RFSD=1 73 74 L1RXD (IN PUT) 76 78 L1ST(1--4) (OUTPUT) BIT 0 77 79 84 L1CLKO (OUTPUT ) 67 2129A-HIREL-08/02 Figure 56. SI Transmit Timing Diagram (DSC = 0) 71 L1TCLK (FE=0, CE=0) (IN PUT) 72 L1TCLK (FE=1, CE=1) (IN PUT) 73 75 L1TSYNC (IN PUT) 74 TFSD=0 80a L1TX D (OUTPUT) 78a L1ST(1--4) (OUTPUT) 78 BIT 0 80 79 81 70 68 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 57. SI Transmit Timing with Double Speed Clocking (DSC = 1) L1RCLK (FE=0, CE=0) (Input) 72 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input) 73 74 L1TXD (Output) BIT0 80 78a L1ST(4-1) (Output) 78 84 L1CLKO (Output) 79 81 83a 69 2129A-HIREL-08/02 Figure 58. IDL Timing 70 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 71 71 74 B17 B16 72 81 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M B17 B16 B15 B14 B13 76 78 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 85 86 87 L1RCLK (Input) 1 TSPC860 73 L1RSYNC (Input) 80 L1TXD (Output) 77 L1RXD (Input) L1ST(4-1) (Output) L1RQ (Output) L1GR (Input) 2129A-HIREL-08/02 TSPC860 SCC In NMSI Mode - External Clock Electrical Specifications The electrical specifications in this document are preliminary. All Frequencies Num 100 101 102 103 104 105 106 107 108 Notes: Characteristic RCLK1 and TCLK1 Width High16 RCLK1 and TCLK1 Width Low RCLK1 and TCLK1 Rise/Fall Time TXD1 Active Delay (From TCLK1 Falling Edge) RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) CTS1 Setup Time to TCLK1 Rising Edge RXD1 Setup Time to RCLK1 Rising Edge RXD1 Hold Time from RCLK1 Rising Edge CD1 Setup Time to RCLK1 Rising Edge (2) (1) Min 1/SYNCCLK 1/SYNCCLK+5 - 0 0 5 5 5 5 Max - - 15 50 50 - - - - Unit ns ns ns ns ns ns ns ns ns 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1. 2. Also applies to CD and CTS hold time when they are used as an external sync signals. SCC in NMSI Mode - Internal Clock Electrical Specifications The electrical specifications in this document are preliminary. Table 16. NMSI External Clock Timing All Frequencies Num 100 102 103 104 105 106 107 108 Notes: Characteristic RCLK1 and TCLK1 RCLK1 and TCLK1 Rise/Fall Time TXD1 Active Delay (From TCLK1 Falling Edge) RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) CTS1 Setup Time to TCLK1 Rising Edge RXD1 Setup Time to RCLK1 Rising Edge RXD1 Hold Time from RCLK1 Rising Edge CD1 Setup Time to RCLK1 Rising Edge (2) Min 0 - 0 0 40 40 0 40 Max SYNCCLK/3 - 30 30 - - - - Unit MHz ns ns ns ns ns ns ns 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1 2. Also applies to CD and CTS hold time when they are used as an external sync signals. 71 2129A-HIREL-08/02 Figure 59. SCC NMSI Receive Timing Diagram 102 RCLK1 100 106 RXD1 (IN PUT) 107 108 CD1 (IN PUT) 107 CD1 (SYNC IN PUT) 102 101 Figure 60. SCC NMSI Transmit Timing Diagram 102 TCLK 1 102 103 TXD1 (OUTPUT) 105 RTS1 (OUTPUT) 104 CTS1 (IN PUT) 107 CTS1 (SYNC IN PUT) 104 100 101 72 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 61. HDLC Bus Timing Diagram 102 TCLK 1 102 103 TXD1 (OUTPUT) 104 RTS1 (OUTPUT) 107 105 CTS1 (ECHO IN PUT 104 100 101 Ethernet Electrical Specifications All Frequencies Num 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Characteristic CLSN Width High RCLK1 Rise/Fall Time RCLK1 Width Low RCLK1 Clock Period(1) RXD1 Setup Time RXD1 Hold Time RENA Active Delay (From RCLK1 Rising Edge of the Last Data Bit) RENA Width Low TCLK1 Rise/Fall Time TCLK1 Width Low TCLK1 Clock Period (1) Min 40 - 40 80 20 5 10 100 - 40 99 10 10 10 10 10 10 1 (2) Max - 15 - 120 - - - - 15 - 101 50 50 50 50 50 50 - 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK ns ns TXD1 Active Delay (From TCLK1 Rising Edge) TXD1 Inactive Delay (From TCLK1 Rising Edge) TENA Active Delay (From TCLK1 Rising Edge) TENA Inactive Delay (From TCLK1 Rising Edge) RSTRT Active Delay (From TCLK1 Falling Edge) RSTRT Inactive Delay (From TCLK1 Falling Edge) REJECT Width Low CLKO1 Low to SDACK Asserted - 139 CLKO1 Low to SDACK Negated(2) - Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1 2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. 73 2129A-HIREL-08/02 Figure 62. Ethernet Collision Timing Diagram CLSN(CTS1) (IN PUT) 120 Figure 63. Ethernet Receive Timing Diagram 121 RCLK1 124 RXD1 (IN PUT) 125 127 RENA (CD1) (IN PUT) 126 123 121 LA ST BIT Figure 64. Ethernet Transmit Timing Diagram 128 TCLK 1 121 131 TXD1 (OUTPUT) 133 TENA (RTS1) (IN PUT) 134 132 128 129 RENA (CD1) (IN PUT) (NOTE 2) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. 74 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 65. CAM Interface Receive Start Timing Diagram RCLK1 RXD1 (IN PUT) 0 1 START FRAM E 1 bit #1 bit #2 136 125 RSTRT (OUTPUT) Figure 66. CAM Interface REJECT Timing Diagram 137 SMC Transparent AC Electrical specifications All Frequencies Num 150 151 151A 152 153 154 Characteristic SMCLK Clock Period SMCLK Width Low SMCLK Width High SMCLK Rise/Fall Time TXD1 Active Delay (From CLK1 Falling Edge) RXD1/SYNC1 Setup Time (1) Min 100 50 50 - 10 20 5 Max - - - 15 50 - - Unit ns ns ns ns ns ns ns 155 RXD1/SYNC1 Hold Time Note: 1. The ratio SYNCCLK/SMCLK must be greater or equal to 2/1. 75 2129A-HIREL-08/02 Figure 67. SMC Transparent Timing Diagram 152 152 SMCL K 150 TXD1 (OUTPUT) 151 151a 154 155 (1) 153 SYNC1 154 155 RXD1 (IN PUT) Note: 1. This delay is equal to an integer number of "character length" clocks. SPI Master AC Electrical Specifications All Frequencies Num 160 161 162 163 164 165 166 167 Characteristic Master Cycle Time Master Clock (SCK) High or Low Time Master Data Setup Time (Inputs) Master Data Hold Time (Inputs) Master Data Valid (After SCK Edge) Master Data Hold Time (Outputs) Rise Time Output Fall Time Output Min 4 2 50 0 - 0 - - Max 1024 512 - - 20 - 15 15 Unit tcyc tcyc ns ns ns ns ns ns 76 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 68. SPI Master (CP = 0) Timing Diagram 160 161 161 SPICL K Ci=0 OUTPUT 163 SPICL K Ci=1 OUTPUT 166 162 SPIMI SO IN PUT msb in data lsbin 164 SPIMOSI OUTPUT MSB OUT 167 165 data L SB OUT 166 MSBOUT msbin 167 167 166 Figure 69. SPI Master (CP = 1) Timing Diagram 160 161 SPICL K 161 Ci=0 OUTPUT 163 SPICL K Ci=1 OUTPUT 166 162 SPIMI SO IN PUT SPIMOSI OUTPUT msb in data lsbin 164 165 MSB OUT 167 data L SB OUT 166 MSBOUT msbin 167 167 166 77 2129A-HIREL-08/02 SPI Slave AC Electrical Specifications All Frequencies Num 170 171 172 173 174 175 176 177 Characteristic Slave Cycle Time Slave Enable Lead Time Slave Enable Lag Time Slave Clock (SPICLK) High or Low Time Slave Sequential Transfer Delay (Does Not Require Deselect) Slave Data Setup Time (Inputs) Slave Data Hold Time (Inputs) Slave Access Time Min 2 15 15 1 1 20 20 - Max - - - - - - - 50 Unit tcyc ns ns tcyc tcyc ns ns ns Figure 70. SPI Slave (CP = 0) Timing Diagram 172 SPISEL IN PUT 173 173 SPICL K Ci=0 IN PUT 182 170 181 174 171 SPICL K Ci=1 IN PUT 177 180 SPIMI SO OUTPUT 175 176 SPIMOSI IN PUT MSB IN MSB OUT 181 182 DAT A L SB OUT 179 178 UNDE F MSB OUT DAT A 182 LSB IN 181 M SB IN 78 TSPC860 2129A-HIREL-08/02 TSPC860 Figure 71. SPI Slave (CP = 1) Timing Diagram 172 SPISEL IN PUT 173 173 SPICL K Ci=0 IN PUT 171 181 SPICL K Ci=1 IN PUT 182 177 SPIMI SO OUTPUT UNDE F 175 176 SPIMOSI IN PUT MSBIN 182 DAT A 181 L SBIN MSBIN MSBOUT DAT A 179 L SBOUT MSBOUT 180 178 181 170 182 174 TWI AC Electrical Specifications - SCL < 100 kHz All Frequencies Num 200 200 202 203 204 205 206 207 208 209 210 211 Notes: Characteristic SCL Clock Frequency (SLAVE) SCL Clock Frequency (MASTER) (1) Min 0 1.5 4.7 4.7 4.0 4.7 4.0 0 250 - - 4.7 Max 100 100 - - - - - - - 1 300 - Unit KHz KHz s s s s s s ns s ns s Bus Free Time Between Transmissions LOW Period of SCL HIGH Period of SCL START Condition Setup Time START Condition Hold Time DATA Hold Time DATA Setup Time SDL/SCL Rise Time SDL/SCL Fall Time STOP Condition Setup Time 1. SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) * pre_scaler * The ratio SYNCCLK/(BRGCLK/pre_scaler) must be greater or equal to 4/1. 79 2129A-HIREL-08/02 TWI AC Electrical Specifications - SCL > 100 kHz Num 200 200 202 203 204 205 206 207 208 209 210 Characteristic SCL Clock Frequency (SLAVE) SCL Clock Frequency (MASTER)(1) Bus Free Time Between Transmissions LOW Period of SCL HIGH Period of SCL START Condition Setup Time START Condition Hold Time DATA Hold Time DATA Setup Time SDL/SCL Rise Time SDL/SCL Fall Time Expression fSCL fSCL Min 0 BRGCLK/16512 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 0 1/(40 * fSCL) - - Max BRGCLK/48 BRGCLK/48 - - - - - - - 1/(10 * fSCL) 1/(33 * fSCL) - Unit Hz Hz s s s s s s s s s s 211 STOP Condition Setup Time 1/(2.2 * fSCL) Notes: 1. SCL frequency is given by SCL = BrgClk_frequency/((BRG register + 3) * pre_scaler The ratio SYNCCLK/(BRG_CLK/pre_scaler) must be greater or equal to 4/1. Figure 72. TWI Bus Timing Diagram SDA 202 205 SCL 209 206 210 211 203 207 204 208 80 TSPC860 2129A-HIREL-08/02 TSPC860 Preparation For Delivery Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. Power Consideration The average chip-junction temperature, Tj, in C can be obtained from the equation: Tj = TA + (PD * JA) where TA = Ambient temperature, C JA = Package thermal resistance, junction to ambient, C/W PD = PINT + PI/O PINT = IDD x VDD, watts - chip internal power PI/O = Power dissipation on input and output pins - user determined For most applications PI/O < 0.3 * PINT and can be neglected. If PI/O is neglected, an approximate relationship between PD and TJ is: PD = K / (TJ + 273C) Solving equations (1) and (2) for K gives: K = PD * T (TA + 273C) + JA * PD2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P D (at equilibrium) for a known T A. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2) (1) Layout Practices Each VCC pin on the TSPC860 should be provided with a low-impedance path to the board's supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 F bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the TSPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient current in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. 81 2129A-HIREL-08/02 Functional Units Description The TSPC860 PowerQUICC integrates the Embedded PowerPC Core with high performance, low power peripherals to extend the Motorola Data Communications family of embedded processors even farther into high end communications and networking products. The TSPC860 PowerQUICC is comprised of three modules which all use the 32-bit internal bus: the Embedded PowerPC Core, the System Integration Unit (SIU), and the Communication Processor Module (CPM). The TSPC860 PowerQUICC block diagram is shown in Figure 1. The Embedded PowerPC Core is compliant with the Book 1 specification for the PowerPC architecture. The Embedded PowerPC Core is a fully static design that consists of two functional blocks; the integer block and the load/store block. It executes all integer and load/store operations directly on the hardware. The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. The core interface to the internal and external buses is 32 bits. The core uses a two instruction load/store queue, a four instruction prefetch queue, and a six instruction history buffer. The core does branch folding and branch prediction with conditional pre-fetch but without conditional execution. The Embedded PowerPC Core can operate on 32-bit external operands with one bus cycle. The PowerPC integer block supports 32 x 32-bit fixed point general purpose registers. It can execute one integer instruction each clock cycle. Each element in the integer block is clocked only when valid data is present in the data queue ready for operation. This assures that the power consumption of the device is held to the absolute minimum required to perform an operation. The Embedded PowerPC Core is integrated with MMU's as well as 4 kbyte instruction and data caches. Each MMU provides a 32 entry, fully associative instruction and data TLB, with multiple page sizes of: 4 KB, 16 KB, 512 KB, 256 KB and 8 MB. It will support 16 virtual address spaces with 8 protection groups. Three special registers are available as scratch registers to support software table walk and update.The instruction cache is 4 kilobytes, two-way, set associative with physical addressing. It allows single cycle access on hit with no added latency for miss. It has four words per line, supporting burst line fill using Least Recently Used (LRU) replacement. The cache can be locked on a per line basis for application critical routines. The data cache is 4 kilobytes, two-way, set associative with physical addressing. It allows single cycle access on hit with one added clock latency for miss. It has four words per line, supporting burst line fill using LRU replacement. The cache can be locked on a per line basis for application critical routines. The data cache can be programmed to support copy-back or write-through via the MMU. The inhibit mode can be programmed per MMU page. The Embedded PowerPC Core with its Instruction and data caches delivers approximately 52 MIPS at 40 MHz, using Dhrystone 2.1, based on the assumption that it is issuing one instruction per cycle with a cache hit rate of 94%. The Embedded PowerPC Core contains a much improved debug interface that provides superior debug capabilities without causing any degradation in the speed of operation. This interface supports six watchpoint pins that are used to detect software events. Internally it has eight comparators, four of which operate on the effective address on the address bus. The remaining four comparators are split, with two comparators the effective address on the data bus, and two comparators operating on the data on the data bus. The Embedded PowerPC Core can compare using =, , <, > conditions to generate watchpoints. Each watchpoint can then generate a breakpoint that can be programmed to trigger in a programmable number of events. Embedded PowerPC Core 82 TSPC860 2129A-HIREL-08/02 TSPC860 System Interface Unit (SIU) The SIU on the TSPC860 PowerQUICC integrates general-purpose features useful in almost any 32-bit processor system, enhancing the performance provided by the system integration module (SIM) on the TS68EN360 QUICC device. Although the Embedded PowerPC Core is always a 32-bit device internally, it may be configured to operate with an 8-, 16- or 32-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode. The SIU also provides power management functions, Reset control, PowerPC decrementer, PowerPC time base and PowerPC real time clock. The memory controller will support up to eight memory banks with glueless interfaces to DRAM, SRAM, SSRAM, EPROM, Flash EPROM, SRDRAM, EDO and other peripherals with two-clock access to external SRAM and bursting support. It provides variable block sizes from 32 kilobytes to 256 megabytes. The memory controller will provide 0 to 15 wait states for each bank of memory and can use address type matching to qualify each memory bank access. It provides four byte enable signals for varying width devices, one output enable signal and one boot chip select available at reset. The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be defined in depths of 256K, 512k, 1M, 2M, 4M, 8M, 16M, 32M, or 64M for all port sizes. In addition the memory depth can be defined as 64K and 128K for 8-bit memory or 128M and 256M for 32-bit memory. The DRAM controller supports page mode access for successive transfers within bursts. The TSPC860 will support a glueless interface to one bank of DRAM while external buffers are required for additional memory banks. The refresh unit provides CAS before RAS, a programmable refresh timer, refresh active during external reset, disable refresh modes, and stacking up to 7 refresh cycles. The DRAM interface uses a programmable state machine to support almost any memory interface. PCMCIA Controller The PCMCIA interface is a master (socket) controller and is compliant with release 2.1. The interface will support up to two independent PCMCIA sockets requiring only external transceivers/buffers. The interface provides 8 memory or I/O windows where each window can be allocated to a particular socket. If only one PCMCIA port is being used, the unused PCMCIA port may be used as general-purpose input with interrupt capability. The TSPC860 PowerQUICC supports a wide range of power management features including Full On, Doze, Sleep, Deep Sleep, and Low Power Stop. In Full On mode the TSPC860 processor is fully powered with all internal units operating at the full speed of the processor. A Gear mode is provided which is determined by a clock divider, allowing the OS to reduce the operational frequency of the processor. Doze mode disables core functional units other than the time base decrementer, PLL, memory controller, RTC, and then places the CPM in low power standby mode. Sleep mode disables everything except the RTC and PIT, leaving the PLL for lower power but slower wake-up. Low Power Stop disables all logic in the processor except the minimum logic required to restart the device, providing the lowest power consumption but requiring the longest wake-up time. Power Management 83 2129A-HIREL-08/02 Communications Processor Module (CPM) The TSPC860 PowerQUICC is the next generation TS68EN360 QUICC and like its predecessor implements a dual processor architecture. This dual processor architecture provides both a high performance general purpose processor for application programming use as well as a special purpose communication processor (CPM) uniquely designed for communications needs. The CPM contains features that allow the TSPC860 PowerQUICC to excel in communications and networking products as did the TS68EN360 QUICC which preceded it. These features may be divided into three sub-groups: * * * Communications Processor (CP) Sixteen Independent DMA (SDMA) Controllers Four General-Purpose Timers The CP provides the communication features of the TSPC860 PowerQUICC. Included are a RISC processor, four Serial Communication Controllers (SCC) four Serial Management Controllers (SMC), one Serial Peripheral Interface (SPI), one I2 Interface, 5 kilobytes of dual-port RAM, an interrupt controller, a time slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and sixteen serial DMA channels to support the SCCs, SMCs, SPI, and TWI. The SDMAs provide two channels of general-purpose DMA capability for each communications channel. They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. The four general-purpose timers on the CPM are identical to the timers found on the MC68360 and still support the internal cascading of two timers to form a 32-bit timer. The TSPC860 PowerQUICC maintains the best features of the TS68EN360 QUICC, while making changes required to provide for the increased flexibility, integration, and performance requested by customers demanding the performance of the powerPC architecture. The addition of a Multiply-And-Accumulate (MAC) function on the CPM further enhances the TSPC860 PowerQUICC, enabling various modem and DSP applications. Because the CPM architectural approach remains intact between the TSPC860 PowerQUICC and the TS68EN360 QUICC, a user of the TS68EN360 QUICC can easily become familiar with the TSPC860 PowerQUICC. 84 TSPC860 2129A-HIREL-08/02 TSPC860 Software Compatibility Issues The following list summarizes the major software differences between the TS68EN360 QUICC and the TSPC860 PowerQUICC: * Since the TSPC860 PowerQUICC uses an Embedded PowerPC Core, code written for the TS68EN360 must be recompiled for the PowerPC instruction set. Code which accesses the TS68EN360 peripherals requires only minor modifications for use with the TSPC860. Although the functions performed by the PowerQUICC SIU are similar to those performed by the QUICC SIM, the initialization sequence for the SIU is different and therefore code that accesses the SIU must be rewritten. Many developers of 68K compilers now provide compilers which also support the PowerPC architecture. The addition of the MAC function to the TSPC860 CPM block to support the needs of higher performance communication software is the only major difference between the CPM on the TS68EN360 and that on the TSPC860. Therefore the registers used to initialize the QUICC CPM are similar to the TSPC860 CPM, but there are some minor changes necessary for supporting the MAC function. When porting code from the TS68EN360 CPM to the TSPC860 CPM, the software writer will find new options for hardware breakpoint on CPU commands, address, and serial request which are useful for software debugging. Support for single step operation with all the registers of the CPM visible makes software development for the CPM on the TSPC860 processor even simpler. * * TSPC860 PowerQUICC Glueless System Design A fundamental design goal of the TSPC860 PowerQUICC was ease of interface to other system components. Figure 72 on page 80 shows a system configuration that offers one EPROM, one flash EPROM, and supports two DRAM SIMMs. Depending on the capacitance on the system bus, external buffers may be required. From a logic standpoint, however, a glueless system is maintained. Figure 73. TSPC860 System Configuration PowerQUICC MPC860 CS0 OE Data Address 8-bit boot EPROM (Flash or Regular) CE (Enable) OE (Output Enable) WE (Write) Data Address 8, 16 or 32-bit SRAM CS7 WE[3-0] E (Enable) G (Output Enable) W (Write) Data Address 16 or 32 Bit Two DRAM SIMMs (Optional Parity) RAS2 RAS1 CAS[3-0] Buffer PRTY[3-0] RAS RAS CAS[3-0] W (write) Data Address Parity 85 2129A-HIREL-08/02 Preparation For Delivery Marking Each microcircuit is legible and permanently marked with the following information at minimum: * * * * * * ATMEL logo, Manufacturer's part number, Class B identification if applicable, Date-code of inspection lot, ESD identifier if available, Country of manufacturing. Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: a) Devices should be handled on benches with conductive and grounded surfaces. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50% if practical. 86 TSPC860 2129A-HIREL-08/02 TSPC860 Package Dimensions Plastic Ball Grid Array 4X 0.20 A C 0.20 C 0.25 C 0.35 C D E2 E D2 TOP VIEW D1 18X B e NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETER S. 3. DIMENSION b IS THE SOLDER BALL DIAMETERMEASURED PARALLEL TO DATUM C. MILLIMETERS DI M MI N M AX A -----2.05 A1 0.50 0.70 A2 0.95 1.35 A3 0.70 0.90 b 0.60 0.90 D 25.00 BSC D1 22.86 BSC D2 22.40 22.60 e 1.27 BSC E 25.00 BSC E1 22.86 BSC E2 22.40 22.60 W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 A2 A3 A1 E1 A SIDE VIEW 357X b 0.03 M C A B 0.15 M C BOTTOM VIEW 87 2129A-HIREL-08/02 Ordering Information TS (X) PC860 SR M ZP U 66 D Revision level Prefix Prototype Type Version MH, SR Temperature range : TC M : -55, +125C V : -40, +110C B: rev B. 0 C1: rev C.1 D4: rev D.4 Max internal processor speed (2) 40 50 66 80 : : : : 40 MHz 50 MHz 66 MHz (SR only) 80 MHz (SR only) (TBC) Screening level (1) U Package ZP : PBGA : Upscreening (1) For availability of the different versions, contact your sales office. Definitions Datasheet Status Objective Specification Target Specification Preliminary Specification site Preliminary Specification site Product Specification Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. This datasheet contains target and goal specification for discussion with customer and application validation. This datasheet contains target or goal specification for product development. This datasheet contains preliminary data. Additional data may be published later; could include simulation result. This datasheet also contains characterization results. This datasheet contains final product specification. Validity Before design phase. Valid during the design phase. Valid before characterization phase. Valid before the industrialization phase. Valid for production purpose. 88 TSPC860 2129A-HIREL-08/02 TSPC860 Life Support Applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 89 2129A-HIREL-08/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. The PowerPC names and the PowerPC logotype are trademarks of International Business Machines Corporation, used under license therform. Motorola is the registered trademark of Motorola, Inc. Other terms and product names may be the trademarks of others. 2129A-HIREL-08/02 0M |
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