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| High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM(R) Embedded Memory Macro M1T1HT18PZ32E * High Performance 1T-SRAM Standard Macro * 200 MHz operation * 1-Clock cycle time * Pipelined read access timing * Late-late write mode timing * 32-Bit wide data buses * Byte Write Enables * Simple standard SRAM interface * Fast delivery * Ultra-Dense Memory 2 * 3.8mm size per macro instance * Redundancy & fuses included in macro area * Silicon-Proven 1T-SRAM Technology * Qualification programs completed * Products in volume production * High Yield and Reliability * Built-in redundancy for enhanced yield * Standard Logic Process * TSMC 0.18m CL018G process * Logic design rules * Uses 4 metal layers * Routing over macro possible in layers 5+ * Power * Single voltage 1.8V Supply * Low power consumption adr[14:0] din[31:0] dout[31:0] bweb[3:0] rdb wrb clk rstb mvddcore mvsscore mvdd mvss General Description The M1T1HT18PZ32E macro is a 1Mbit (1,084,576 bits), high speed, embedded 1T-SRAM macro. The macro is organized as 32K(32,768) words of 32 bits. The macro employs a pipelined read timing interface with late write timing. Write control over individual bytes in the input data is achieved through the use of the byte write enable (bweb) input signals. The macro is implemented using MoSys 1T -SRAM technology, resulting in extremely high density and performance. M1T1HT18PZ32E Rev 2.doc (c) 2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 Page 1 High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM(R) Embedded Memory Macro M1T1HT18PZ32E Memory Interface Signal List Signal Name adr[14:0] bweb[3:0] Valid Positive clk edge Positive clk edge Logic Positive Negative Direction Input Input rdb wrb din[31:0] dout[31:0] rstb clk mvddcore mvsscore mvdd mvss Positive clk edge Positive clk edge Positive clk edge Positive clk edge Positive clk edge Clock Negative Negative Positive Positive Negative Positive Input Input Input Output Input Input Description Memory address Memory byte write enables bweb[n] = 0 enables data write bweb[n] = 1 disables data write bweb[3] controls writing of din[31:24] bweb[2] controls writing of din[23:16] bweb[1] controls writing of din[15:8] bweb[0] controls writing of din[7:0] Memory read Memory write Memory data in bus Memory data out bus Memory initialization reset Memory Clock Memory core supply voltage Memory core ground Memory interface supply voltage Memory interface ground Recommended Operating Conditions Symbol VDD TJ tCYC tCKH tCKL Parameter Supply Voltage Range (1.8V 10%) Junction Temperature Cycle Time Clock High Clock Low Condition Operating Nominal VDD Operating Operating Operating Min 1.62 0 5.0 0.45*tCYC 0.45*tCYC Max 1.98 125 33* 0.55*tCYC 0.55*tCYC Units V C ns ns ns Note*: Minimum clock frequency limit adjustable to meet system timing requirements Power Requirements Symbol IDD1 IDD2 Input Loading Symbol CDIN CADR CCTL CCLK Condition din signal input loading adr signal input loading rdb, wrb, bweb, rstb signal input loading clk signal input loading Load Capacitance 0.2 0.2 0.2 0.5 Units pF pF pF pF Condition Operating current, VDD=1.8V, clock frequency = 200MHz, output not loaded, memory accessed every clock Idle current, VDD =1.8V, clock frequency =200MHz, memory not accessed Current per Instance 0.7 0.3 Units mA/MHz mA/MHz M1T1HT18PZ32E Rev 2.doc (c) 2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 Page 2 High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM(R) Embedded Memory Macro M1T1HT18PZ32E AC Timing Characteristics at Recommended Operating Conditions All times in nanoseconds Bolded numbers reflect the critical timing parameters Parameter tAS tAH tCS tCH tDS tDH tKQ tKQE tKQX Description Address Setup Address Hold Control Setup Control Hold Write Data Setup Write Data Hold Clock to Data Valid Data valid extrinsic delay per pF Clock to Data not valid Condition Min. Min. Min. Min. Min. Min. Max. Max. Min. Slow 1.0 0.5 1.0 0.5 1.0 0.5 3.3 0.8 0.8 Typical 0.8 0.4 0.8 0.4 0.8 0.4 2.9 0.6 0.6 Fast 0.6 0.3 0.6 0.3 0.6 0.3 2.5 0.4 0.4 tCYC clk tAS adr bweb A tAH tCS control wrb/rdb tCKL tCKH tCH dout tKQ rD tKQX din wD tDS tDH . General AC Timing M1T1HT18PZ32E Rev 2.doc (c) 2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 Page 3 High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM(R) Embedded Memory Macro M1T1HT18PZ32E Memory macro implements a synchronous reset to force state machines into a known state after power-up. This reset does not clear the memory contents. The clock must be running for at least two cycles before the Reset (rstb) signal will be correctly sampled as shown above. The Reset (rstb) signal must be active for at least ten (10) clock periods to initialize all internal circuitry. Independent of the Reset (rstb) signal, after power has stabilized to a voltage within the operating specification and the clock is operating within its timing specifications, there must be at least 128 clock cycles before any read or write access. >128 clk clk >10 clk rstb rdb or wrb Initialization Timing M1T1HT18PZ32E Rev 2.doc (c) 2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 Page 4 High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM(R) Embedded Memory Macro M1T1HT18PZ32E OPERATION TRUTH TABLE rdb 0 0 1 1 wrb 0 1 0 1 Operation Illegal Read Write Nop FUNCTIONAL OPERATION Address and command clocked in by rising clock edge. Read data transfers occur in the clock cycle following the next clock rising edge. Write data transfers occur in the following clock cycle This standard macro uses user-managed refresh hiding. Review conditions with MoSys to finalize the specification. clk clk adr A adr bweb A rdb wrb dout rD din rW S Single Cycle Read Timing Single Cycle Write M1T1HT18PZ32E Rev 2.doc (c) 2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 Page 5 High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM(R) Embedded Memory Macro M1T1HT18PZ32E clk adr bweb A B C D E wrb WR WR rdb RD RD dout rDA rDC rDD din wDB wDE Multiple Cycle Timing MEMORY BLOCK ESTIMATES* 1650um 2 Mem Core Power and 2 Mem Core Ground 32Kx32 1T-SRAM 2300um 2 Mem I/F Power and 2 Mem I/F Ground I/F Digital Interface Pins Note*: Approximate dimensions. Exact dimensions appear on place and route phantom Physical Layout M1T1HT18PZ32E Rev 2.doc (c) 2004 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 Page 6 |
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