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CMOS Static RAM 256K (32K x 8-Bit) Features High-speed address/chip select time - Military: 25/35/45/55/70/85/100ns (max.) - Industrial: 25/35ns (max.) - Commercial: 20/25/35ns (max.) low power only Low-power operation Battery Backup operation - 2V data retention Produced with advanced high-performance CMOS technology Input and output directly TTL-compatible Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and 32-pin LCC Military product compliant to MIL-STD-883, Class B IDT71256S IDT71256L Description The IDT 71256 is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Address access times as fast as 20ns are available with power consumption of only 350mW (typ.). The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to and remain in, a low-power standby mode as long as CS remains HIGH. In the full standby mode, the low-power device consumes less than 15W, typically. This capability provides significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 5W when operating off a 2V battery. The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil SOJ, a 28-pin (600 mil) plastic DIP, and a 32-pin LCC providing high board level packing densities. The IDT71256 military RAM is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. x x x x x x x Functional Block Diagram A0 ADDRESS DECODER A14 262,144 BIT MEMORY ARRAY VCC GND I/O0 INPUT DATA CIRCUIT I/O7 I/O CONTROL CS OE WE , CONTROL CIRCUIT 2946 drw 01 FEBRUARY 2001 1 (c)2000 Integrated Device Technology, Inc. DSC-2946/9 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Pin Configurations A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 Truth Table(1) WE CS H VHC L L L OE X X H L X I/O High-Z High-Z High-Z DOUT DIN Function Standby (ISB) Standby (ISB1) Output Disabled Read Data Write Data 2946 tbl 02 D28-3 P28-1 D28-1 SO28-5 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 2946 drw 02 X X H H L NOTE: 1. H = VIH, L = VIL, X = Don't care. DIP/SOJ Top View INDEX Absolute Maximum Ratings(1) Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. Ind. Mil. Unit V -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 A7 A12 1 A1 A14 NC V VCC A WE A13 TA TBIAS 0 to +70 -40 to +85 -55 to +125 o C C 43 2 1 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 13 32 31 30 29 28 27 26 L32-1 25 24 23 22 21 A8 A9 A11 NC OE A10 CS I/O7 I/O8 , , 2946 drw 03 -55 to +125 -55 to +125 -65 to +135 o TSTG PT IOUT -55 to +125 -55 to +125 -65 to +150 1.0 50 1.0 50 1.0 50 o C W mA 2946 tbl 03 14 15 16 17 18 19 20 32-Pin LCC Top View NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. I/O1 I/O2 GND NC I/O3 I/O4 I/O5 Pin Descriptions Name A0 - A14 I/O0 - I/O7 CS WE OE GND VCC Description Address Inputs Data Input/Output Chip Select Write Enable Output Enable Ground Power 2946 tbl 01 Capacitance (TA = +25C, f = 1.0MHz) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. 11 11 Unit pF pF 2946 tbl 04 NOTE: 1. This parameter is determined by device characterization, but is not production tested. 2 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Grade Military Industrial Commercial Temperature -55OC to +125OC -40OC to +85OC 0 C to +70 C O O Recommended DC Operating Conditions Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 ____ GND 0V 0V 0V Vcc 5V 10% 5V 10% 5V 10% 2946 tbl 05 Max. 5.5 0 6.0 0.8 Unit V V V V 2946 tbl 06 ____ NOTE: 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle. DC Electrical Characteristics(1,2) (VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71256S/L20 Power Symbol ICC Parameter Dynamic Operating Current CS < VIL, Outputs Open VCC = Max., fMAX(2) Standby Power Supply Current (TTL Level), CS > VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level), CS > VHC, VCC = Max., f = 0 S L S L S L ____ ____ 71256S/L25 Com'l & Ind ____ 71256S/L35 Com'l. & Ind ____ 71256S/L45 Com'l. ____ Com'l. Mil. Mil. 150 130 20 3 20 1.5 Mil. 140 120 20 3 20 1.5 Mil. Unit 135 115 20 3 20 1.5 2946 tbl 07 mA 135 ____ ____ 115 ____ 105 ____ ____ ISB ____ ____ mA 3 ____ ____ 3 ____ 3 ____ ____ ISB1 ____ ____ mA 0.4 ____ 0.4 0.4 ____ 71256S/L55 Symbol ICC Parameter Dynamic Operating Current CS < VIL, Outputs Open VCC = Max., fMAX(2) Standby Power Supply Current (TTL Level), CS > VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level), CS > VHC, VCC = Max., f = 0 Power S L S L S L Mil. 135 115 20 3 20 1.5 71256S/L70 Mil. 135 115 20 3 20 1.5 71256S/L85 Mil. 135 115 20 3 20 1.5 71256S/L100 Mil. 135 115 20 3 20 1.5 2946 tbl 08 Unit mA ISB mA ISB1 mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling. 6.42 3 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2 2946 tbl 09 5V 480 DATA OUT 255 30pF* DATA OUT 255 5V 480 5pF* , 2946 drw 04 2946 drw 05 , Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) Figure 1. AC Test Load *Includes scope and jig capacitances DC Electrical Characteristics (VCC = 5.0V 10%) IDT71256S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. VOH Output High Voltage IOH = -4mA, VCC = Min. MIL. COM"L & IND. MIL. COM"L & IND. Min. ____ ____ IDT71256L Max. 10 5 10 5 0.4 0.5 ____ Typ. ____ ____ Min. ____ ____ Typ. ____ ____ Max. 5 2 5 2 0.4 0.5 ____ Unit A A V ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 2.4 2.4 V 2946 tbl 10 Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V) Typ.(1) VCC @ Symbol VDR ICCDR tCDR Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CS > VHC Test Condition ____ Max. VCC @ 3.0V ____ Min. 2.0 ____ ____ 2.0V ____ 2.0V ____ 3.0V ____ Unit V A ns MIL. COM'L. & IND. ____ ____ ____ ____ 500 120 ____ 800 200 ____ 0 tRC(2) ____ ____ tR(3) ____ ____ ____ ____ ns 2946 tbl 11 NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. 4 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Low VCC Data Retention Waveform DATA RETENTION MODE VCC tCDR CS VIH 4.5V VDR 2V VIH 2946 drw 06 4.5V tR VDR AC Electrical Characteristics (VCC = 5.0V 10%, All Temperature Ranges) 71256L20(1) Symbol Parameter Min. Max. 71256S25 71256L25 Min. Max. 71256S35 71256L35 Min. Max. 71256S45(3) 71256L45(3) Min. Max. Unit Read Cycle tRC tAA tACS tCLZ(2) tCHZ(2) tOE tOLZ(2) tOHZ(2) tOH Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Desele ct to Output in High-Z Output Enable to Output Valid Output Enab le to Output in Low-Z Output Disab le to Output in High-Z Output Hold from Address Change 20 ____ ____ ____ 25 ____ ____ ____ 35 ____ ____ ____ 45 ____ ____ ____ ns ns ns ns ns ns ns ns ns 20 20 ____ 25 25 ____ 35 35 ____ 45 45 ____ 5 ____ 5 ____ 5 ____ 5 ____ 10 10 ____ 11 11 ____ 15 15 ____ 20 20 ____ ____ ____ ____ ____ 2 2 5 2 2 5 2 2 5 0 ____ 8 ____ 10 ____ 15 ____ 20 ____ 5 Write Cycle tWC tCW tAW tAS tWP tWR tDW tWHZ tDH tOW(2) (2) Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Write Enab le to Output in High-Z Data Hold from Write Time Output Active from End-of-Write 20 15 15 0 15 0 11 ____ ____ ____ 25 20 20 0 20 0 13 ____ ____ ____ 35 30 30 0 30 0 15 ____ ____ ____ 45 40 40 0 35 0 20 ____ ____ ____ ns ns ns ns ns ns ns ns ns ns 2946 tbl 12 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 10 ____ 11 ____ 15 ____ 20 ____ 0 5 0 5 0 5 0 5 ____ ____ ____ ____ NOTES: 1. 0 to +70C temperature range only. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. -55C to +125C temperature range only. 6.42 5 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V 10%, Military Temperature Ranges) 71256S55(1) 71256L55(1) Symbol Parameter Min. Max. 71256S70(1) 71256L70(1) Min. Max. 71256S85(1) 71256L85(1) Min. Max. 71256S100(1) 71256L100(1) Min. Max. Unit Read Cycle tRC tAA tACS tCLZ(2) tCHZ(2) tOE tOLZ(2) tOHZ(2) tOH Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Desele ct to Output in High-Z Output Enable to Output Valid Output Enab le to Output in Low-Z Output Disab le to Output in High-Z Output Hold from Address Change 55 ____ ____ 70 ____ ____ 85 ____ ____ 100 ____ ____ ns ns ns ns ns ns ns ns ns 55 55 ____ 70 70 ____ 85 85 ____ 100 100 ____ ____ ____ ____ ____ 5 ____ 5 ____ 5 ____ 5 ____ 25 25 ____ 30 30 ____ 35 35 ____ 40 40 ____ ____ ____ ____ ____ 0 0 5 0 0 5 0 ____ 0 ____ 25 ____ 30 ____ 35 ____ 40 ____ 5 5 Write Cycle tWC tCW tAW tAS tWP tWR tDW tWHZ(2) tDH tOW(2) Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Write Enab le to Output in High-Z Data Hold from Write Time (WE) Output Active from End-of-Write 55 50 50 0 40 0 25 ____ ____ 70 60 60 0 45 0 30 ____ ____ 85 70 70 0 50 0 35 ____ ____ 100 80 80 0 55 0 40 ____ ____ ns ns ns ns ns ns ns ns ns ns 2946 tbl 13 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 25 ____ 30 ____ 35 ____ 40 ____ 0 5 0 5 0 5 0 5 ____ ____ ____ ____ NOTES: 1. -55 to +125C temperature range only. 2. This parameter is guaranteed by device characterization, but is not production tested. 6 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE tOLZ (5) CS tACS tCLZ (5) DATAOUT 2946 drw 07 tOH tOHZ(5) tCHZ(5) Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT , 2946 drw 08 tOH Timing Waveform of Read Cycle No. 2(1,3,4) CS tACS tCLZ (5) DATAOUT 2946 drw 09 tCHZ(5) NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state. 6.42 7 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6) t WC ADDRESS tOHZ (5) OE tAW CS t AS WE tWZ (5) DATAOUT (3) t WP (6) tWR t OW (3) tDW DATAIN tDH 2946 drw 10 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4) tWC ADDRESS tAW CS t AS WE tDW DATAIN 2946 drw 11 tCW(6) t WR tDH2 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW. 8 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Ordering Information Commercial & Industrial IDT 71256 Device Type X Power XX Speed XXX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C) Y P 300 mil SOJ (SO28-5) 600 mil Plastic DIP (P28-1) 20 25 35 300 mil SOJ Only, Commercial Only Speed in nanoseconds , L Low Power Only 2946 drw 13 Ordering Information Military IDT 71256 Device Type X Power XXX Speed XXX Package X Process/ Temperature Range B Military (-55C to +125C) Compliant to MIL-STD-883, Class B TD D L32 300 mil CERDIP (D28-3) 600 mil CERDIP (D28-1) Leadless Chip Carrier (32-pin) (L32-1) 25 35 45 55 70 85 100 Speed in nanoseconds S L Standard Power Low Power 2946 drw 12 6.42 9 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Datasheet Document History 11/4/99 Pp. 1-5, 9 Pg. 1 Pg. 2 Pg. 3 Pg. 5 Pg. 6 Pg. 8 Pg. 9 Pg. 10 08/09/00 02/01/01 Updated to new format Added Industrial Temperature Range offerings Removed 30, 120, and 150ns military and 45ns commercial speed grade offerings. Removed P28-2 package from DIP/SOJ Top View Removed 30ns and 45ns (Commercial only) speed grade offerings from DC Electrical table Revised notes and footnotes Removed 30ns speed grade offering from AC Electrical table Revised notes and footnotes Expressed Military Temperature range on AC Electrical table Revised notes and footnotes Removed Note 1 and renumbered notes and footnotes Revised Ordering Information and presented by temperature range offering Added Datasheet Document History Not recommended for new designs Remove "Not recommended for new designs" CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax:408-492-8674 www.idt.com for Tech Support: sramhelp@idt.com 800 544-7726, x4033 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 10 |
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