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DS1232 MicroMonitor Chip
www.dalsemi.com
FEATURES
Halts and restarts an out-of-control microprocessor Holds microprocessor in check during power transients Automatically restarts microprocessor after power failure Monitors pushbutton for external override Accurate 5% or 10% microprocessor power supply monitoring Eliminates the need for discrete components Space-saving, 8-pin mini-DIP Optional 16-pin SOIC surface mount package Industrial temperature -40C to +85C available, designated N
PIN ASSIGNMENT
PBRST TD TOL GND 1 2 3 4 8 7 6 5 VCC ST RST RST
DS1232 8-Pin DIP (300-mil) See Mech. Drawings Section
NC PBRST NC TD NC TOL NC GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC VCC NC ST NC RST NC RST
DS1232S 16-Pin SOIC (300-mil) See Mech. Drawings Section
PIN DESCRIPTION
PBRST
TD TOL GND RST
RST ST
VCC NC
- Pushbutton Reset Input - Time Delay Set - Selects 5% or 10% VCC Detect - Ground - Reset Output (Active High) - Reset Output (Active Low, open drain) - Strobe Input - +5 Volt Power - No Connections
DESCRIPTION
The DS1232 MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply, software execution, and external override. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize. 1 of 7 111899
DS1232/DS1232S
The second function the DS1232 performs is pushbutton reset control. The DS1232 debounces the pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a watchdog timer. The DS1232 has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds.
OPERATION - POWER MONITOR
The DS1232 detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When VCC falls below a preset level as defined by TOL (Pin 3), the VCC comparator outputs the signals RST (Pin 5) and RST (Pin 6). When TOL is connected to ground, the RST and RST signals become active as VCC falls below 4.75 volts. When TOL is connected to VCC, the RST and RST signals become active as VCC falls below 4.5 volts. The RST and RST are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid VCC. On power-up, RST and RST are kept active for a minimum of 250 ms to allow the power supply and processor to stabilize.
OPERATION - PUSHBUTTON RESET
The DS1232 provides an input pin for direct connection to a pushbutton (Figure 2). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that RST and RST signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level.
OPERATION - WATCHDOG TIMER
A watchdog timer function forces RST and RST signals to the active state when the ST input is not stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to VCC. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive. If a high-to-low transition occurs on the ST input pin prior to timeout, the watchdog timer is reset and begins to timeout again. If the watchdog timer is allowed to timeout, then the RST and RST signals are driven to the active state for 250 ms minimum. The ST input can be derived from microprocessor address signals, data signals, and/or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To guarantee that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum shown in Table 1. A typical circuit example is shown in Figure 3.
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DS1232/DS1232S
MICROMONITOR BLOCK DIAGRAM Figure 1
PUSHBUTTON RESET Figure 2
WATCHDOG TIMER Figure 3
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DS1232/DS1232S
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
TIMING DIAGRAM: STROBE INPUT Figure 5
WATCHDOG TIMEOUTS Table 1
TD PIN GND Float VCC TIME-OUT MIN 62.5 ms 250 ms 500 ms TYP 150 ms 600 ms 1200 ms MAX 250 ms 1000 ms 2000 ms
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DS1232/DS1232S
TIMING DIAGRAM: POWER-DOWN Figure 6
TIMING DIAGRAM: POWER-UP Figure 7
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DS1232/DS1232S
ABSOLUTE MAXIMUM RATINGS*
Voltage on V CC Pin Relative to Ground Voltage on I/O Relative to Ground Operating Temperature Operating Temperature (Industrial Version) Storage Temperature Soldering Temperature * -0.5V to +7.0V -0.5V to VCC + 0.5V 0C to 70C -40C to +85C -55C to +125C 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage
ST ST
(0C to 70C)
TYP 5.0 MAX 5.5 VCC+0.3 +0.8 UNITS V V V NOTES 1 1 1
SYMBOL VCC VIH VIL
MIN 4.5 2.0 -0.3
and PBRST Input High Level and PBRST Input Low Level
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Output Current @ 2.4V Output Current @ 0.4V Low Level @ RST Output Voltage @ -500 A Operating Current VCC Trip Point (TOL=GND) VCC Trip Point (TOL=VCC) SYMBOL IIL IOH IOL VOL VOH ICC VCCTP VCCTP 4.50 4.25 VCC -0.5V MIN -1.0 -8 8
(0C to 70C; VCC=4.5 to 5.5V)
TYP -10 10 0.4 VCC -0.1V 0.5 4.62 4.37 2.0 4.74 4.49 MAX +10 UNITS A mA mA V V mA V V 1 1, 7 2 1 1 NOTES 3 5
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 pF pF
(tA=25C)
UNITS NOTES
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DS1232/DS1232S
AC ELECTRICAL CHARACTERISTICS
PARAMETER
PBRST
(0C to 70C; VCC=5V 10%)
MIN 20 250 20 100 300 250 0 610 5 20 1000 175 TYP 610 MAX 1000 UNITS ms ms ns s s ms s ms 4 6, 8 NOTES
= VIL
SYMBOL tPB tRST tST tRPD tF tRPU tR tPDLY
RESET Active Time
ST
Pulse Width
VCC Fail Detect to RST and RST VCC Slew Rate 4.75V to 4.25V VCC Detect to RST and RST Transition VCC Slew Rate 4.25V to 4.75V
PBRST
Stable Low to RST and RST
NOTES:
1. All voltages referenced to ground. 2. Measured with outputs open. 3. PBRST is internally pulled up to VCC with an internal impedance of 10k typical. 4. tR = 5 s. 5. RST is an open-drain output. 6. Must not exceed tTD minimum. See Table 1. 7. RST remains within 0.5V of VCC on power-down until VCC drops below 2.0V. RST remains within 0.5V of GND on power-down until VCC drops below 2.0V. 8. Watchdog can not be disabled. It must be strobed to avoid resets.
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