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INTEGRATED CIRCUITS
74F777 Triple bidirectional latched bus transceiver (3-State + open collector)
Product specification IC15 Data Handbook 1992 May 19
Philips Semiconductors
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + Open Collector)
74F777
FEATURES
* Latching transceiver * High drive Open Collector output current with minimum output
swing
range of 20 to 50 ohms and is terminated on each end with a 30 to 40 ohm resistor. The 74F777 is a triple bidirectional transceiver with Open Collector B and 3-State A port output drivers. A latch function is provided for the A port signals. The B port output driver is designed to sink 100mA from 2 volts to minimize crosstalk and ringing on the bus. A separate output threshold clamp voltage (VX) is provided to prevent the A port output High level from exceeding future high density processor supply voltage levels. For 5 volt systems, VX is simply tied to VCC. TYPE 74F777 TYPICAL PROPAGATION DELAY 7.0ns TYPICAL SUPPLY CURRENT( TOTAL) 45mA
* Compatible with Test Mode (TM) bus specification * Controlled output ramp * Multiple package options * Industrial temperature range available (-40C to +85C)
DESCRIPTION
The 74F777 is a triple bidirectional latched bus transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. This bus has a loaded characteristics impedance
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C 20-pin plastic DIP (300 mil) 20-pin PLCC N74F777N N74F777A INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F777N I74F777A SOT146-1 SOT380-1 PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS A0 - A2 B0 - B2 OEA0 - OEA2 OEB0 - OEB2 LE0 - LE2 A0 - A2 PNP latched inputs Data inputs with threshold circuitry A output enable inputs (active-High) B output enable inputs (active-Low) Latch enable inputs (active-Low) 3-State outputs DESCRIPTION 74F (U.L.) HIGH/LOW 3.5/0.117 5.0/0.167 1.0/0.033 1.0/0.033 1.0/0.033 150/40 OC/166.7 LOAD VALUE HIGH/LOW 70A/70A 100A/100A 20A/20A 20A/20A 20A/20A 3mA/24mA OC/100mA
B0 - B2 Open Collector outputs Note to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. OC = Open Collector.
May 19, 1992
2
853-1645 06772
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + Open Collector)
74F777
PIN CONFIGURATION
LE0 LE1 LE2 OEA0 A0 OEA1 A1 OEA2 A2 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC
LOGIC DIAGRAM
OEB0 VX GND B0 B1 B2 GND OEB0 OEB1 OEB2 LE1 A1 OEA0 OEB1 4 12 2 LE 7 Data Q LE0 A0 1 LE 5 Data Q 17 B0 13
16
B1
GND 10
SF00432
OEA1 OEB2
6 11 3 LE 9 Data Q
PIN CONFIGURATION PLCC
LE1 LE2 LE0 Vcc Vx
LE2 A2
15
B2
3 OEA0 A0 OEA1 A1 OEA2 4 5 6 7 8 9 A2
2
1
20
19 18 GND 17 B0
OEA2
8
VCC = Pin 20, VX = Pin 19, GND = Pin 10, 14, 18
PLCC
16 B1 15 B2 14 GND
SF00436
IEC/IEEE SYMBOL
13 EN 1 5 C1 ID 17
10 GND
11 OEB2
12 OEB1
13 OEB0
SF00433
4 12 2 EN
LOGIC SYMBOL
5 7 9
16
7 6 11 3 9 8 15
1 2 3 4 6 8 13 12 11 19
LE0 LE1 LE2 OEA0 OEA1 OEA2 OEB0 OEB1 OEB2 VX
A0 A1 A2
SF00435
B0 B1 B2
VCC = Pin 20, VX = Pin 19, GND = Pin 10, 14, 18
17 16 15
SF00434
May 19, 1992
3
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + Open Collector)
74F777
FUNCTION TABLE
INPUTS An H L X - - - - H L X - - - - Bn* X X X - H L - X X X H L H L LEn L L H L H H H L L H L L H H OEAn L L L H H H H L L L H H H H OEBn L L L L L L L H H H H H H H LATCH STATE H L Qn (1) H (2) H (2) Qn H L Qn H L Qn Qn OUTPUTS An Z Z Z (1) H L Qn Z Z Z H L H L Bn H** L Qn (1) Z(2) Z(2) Qn Z Z Z Z Z Z Z B 3-State, data from B to A B and A 3-State A 3-State, latched data to B Feedback: A to B, B to A Preconditioned latch enabling data transfer from B to A Latch state to A and B A 3-State, data from A to B OPERATING MODE
Qn Notes to function table H = High voltage level L = Low voltage level X = Don't care - = Input not externally driven Z = High impedance (off) state Qn = High or Low voltage level one setup time prior to the Low-to-High LE transition. (1) = Condition will cause a feedback loop path: A to B and B to A. (2) = The latch must be preconditioned such that B inputs may assume a High or Low level while OEB0 and OEB1 are Low and LE is High. Bn* =Precaution should be taken to insure the B inputs do not float. If they do they are equal to Low state. H**= Goes to level of pull-up voltage. Each latch is independent. The latches may be run in any combination of modes.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VX VIN Supply voltage Threshold control Input voltage OEBn, OEAn, LEn A0 - A2, B0 - B2 IIN VOUT IOUT Input current Voltage applied to output in High output state Current applied to output in Low output state Tamb Operating free air temperature range Tstg Storage temperature range A0 - A2 B0 - B2 Commercial range Industrial range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +5.5 -30 to +5 -0.5 to VCC 48 200 0 to +70 -40 to +85 -65 to +150 UNIT V V V V mA V mA mA
C C C
May 19, 1992
4
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + Open Collector)
74F777
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Except B0 - B2 B0 - B2 Except B0 - B2 B0 - B2 Except A0 - A2 A0 - A2 Except A0 - A2 A0 - A2 B0 - B2 Operating free-air temperature range Commercial range Industrial range 0 -40 PARAMETER MIN 4.5 2.0 1.6 0.8 1.43 -18 -40 -3 24 100 +70 +85 LIMITS NOM 5.0 MAX 5.5 V V V V V mA mA mA mA mA UNIT
C C
May 19, 1992
5
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + Open Collector)
74F777
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL IOH IOFF VOH PARAMETER High-level output current Power-off output current High-level output voltage B0 - B2 B0 - B2 A0 - A24 A0 - B0 - B2 A24 TEST CONDITIONS1 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = MIN, IOH = -3mA, VX =VCC VIL = MAX, IOH = -4mA, VX = 3.13V VIH = MIN and 3.47V VCC = MIN, IOL = 20mA, VX = Vcc VIL = MAX, IOL = 100mA VIH = MIN IOL = 4mA VCC = MIN, II = IIK VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 5.5V VCC = MAX, VI = 2.7V, Bn - An = 0V VCC = MAX, VI = 2.1V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.3V VCC = MAX, VO = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VX = VCC, LE = OEAn = OEBn = 2.7V, A0 - A2 = 2.7V, B0 - B2 = 2.0V, VCC = MAX, VX = 3.13 & 3.47V, LE = OEAn = 2.7V, OEBn = A0 - A2 = 2.7V, B0 - B2 = 2.0V IOS ICC Short circuit output current3 Supply current (total) A0 - A2 only ICCH ICCL ICCZ VCC = MAX, Bn = 1.8V, OEAn = 2.0V, OEBn = 2.7V VCC = MAX VCC = MAX, VIL = 0.5V VCC = MAX, VIL = 0.5V -100 -10 -60 40 55 45 MIN LIMITS TYP2 MAX 100 100 VCC VX 0.50 1.15 0.40 -0.5 -1.2 100 1 20 100 -20 -100 70 -70 100 10 -150 60 80 67 UNIT A A V V V V V V V A mA A A A A A A A A mA mA mA mA
2.5 2.5
VOL VIK II
Low-level output voltage Input clamp voltage Input current at maximum input voltage
IIH
High-level input current
IIL IOZH + IIH IOZL + IIL IX
Low-level input current Off-state output current, High level voltage applied Off-state output current, Low level voltage applied High level control current
A0 - A2 Except A0 - A2 OEBn, OEAn, LEn A0 - A2, B0 - B2 OEBn, OEAn, LEn B0 - B2 OEBn, OEAn, LEn B0 - B2 A0 - A2 A0 - A2
Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. Unless otherwise specified, VX =VCC for all test condition. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are for VIH =1.8v and VIL = 1.3V.
May 19, 1992
6
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + Open Collector)
74F777
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 30pF, RL = 9 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Bn to An Output enable time to High or Low OEAn to An Output Disable time from High or Low OEAn to An Waveform 1 8.5 7.5 8.0 9.0 1.5 1.5 TYP 10.5 9.5 10.0 11.0 3.0 3.0 MAX 13.0 12.0 13.0 14.0 6.0 6.0 Tamb = 0C to +70C VCC = +5.0V 10% CL = 30pF, RL = 9 MIN 8.0 7.5 7.0 8.0 1.0 1.0 MAX 14.5 12.5 14.5 15.5 6.5 6.0 Tamb = -40C to +85C VCC = +5.0V 10% CL = 30pF, RL = 9 MIN 8.0 7.5 7.0 8.0 1.0 1.0 MAX 14.5 12.5 14.5 15.5 6.5 6.0 ns UNIT
Waveform 3, 4
ns
Waveform 3, 4
ns
B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CD= 30pF, RU = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL Propagation delay An to Bn Propagation delay LEn to Bn Enable/disable time OEBn to An Transition time, B port 1.3V to 1.7V, 1.7V to 1.3V Waveform 1 Waveform 1 Waveform 1 Test Circuits and Waveforms 3.0 5.0 3.5 5.5 3.0 6.0 0.5 0.5 TYP 4.5 6.5 5.5 7.5 5.0 8.0 4.0 2.0 MAX 7.0 9.0 8.0 10.5 7.5 10.5 4.5 4.5 Tamb = 0C to +70C VCC = +5.0V 10% CD = 30pF, RU = 9 MIN 2.5 4.5 3.0 5.0 3.0 5.5 0.5 0.5 MAX 8.0 10.0 9.0 11.5 8.0 12.0 7.0 4.5 Tamb = -40C to +85C VCC = +5.0V 10% CD= 30pF, RU = 9 MIN 2.5 4.5 3.0 5.0 3.0 5.5 0.5 0.5 MAX 8.0 10.0 9.0 11.5 8.0 12.0 7.0 4.5 ns ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS TEST CONDITION Tamb = +25C VCC = +5.0V CD= 30pF, RU = 9 MIN tsu (H) tsu (L) th (H) th (L) tw (L) Setup time An to LEn Hold time An to LEn LEn pulse width, Low Waveform 2 Waveform 2 Waveform 2 4.0 4.5 0.0 0.0 5.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CD = 30pF, RU = 9 MIN 4.5 4.5 0.0 0.0 6.5 MAX Tamb = -40C to +85C VCC = +5.0V 10% CD= 30pF, RU = 9 MIN 4.5 4.5 0.0 0.0 6.5 MAX ns ns ns
SYMBOL
PARAMETER
UNIT
AC WAVEFORMS
An, Bn, OEBn VM tPLH VM tPHL tsu(L) An, Bn VM VM LEn VM VM An VM VM th(L) VM tsu(H) tw(L) VM VM th(H)
SF00437
SF00438
Waveform 1. Propagation delay, data to output and enable/disable time OEBn to Bn
Waveform 2. Data set-up and hold times and LE pulse width
May 19, 1992
7
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + Open Collector)
74F777
OEAn
VM tPZH
VM tPHZ VM 0V VOH -0.3V
OEAn
VM tPZL
VM tPLZ VM VOL +0.3V
An
An
SF00439
SF00440
Waveform 3. 3-State output enable time to High level and Waveform 4. 3-State output enable time to Low level and output output disable time from High level disable time from Low level Notes to AC waveforms For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open
VIN PULSE GENERATOR RT D.U.T. tTLH (tr ) CL RL POSITIVE PULSE 10% 90% VM tw tTHL (tf ) AMP (V) 90% VM 10% low V 90% VCC 7.0V VOUT RL NEGATIVE PULSE VM 10% tTHL (tf ) tw VM 10% tTLH (tr ) low V 90% AMP (V)
Test circuit for 3-State outputs on A port
VCC 7.0V
Input pulse definition INPUT PULSE REQUIREMENTS family amplitude Low V A port 3.0V 2.0V 0.0V 1.0V VM 1.5V 1.0V rep. rate 1MHz 1MHz tw tTLH tTHL 2.5ns 4.0ns 500ns 2.5ns 500ns 4.0ns
VIN PULSE GENERATOR RT D.U.T.
VOUT
RU
CD
B port
Test circuit for outputs on B port DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RU = Pull up resistor; see AC electrical characteristics for value. CD = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
SF00431
May 19, 1992
8
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + open collector)
74F777
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1992 May 19
9
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + open collector)
74F777
PLCC20: plastic leaded chip carrier; 20 leads
SOT380-1
1992 May 19
10
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + open collector)
74F777
NOTES
1992 May 19
11
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3-State + open collector)
74F777
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05178
Philips Semiconductors
yyyy mmm dd 12

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