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19-2931; Rev 0; 8/03
-48V Hot-Swap Controller with External RSENSE
General Description
The MAX5920A/MAX5920B are hot-swap controllers that allow a circuit card to be safely hot plugged into a live backplane. The MAX5920A/MAX5920B operate from -20V to -80V and are well-suited for -48V power systems. These devices are pin and function compatible with the LT4250 and pin compatible with the LT1640. The MAX5920A/MAX5920B provide a controlled turn-on to circuit cards preventing glitches on the power-supply rail and damage to board connectors and components. The MAX5920A/MAX5920B provide undervoltage, overvoltage, and overcurrent protection. These devices ensure the input voltage is stable and within tolerance before applying power to the load. Both the MAX5920A and MAX5920B protect a system against overcurrent and short-circuit conditions by turning off the external MOSFET in the event of a fault condition. The MAX5920A/MAX5920B also provide protection against input voltage steps. During an input voltage step, the MAX5920A/MAX5920B limit the current drawn by the load to a safe level without turning off power to the load. Both devices feature an open-drain power-good status output (PWRGD for the MAX5920A or PWRGD for the MAX5920B) that can be used to enable downstream converters. A built-in thermal-shutdown feature is also included to protect the external MOSFET in case of overheating. The MAX5920A/MAX5920B are available in an 8-pin SO package. Both devices are specified for the extended -40C to +85C temperature range.
Features
o Allows Safe Board Insertion and Removal from a Live -48V Backplane o Pin- and Function-Compatible with LT4250L (MAX5920A) o Pin-Compatible with LT1640L (MAX5920A) o Pin- and Function-Compatible with LT4250H (MAX5920B) o Pin-Compatible with LT1640H (MAX5920B) o Circuit-Breaker Immunity to Input Voltage Steps and Current Spikes o Withstands -100V Input Transients with No External Components o Programmable Inrush and Short-Circuit Current Limits o Operates from -20V to -80V o Programmable Overvoltage Protection o Programmable Undervoltage Lockout o Powers Up into a Shorted Load o Power-Good Control Output o Thermal Shutdown Protects External MOSFET
MAX5920
Ordering Information
PART MAX5920AESA MAX5920BESA TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 SO 8 SO
Applications
Telecom Line Cards Network Switches/Routers Central-Office Line Cards Server Line Cards Base-Station Line Cards
Pin Configuration
TOP VIEW
PWRGD (PWRGD)
1 2 3
8 7
VDD DRAIN GATE SENSE
Typical Operating Circuit and Selector Guide appear at end of data sheet.
OV UV
MAX5920A MAX5920B
6 5
VEE 4
SO
( ) FOR MAX5920B.
________________________________________________________________ Maxim Integrated Products
1
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-48V Hot-Swap Controller with External RSENSE MAX5920
ABSOLUTE MAXIMUM RATINGS
All Voltages are Referenced to VEE, Unless Otherwise Noted. Supply Voltage (VDD - VEE ) .................................-0.3V to +100V DRAIN, PWRGD, PWRGD ....................................-0.3V to +100V PWRGD to DRAIN ................................................ -0.3V to +95V PWRGD to VDD ........................................................-95V to +85V SENSE (Internally Clamped) .................................-0.3V to +1.0V GATE (Internally Clamped) ....................................-0.3V to +18V UV and OV..............................................................-0.3V to +60V Current Through SENSE ...................................................40mA Current into GATE...........................................................300mA Current into Any Other Pin................................................20mA Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.9mW/C above +70C)..................471mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = 0V, VDD = 48V, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted.) (Notes 1, 4)
PARAMETER POWER SUPPLIES Operating Input Voltage Range Supply Current Gate Pin Pullup Current Gate Pin Pulldown Current External Gate Drive GATE to VEE Clamp Voltage CIRCUIT BREAKER Current-Limit Trip Voltage SENSE Input Bias Current UNDERVOLTAGE LOCKOUT Internal Undervoltage Lockout Voltage High Internal Undervoltage Lockout Voltage Low UV PIN UV High Threshold UV Low Threshold UV Hysteresis UV Input Bias Current OV PIN OV High Threshold OV Low Threshold OV Voltage Reference Hysteresis OV Input Bias Current DRAIN Input Bias Current VOVH VOVL VOVHY IINOV IDRAIN VOV = VEE VDRAIN = 48V -0.5 10 80 OV voltage increasing OV voltage decreasing 1.235 1.189 1.255 1.205 50 0 250 1.275 1.221 V V mV A A VUVH VUVL VUVHY_ IINUV -0.5 UV voltage increasing UV voltage decreasing 1.240 1.105 1.255 1.125 130 0 1.270 1.145 V V mV A VUVLOH VUVLOL VDD increasing VDD decreasing 13.8 11.8 15.4 13.4 17.0 15.0 V V VCL VCL = VSENSE - VEE VSENSE = 50mV 40 -1 50 -0.2 60 0 mV A VDD IDD IPU IPD VGATE VGSCLMP (Note 2) GATE drive on, VGATE = VEE GATE drive off , VGATE = 2V VGATE - VEE, 20V VDD 80V VGATE - VEE, IGS = 30mA -30 24 10 15 20 0.7 -45 50 13.5 16.4 80 2 -60 70 18 18 V mA A mA V V SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE DRIVER AND CLAMPING CIRCUITS
PWRGD OUTPUT SIGNAL REFERENCED TO DRAIN
2
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-48V Hot-Swap Controller with External RSENSE
ELECTRICAL CHARACTERISTICS (continued)
(VEE = 0V, VDD = 48V, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted.) (Notes 1, 4)
PARAMETER DRAIN Threshold for Power-Good GATE High Threshold PWRGD, PWRGD Output Leakage PWRGD Output Low Voltage PWRGD Output Low Voltage OVERTEMPERATURE PROTECTION Overtemperature Threshold Overtemperature Hysteresis AC PARAMETERS OV High to GATE Low UV Low to GATE Low OV Low to GATE High UV High to GATE High SENSE High to GATE Low Current Limit to GATE Low DRAIN Low to PWRGD Low DRAIN Low to (PWRGD - DRAIN) High GATE High to PWRGD Low GATE High to (PWRGD-DRAIN) High TURN-OFF Latch-Off Period tOFF (Note 3) 128 x tPHLCL ms tPHLOV tPHLUV tPLHOV tPLHVL tPHLSENSE tPHLCL tPHLDL MAX5920B, Figures 1a, 5a MAX5920A, Figures 1a, 5b tPHLGH MAX5920B, Figures 1a, 5b 2.5 3.4 1.6 s Figures 1a, 2 Figures 1a, 3 Figures 1a, 2 Figures 1a, 3 Figures 1a, 4a Figures 1b, 4b MAX5920A, Figures 1a, 5a 350 0.5 0.4 3.3 3.4 1 500 1.8 s 3 650 s s s s s s TOT THYS Junction temperature, temperature rising 135 20 C C SYMBOL VDL VGH IOH VOL VOL CONDITIONS VDRAIN - VEE threshold for power-good condition, DRAIN decreasing VGATE - VGATE threshold for power-good condition, VGATE - VGATE decreasing PWRGD (MAX5920A) = 80V, VDRAIN = 48V, PWRGD (MAX5920B) = 80V, VDRAIN = 0V VPWRGD - VEE; VDRAIN - VEE < VDL, ISINK = 5mA (MAX5920A) VPWRGD - VDRAIN; VDRAIN = 5V, ISINK = 5mA (MAX5920B) 0.11 0.11 MIN 1.1 1.0 TYP 1.7 1.6 MAX 2.0 2.0 10 0.4 0.4 UNITS V V A V V
MAX5920
Note 1: Note 2: Note 3: Note 4:
All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE, unless otherwise specified. Current into VDD with UV = 3V, OV, DRAIN, PWRGD, SENSE = VEE, GATE = floating. Minimum duration of GATE pulldown following a circuit-breaker fault. The circuit breaker can be reset during this time by toggling UV low, but the GATE pulldown does not release until tOFF has elapsed. Limits are 100% tested at TA = +25C and +85C. Limits at -40C are guaranteed by design.
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-48V Hot-Swap Controller with External RSENSE MAX5920
Typical Operating Characteristics
(VDD = 48V, VEE = 0V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5920 toc01
GATE VOLTAGE vs. SUPPLY VOLTAGE
TA = +25C 14 13 GATE VOLTAGE (V) 12 11 10 9 8 7
MAX5920 toc02
CURRENT-LIMIT TRIP VOLTAGE vs. TEMPERATURE
MAX5920 toc03
900 800 SUPPLY CURRENT (A) 700 600 500 400 300 200 100 0 0 20 40 60 80 TA = -40C TA = +85C TA = +25C
15
53 52 TRIP VOLTAGE (mV) 51 50 49 48 47 46
100
0
20
40
60
80
100
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
GATE PULLUP CURRENT vs. TEMPERATURE
MAX5920 toc04
GATE PULLDOWN CURRENT vs. TEMPERATURE
65 GATE PULLDOWN CURRENT (mA) 60 55 50 45 40 35 30 25 VGATE = 2V
MAX5920 toc05
GATE PULLDOWN CURRENT vs. OVERDRIVE
175 150 125 100 75 50 25 0 MAX5920 VGATE = 2V
MAX5920 toc06
45.0 44.8 GATE PULLUP CURRENT (A) 44.6 44.4 44.2 44.0 43.8 43.6 43.4 43.2 43.0
VGATE = 0V
70
200 GATE PULLDOWN CURRENT (mA)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
10
100 OVERDRIVE (mV)
1000
TEMPERATURE (C)
TEMPERATURE (C)
PWRGD OUTPUT LOW VOLTAGE vs. TEMPERATURE (MAX5920A)
MAX5920 toc07
PWRGD OUTPUT LEAKAGE CURRENT vs. TEMPERATURE (MAX5920B)
PWRGD OUTPUT LEAKAGE CURRENT (nA) VDRAIN - VEE > 2.4V
MAX5920 toc08
50 PWRGD OUTPUT LOW VOLTAGE (mV) 45 40 35 30 25 20 15 10 5 0
100
IOUT = 1mA
10
1
0.1
0.01
0.001 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
4
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-48V Hot-Swap Controller with External RSENSE MAX5920
R 5k PWRGD/PWRGD OV VOV VDD DRAIN VDRAIN VS 48V
V+ 5V
MAX5920A MAX5920B
UV VUV GATE
VEE
SENSE VSENSE
Figure 1a. Test Circuit 1
PWRGD/PWRGD OV
VDD DRAIN VS 48V 10k VS 20V
UV VUV VEE
MAX5920A MAX5920B
10 GATE 0.1F N IRF530
SENSE
10
Figure 1b. Test Circuit 2
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5
-48V Hot-Swap Controller with External RSENSE MAX5920
Timing Diagrams
2V 1.255V OV 1.205V
UV 0V 2V 1.125V tPHLUV tPLHUV 1.255V
0V
tPHLOV tPLHOV
GATE
GATE 1V 1V
1V
1V
Figure 2. OV to GATE Timing
Figure 3. UV to GATE Timing
100mV SENSE VEE
60mV UV tPHLSENSE tPHLCL
GATE GATE 1V 1V 1V
Figure 4a. SENSE to GATE Timing
Figure 4b. Active Current-Limit Threshold
6
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-48V Hot-Swap Controller with External RSENSE
Timing Diagrams (continued)
DRAIN
1.4V
MAX5920
1.4V
VGATE - VGATE = 0V
tPHLDL PWRGD 1V
VEE
GATE tPHLGH
PWRGD
VEE
1V
VEE
1.4V
DRAIN
VGATE - VGATE = 0V
1.4V VEE
GATE VEE tPHLGH
tPHLDL PWRGD 1V
PWRGD VPWRGD - VDRAIN = 0V 1V
VPWRGD - VDRAIN = 0V
Figure 5a. DRAIN to PWRGD/PWRGD Timing
Figure 5b. GATE to PWRGD/PWRGD Timing
Block Diagram
VDD
UVLO UV
VCC AND REFERENCE GENERATOR
VCC
MAX5920A MAX5920B
REF
PWRGD PWRGD OUTPUT DRIVE REF LOGIC
OV 50mV
GATE DRIVER
VDL
VGH VGATE
VEE VEE SENSE GATE DRAIN
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7
-48V Hot-Swap Controller with External RSENSE MAX5920
Pin Description
PIN MAX5920A MAX5920B 1 -- NAME FUNCTION Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced to VEE. PWRGD is latched low when VDRAIN - VEE VDL and VGATE > (VGATE - VGH), indicating a power-good condition. PWRGD is open drain otherwise. Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced to DRAIN. PWRGD latches in a high-impedance state when VDRAIN - VEE VDL and VGATE > (VGATE - VGH), indicating a power-good condition. PWRGD is pulled low to DRAIN otherwise. Input Pin for Overvoltage Detection. OV is referenced to VEE. When OV is pulled above VOVH voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the OV pin voltage reduces to VOVL. Input Pin for Undervoltage Detection. UV is referenced to VEE. When UV is pulled above VUVH voltage, the GATE is enabled. When UV is pulled below VUVL, GATE is pulled low. UV is also used to reset the circuit breaker after a fault condition. To reset the circuit breaker, pull UV below VUVL. The reset command can be issued immediately after a fault condition; however, the device does not restart until a tOFF delay time has elapsed after the fault. Device Negative Power-Supply Input. Connect to the negative power-supply rail. Current-Sense Voltage Input. Connect to an external sense resistor and the external MOSFET source. The voltage drop across the external sense resistor is monitored to detect overcurrent or short-circuit fault conditions. Connect SENSE to VEE to disable the currentlimiting feature. Gate Drive Output. Connect to gate of the external N-channel MOSFET. Output-Voltage Sense Input. Connect to the output-voltage node (drain of external N-channel MOSFET). Place the MAX5920_ so the DRAIN pin is close to the DRAIN of the external MOSFET for the best thermal protection. Positive Power-Supply Rail Input. This is the power ground in the negative-supply voltage system. Connect to the higher potential of the power-supply inputs.
PWRGD
--
1
PWRGD
2
2
OV
3
3
UV
4
4
VEE
5
5
SENSE
6 7
6 7
GATE DRAIN
8
8
VDD
Detailed Description
The MAX5920A/MAX5920B are integrated hot-swap controllers for -48V power systems. They allow circuit boards to be safely hot plugged into a live backplane without causing a glitch on the power-supply rail. When circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board's power module or switching power supply can draw large inrush currents as they charge. The inrush currents can cause glitches on the system power-supply rail and damage components on the board.
The MAX5920A/MAX5920B provide a controlled turn-on to circuit cards preventing glitches on the power-supply rail and damage to board connectors and components. Both the MAX5920A and MAX5920B provide undervoltage, overvoltage, and overcurrent protection. The MAX5920A/MAX5920B ensure the input voltage is stable and within tolerance before applying power to the load. The devices also provide protection against input voltage steps. During an input voltage step, the MAX5920A/MAX5920B limit the current drawn by the load to a safe level without turning off power to the load.
8
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-48V Hot-Swap Controller with External RSENSE
Board Insertion
Figure 6a shows a typical hot-swap circuit for -48V systems. When the circuit board first makes contact with the backplane, the DRAIN to GATE capacitance (Cgd) of Q1 pulls up the GATE voltage to roughly IVEE x Cgd / Cgd + CgsI. The MAX5920_ features an internal dynamic clamp between GATE and VEE to keep the gate-tosource voltage of Q1 low during hot insertion, preventing Q1 from passing an uncontrolled current to the load. For most applications, the internal clamp between GATE and VEE of the MAX5920A/MAX5920B eliminates the need for an external gate-to-source capacitor. Resistor R3 limits the current into the clamp circuitry during card insertion. Capacitor C2 provides a feedback signal to accurately limit the inrush current. The inrush current can be calculated: IINRUSH = IPU x CL / C2 where CL is the total load capacitance, C3 + C4, and IPU is the MAX5920_ gate pullup current. Figure 6b shows the inrush current waveform. The current through C2 controls the GATE voltage. At the end of the DRAIN ramp, the GATE voltage is charged to its final value. The GATE-to-SENSE clamp limits the maximum VGS to about 18V under any condition.
MAX5920
Board Removal
If the circuit card is removed from the backplane, the voltage at the UV pin falls below the UVLO detect threshold, and the MAX5920_ turns off the external MOSFET.
Power-Supply Ramping
The MAX5920A/MAX5920B can reside either on the backplane or the removable circuit board (Figure 6a). Power is delivered to the load by placing an external N-channel MOSFET pass transistor in the power-supply path. After the circuit board is inserted into the backplane and the supply voltage at VEE is stable and within the undervoltage and overvoltage tolerance, the MAX5920A/MAX5920B turn on Q1. The MAX5920A/ MAX5920B gradually turn on the external MOSFET by charging the gate of Q1 with a 45A current source.
Current Limit and Electronic Circuit Breaker
The MAX5920_ provides current-limiting and circuitbreaker features that protect against excessive load current and short-circuit conditions. The load current is monitored by sensing the voltage across an external sense resistor connected between VEE and SENSE.
-48V RTN (SHORT PIN) -48V RTN R4 549k 1% UV R5 6.49k 1% * R6 10k 1% OV VEE SENSE PWRGD
VDD
MAX5920B
GATE R3 1k 5% R2 10 5% C2 15nF 100V GATE IN VIN+ C3 0.1F 100V C4 100F 100V VICOR VI-J3D-CY DRAIN
10nF
R1 0.02 5% -48V *DIODES INC. SMAT70A. **OPTIONAL.
C1** 470nF 25V
Q1 IRF530
VIN-
Figure 6a. Inrush Control Circuitry _______________________________________________________________________________________ 9
-48V Hot-Swap Controller with External RSENSE MAX5920
INRUSH CURRENT 1A/div GATE - VEE 10V/div
voltage of the external MOSFET, thereby reducing the load current. When V SENSE - V EE < V CL , the MAX5920A/MAX5920B pull the GATE pin high by a 45A (IPU) current.
Driving into a Shorted Load
In the event of a permanent short-circuit condition, the MAX5920A/MAX5920B limit the current drawn by the load to VCL / RSENSE for a period of tPHLCL, after which the circuit breaker trips. Once the circuit breaker trips, the GATE of the external FET is pulled low by 50mA (IPD) turning off power to the load.
CONTACT BOUNCE
DRAIN 50V/div VEE 50V/div
Immunity to Input Voltage Steps
The MAX5920A/MAX5920B guard against input voltage steps on the input supply. A rapid increase in the input supply voltage (VDD - VEE increasing) causes a current step equal to I = CL x VIN / T, proportional to the input voltage slew rate (VIN / T). If the load current exceeds V CL / R SENSE during an input voltage step, the MAX5920A/MAX5920B current limit activates, pulling down the gate voltage and limiting the load current to VCL / RSENSE. The DRAIN voltage (VDRAIN) then slews at a slower rate than the input voltage. As the drain voltage starts to slew down, the drain-to-gate feedback capacitor C2 pushes back on the gate, reducing the gate-tosource voltage (VGS) and the current through the external MOSFET. Once the input supply reaches its final value, the DRAIN slew rate (and therefore the inrush current) is limited by the capacitor C2 just as it is limited in the startup condition. To ensure correct operation, RSENSE must be chosen to provide a current limit larger than the sum of the load current and the dynamic current into the load capacitance in the slewing mode. If the load current plus the capacitive charging current is below the current limit, the circuit breaker does not trip.
4ms/div
Figure 6b. Input Inrush Current
If the voltage between VEE and SENSE reaches the current-limit trip voltage (VCL), the MAX5920_ pulls down the GATE pin and regulates the current through the external MOSFET so VSENSE - VEE < VCL. If the current drawn by the load drops below VCL / RSENSE limit, the GATE pin voltage rises again. However, if the load current is at the regulation limit of VCL / RSENSE for a period of tPHLCL, the electronic circuit breaker trips, causing the MAX5920A/MAX5920B to turn off the external MOSFET. After an overcurrent fault condition, the circuit breaker is reset by pulling the UV pin low and then pulling UV high or by cycling power to the MAX5920A/MAX5920B. Unless power is cycled to the MAX5920A/MAX5920B, the device waits until tOFF has elapsed before turning on the gate of the external FET.
Overcurrent Fault Integrator
The MAX5920_ feature an overcurrent fault integrator. When an overcurrent condition exists, an internal digital counter increments its count. When the counter reaches 500s (the maximum current-limit duration) for the MAX5920_, an overcurrent fault is generated. If the overcurrent fault does not last 500s, then the counter begins decrementing at a rate 128 (maximum currentlimit duty cycle) times slower than the counter was incrementing. Repeated overcurrent conditions will generate a fault if duty cycle of the overcurrent condition is greater than 1/128.
INRUSH CURRENT 2A/div GATE - VEE 4V/div
Load-Current Regulation
The MAX5920A/MAX5920B accomplish load-current regulation by pulling current from the GATE pin whenever V SENSE - V EE > V CL (see Typical Operating Characteristics). This decreases the gate-to-source
10
CONTACT BOUNCE
VEE 50V/div
4ms/div
Figure 7a. Startup Into a Short Circuit ______________________________________________________________________________________
-48V Hot-Swap Controller with External RSENSE MAX5920
DRAIN 50V/div GATE - VEE 10V/div DRAIN 20V/div
VEE 20V/div
ID (Q1) 5A/div
ID (Q1) 5A/div
1ms/div
400s/div
Figure 7b. Short-Circuit Protection Waveform
Figure 8. Voltage Step-On Input Supply
-48V RTN (SHORT PIN) -48V RTN R4 549k 1% UV R5 6.49k 1% * OV VEE SENSE PWRGD
VDD
MAX5920A
GATE R3 1k 5% R7 220 5% R1 0.02 5% C1 150nF 25V Q1 IRF530 C2 3.3nF 100V DRAIN C3 0.1F 100V C4 22F 100V
R6 10k 1%
D1 BAT85
R2 10 5%
-48V *DIODES INC. SMAT70A.
Figure 9. Circuit for Input Steps with Small C1
For C2 values less than 10nF, a positive voltage step on the input supply can result in Q1 turning off momentarily, which can shut down the output. By adding an additional resistor and diode, Q1 remains on during the voltage step. This is shown as D1 and R7 in Figure 9. The purpose of D1 is to shunt current around R7 when the power pins first make contact and allow C1 to hold the GATE low. The value of R7 should be sized to generate an R7 x C1 time constant of 33s.
internally connected to analog comparators with 130mV (UV) and 50mV (OV) of hysteresis. When the UV voltage falls below its threshold or the OV voltage rises above its threshold, the GATE pin is immediately pulled low. The GATE pin is held low until UV goes high and OV is low, indicating that the input supply voltage is within specification. The MAX5920_ includes an internal lockout (UVLO) that keeps the external MOSFET off until the input supply voltage exceeds 15.4V, regardless of the UV input. The UV pin is also used to reset the circuit breaker after a fault condition has occurred. The UV pin can be pulled below VUVL to reset the circuit breaker.
Undervoltage and Overvoltage Protection
The UV and OV pins can be used to detect undervoltage and overvoltage conditions. The UV and OV pins are
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11
-48V Hot-Swap Controller with External RSENSE MAX5920
-48V RTN (SHORT PIN) -48V RTN R7 1M 5% C4 1F 100V * OV VEE SENSE R6 549k 1% NODE1 PWRGD R4 549k 1% UV
VDD NODE1 50V/div
MAX5920A
R6 10k 1% Q2 2N2222 D1 1N4148 R8 510k 5% Q3 ZVN3310 P R1 0.02 5% R5 6.49k 1% GATE R3 1k 5% R2 10 5% C2 3.3nF 100V DRAIN
C3 100F 100V
GATE 2V/div
C1 470nF 25V
1s/div
-48V *DIODES INC. SMAT70A.
N Q1 IRF530
Figure 10. Automatic Restart After Current Fault
-48V RTN (SHORT PIN) -48V RTN R4 R4 + R5 + R6 R5 + R6 R5 R4 + R5 + R6 VOV = 1.255 R6 R6 2 OV VEE 4 3 UV 8 VDD
Figure 11 shows how to program the undervoltage and overvoltage trip thresholds using three resistors. With R4 = 549k, R5 = 6.49k, and R6 = 10k, the undervoltage threshold is set to 38.5V (with a 43V release from undervoltage), and the overvoltage is set to 71V. The resistordivider also increases the hysteresis and overvoltage lockout to 4.5V and 2.8V at the input supply, respectively.
PWRGD/PWRGD Output
The PWRGD (PWRGD) output can be used directly to enable a power module after hot insertion. The MAX5920A (PWRGD) can be used to enable modules with an active-low enable input (Figure 13), while the MAX5920B (PWRGD) is used to enable modules with an active-high enable input (Figure 12). The PWRGD signal is referenced to the DRAIN terminal, which is the negative supply of the power module. The PWRGD signal is referenced to VEE. When the DRAIN voltage of the MAX5920A is high with respect to VEE or the GATE voltage is low, the internal pulldown MOSFET Q2 is off and the PWRGD pin is in a high-impedance state (Figure 13). The PWRGD pin is
VUV = 1.255
MAX5920A MAX5920B
-48V
Figure 11. Undervoltage and Overvoltage Sensing 12
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-48V Hot-Swap Controller with External RSENSE MAX5920
-48V RTN (SHORT PIN) -48V RTN VDD R4 ACTIVE-HIGH ENABLE MODULE VIN+ VOUT+
MAX5920B
UV
I1 N
PWRGD ON/OFF Q2 C3
R5
VGH Q3 VGATE
N VINVEE VDL VOUT-
*
OV
R6 VEE SENSE GATE R3
DRAIN
C2
C1 R1 -48V *DIODES INC. SMAT70A. Q1
R2
Figure 12. Active-High Enable Module
-48V RTN (SHORT PIN) -48V RTN VDD R4
ACTIVE-LOW ENABLE MODULE VIN+ VOUT+
MAX5920A
UV
I1
PWRGD ON/OFF C3
R5
VGH VGATE
N
Q2 VINVOUT-
VEE VDL
*
OV
R6 VEE SENSE GATE R3
DRAIN
C2
C1 R1 -48V *DIODES INC. SMAT70A. Q1
R2
Figure 13. Active-Low Enable Module ______________________________________________________________________________________ 13
-48V Hot-Swap Controller with External RSENSE MAX5920
-48V RTN (SHORT PIN) -48V RTN R7** 51k 5% VDD UV R5 6.49k 1% * OV VEE SENSE PWRGD PWRGD
R4 549k 1%
MAX5920A
GATE R3 1k 5% C2 15nF 100V C3 100F 100V DRAIN MOC207
R6 10k 1%
R1 0.02 5% -48V *DIODES INC. SMAT70A. **OPTIONAL.
C1** 470nF 25V
R2 10 5%
Q1 IRF530
Figure 14. Using PWRGD to Drive an Optoisolator
pulled high by the module's internal pullup current source, turning the module off. When the DRAIN voltage drops below VDL and the GATE voltage is greater than VGATE - VGH, Q2 turns on and the PWRGD pin pulls low, enabling the module. The PWRGD signal can also be used to turn on an LED or optoisolator to indicate that the power is good (Figure 14) (see the Component Selection Procedure section). When the DRAIN voltage of the MAX5920B is high with respect to VEE (Figure 12) or the GATE voltage is low, the internal MOSFET Q3 is turned off so that I1 and the internal MOSFET Q2 clamp the PWRGD pin to the DRAIN pin. MOSFET Q2 sinks the module's pullup current, and the module turns off. When the DRAIN voltage drops below V DL and the GATE voltage is greater than VGATE - VGH, MOSFET Q3 turns on, shorting I1 to VEE and turning Q2 off. The pullup current in the module pulls the PWRGD pin high, enabling the module.
MAX5920A/MAX5920B include an internal clamp that ensures the GATE voltage of the external MOSFET never exceeds 18V. During a fast-rising VDD, the clamp also keeps the GATE and SENSE potentials as close as possible to prevent the FET from accidentally turning on. When a fault condition is detected, the GATE pin is pulled low with a 50mA current.
Thermal Shutdown
The MAX5920A/MAX5920B include internal die-temperature monitoring. When the die temperature reaches the thermal-shutdown threshold, T OT , the MAX5920A/ MAX5920B pull the GATE pin low and turn off the external MOSFET. If a good thermal path is provided between the MOSFET and the MAX5920A/MAX5920B, the device offers thermal protection for the external MOSFET. Placing the MAX5920A/MAX5920B near the drain of the external MOSFET offers the best thermal protection because most of the power is dissipated in its drain. After a thermal shutdown fault has occurred, the MAX5920A/MAX5920B turn the external FET off. To clear a thermal shutdown fault condition, toggle the UV pin or cycle the power to the device. The device keeps the external FET off for a minimum time of tOFF after UV is toggled, allowing the MOSFET to cool down. The device restarts after the temperature drops 20C below the thermal-shutdown threshold.
GATE Pin Voltage Regulation
The GATE pin goes high when the following startup conditions are met: the UV pin is high, the OV pin is low, the supply voltage is above VUVLOH, and (VSENSE - VEE) is less than 50mV. The gate is pulled up with a 45A current source and is regulated at 13.5V above V EE . The
14
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-48V Hot-Swap Controller with External RSENSE
Applications Information
Sense Resistor
The circuit-breaker current-limit threshold is set to 50mV (typically). Select a sense resistor that causes a drop equal to or above the current-limit threshold at a current level above the maximum normal operating current. Typically, set the overload current to 1.5 to 2.0 times the nominal load current plus the load-capacitance charging current during startup. Choose the sense resistor power rating to be greater than (VCL)2 / RSENSE. Although the suggested optocoupler is not specified for operation below 5mA, its performance is adequate for 36V temporary low-line voltage where LED current would then be 2.2mA to 3.7mA. If R7 is set as high as 51k, optocoupler operation should be verified over the expected temperature and input voltage range to ensure suitable operation when LED current 0.9mA for 48V input and 0.7mA for 36V input. If input transients are expected to momentarily raise the input voltage to >100V, select an input transient-voltage-suppression diode (TVS) to limit maximum voltage on the MAX5920 to less than 100V. A suitable device is the Diodes Inc. SMAT70A telecom-specific TVS. Select Q1 to meet supply voltage, load current, efficiency, and Q1 package power-dissipation requirements: BVDSS 100V ID(ON) 3 x ILOAD DPAK, D2PAK, or TO-220AB The lowest practical RDS(ON), within budget constraints and with values from 14m to 540m, are available at 100V breakdown. Ensure that the temperature rise of Q1 junction is not excessive at normal load current for the package selected. Ensure that ICB current during voltage transients does not exceed allowable transient-safe operating-area limitations. This is determined from the SOA and transient-thermal-resistance curves in the Q1 manufacturer's data sheet. Example 1: ILOAD = 2.5A, efficiency = 98%, then VDS = 0.96V is acceptable, or RDS(ON) 384m at operating temperature is acceptable. An IRL520NS 100V NMOS with R DS(ON) 180m and I D(ON) = 10A is available in D2PAK. (A Vishay Siliconix SUD40N10-25 100V NMOS with RDS(ON) 25m and ID(ON) = 40A is available in DPAK, but may be more costly because of a larger die size). Using the IRL520NS, VDS 0.625V even at +80C so efficiency 98.6% at 80C. PD 1.56W and junction temperature rise above case temperature would be 5C due to the package JC = 3.1C/W thermal resistance. Of course, using the SUD40N10-25 would yield an efficiency greater than 99.8% to compensate for the increased cost.
MAX5920
Component Selection Procedure
* * * * Determine load capacitance: CL = C2 + C3 + module input capacitance Determine load current, ILOAD. Select circuit-breaker current, for example: ICB = 2 x ILOAD Calculate RSENSE: 50mV ICB Realize that ICB varies 20% due to trip-voltage tolerance. RSENSE = * Set allowable inrush current: IINRUSH 0.8 x 40mV - ILOAD or RSENSE IINRUSH + ILOAD 0.8 x ICB(MIN)
*
Determine value of C2: 45A x CL C2 = IINRUSH Calculate value of C1: - VGS(TH) V C1 = (C2 + Cgd) x IN(MAX) VGS(TH)
*
*
Determine value of R3: 150s (typically 1k) R3 C2
* Set R2 = 10. * If an optocoupler is utilized as in Figure 14, determine the LED series resistor: V - 2V R7 = IN(NOMINAL) 3mA ILED 5mA
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15
-48V Hot-Swap Controller with External RSENSE MAX5920
If ICB is set to twice ILOAD, or 5A, VDS momentarily doubles to 1.25V. If COUT = 4000F, transient-line input voltage is 36V, the 5A charging-current pulse is: 4000F x 1.25V t= = 1ms 5A Entering the data sheet transient-thermal-resistance curves at 1ms provides a JC = 0.9C/W. PD = 6.25W, so tJC = 5.6C. Clearly, this is not a problem. Example 2: ILOAD = 10A, efficiency = 98%, allowing VDS = 0.96V but RDS(ON) 96m. An IRF530 in a D2PAK exhibits RDS(ON) 90m at +25C and 135m at +80C. Power dissipation is 9.6W at +25C or 14.4W at +80C. Junction-to-case thermal resistance is 1.9W/C, so the junction temperature rise would be approximately 5C above the +25C case temperature. For higher efficiency, consider IRL540NS with R DS(ON) 44m. This allows = 99%, PD 4.4W, and TJC = +4C (JC = 1.1C/W) at +25C. Thermal calculations for the transient condition yield I CB = 20A, V DS = 1.8V, t = 0.5ms, transient JC = 0.12C/W, PD = 36W and tJC = 4.3C.
HIGH-CURRENT PATH
SENSE RESISTOR
SENSE VEE MAX5920A MAX5920B
Figure 15. Recommended Layout for Kelvin-Sensing Current Through Sense Resistor
Layout Guidelines
Good thermal contact between the MAX5920A/ MAX5920B and the external MOSFET is essential for the thermal-shutdown feature to operate effectively. Place the MAX5920A/MAX5920B as close as possible to the drain of the external MOSFET and use wide circuit-board traces for good heat transfer (see Figure 15).
Selector Guide
PART MAX5920AESA MAX5920BESA PWRGD POLARITY Active low (PWRGD) Active high (PWRGD) FAULT MANAGEMENT Latched Latched
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______________________________________________________________________________________
-48V Hot-Swap Controller with External RSENSE
Typical Operating Circuit
BACKPLANE -48V RTN -48V RTN (SHORT PIN) CIRCUIT CARD
MAX5920
VDD UV PWRGD
MAX5920A
OV VEE SENSE GATE DRAIN
VIN+ LUCENT JW050A1-E N -48V (INPUT2) INPUT2 VIN-
-48V (INPUT1)
INPUT1
Chip Information
TRANSISTOR COUNT: 2645 PROCESS: BiCMOS
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17
-48V Hot-Swap Controller with External RSENSE MAX5920
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D C
A e B A1
0 -8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SOICN .EPS

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