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MA31750 MA31750
High Performance MIL-STD-1750 Microprocessor
Replaces July 1999 version, DS3748-7.0 DS3748-8.0 January 2000
The Dynex Semiconductor MA31750 is a single-chip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD1750B. The processor executes all mandatory instructions and many optional features are also included. Interrupts, fault handling, memory expansion, Console, timers A and B, and their related optional instructions are also supported in full accordance with MIL-STD-1750. The MA31750 offers a considerable performance increase over the existing MAS281. This is achieved by using a 32-bit internal bus structure with a 24 x 24 bit multiplier and 32-bit ALU. Other performance-enhancing features include a 32-bit shift network, a multi-port register file and a dedicated address calculation unit.
The MA31750 has on-chip parity generation and checking to enhance system integrity. A comprehensive built-in self-test has also been incorporated, allowing processor functionality to be verified at any time. Console operation is supported through a parallel interface using command/data registers in l/O space. Several discrete output signals are produced to minimise external logic. Control signals are also provided to allow inclusion of the MA31750 into a multiprocessor or DMA system. The processor can directly access 64KWords of memory in full accordance with MIL-STD-1750A. This increases to 1MWord when used with the optional MA31751 memory management unit (MMU). 1750B mode allows the system to be expanded to 8MWord with the MMU.
Parity
Bus arb.
Bus Control
Address
Data CLK ebf uAddr
C0
IO control
C1
Microcode ROM
IC A IB X BR
DOUT Register file
Sequencer
Microcode control words to other blocks uData
Address generator
IA
rap
R bus S bus ir Ints
ALU
Qshift
sc
Multiplier
Shift network
abort
Interrupt controller
Faults INTAKN BUSFAULTN
Y bus mov aluv bf
Flags
Figure 1: Architecture
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1. ARCHITECTURE
The Dynex Semiconducor MA31750 Microprocessor is a high performance implementation of the MIL-STD-1750A (Notice 1) Instruction Set Architecture. Figure 1 depicts the architectural details of the chip. Two key features of this architecture which contribute to the overall high performance of the MA31750 are a 32-bit shift network and a 24-bit parallel multiplier. These sub-systems allow the MA31750 to perform multi-bit shifts, multiplications,divisions and normalisations in a fraction of the clock cycles required on machines not having such resources. This is especially true of floating-point operations, in which the MA31750 excels. Such operations constitute a large proportion of the Digital Avionics Instruction Set (DAIS) mix and generally a high percentage of many signal processing algorithms, therefore having a significant impact on system performance. Key features include: 1) A three-bus (R, S, and Y) datapath consisting of an arithmetic/logic unit (ALU), three-port register file, shift network, parallel multiplier and flags block; 2) Four instruction fetch registers C0,C1, IA, and IB; 3) Two operand transfer registers DI, and DO; 4) Two address registers IC and A; 5) A state sequencer; 6) Micro-instruction decode logic. The relationship between these functional blocks is shown in Figure 1.
2. ADDITIONAL FEATURES
The MA31750 may be operated in one of two basic user selectable modes. 1750A mode follows the requirements of MIL-STD-1750A (Notice 1) and implements all of the mandatory features of this standard. In addition, many of the optional features such as interval timers A and B, a watchdog timer and parity checking are included. 1750B mode, when selected, allows the user access to a range of new instructions and features as described in the Draft MIL-STD-1750B, Option 2. These include a range of unsigned arithmetic operations and expanded addressing support instructions. 2.1. MIL-STD-1750 OPTIONAL FEATURES In addition to implementing all of the required features of MIL-STD-1750A and the Draft standard MIL-STD-1750B, the MA31750 also incorporates a number of optional features. Interval timers A and B as well as a trigger-go counter are provided. Most specified XIO commands are decoded directly on the chip and an additional set of commands, associated with MMU and BPU operations, are also decoded on chip. 2.2. BUS ARBITRATION The MA31750 has a number of extra control lines to allow its use in a system utilising multiple processors. A bus request and grant system coupled with external arbitration logic allows common data and address buses to be used between devices. A lock request pin is also provided to allow the processor to maintain control of the buses when modifying areas of shared memory. 2.3. MEMORY BLOCK PROTECTION The basic MMU function allows write or execute protection to be applied on 4KWord block boundaries. This may be further resolved to 1kWord blocks by the inclusion of a Block Protect Unit (BPU). The MA31751 can act as both an MMU and a BPU in 1750A mode, operating with the full compliment of 1MWord of memory. It will also support expansion to 8MWord in accordance with Draft MIL-STD-1750B.
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3. MODES OF OPERATION
MA31750 operating modes include: (1) initialisation, (2) instruction execution, (3) interrupt servicing, (4) fault servicing, (5) timer operations and (6) console operation. 3.1. INITIALISATION The MA31750 executes a microcoded initialisation routine in response to a hardware reset or power-up. Figure 3 shows a cycle-by-cycle breakdown of this routine. The operations performed are dependent on the system configuration read by the processor during startup. Figure 2 summarises the resulting initialisation state.
MA31750 Instruction Counter Status Word Fault Register Zero Fault Mask Register (1750B) Pending Interrupt Register Interrupt Mask Register General Registers Interrupts Timers A and B Timer Reset Registers (1750B) Trigger-Go Counter TGON Line Start-Up ROM DMA MMU Page Registers AL/W/E fields Page Register PPA field BPU Memory Protect RAM Global Memory Protect
The last action performed by the initialisation routine is to load the instruction pipeline. Instruction fetches start at memory location zero with AS = 0, PS = 0 and PB = 0 and will be from the Start-Up ROM (SUR) if implemented. Whether BIT passes or not, the processor will begin instruction execution at this point. The system start-up code may include a routine to enable and unmask interrupts in order to detect and respond to a BIT failure if required.
Addr 0 1 *2 3 1F 20 21 4 5 6 13 14 15 16 *17 *18 19 1A 1B 1C *1D 1E 7 8 9 A B C D E *F 10 32 33 34 35 36 11 12 *3F8 *3F9 Operation PIC initialised A<-- 0x8410 Read external configuration register from 8410H (CONFWN asserted low) If BPU, N<-- 128 else N<-- 0 Decrement N; branch to 21 if N >= 0 Write internal configuration register If no MMU, br to 7 N <-- 256 Decrement N Write MMU Instruction Page Register N Write MMU Operand Page Register N; branch to 16 if N>0 A <-- 0400H N <-- 16 PBSR <-- N Write Memory control register to MMU with PB = N Decrement N; branch if N >= 0 to 1B A <-- 0 IC <-- A Br to BIT if required Br if no SUR to 00D Re-init PIC Zero SW Br to 011 if BIT passed (or not run)
Zero Zero Zero All ones Zero Zero Undefined Disabled Zeroed and started Zero Reset and started High Enabled Disabled
Zero Logical to physical
Zero (disabled) Enabled
Figure 2: Initialization State
Set FT bit 13 Init DMAE, SUREN, NPU
Fetch first word from 0 Fetch second word from 1 First instruction first cycle * Indicates an external cycle
Figure 3: Initialization Sequence
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3.1.1. CONFIGURATION REGISTER The system configuration register allows the MA31750 to function with a variety of different system designs. Implemented features such as a BPU should be indicated as present by setting bits in an externally-implemented 16-bit latch - see figure 4 for bit assignments. The latch must be placed in IO space at the address defined by XIO RCW (8410) shown in the table of XIO commands, Figure 20c. The processor decodes this command internally and produces a discrete output signal CONFWN which may be used as the external register Output Enable control.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15 MMU Select 0 BPU Select 0 1 = Console operation enabled MMU Select 1 Interrupt sensitivity (1 = level, 0 = edge) MMU Select 2 Parity sense (1 = odd, 0 = even) 1= BIT on power-up 1 = Start-Up ROM present 1 = DMA device present 1=1750A mode, 0=1750B mode 1=Instruction set expansion enabled BPU Select 1 BPU Select 2 Reserved for future expansion Function
Selected bit Function MMU2 MMU1 MMU0 0 0 0 No MMU in system 0 0 1 1 Page Bank (PB0) 0 1 0 2 Page Banks (PB0-1) 0 1 1 4 Page Banks (PB0-3) 1 0 0 8 Page Banks (PB0-7) 1 0 1 16 Page Banks (PB0-15) 1 1 X 16 Page Banks (PB0-15) Note: In 1750A mode, setting any or all of the MMU select bits indicates the presence of an MMU.
Figure 5: MMU Selection Bits
3.1.2. BUILT-IN TEST (BIT) BIT consists of ten subroutines, as outlined in Figure 6. If all ten subroutines execute successfully, or no BIT is selected in the configuration word, a BIT pass is flagged (seen externally as NPU raised high by the initialization routine). If any part of BIT fails, a corresponding bit identifying the failed subroutine is set in General Register R0, Fault Bit 13 is set in the Fault register (FT) and NPU is left in the low state. Figure 6 defines the coding of BIT results in R0. In the event of such a failure, the resulting processor reset state will be dependent on where in BIT the error occurred and may not be the same as that shown in figure 2. A BIT failure indication in FT will set the level 1 interrupt request bit of the Pending Interrupt (Pl) register. Since initialisation disables and masks interrupts, this interrupt request will not be asserted. Any external interrupts or faults occurring during BIT will be cleared before program execution begins and will not be serviced.
Test Coverage Machine Cycles 47 79 18 5632 Bit set on fail 7 7 8 9 10 11 12 13 14 15
Figure 4: Configuration Word Bits
The processor maintains an internal configuration register which is updated from the external register during initialisation and during the execution of a NOP/BPT (No-op/Breakpoint) instruction. The internal configuration register is used to control the CPU. Note that although the external register can be read using XIO RCW, this does not affect the internal configuration. Note: if the interrupt level/edge trigger select bit - (bit 4) is changed in the internal register during normal operation of the device, one or more spurious interrupts may occur. When in 1750B mode, the processor needs to know how many Page Banks are implemented in the external system so that Status Word changes can be protected properly. MILSTD-1750B allows the options 0,1,2,4,8 or 16. The actual selection should be coded into the three configuration register bits MMU0, MMU1 and MMU2 as shown in figure 5. In 1750A mode, setting any of the MMU select bits indicates the presence of an MMU, the actual code is unimportant in this mode. BPU selects bits 2:0 should be set to indicate how much BPU-protected memory exists on the system. If no BPU is present, all three bits should be zero.
Temporary Registers (T0-T11) General Registers (R0-R15) Flags Block Sequencer Operation and ROM checksum Divide routine Quotient Shift 12 Network Multiplier and ALU 13 Barrel shift Network 13 Interrupts and fault handling and 17 detection Address generator block 13 Instruction pipeline 15 Note: BIT pass is indicated by all zeros in FT bits 13,14, and 15
Figure 6: Built-In Test Coverage
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3.2. INSTRUCTION EXECUTION Once initialisation has been completed, the processor will begin instruction execution. Instruction execution is characterised by a variety of operations, each is one machine cycle in duration (two or more system CLK periods). Depending on the instruction being executed at the time, these operations include: (1) internal CPU cycles, (2) instruction fetches, (3) operand transfers, and (4) input/output transfers. Instruction execution may be interrupted at the end of any individual machine cycle by an interrupt or Console request. Internal cycles are always two CLK periods long, whilst the other cycle types are a minimum of two CLK periods extendable by inserting waitstates. In all cycles except internal cycles, RDN, WRN, DSN and AS strobes are produced to control the transfer and latching of data and address around the system.
Cycle Type Internal Cycle Instruction Fetch
RD/WRN O/IN H L H L
M/ION H H
Operand Read Operand Write IO Read IO Write
H L H L
H H H H
H H L L
Description Used to perform all CPU data manipulation operations where bus activity is not required. Used to keep the instruction pipeline full with instructions and/or their postwords. At least one instruction is always ready for execution when the preceding instruction is completed. During jump and branch instruction execution the pipeline is refilled by two consecutive instruction fetches starting at the new instruction location. It is also refilled as part of interrupt request processing. Used to read in data from the external system and to write results to the system. Input/Output transfers utilize the MIL-STD-1750 XIO and VIO instructions. RD/WN defines the direction of the transfer. IO transfers may be divided into three groups; those commands which are implemented internally by the CPU, those commands which are implemented by external system hardware and those commands defined as illegal by MIL-STD-1750A and B.
Figure 7: External Cycle Types
3.3. IO OPERATION The MA31750 supports a 64KWord addressing space dedicated to IO control and communication in accordance with MIL-STD-1750. The control line MION is asserted low when accessing IO space (see figure 7 above for other strobe states). One of the two commands XIO or VIO is used to specify both data for the transfer and the port address (referred to as an XIO Command in 1750). The CPU contains logic which decodes all internally supported XIO commands and generates the control signals necessary to carry out the commanded action. In addition, the validity of a command not implemented internally is verified. Figure 20c identifies the XIO commands which are internally supported by the MA31750. 3.4. INTERRUPT AND FAULT HANDLING 3.4.1. STATUS WORD (SW) Figure 8 depicts the status register format. This 16-bit word is divided into four, 4-bit sections. Three of these sections [AS, PS and, (1750B mode) PB] are control bits for implementing expanded memory with an external MMU. The fourth section, CS, is used to hold the carry, positive, zero and negative condition flags set by the result of the previous arithmetic operation.
0 CS
34
78 R (PB) PS
11 12 AS
15
Field
Bits
Description
CS
0 1 2 3
CONDITION STATUS C- Carry from an addition or no borrow from a subtraction. P- Result > 0 Z- Result = 0 N- Result < 0 RESERVED (=0) in 1750A mode Page Bank Select in 1750B mode PROCESSOR STATE: (a)- Memory access to key code (b)- Priviledged instruction enable ADDRESS STATE: Page register sets for expanded memory addressing.
R PB PS
4-7 8-11
AS
12-15
Figure 8: Status Word Format
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The AS field is used during expanded memory access to define the page register set to be used for instruction and operand memory references. The PS field is used during memory protect operations to define the access key used for memory accesses. The PS field is also used during execution of privileged Instructions - PS must be zero for such operations to be legal. See Section 4.3 for further information on the use of this field. The PB field is used in conjunction with the AS field in 1750B mode to expand the number of page registers available. Note that attempting to set AS or PB to a non-zero value with no MMU, or setting PB to a non-zero value in 1750A mode is illegal. This will be aborted and a fault 11 will be generated (SW will remain unchanged). 3.4.2. PENDING INTERRUPT REGISTER (PI) This 16-bit register is used to capture and hold interrupts until they can be processed by microcode and user software. A logic 1 is used to represent an active pending interrupt. The Pl register supports three dedicated external, six user-definable external, and seven dedicated internal interrupts. Levelsensitive interrupts are sampled on each rising CLK edge, whilst edge sensitive interrupts are captured immediately.
System Interrupts PWRD 0 1 INT02 2 3 4 5 6 7 INT08 8 9 INT10 INT11 IOI1 INT13 IOI2 INT15 10 11 12 13 14 15
Internal Interrupts (Cannot be disabled or masked) Machine Error (Cannot be disabled)
System Faults MPROE (CPU) MPROE (DMA) PE (CPU memory) 0 1 2 3 4 5 6 FLT7 EXADE or Bus Timeout (CPU memory) 7 8 9 10 11 Reserved SYSF EXADE (DMA) SYSF 12 13 14 15
Internal Faults
Floating-Point Overflow Fixed-Point Overflow Executive call (Cannot be disabled or masked) Floating-Point Underflow Timer A Overflow
PE (CPU IO) PE (DMA) EXADE or Bus Timeout (CPU IO)
Parallel IO Transfer Error
Timer B Overflow
Illegal Instruction Opcode Priviledged Instruction Unimplemented Address State
MA31750 BIT Fail
Figure 9: Pending Interrupt Bit Assignments
Figure 10: Fault Register Bit Assignments
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3.4.3. MASK REGISTER (MK) This 16-bit register is used to store the interrupt mask. Interrupts are masked by ANDing each mask bit with its corresponding Pl register bit. ie. A logic zero in a given bit position indicates that the corresponding bit in the Pl register will be masked. Interrupts which are masked will be captured in the Pl register but will not be acted on until unmasked. Interrupt level zero can not be masked. 3.4.4. PRIORITY ENCODER This encoder generates an interrupt request to the sequencer block whenever one or more unmasked interrupts are pending and enabled in the Pl. The highest priority unmasked pending interrupt is encoded as a 4-bit vector. This vector is used during interrupt servicing in order to create the interrupt linkage and service pointers. 3.4.5. FAULT REGISTER (FT) This 16-bit register is used to capture and hold both internal and user implemented external faults using positive logic, i.e., a logic one represents a fault. Bus cycle faults are captured at the end of each machine cycle whilst the two general purpose faults SYSFN and FLT7N are set when the low time exceeds the minimum pulse width. Setting any one or more faults in FT will cause a level 1 (machine error) interrupt request. Once a fault is set in FT, it may only be cleared via an XIO command. In 1750B mode, a fault mask register is provided to allow selective masking of fault conditions. Section 4 (Software Considerations) contains further information. Figure 27 shows the fault register assignments. 3.4.6. MEMORY FAULT PAGE AND ADDRESS REGISTERS These registers capture the page and address information at the end of each external cycle until a memory fault occurs. Faults setting bits 0, 1, 2 and 8 in the fault register cause the registers to stop latching new address information, so retaining information about the address at which the fault occured. The registers can be read (using the GPS defined XIOs RMFP and RMPA). The fault register must be cleared and both memory fault registers read before latching can restart. The information stored in the memory fault registers is as follows: MFPR[0:3] A[0:3] MFPR[12:15] AS[0:3] MFPR[4:7] MFPR[8:10] PB[0:3](ASOB) Res MFAR[0:15] A[0:15] MFPR[11] ION
CPU status at time of interrupt
Interrupt 0
Linkage Pointer 0 Service Pointer 0 Linkage Pointer 1 Service Pointer 1
Old Interrupt Mask Old Status Word Old Instruction Counter
Interrupt 1
Status at start of Service Routine New Interrupt Mask
Interrupt 15
Linkage Pointer 15 Service Pointer 15
New Status Word New Instruction Counter
Figure 11: Interrupt Vectoring
3.4.7. INTERRUPT SERVICING Nine user interrupt request inputs are provided for programmed response to asynchronous system events. A low on any of these inputs will be detected at the rising edge of CLK (level sensitive interrupts only) and latched into the Pending Interrupt (Pl) register on the falling edge of CLK at the end of the current CPU cycle. This sequence occurs whether interrupts are enabled or disabled or whether the specific interrupt is masked or unmasked. More details of interrupt operations are available in Applications Note 4. All of the user interrupts PWRDN, INT02N - INT15N may be programmed to be either level or edge sensitive by setting or clearing the appropriate bit in the system configuration register. If edge sensitivity is selected then an interrupt request input must return to the high state before a subsequent request on that input will be detected. If level sensitivity is selected then holding an interrupt input low will cause a new interrupt to be latched following each service. Note that interrupts IOI1N and IOI2N are level sensitive only. In order that the system may recognise when a service has been started, an interrupt acknowledge pin is provided. During the microcoded interrupt service routine execution, the processor will read the Linkage Pointer address in memory. During this operand read cycle, the processor will also assert INTAKN low, which may be used in conjunction with AS and address bus bits A[11:14] to reveal the priority level of the interrupt being serviced. (A[11:14] = 0 indicates level 0 interrupt, A[11:14] = 1 indicates level 1 interrupt, and so on). INTAKN should also be used to remove level-sensitive interrupt requests to ensure that repeated requests are not generated.
Note: MFPR[11] is the inverse of OIN.
These registers are only available if there is an MMU in the system. If there is no MMU present, then the RMFP and RMFA XIO commands become illegal. The address information held in these registers can be used to restart code after a memory fault has occurred. Bits [6:7] of the OAS register store information on the type of instruction which was being executed when the fault occured: 00 branch that was taken 01 single word instruction 10 double word instruction (Subtracting this value from the saved address will give the address of the failed instruction unless it was a branch that was taken).
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Interrupt LP No. Address PWRD 0 20 ME 1 22 INT02 2 24 FI.P o/f 3 26 Fx.P o/f 4 28 BEX 5 2A FI.P u/f 6 2C Timer A 7 2E INT08 8 30 Timer B 9 32 INT10 10 34 INT11 11 36 IOI1 12 38 INT13 13 3A IOI2 14 3C INT15 15 3E Note: Addresses (in hex) are in operand SP Address 21 23 25 27 29 2B 2D 2F 31 33 35 37 39 3B 3D 3F space
If an address state fault occurs during the service routine, interrupt level 1 will be set. This interrupt will be serviced when interrupts are re-enabled unless it is masked by the new value in MK. 3.4.8. FAULT SERVICING Five user fault inputs are provided. A low on any of the three bus-cycle-related fault inputs, EXADEN, MPROEN or PEN, will be latched into the Fault Register (FT) on the next falling edge of AS. A low on either of the two general purpose fault inputs, FLT7N or SYSFN, will be latched immediately and will be sampled into the appropriate bit of FT on the falling edge of AS. Any fault which sets a bit in the FT immediately causes a level 1 pending interrupt to be entered into the PI register. This interrupt is maskable but may not be disabled. This interrupt will be serviced at the end of the currently executing 1750 instruction if not masked. The microcoded interrupt service routine reads the interrupt priority vector and clears the bit relating to the serviced interrupt from the PI. However, the FT retains the set fault bits until the FT is cleared using the XIO RCFR command. (A non-destructive read of the FT is provided by the XIO RFR command.) Anti-repeat logic between the FT and the PI prevents the same fault being latched and serviced twice. However, as all FT bits are ORed together and input to PI bit 1, this also prevents any other faults being serviced until the fault register has been cleared. It is imperative, therefore, that the fault service routine executes a RCFR XIO before exiting. Different types of faults are serviced slightly differently as follows: 3.4.8.1. MPROEN and EXADEN If MPROEN and/or EXADEN are low on a falling clock edge with AS and DSN high (see figure 23a), the processor will wait in this state. If either fault input remains low during two falling edges of TCLK, the cycle is forced to complete but RDN/ WRN and DSN are inhibited (see figure 24b). This allows the processor to prevent erroneous accesses. An access fault will be registered as AS falls at the end of the cycle. 3.4.8.2. PEN External parity errors are latched into the FT on the falling edge of AS. The fault bit set is dependant upon the type of transfer taking place (memory, IO or DMA). 3.4.8.3. FLT7N and SYSFN These faults are latched immediately, but are not sampled into the fault register until the following falling edge of AS. 3.4.9. PARITY GENERATION AND CHECKING The MA31750 features on-chip parity generation and checking on all data bus transfers. Data generated by the processor has a parity bit attached to it to allow external logic to verify write transfers. On read transfers, the processor will check the incoming parity (if enabled) and will generate the appropriate parity error fault if detected. However, the data to be checked is only available as DSN rises at the end of the cycle so the error flag is generated and latched in the cycle following the erroneous cycle. Parity checking may be
Figure 12: Interrupt Pointer Address
When an interrupt request is latched into Pl, it is ANDed with its corresponding mask bit in the mask register (MK). NOTE: Interrupt level 0 is non-maskable. Any unmasked pending interrupts are output to the priority encoder where the highest priority is encoded as a 4-bit vector. If interrupts are enabled and an unmasked interrupt is pending, the priority encoder will assert an interrupt request to the sequencer. 1 or 2 extra CLKs will be inserted into the machine cycle on which the interrupt request is asserted. Upon completing execution of each MIL-STD-1750A or B instruction, the sequencer checks the state of the priority encoder interrupt request. If a request is asserted, the sequencer branches to the microcode interrupt service routine. This routine reads the 4-bit pending interrupt vector and then uses this value to calculate the appropriate interrupt linkage (old processor context save area) and service (new context load area) pointers. Figure 11 depicts this relationship. Figure 12 defines the pointer values. Using the linkage and service pointers, the microcode interrupt service routine performs the following: (1) the current contents of the status word, mask register, and instruction counter are saved; (2) a write status word (WSW) I/O command is executed with an all zero data word; (3) the new mask is loaded into MK and interrupts are disabled; (4) the new status word is read and checked for a valid Address State (AS[0:3]) field - If the address state is non-zero and an MMU is not present, AS[0:3] is set to zero and fault 11 (address state error) is set in the fault register FT); (5) a write status word command using the new status word is performed; and (6) the new IC value is loaded into IC, the instruction pipeline is flushed and refilled starting at the new address, and instruction execution begins. [NOTE: The steps listed above represent a summary of actions performed during interrupt servicing and do not necessarily reflect the actual order in which these events take place.]
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disabled when operating with devices which do not support parity generation by asserting the DPARN (Disable Parity) input low. The checking polarity (odd or even) is selectable with Configuration Register bit 6. 3.5. TIMER OPERATIONS The MA31750 implements interval timers A and B, a trigger-go counter, and a bus fault timer. A discussion of each follows: 3.5.1. TIMERS A AND B Two general-purpose, 16-bit timers are provided in the processor. Timer A is clocked by the TCLK input; timer B is clocked by an internally generated TCLK/10. The divider circuit is reset when Timer B is reset to give deterministic processor operation. MIL-STD-1750 requires TCLK to be a 100kHz pulse train. If allowed to overflow, timers A and B will set level 7 and level 9 interrupt requests respectively. Each timer can be read, loaded, started and stopped by using XIO commands as identified in figure 20c. Each timer has associated with it a reset register from which the timer is automatically loaded following a software reset or overflow. These registers are initially loaded with zero but may be reloaded from software (using the XIO instructions OTA and OTB) to provide greater control over the count period. The MA31750 timers A and B will be disabled when the device enters Console mode, as required by MIL-STD-1750A Notice 1. 3.5.2. TRIGGER-GO COUNTER This 16-bit counter is clocked by the TCLK input and is typically used as a system "watchdog" timer. It is enabled during system initialisation and may be preset under software control to give a wide range of timeout intervals. In order that the count period may be controlled, a reset register is provided. On reset, this register is loaded with zero, but can be reloaded under software control to take any value between 0 and FFFF16 (a value of zero gives the maximum count period). This allows the timeout period to be varied between 20us and 0.65s. Note that there is no value which disables the timer. The counter is incremented on each TCLK falling edge. Whenever the trigger-go counter overflows, TGON drops low and remains low until the counter is reloaded from the reset register via the GO internal XIO command. TGON low would typically be used to initiate a user-defined system recovery action such as a system reset. 3.5.3. BUS FAULT TIMER All bus operations are monitored to ensure timely completion. A hardware timeout circuit is enabled at the start of each memory and l/O transfer (DSN high-to-low transition) and is reset upon receipt of the external ready (RDYN) signal. If this circuit fails to reset within a minimum of one TCLK period or a maximum of two TCLK periods, either bit 8 (if the transaction is with memory) or bit 5 (if the transaction is with l/ O) of the Fault Register (FT) is set. This sets Pending Interrupt level 1 and causes the strobes to be suppressed and the current bus cycle to be aborted. The MIL-STD-1750 instruction is aborted, and control passes to the level 1 interrupt service routine (if the level 1 interrupt is unmasked). The timeout mechanism is disabled and reset if DTON is asserted low. 3.6. CONSOLE OPERATION The MA31750 is capable of interfacing directly to an external console, allowing the developer to: examine and change the contents of internal registers, memory and IO devices; single step code and halt the processor. Applications Note 3 provides a full description of the Console interface, its implementation and operation. 3.7. MULTIPROCESSOR SUPPORT Once initialisation has been completed, the processor will begin instruction execution by executing a sequence of microinstructions, each one machine cycle (two system clock periods) long. Each machine cycle may perform either an internal or an external operation; if the operation is purely internal then the system busses will not be in use and may be reassigned to another processor. An external machine cycle (indicated by REQN low during the second half of the previous cycle) will cause the processor to stall upon completion of the current microcycle, awaiting GRANTN asserted low. Whilst GRANTN is high the busses remain undriven. In simple, single processor systems which use no DMA devices the GRANTN line should be tied to GND to allow the processor to retain control of the busses. The LOCKN and REQN pins can be left open-circuit in this case. Applications Note 11 provides further information for designers of systems with more than one bus master.
4. SOFTWARE CONSIDERATIONS
4.1. OPERATING MODES The MA31750 is capable of being operated in one of two basic modes as previously mentioned. These are described in detail below: 4.1.1 1750A MODE 1750A mode is a full implementation of MIL-STD-1750A (Notice 1) and includes some of the optional features mentioned in this standard. 4.1.2 1750B MODE 1750B mode is an implementation of the proposed MILSTD-1750B, Option 2, Draft of 17th July 1988. This mode extends the basic 1750A mode operation. Note that the transcendental functions SIN, COS, LN etc. (Option 3 of MILSTD-1750B) are not supported. Features new to MIL-STD1750B which are in violation of MIL-STD-1750A are only enabled in 1750B mode. The additional instructions available in 1750B mode are detailed in figure 20b. 4.2. ACCESSING IO USING XIO AND VIO COMMANDS MIL-STD-1750 defines a 64KWord addressing space which is available exclusively for accessing IO resources. Two special commands, XIO and VIO, are provided as part of the instruction set for accessing this space. Port addresses are specified as a 16-bit Command word which is supplied as a parameter to the XIO/VIO instruction. The MSB of the Command word indicates the direction of data transfer between the port and the register specified in the XIO command (a 1 in the MSB indicates that the port is being read, whilst 0 indicates a write to the port).
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Output 0000-03FF 0400-1FFF 2000-20FF 2100-2FFF 3000-3FFF 4000-40FF 4100-4CFF 4D00-4FFF 5000-50FF 5100-51FF 5200-52FF 5300-7FFF Input 8000-83FF 8400-9FFF A000-A0FF A100-AFFF B000-BFFF C000-CFFF C100-CCFF CD00-CFFF D000-D0FF D100-D1FF D200-D2FF D300-FFFF Usage PIO Spare CPU and auxiliary register control Reserved Spare CPU and auxiliary register control Reserved Extended memory protect RAM Memory protect RAM MMU Instruction Page Registers MMU Operand Page Registers Spare 4.4. USING START-UP ROM The transition between code execution from Start-up ROM and system RAM must be made with care. If a system overlays RAM with the Start-Up ROM and the transition is made by simply executing XIO DSUR from the ROM, then the instruction pipeline will contain the value stored in the ROM location immediately following the XIO DSUR command. This value will be treated as an instruction and the processor will attempt to execute it. In such cases, it is recommended that DSUR be followed by an unconditional branch instruction with offset, i.e. the BR instruction. An alternative approach is simply to jump to a portion of RAM not overlaid by the Start-Up ROM and execute DSUR from RAM. 4.5. USING SOFTWARE TIMERS A AND B The MA31750 implements the two software timers, A and B as defined in the MIL-STD 1750A specification. These are general purpose timers which are clocked at 100kHz and 10kHz respectively, giving clock `tick' intervals of 10us and 100us respectively. They may be started using the XIO TAS and XIO TBS instructions, and stopped using XIO TAH and XIO TBH. If a timer is allowed to overflow (FFFF16 - 000016) it will generate pending interrupt levels 7 (A) or 9 (B). In 1750B mode each timer has associated with it a reset register which may be loaded with any 16-bit value from software. If a timer is allowed to overflow, an automatic reset will take place which will reload the timer with the value held in its on-chip reset register, provided that the timer had previously been loaded using XIO OTA/OTB. If this is not the case, then the timers will reset to zero on overflow. Each of the reset registers is initialised to zero but may be changed using XIO OTAR or XIO OTBR. 4.6. FAULT MASK REGISTER A fault mask register is accessible in 1750B mode. Its function is similar to that of the Interrupt Mask register and allows selective enabling and disabling of all bits in the Fault Register. All faults are maskable. Setting a bit in this register allows the corresponding fault bit to be seen by the system. The mask register is loaded with FFFF16 on initialisation. 4.7. GENERAL REGISTERS R0-R15 There are 16 general purpose registers defined by MILSTD-1750; each is 16-bits wide. Adjacent registers may be concatenated to provide storage for the larger data formats (Double Integer and Float - 32-bit; Extended Float - 48-bit). The first register in the set stores the most significant data word and is the register specified when referring to the value. Wrap-around occurs between R15 and R0. Although generally all registers are the same, certain registers are notionally assigned to particular tasks, see figure 15.
Figure 13: XIO Command Channel Grouping
XIO command addresses are grouped by the Standard according to function. Certain groups are `reserved' and must not be implemented. Attempts to read or write these areas will be prevented by the processor and a fault will be logged in the fault register. Other groups are designated `spare' and may be implemented as required by the system designer. Note, however, that there is a third group which access system resources such as MMU page registers and interrupt control registers which are not available to the user to implement. A summary of the XIO map is provided in figure 13, whilst the detailed list of implemented command addresses is shown in Figure 20c. The VIO (Vectored IO) command allows a number of IO operations to be executed in a sequence from a table. Applications Note 8 gives further information on the use of this command. Both XIO and VIO are priveleged commands and as such can only be executed when the Status Word PS field is zero. 4.3. PROCESSOR STATE AND PRIVILEGED INSTRUCTIONS The Processor State is defined by a 4-bit value held in the processor Status Word. If the value is made non-zero then attempts to execute the commands XIO, VIO or LST will be aborted and a fault will be raised. This is intended to deny direct access to the hardware from user applications (running in PS0), whilst allowing the Operating System (operating with PS=0) access to the system IO and interrupt resources. If an MMU is present on the system the PS field is used in conjunction with the page register Access Key field to provide a further level of protection to the system. When PS=0 access is granted to all pages, irrespective of their key value. If PS is non-zero, access is only permitted if the Access Key is equal to the PS value, or the Access Key is 15. Access Key 15 should be applied to a shared area of code or data, and is accessable to all PS values.
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4.8. MIL-STD-1750 DATA TYPES The MA31750 fully supports 16-bit fixed-point singleprecision, 32-bit fixed-point double-precision, 32-bit floatingpoint, and 48-bit extended precision floating- point data types. Figure 16 depicts the formats of these data types. All numerical data is represented in two's complement form. Floating-point numbers are represented by a fractional two's complement mantissa with an 8-bit two's complement exponent. All floating-point operands are expected to be normalised. If not normalised, the results from an instruction are not defined. 4.9. MIL-STD-1750 ADDRESSING MODES The MA31750 supports the eight basic addressing modes specified in MIL-STD-1750A. These addressing modes are depicted in Figure 18 and are defined below. In binary operations one operand is assumed to be in a register (specified as part of the opcode) whilst the second operand (the Derived Operand, DO) is taken from a source which is dependent upon the addressing mode, see figure 17. Many adddressing modes may be specified as indexable: the index register may be any of the general purpose registers R1-R15 (if 0 is specified then the non-indexable form is used). For Base Relative addressing modes the first operand is fixed as part of the instruction (either R0 for Double Integer operations, or R2 for Single Integer operations). 4.10. MEMORY ADDRESSING CAPABILITY In accordance with MIL-STD-1750A, the MA31750 can access a 64KWord address space directly. With the addition of a single external Dynex Semiconductor MA31751 chip, configured as a Memory Management Unit (MMU), this address space may be expanded to 1MWord (1750A mode) or 8MWord (1750B mode). The MA31751 data sheet gives further information on the MMU/BPU chip and on the memory management scheme employed. Note that whilst one MMU can be used to provide the full range of physical addresses to the system memory, the logical addressing capability may also be expanded by adding further MMU devices up to a maximum of 16.
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Status Word (SW)
Instruction Counter (IC)
Fault Register (FT) Fault Mask (1750B only)
Pending Interrupt (PI) Interrupt Mask (MK)
Timer A Timer A reset (1750B only) Timer B Timer B reset (1750B only)
Trigger-Go Reset Register
Configuration
Figure 14: Register Set Model
Register(s) R0 R2 R3-R11 R12-R15 R15
Notional Use or Restriction on Use Cannot be used as an index register With R1: Implied register in Double mode Base Relative addressing Implied register in Single mode Base Relative addressing General purpose Base relative registers Stack pointer in PSHM and POPM operations
Figure 15: General Register Usage
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Byte MSB LSB MSB LSB Upper byte 0 Lower byte 15 Unsigned Single Precision Fixed-Point (1750B) MSB LSB Unsigned value 15 0 15
Single Precision Fixed-Point MSB LSB Value 0
Double-Precision Fixed-Point MSB Value 0 Unsigned Double Precision Fixed-Point (1750B) MSB Unsigned value 0 Floating Point MSB Mantissa 0 Extended Precision Floating Point MSB Mantissa (Most significant) 0
LSB
31
Note: All values are Signed 2s complement unless shown as unsigned.
LSB
31
LSB MSB
LSB
Exponent 23 24 31
LSB MSB
LSB MSB
LSB
Exponent 23 24
Mantissa (Least Sig.) 47
31 32
Figure 16: Data Formats
Mode R D, DX I, IX IM, IMX ISP ISN ICR B BX S Name Register Direct Memory Direct Memory Indirect Immediate Long Immediate Short Positive Immediate Short Negative Instruction Counter Relative Base Relative Base Relative Indexed Special Derived Operand The operand is contained in a regular specified by the instruction. The instruction postword (plus RX if RX 0), contains the memory address of the operand. The instruction postword (plus RX if RX 0) contains the address of the address which holds the operand. The instruction postword (plus RX if RX 0) holds the operand. The operand value is specified as part of the instruction. (ISP specifies values between 0001 H and 0010H, ISN specifies values between FFFFH and FFEFH). The operand value is specified as part of the instruction. (ISP specifies values between 0001n and 0010n, ISN specifies values between FFFFn and FFEFn). A 2s-complement, 8-bit displacement which is sign-extended and added to the Instruction counter to provide an offset of -128 to +127. Data at address given by: contents of specified base register (R12-R15, specified by opcode), plus unsigned 8-bit displacement field from opcode. Data at address given by contents of specified base register (R12-R15, specified by opcode), plus contents of RX register if RX R0 See instruction for details.
Figure 17: Address Mode Summary
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INSTRUCTION
MODE 1. Register Direct "R" 0 2. Memory Direct "D" "DX" OC RX = 0 (Non-indexed) RX 0 (Indexed) 0 3. Memory Indirect "I" "IX" 4. Immediate Long a. Not indexable "IM" OC RX = 0 (Non-indexed) RX 0 (Indexed) 0 OC 0 b. Indexable "IM" "IMX" 5. Immediate Short a. Positive "ISP" b. Negative "ISN" 0 6. IC Relative "ICR" 0 7. Base Relative a. Not Indexable "B" OC BR' = BR - 12 0 b. Indexable "B" "BX" OC 56 BR' 78 11 12 OCX RX 15 OC 56 BR' 78 DU OC RX = 0 (Non-indexed) RX 0 (Indexed) 0 OC 0 OC 78 D 78 RA 78 RA 11 12 I 15 11 12 I 15 15 78 RA 78 RA 11 12 RX 11 12 OCX 15 16 15 16 78 RA 11 12 RX 15 16 MSB 0 OC 78 RA 78 RA 11 12 RX FORMAT 11 12 RB MSB 15 16 LSB 15
POSTWORD
LSB 31 A
31 A
31 I 31 I
Legend 15 OC RA RB RX A OCX I D BR' DU S1, S2 = Operation Code = Destination Register = Source Register = Index Register = Address (logical) = Extension to Operation Code = Immediate Data = Displacement = Base Register Reference = Displacement (positive) = Special Code
RX = 0 (Non-indexed) RX 0 (Indexed) 0 78 OC S1 11 12 S2 15
8. Special "S"
Figure 18: Addressing Modes
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5. PERFORMANCE
5.1. BENCHMARKING Figure 20a defines the number and type of machine cycles associated with each MIL-STD-1750 instruction. This information may be used when benchmarking MA31750 performance. The Digital Avionics Instruction Set (DAIS) mix, which defines a typical frequency of occurrence for MIL-STD1750A instructions, is used here for this purpose. One problem with the DAIS mix is that it does not reflect the impact of data dependencies on system performance. E.g. a multiplication in which the operand is zero may be performed much faster than one with two non-zero operands. Realistic benchmarks must therefore take both the instruction mix and data dependencies into account. To this end, machine cycle counts in figure 20a which have data dependencies are annotated with either an "a" or "wa" suffix. An "a" suffix reflects an average number of machine cycles (where each of several possibilities is equally likely) and a "wa" suffix reflects a weighted average number of machine cycles (where some data possibilities are more likely than others). Weighted averages are only applicable to floating-point operations. Normalisation and alignment operations are also represented. Figure 19 shows MA31750 throughput, at various frequencies and wait states, for the floating point DAIS mix. 5.2. EXPANDED MEMORY PERFORMANCE The inclusion of an MMU (Memory Management Unit) will degrade the throughput performance of the processor in two ways. Firstly, each memory access will have an additional overhead associated with the formation of the extended address from the MMU. This may require that the processor inserts wait states to lengthen each external cycle. Secondly, the MMU itself may require that some `housekeeping' work be done by the processor, which will lengthen the program execution time. There are no widely accepted benchmarks which may be used to measure the resultant decrease in throughput.
3.5 3 2.5 Performance (MIPS) 2
25MHz
1.5
20MHz
1 0.5 0 0 1 2 Waitstates 3
15MHz 10MHz 5MHz
4
Figure 19: Throughput (MIPS) with Waitstates
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5.3. INSTRUCTION SUMMARY
OPERATION
Mnem.
Format
Opcode (Ext)
Memory cycles
Internal Cycles
SINGLE LOAD/STORE Single Precision Load
Double-Precision Load
Single-Precision Store
Store Non-Negative Constant Double-Precision Store
Load Multiple Registers Store Multiple Registers
COMPARE Single-Precision Compare
LR LB LBX LISP LISN L LIM LI DLR DLB DLBX DL DLI STB STBX ST STI STC STCI DSTB DSTX DST DSTI LM STM
CR CB CBX CISP CISN C CIM CBL DCR DC LUB LUBI LLB LLBI STUB SUBI STLB SLBI XBR
R B BX ISP ISN D,DX IM,IMX I,IX R B BX D,DX I,IX B BX D,DX I,IX D,DX I,IX B BX D,DX I,IX D,DX D,DX
R B BX ISP ISN D,DX IM D,DX R D,DX D,DX I,IX D,DX I,IX D,DX I,IX D,DX I,IX S
81 0X 4X 0 82 83 80 85 84 87 0X 4X 1 86 88 0X 4X 2 90 94 91 92 0X 4X 3 96 98 89 99
F1 3X 4X C F2 F3 F0 4A A F4 F7 F6 8B 8D 8C 8E 9B 9D 9C 9E EC
1 2 2 1 1 3 2 4 1 3 3 4 5 2 2 3 4 3 4 3 3 4 5 3+n 2+n
1 2 2 1 1 3 2 4 1 4 3 4 3 4 4 5 4 5 1
0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1
0 1 1 1 0 0 0 2.7a 0 0 1 1 0 0 0 0 1 1 0
Compare Between Limits Double-Precision Compare BYTE Load From Upper Byte Load From Lower Byte Store Into Upper Byte Store Into Lower Byte Exchange Bytes in Register
Figure 20a: Instruction Summary
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OPERATION
INTEGER ARITHMETIC Single-Precision Integer Add
Mnem.
Format
Opcode (Ext)
A1 1X 4X 4 A2 A0 4A 1 A3 A4 A5 A7 A6 B1 1X 4X 5 B2 B0 4A 2 B3 B4 B5 B7 B6 C1 C2 C3 C0 4A 4 C5 1X 4X 6 C4 4A 3 C7 C6 D1 D2 D3 D0 4A 6 D5 1X 4X 7 D4 4A 5 D7 D6
Memory cycles
1 2 2 1 3 2 4 1 1 1 4 1 2 2 1 3 2 4 1 1 1 4 1 1 1 3 2 1 2 2 3 2 1 4 1 1 1 3 2 1 2 2 3 2 1 4
Internal Cycles
0 1 1 0 0 0 0 1.5a 1.5a 0 0 0 1 1 1 0 0 0 1 1 0 0 2 2 3 2 2 1 2 2 1 1 16.5a 16.5a 23.5a 23.5a 23.5a 23.5a 23.5a 28a 29a 29a 28a 28a 41a 41a
Increment Memory by a Positive Integer Single-Precision Absolute Value Double-Precision Absolute Value Double-Precision Integer Add
AR AB ABX AISP A AIM INCM ABS DABS
R B BX ISP D,DX IM D,DX R R R D,DX R B BX ISP D,DX IM D,DX R R R D,DX R ISP ISN D,DX IM R B BX D,DX IM R D,DX R ISP ISN D,DX IM R R BX D,DX IM R D,DX
DAR DA Single Precision Integer Subtract SR SBB SBBX SISP S SIM Decrement Memory by a Positive DECM Integer Single-Precision Negate NEG Double-Precision Negate DNEG Double-Precision Integer DSR Subtract DS Single-Precision Integer Multiply MSR with 16-Bit Product MISP MISN MS MSIM Single-Precision Integer Multiply MR with 32-Bit Product MB MBX M MIM Double-Precision Integer Multiply DMR DM Single-Precision Integer Divide DVR with 16-Bit Dividend DISP DISN DV DVIM Single-Precision Integer Divide DR with 32-Bit Dividend DB DBX D DIM Double-Precision Integer Divide DDR DD
Figure 20a (continued): Instruction Summary
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OPERATION
LOGICAL Inclusive Logical-OR
Mnem.
Format
Opcode (Ext)
E1 3X 4X F E0 4A 8 E3 3X 4X E E2 4A 7 E5 E4 4A 9 E7 E6 4A B 51 50 52 54 53 55 57 56 58 59 5A 5C 5E 97
Memory cycles
1 2 2 3 2 1 2 2 3 2 1 3 2 1 3 2 1 4 5 1 4 5 1 3 4 2 1 1 1 4
Internal Cycles
0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.5a 0 0 0 1
Logical-AND
Exclusive Logical-OR
Logical NAND
Set Bit
Reset Bit
Test Bit
Test and Set Bit Set Variable Bit Reset Variable Bit Test Variable Bit Store Register Through Mask
ORR ORB ORBX OR ORIM ANDR ANDB ANDX AND ANDM XORR XOR XORM NR N NIM SBR SB SBI RBR RB RBI TBR TB TBI TSB SVBR RVBR TVBR SRM
R B BX D,DX IM R B BX D,DX IM R D,DX IM R D,DX IM R D,DX I,IX R D,DX I,IX R D,DX I,IX D,DX R R R D,DX
JUMP/BRANCH Jump on Condition
Jump to Subroutine Subtract One and Jump Branch Unconditionally Branch if Equal to (Zero) Branch if Less than (Zero) Branch to Executive Branch if Less than or Equal to (Zero) Branch if Greater than (Zero) BGT Branch if Not Equal to (Zero) BNZ Branch if Greater than or Equal to BGE (Zero)
JC JCI JS SOJ BR BEZ BLT BEX BLE
D,DX I,IX D,DX D,DX ICR ICR ICR S ICR ICR ICR ICR
70 71 72 73 74 75 76 77 78 79 7A 7B
3a 3.5a 2 3a 2 2a 2a 11 2a 2a 2a 2a
0 0 1 0 1 0 0 14 0 0 0 0
Figure 20a (continued): Instruction Summary
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MA31750
OPERATION Mnem. Format Opcode (Ext) Memory cycles Internal Cycles
EXTENDED PRECISION Extended-Precision FloatingPoint Load Extended-Precision FloatingPoint Store Floating-Point Absolute Value of Register Floating-Point Negate Register Floating-Point Compare
EFL EFST FABS FNEG FCR FCB FCBX FC EFCR EFC FAR FAB FABX FA EFAR EFA FSR FSB FSBX FS EFSR EFS FMR FMB FMBX FM EFMR EFM FDR FDB FDBX FD EFDR EFD
D,DX D,DX R R R B BX D,DX R D,DX R B BX D,DX R D,DX R B BX D,DX R D,DX R B BX D,DX R D,DX R B BX D,DX R D,DX
D,DX S S 5
8A 9A AC BC F9 3X 4X D F8 FB FA A9 2X 4X 8 A8 AB AA B9 2X 4X 9 B8 BB BA C9 2X 4X A C8 CB CA D9 2X 4X B D8 DB DA
7E 7F 8F 9F
5 5 1 1 1 3 3 4 1 5 1 3 3 4 1 5 1 3 3 4 1 5 1 3 3 4 1 5 1 3 3 4 1 5
3 3
0 0 2wa 3wa 3.7wa 3.7wa 3.7wa 3.7wa 4wa 2wa 7wa 8.5wa 8.5wa 8.5wa 21wa 20wa 9wa 10wa 10wa 9wa 23wa 22wa 1 2 2 1 33wa 32wa 42.8wa 43.8wa 43.8wa 42.8wa 112.6wa 112.6wa
1 1
Extended-Precision FloatingPoint Compare Floating-Point Add
Extended-Precision FloatingPoint Add Floating-Point Subtract
Extended-Precision FloatingPoint Subtract Floating-Point Multiply
Extended-Precision FloatingPoint Multiply Floating-Point Divide
Extended-Precision FloatingPoint Divide
STACK Stack IC and Jump to Subroutine Unstack IC and return from Subroutine Pop Multiple registers off the Stack Push Multiple Registers onto the Stack
SJS URS POPM PSHM
1+n (n=0 to 4 15) 1+n (n=0 to 8 15)
Figure 20a: Instruction Summary
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OPERATION
CONVERT Convert Floating-Point to 16-Bit Integer Convert 16-Bit Integer to Floating-Point Convert Extended-Precision Floating-Point to 32-Bit Integer Convert 32-Bit Integer to Extended-Precision FloatingPoint
Mnem.
Format
Opcode (Ext)
E8 E9 EA EB
Memory cycles
1 1 1 1
Internal Cycles
7.1a 3 8.5a 9
FIX FLT EFIX EFLT
R R R R
SHIFT Shift Left Logical SLL Shift Right Logical SRL Shift Right Arithmetic SRA Shift Left Cyclic SLC Double Shift Left Logical DSLL Double Shift Right Logical DSRL Double Shift Right Arithmetic DSRA Double Shift Left Cyclic DSLC Shift Logical, Count in Register SLR Shift Arithmetic, Count in SAR Register Shift Cyclic, Count in Register SCR Double Shift Logical, Count in DSLR Register Double Shift Arithmetic, Count in DSAR Register Double Shift Cyclic, Count in DSCR Register
R R R R R R R R R R R R R R
60 61 62 63 65 66 67 68 6A 6B 6C 6D 6E 6F
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 2 5a 2 2 5 2
I/O (See I/O Command Summary) Execute I/O Vectored I/O (n transfers) SPECIAL Move Multiple Words, Memoryto-memory (n-words moved) Exchange Words in Registers Load Status No Operation Break Point
XIO** VIO** MOV XWR LST** LSTI** NOP BPT
IM,IMX D,DX S R D,DX I,IX S S
48 49 93 ED 7D 7C FF 00 FF FF
3 *** 1+2n 1 6 7 1 1
4.3a *** 7 2 1 1 2 6
Figure 20a (continued): Instruction Summary
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OPERATION Mnem. Format Opcode (Ext) Memory cycles Internal Cycles
1750B MODE INSTRUCTIONS The following instructions may only be executed in 1750B mode and are illegal in 1750A 'LONG' LOADS AND STORES Long Load Single Long Load Double Long Load Extended Precision Floating-Point Long Store Single Long Store Double Long Store Extended Precision Floating-Point UNSIGNED ARITHMETIC Unsigned Integer Add Unsigned Integer Subtract Unsigned Integer Compare LSL LDL LEFL LSS LDS LEFS S S S S S S CC CD CE DC DD DE 3 4 5 4 6 8 11 20 27 9 16 23
UAR UA USR US UCR UC UCIM
R D,DX R D,DX R D,DX IM
AD AE BD BE FC FD 4A 0
1 3 1 3 1 3 2
4 4 4 4 5 5 5
BYTE LOADS AND STORES Load Byte Load Byte With Increment Store Byte Store Byte With Increment BIT OPERATION Search First Bit Set
Notes: a wa ** ***
LBY LBYI SBY SBYI
S S S S
BF AF DF CF
2 2 2 2
3 3 3 3
SFBS
R
95
1
3.75a
Average if more than one alternative exists. Weighted average where data dependency exists. Privileged instruction - illegal if PS0. VIO execution time dependent on number and type of transfer.
Figure 20b: MIL-STD-1750B Instruction Summary
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5.4 I/O COMMAND SUMMARY
O pe ra t ion I mple me nt e d in CP U 1 7 5 0 A or B mode Set Interrupt Mask Clear Interrupt Request Enable Interrupts Disable Interrupts Reset Pending Interrupt Set Pending Interrupt Reg. Write Output Discrete Reg. Reset Normal Power Up Line Write Status Word Enable Start-Up ROM 3 Disable Start-Up ROM 3 Direct Memory Access Enable3 Direct Memory Access Disable3 Timer A Start Timer A Halt Output Timer A Reset Trigger-Go Timer B Start Timer B Halt Output Timer B Read Interrupt Mask Read Pending Interrupt Reg. Read Output Discrete Reg. Read Status Word Read and Clear Fault Reg. Input Timer A Input Timer B Read Memory Fault Status G P S De f ine d X I O s Set Fault Register Load OAS register Output Trigger-Go Reset Reg. Write Page Bank Select Read Fault Register (No clear) Read Linkage Pointer Read Processor Status Read OAS register Read Memory Fail Address Read Memory Fail Page Read Internal Config. Word Run Built In Test Input Trigger-Go Reset Reg. Read External Configuration Mne m Code Ext1
SMK CLIR ENBL DSBL RPI SPI OD RNS WSW ESUR DSUR DMAE DMAD TAS TAH OTA GO TBS TBH OTB RMK RPIR RDOR RSW RCFR ITA ITB RMFS
2000 2001 2002 2003 2004 2005 2008 200A 200E 4004 4005 4006 4007 4008 4009 400A 400B 400C 400D 400E A000 A004 A008 A00E A00F C00A C00E A00D
No No No No No No Yes No Yes No No No No No No No No No No No No No Yes No No No No No
Implemented in CPU, 1750B mode only. Output Timer A Reset Reg. Output Timer B Reset Reg. Input Timer A Reset Register 2 Input Timer B Reset Register 2 Set Fault Mask Write Page Bank Select Read Page Bank Select Read Fault Mask Implemented in BPU Memory Protect Enable3 Load Memory Protect RAM 3 Read Memory Protect RAM 3 Load Ext Mem. Protect RAM 3,5 Read Ext. Mem. Protect RAM 3,5 Implemented in MMU Write Instruction Page Reg.3 Write Operand Page Reg. 3 Read Instruction Page Reg.3 Read Operand Page Reg. 3 Implemented in Console Console Data Output 4 Console Command 4 Console Data Input 4
6
OTAR OTBR ITAR ITBR SFMK WPBS RPBS RFMK
4002 400F C002 C00F 2006 200F A00C A006
No No No No No No No No
MPEN LMP RMP LXMP RXMP
4003 50XX D0XX 4XXX CXXX
Yes Yes Yes Yes Yes
WIPR WOPR RIPR ROPR
51XY 52XY D1XY D2XY
Yes Yes Yes Yes
CO CC CI
4000 8402 C000
Yes Yes Yes
SFR LOS OTGR WPBS RFR RLP RPS ROS RMFA RMFP ICW BIT ITGR RCW
0401 0406 040E 200C 8401 8404 8405 8406 8407 8408 840C 840D 840E 8410
No No No No No No No No No No No No No Yes
Reserved by GPS (Unavailable to the user) Initialise Interrupt Logic Set NPU Write Internal config word Write Memory Config. Reg. FMCR
PINIT RNPU WCW WMCR FMCR
0403 No 040A No 040C No 0400 Yes A010 No
Spare and Output 04XX-1FXX 21XX-2fXX 30XX-3FXX 41XX-4FXX 53XX-7FXX
1 External 2
Reserved Input 84XX-9FXX A1XX-AFXX B0XX-BFXX C1XX-CFXX D3XX-FFXX
Addresses
Spare Reserved Spare Reserved Spare
cycles output on the address bus GPS defined 1750B XIO's Reserved Addresses 3 Command illegal if device not implemented in config word 4 External cycle needing external ready generation 5 Only implemented in 1750B 6 The address 4001 and C001 are implemented but have no effect in the 31750.
Figure 20c: Internal I/O Command Summary
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6. TIMING DIAGRAMS
Zero-waitstate Cycle
CLKOUT
4
One Waitstate Cycle
5
AS
53 1 2
A0-A15
3
AS0-3 PB0-3
57, 59
RD/WN O/IN M/ION
58, 60
8
DSN
9
8
RDN
9
WR N
6
D0-D16 Read data Read data
7 10
RDY N
11
DPAR N
42
46
SNEW
47
43
Figure 21: Read Cycle Timings
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MA31750
Zero-waitstate Cycle
CLKOUT
One Waitstate Cycle
4 5
AS
53
1
A0-A15
2
3
AS0-3 PB0-3
57, 59
RD/WN O/IN M/ION
58, 60
8
DSN
9
RDN
8
WRN
9
12
D0-D16 Write data from MA31750
13
14
Write data from MA31750
15
10
RDYN
46
SNEW
47
11
Note: Write data is guaranteed valid after DSN and WRN rise (timing 13)
Figure 22: Write Cycle Timings
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MA31750
Wait 1
CLKOUT
Wait 2
AS
50
MPROEN
51
EXADEN
50
51
WRN DSN
SNEW
Notes: Diagram shows a WRITE cycle but is also applicable to READ cycles. Cycle 'Wait 1' is introduced by MPROEN low. Cycle 'Wait 2' is introduced by EXADEN low. Strobes RDN/WRN and DSN are not asserted until faults are clear. If either MPROEN or EXADEN remains low for two successive falling edges of TCLK, the relevant fault is logged in the fault register.
Figure 23a: MPROEN and EXADEN Timings
CLKOUT
1
TCLK Busfault timeout occurs here. AS
2
38 39
MPROEN OR EXADEN
54
BUSFAULTN
WRN DSN
Strobes suppressed
SNEW
Notes: Bus fault timeout occurs after two consecutive TCLK falling edges. Strobes are suppressed for the duration of the erroneous cycle. Normal operation resumes with the following cycle.
Figure 23b: Bus Fault Timeout
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MA31750
Transfer
CLK
GRANTN removed
Bus released
20
AS
17
REQN
16 18
GRANTN
DSN RDWN OIN MION RDN WRN D0-16 A0-15
19
21
IO Pending
CLKOUT
Transfer, bus locked
Transfer
AS
23
REQN
GRANTN
26
LOCKN
26
DSN RDWN OIN MION RDN WRN D0-16 A0-15
23
Notes: Processor will drive busses and controls as soon as GRANTN is applied LOCKN can be overriden by deasserting GRANTN
Figure 24: Bus Arbitration Timing
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MA31750
Normal Operation
CLKOUT
Reset
Config read
Normal Operation
27
RESET N
28
CONFW N
32 33
40 41
AS O/IN DSN WRN RDN RDWN M/ION LOCKN REQN INTAKN BUSFAULTN TGON
29
29
30
SUREN DMAE NPU
31 29 30 30 46
SNEW
47
Figure 25: Reset Timing
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MA31750
Normal Operation
CLKOUT
Reset
Internal Cycles
Config Read
RESET N
GRANTN
CONFW N
24
AS O/IN DSN WRN RDN RDWN M/ION LOCKN
23
SUREN DMAE
NPU
SNEW
A[0:15] PB[0:3] AS[0:3]
D[0:16]
Figure 26: GRANTN during RESETN Low
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MA31750
CLKOUT
35
Interrupt
36 Level-sensitive Interrupts
CLKOUT
37
Interrupt FLT7N SYSFN
DSN
61
FLT7N SYSFN
Edge-sensitive Interrupts and Asynchronously Captured Faults
AS
38
MPROEN EXADEN PEN
39
Pending Interrupt
Level-sensitive Faults Notes: A fault causes an internal Pending Interrupt request shortly after the fault has been latched into the fault register (on AS )
Figure 27: External Interrupt and Fault Timing
CLKOUT
AS
48
SUREN DMAE
49
40
CONFWN
40
41
DISCON
41
62
NPU
62
25
INTAKN
25
Figure 28: Discrete Timings
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MA31750
TCLK XIO GO completes
CLKOUT
COUNT
FFFF 16
FFFF 16
0000 16
0000 16
44
TGON
52
64 63
DTON Note: TGON remains low until reset by XIO GO
Figure 29: Trigger Go Timing
CLKOUT
A[0:15]
8402 16
Console CMD register CSN
45
CONREQN
Notes: Console CMD register CSN (Chip Select) is derived by decoding XIO CCMD
Figure 30: Console Request Timings
End of cycle
CLKOUT
43
DPARN
42
Figure 31: DPARN Timing
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No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Parameter ADDRESS valid to AS rising ADDRESS valid after AS falling CLKOUT low to ADDRESS valid CLKOUT rising to AS rising CLKOUT falling to AS falling Data setup to RDN rising Data hold after RDN rising CLKOUT falling to DSN, RDN, WRN falling CLKOUT falling to DSN, RDN, WRN rising RDYN setup to CLKOUT falling RDYN hold after CLKOUT falling WRN falling to write data valid Write data valid after WRN rising (Test Load 2) DSN falling to data bus driven (write) (Test Load 2) DSN rising to data bus hi-Z (write) (Test Load 2) CLKOUT falling to REQN falling CLKOUT falling to REQN rising GRANTN setup to CLKOUT falling GRANTN hold after CLKOUT falling CLKOUT falling to control, strobes and busses hi-Z (GRANTN removed) (Test Load 2) CLKOUT falling to control, strobes and busses hi-Z (GRANTN removed) (Test Load 2) AS falling to control, strobes and busses hi-Z (GRANTN removed) (Test Load 2) GRANTN falling to control, strobes and busses driven GRANTN rising to control, strobes and busses undriven (RESETN = LOW) CLKOUT falling to INTAKN changing CLKOUT falling to LOCKN valid RESETN low pulse width RESETN low to strobes inactive (GRANTN = LOW) RESETN high to strobes valid (GRANTN = LOW) RESETN falling to DMAE, NPU low, SUREN high RESETN rising to DMAE, SUREN, NPU initialized RESETN rising to first bus cycle (configuration word read) RESETN rising to CONFWN low RESETN rising to first instruction fetch Interrupt setup to CLKOUT rising (level sensitive) Interrupt hold after CLKOUT rising (level sensitive) Interrupt pulse width (edge-sensitive) MPROEN/EXADEN/PEN setup to AS falling (MPROEN and EXADEN sampled on early time-out) MPROEN/EXADEN/PEN hold after AS falling (MPROEN and EXADEN sampled on early time-out) CLKOUT falling to CONFWN changing CLKOUT falling to DISCON changing DPARN setup to CLKOUT falling DPARN hold after CLKOUT falling TCLK falling to TGON low CONREQN hold after Console Command Chip Selection CLKOUT falling to SNEW rising CLKOUT falling to SNEW falling CLKOUT falling to SUREN/DMAE valid CLKOUT falling to SUREN/DMAE invalid MPROEN/EXADEN setup to CLKOUT falling (to insert early wait states) MPROEN/EXADEN hold after CLKOUT falling (to insert early wait states) CLKOUT falling to TGON rising (following XIO GO) AS low pulse width AS falling to BUSFAULTN valid CLK rising to CLKOUT rising CLK falling to CLKOUT falling MION valid to AS rising MION valid after AS falling OIN/RDWN valid to AS rising OIN/RDWN valid after AS falling SYSFN/FLT7N setup to CLKOUT (at end of cycle) CLKOUT falling to NPU changing DTON setup to TCLK falling DTON hold after TCLK falling Min. TL-25 5 15 0 -5 -5 25 0 5 5 5 15 8 15 0 2 10 4 4 10 4 4 10 10 4 28 6 7 T31+16 15 20 10 5 15 2 8 10 5 5 4 4 4 4 40 0 20 0.5T-5 5 5 TL-20 1 TL-20 1 10 10 10 Max. 25 40 20 15 10 10 35 40 35 40 55 40 25 50 40 25 50 30 35 55 30 50 13960 6 7 T31+16 25 45 45 3 30 30 30 30 80 0.5T+10 45 25 25 25 25 30 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK ns ns ns ns ns ns ns ns ns ns CLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
This timing includes MA31751 Setup Cycles and Built In Test Cycles. Mil-Std-883, Method 5005, Subgroups 9, 10, 11. TL = Low CLK period (ns), TH = High CLK period (ns). Test Conditions: Vdd = 5.0V 10%, Temperature = -55oC to 125oC, Vil = 0.0V, Vih = Vdd. Output loads: All test load 1 unless otherwise specified. Output Threshold: 50% Vdd (Load 1), Vss+1V, Vdd-1V (Load 2).
Figure 32a: Timing Parameters for MA31750
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0.5 Vdd/VDD/VSS 1k To output under test 50pF To output under test 50pF
Test Load 1
Test Load 2
Figure 32b : Output Loads for AC measurements
8. TYPICAL SMALL SYSTEM CONFIGURATION
MPROEN
Interrupts 16 Faults 4 Memory Management Unit (MMU) MA31751
PS, AS 8 DMA Controller
8/11* Processor MA31750 12 Address bus 20/23*
Control CONFWN Configuration tristatable latch Memory Subsystem
16 Data bus
EDAC MA31752/ MA31755 *1750A/1750B mode
Figure 33: Typical Small System Configuration
A Single Board Computer is available to developers. Please call GPS for details.
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MA31750
9. RATING AND CHARACTERISTICS
Parameter Supply voltage Input voltage Current through any I/O pin Operating temperature Storage temperature Min. -0.5 -0.3 -20 -55 -65 Max. 7 VDD+0.3 20 125 150 Units V V mA oC oC
Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Figure 34: Absolute Maximum Ratings
P a ra me t e r Clock Frequency (CLK) TCLK Frequency Min. 0 0 Ma x 16 f CLK / 9 55 Unit s MHz Hz %
Recommended Clock duty cycle 45 MIL-STD-1750 mandates that TCLK be 100kHz Vdd=5V10% over full operating temperature range Mil-Std-883, method 5005, subgroups 7, 8A, 8B
Figure 35: Operating AC Electrical Characteristics
S y mbol VDD VIH VIL VCKH VCKL VOH VOL I IH I IL I OZH I OZL I DDYN I DDS
P a ra me t e rs Supply voltage Input high voltage Input low voltage CLK & TCLK input high voltage CLK & TCLK input low voltage Output high voltage Output low voltage Input high current (Note 1) Input low current (Note 1) I/O tristate high current (Note 1) I/O tristate low current (Note 1) Dynamic supply current @ 16MHz Static supply current
Condit ions I OH=-3mA I OL=5mA -
Tot a l dos e ra dia t ion not e x c e e ding 3 x 1 0 5 Ra d( S i) Min Ty p Ma x 4.5 5.0 5.5 80% VDD VDD-0.5 VDD-0.5 20% VDD VSS+0.5 VSS+0.4 10 -10 50 -50 80 10
Unit s V V V V V V V A A A A mA mA
Vdd=5V10% over full operating temperature range Mil-Std-883, method 5005, subgroups 1, 2, 3 Note 1: Guaranteed but not tested at low temperature (-55C)
Figure 36: Operating DC Electrical Characteristics
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Subgroup 1 2 3 7 8A 8B 9 10 11 Definition Static characteristics specified in Table 36 at +25C Static characteristics specified in Table 36 at +125C Static characteristics specified in Table 36 at -55C Functional characteristics specified in Table 35 at +25C Functional characteristics specified in Table 35 at +125C Functional characteristics specified in Table 35 at -55C Switching characteristics specified in Table 32a at +25C Switching characteristics specified in Table 32a at +125C Switching characteristics specified in Table 32a at -55C
Figure 37: Definition of MIL-STD-883, Method 5005 Subgroups
1000
Static Idd (uA)
800 600 400 200 0
0
1
2
3
4
Input Voltage (V)
Figure 38: Input Characteristic
10. PIN DESCRIPTIONS
A description of each pin function appears in Figure 39. The acronym is presented first, followed by its function and description. Timing characteristics of each of the functions are shown in section 6. All signals - with the exception of CLK and TCLK are CMOS compatible, and are protected by an Electrostatic Discharge (ESD) protection circuit. All output signals are also TTL compatible. CLK and TCLK are Schmitt inputs. Throughout this data sheet, active low signals are denoted by following the signal name with an "N" suffix, e.g.,DSN. If a signal has a dual function, both function names will be used separated by a "/". The function name to the left of the "/" will be active high while the function to the right will be active low, again with an "N" suffix, e.g., RD/WN. All unused inputs should be connected to their inactive state and should not be allowed to float.
5
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MA31750
P in Na me P O WE R VDD GND Func t ion De s c ript ion
Power Supply Ground
DC power supply input - nominally +5V. 0V reference point.
CLO CK S I G NALS CLK System Clock
CLKOUT
TCLK
Schmitt Input clock signal. For correct operation of the timers the CLK frequency should be at least 9 times that of TCLK. Clock Out Buffered reference clock derived directly from the internal clock. This signal is used to reference all of the external strobes and internal timing events and may be used to synchronise an external system to the processor. Timer Clock This Schmitt input clock is used by the internal 16-bit timers A and B and by the Trigger-Go100kHz sq. wave counter. MlL-STD-1750 requires this signal to have a frequency of 100kHz.
S Y S TE M BUS E S A00-A15 Address bus A00 is MSB D00-D16 Data bus D00 is MSB BUS CO NTRO L AS Address Strobe Active HIGH
An active-high address bus which is input during bus cycles not assigned to this CPU. A00 is the most significant bit. An active-high data bus which is tristate during bus cycles not assigned to this CPU. D00 is the most significant bit. D16 is the optional parity check bit.
DSN
M/ION
RD/WN
O/IN
RDN
WRN
RDYN
This active-high bidirectional signal establishes the beginning and end of each bus cycle. The trailing edge (high to low transition) is used to sample bus cycle-related faults into the fault register. The leading edge guarantees that a valid address is on the address bus. During cycles not assigned to this CPU the AS line is an input to allow the falling edge to continue to latch bus cycle related faults into the fault register. Data Strobe This active-low signal indicates the presence of data on the system data bus. During a read cycle DSN goes low to indicate that the processor is requesting data from the bus, whilst in Active LOW a write cycle DSN indicates that data is present on the bus. This signal is tristate in bus cycles not assigned to this CPU. Memory/IO Select This signal indicates whether the current bus cycle is accessing memory (high) or IO (low) addressing space. This signal becomes valid shortly after the start of a machine cycle and Memory=HIGH remains valid throughout. M/ION becomes an input on cycles not assigned to the CPU to IO=LOW ensure that faults are latched into the correct bit of the fault register. Read/Write This signal indicates the direction of data transfer on the system data bus. Data is read in Select. by the processor when high, and written out when low. This signal becomes valid shortly after the start of a machine cycle and remains valid throughout. RD/WN is tristate during Read=HIGH cycles not assigned to this CPU. Write=LOW Operand/Instruct This signal indicates whether the current bus cycle is accessing operand (high) or Select. instruction (low) addressing space. This signal becomes valid shortly after the start of a machine cycle and remains valid throughout. O/IN is an input during cycles not assigned to Operand=HIGH this CPU, to ensure correct operation of the MFPR and the MFAR. Instr.=LOW Read Strobe. This active-low output is asserted low with DSN during read cycles. It is driven high on the same clock edge as that used by the processor to latch the input data. This signal is Active LOW tristate in bus cycles not assigned to this CPU. Write Strobe. This active-low output signal is asserted low with DSN during write cycles. The rising edge should be used by the system to latch data from the data bus. This signal is tristate in bus Active LOW cycles not assigned to this CPU. Ready. This input signal allows the basic machine cycle of the processor to be extended to accommodate slower peripheral or memory devices. Ready may be asserted high to add an Active LOW integer number of CLK cycles (wait states) to the machine cycle. The line must be asserted low to allow processing to proceed. RDYN has no effect on cycles dedicated to internal operations. Not e : If RDYN is held high during two consecutive TCLK high-to-low transitions (with DSN low), a bus timeout fault will occur and will be indicated in the appropriate bit in the fault register. The occurrence of this fault will cause the state sequencer to terminate the current machine cycle and begin the next. At the end of the current macro-instruction execution will branch, unless masked, to the machine error interrupt (level 1) software routine. The DTON signal may be used to override this feature.
Figure 39: Pin Descriptions
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P in Na me Func t ion De s c ript ion
BUS ARBI TRATI O N LOCKN Bus Lock Request. Active LOW
REQN
Bus Request. Active LOW Bus Grant. Active LOW
GRANTN
This active-low output signal indicates to the bus arbiter that the processor is performing an atomic instruction which should not be interrupted. External bus accesses should be denied whilst LOCKN is low. The CPU will lock the bus during read-modify-write instructions such as DECM (Decrement Memory) and TSB (Test & Set Bit). LOCKN remains high during non-locked cycles. This signal is tri-stated on cycles not assigned to this CPU. Not e : LOCKN is advisory only - it may be ignored by the arbiter if neccessary. This active-low output signal is driven low when the CPU requires the bus in the next cycle. This signal may be used as an input to an external bus arbiter. The signal becomes invalid once the CPU has started the requested cycle. This active-low signal is asserted by an external bus arbiter to indicate that the CPU currently has the highest priority bus request. The CPU will begin a bus cycle (if one is pending) commencing with the next CPU clock cycle.
I NTE RRUP TS PWRDN Power-Down Interrupt. Active LOW Interrupt Inputs. INT02N, INT08N, Active LOW INT10N, INT11N, INT13N, INT15N IOI1N, IOI2N
A low on this active low input will be captured in the PI register and sets Pending Interrupt 0. This is the highest priority interrupt and cannot be masked or disabled. A low on any of these active low inputs will be captured in the Pl register and will set Pending Interrupt levels 2, 8, 10, 11, 13, and 15, respectively. Level 2 is the highest priority user level, while level 15 is the lowest priority. These interrupts are maskable and can be disabled. If edge sensitivity has been selected, interrupts will be captured on the falling edge of the interrupt input, otherwise the interrupt will be latched by the falling edge of CLK at the end of the machine cycle. Not e : Interrupt levels 1, 3, 4, 5, 6, 7 and 9 are dedicated to internal machine interrupts. A low on either input will set Pending Interrupt levels 12 or 14 respectively. These inputs are level sensitive only and are captured by the falling edge of CLK at the end of a machine cycle. These inputs can be masked and disabled. This active-low output indicates the start of an interrupt service. When low, the processor outputs the Linkage Pointer (LP) address to the system. The INTAKN signal may be used to remove level-sensitive interrupt inputs: the current interrupt priority can be ascertained by reading the address bus during the cycle in which this output is low.
INTAKN
Interrupt Acknowledge Strobe. Active LOW
FAULTS MPROEN
A low on this input, sampled on falling AS, indicates that an execute protect or write protect fault has been detected. Bit 0 of the fault register is set if this signal is applied during a CPU cycle; bit 1 is set if the line goes low during a DMA cycle. Either condition sets Pending Interrupt level 1. The CPU will prevent access to memory (by inhibiting strobe production) whilst this input is LOW. See 3.4.7.1. To effectively use this feature, MPROEN should be pulled low prior to the start of the next machine cycle. PEN Parity Error A low on this active-low input, sampled on falling AS, informs the CPU that an external parity error has occurred. Bit 2 (memory), 3 (IO) or 4 (DMA) of the Fault Register is set, Active LOW depending upon the type of transfer taking place. This asserts a level 1 Pending Interrupt. EXADEN External Address A low on this active-low input, sampled on falling AS, informs the CPU that an external Error address error has occurred. Bit 8 of the fault register is set if this signal goes low during a memory cycle; bit 5 is set if the signal goes low during an IO cycle and bit 14 is set if a DMA Active LOW has control of the system. Either error condition asserts a level 1 pending interrupt. As with MPROEN, the CPU will prevent access to memory (by inhibiting strobe production) whilst this input is LOW. See 3.4.8.1 FLT7N Fault Level 7 A low at any time on this active-low input sets bit 7 of the fault register, causing a level 1 pending interrupt. This fault is user- definable. Active LOW SYSFN System Fault A low at any time on this active-low input sets bits 13 and 15 of the fault register, causing a level 1 pending interrupt. This fault is user definable. Active LOW BUSFAULTN Illegal address This active-low output drops low if any bus-related fault (MPROEN, EXADEN or PEN) is detected low or if the bus fault timeout circuit causes an interface timeout. Active LOW
Memory Protect Fault. Active LOW
Figure 39 (continued): Pin Descriptions
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P in Na me Func t ion De s c ript ion
MMU CO NTRO L AS[0:3] Address State Active HIGH AS0 is MSB PB[0:3]
This active-high bus indicates the current address state of the CPU. The value on this bus is copied from the Status Word register within the CPU. These lines are inputs during bus cycles not assigned to this CPU, so that the MFPR and the MFAR can store the relevant failure information if a remote failure occurs. Page Bank Select In 1750B mode, this active-high bus indicates the current CPU Page Bank. The value on Active HIGH this bus is copied from the Status Word register within the CPU. These lines are inputs during bus cycles not assigned to this CPU, so that the MFPR and the MFAR can store the PB0 is MSB relevant failure information if a remote failure occurs.
DI S CRE TE S CONFWN Configuration Register Read Strobe Active LOW SNEW Start of New Cycle Strobe Active HIGH DISCON Discretes Output Strobe Active LOW DMAE DMA Enable Active HIGH CONREQN
This active-low output signal is driven low when the processor reads the external configuration register. The line may be used as an output enable for this register. The configuration register is read during initialisation and during the execution of a BPT instruction to determine the system configuration. This active-high output will be asserted high during the first phase of each machine cycle.
This active-low output will be asserted low by the processor during an XIO OD or XIO RDOR command. It may be used as the enable signal for an external discrete output register.
SUREN
NPU
TGON
DTON DPARN RESETN
This active-high output indicates that an external DMA device is enabled. It is disabled (low) following reset and can be toggled under program control using XIO DMAE and XIO DMAD, (if a DMA device is set as present in the configuration register). Console Request This active-low input initiates and controls Console operation following the end of a 1750 instruction. Commands and data are passed to the processor in this mode via three Active LOW dedicated registers in IO space. Console operation takes precedence over Interrupts. Start-Up-ROM This active-low output indicates that start-up ROM is enabled. The signal is asserted low Enable following initialisation or by XIO ESUR. The signal remains asserted until removed with XIO DSUR. When a start-up ROM is present on the system indicated in the configuration word, Active LOW this signal should be used to qualify its chip select or output enable such that the ROM may be accessed only when SUREN is low. Not e : Instruction pipelining must be considered in moving from Start-Up ROM to RAM. See Section 4 on Software Considerations. Normal Power-Up This output is asserted to indicate that the Built-ln-Test (BIT), performed on reset or powerDiscrete up, has passed. The line is asserted low following an external reset and may also be reset by software using the XIO RNS command. Active HIGH Trigger-Go Output This active-low output is asserted low whenever the Trigger-Go counter overflows (rolls Discrete over to 0000). It returns to the high state when the counter is reset by software (using the XIO GO command). Active LOW Disable Timeout A low on this input will reset and disable the bus fault timeout circuit. Active LOW Disable Parity A low on this input will reset and disable the on-chip parity verification. Not e : Parity generation on write data is not disabled by this pin. Active LOW CPU reset This active-low input should be asserted low to reset the processor. The low to high transition will start the initialisation sequence which will perform a Built-In-Test (if Reset=LOW selected), initialising the processor in accordance with MIL-STD-1750 (see figures 2 and 3).
Figure 39 (continued): Pin Descriptions
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11. PIN ASSIGNMENTS AND OUTLINES
MION
DSN RDWN OIN RDN WRN GRANTN REQN LOCKN RDYN RESETN D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TOP VIEW Pin 1 Index 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76
TCLK
GND A15
CLK
A14
A13
A12 A11
AS
A10
A9
A8
A7
A6
A5
A4
A3 A2
A1
A0
CLKOUT DPARN DTON TGON NPU SUREN CONREQN DMAE DISCON SNEW CONFWN PB3 PB2 PB1 PB0 AS3 AS2 AS1 AS0 INTAKN VDD
75 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
EXADEN FLT7N
BUSFAULTN
MPROEN
SYSFN
PWRDN
INT02N
INT08N
INT10N
INT11N INT13N
INT15N
IOI1N
Figure 40a: 84-Lead Flatpack - Package Style F
IOI2N
D11
D12
D13
D14 D15
D16
PEN
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MA31750
Max 0.105
0.012 0.006
0.325 0.250
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
0.020 0.014
TOP VIEW
Pin 1 Index
1 84 83 82 81 80 79 78 77 76 75 73 74
1.167 1.138
Nom 0.050
1.167 1.138
NOTE: All dimensions shown in inches
Figure 40b: 84-Lead Flatpack - Package Style F
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A B C D E BOTTOM VIEW F G H J K L 11 10 9 8 7 6 5 4 3 2 1
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
IOI2N INT15N INT13N INT10N PWRDN INT08N EXADEN D16 D14 D13 D10 AS0 VDD IOI1N INT11N INT02N FLT7N PEN D15 D12 D11
B11 C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3
D08 AS1 INTAKN BUSFAULTN SYSFN MPROEN D09 D07 AS3 AS2 D06 D05 PB2 PB1 PB3 D01 D03 D02 SNEW PB0 CONFWN
F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1
D00 RESETN D04 DISCON DMAE CONREQN REQN LOCKN RDYN SUREN NPU WRN GRANTN TGON DPARN A07 A08 A12 RDWN RDN DTON
K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
TCLK MION A02 A05 A04 A11 A14 CLK DSN OIN CLKOUT A00 A01 A03 A06 A09 A10 A13 A15 GND AS
Figure 41a: 84-Pin Grid Array - Package Style A
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0.105 MAX 11 10 9 8 7 6 5 4 3 2 1 A B C 0.100 D E BOTTOM VIEW F G H J K L 0.070 dia 0.050 +/-0.005 0.00 8
0.900
0.050 +/- 0.004
0.180 =/0.004
0.018 =/-0.002 Pin Detail
1.100 SQ +/- .012
Pin 1 Index
Notes: 1. represents gold plating 50 microns min. over 100 microns nominal nickel. 2. All dimensions are in inches. 3. Default tolerances 1% not less than 0.005 4. Ceramic is 92% Alumina.
Figure 41b: 84-Pin Grid Array - Package Style A
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12. RADIATION TOLERANCE
Total Dose Radiation Testing For product procured to total dose radiation levels, each wafer lot will be approved when all sample devices pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. Dynex Semiconductor can provide radiation testing compliant with MIL STD 883 test method 1019, Ionizing Radiation (Total Dose). Total Dose (Function to specification)* Transient Upset (Stored data loss) Transient Upset (Survivability) Neutron Hardness (Function to specification) Single Event Upset** Latch Up 3x105 Rad(Si) 5x1010 Rad(Si)/sec >1x1012 Rad(Si)/sec >1x1015 n/cm2 1x10-11 Errors/bit day Not possible
* Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 42: Radiation Hardness Parameters
13. RELATED DOCUMENTATION
A number of Applications Notes are available to support the information in this data sheets. Please call for details: Application Note No. 2 No. 3 No. 4 No. 8 No. 11 No. 14 No. 15 Describes 1750B Mode Use of Console Mode Use of Interrupts Use of VIO Instructions Bus Arbitration Use of NMA31750 Samples Pipelining Instructions
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14. ORDERING INFORMATION
Unique Circuit Designator
xMAx31750xxxxx
Device Iteration QA/QCI Process (See Section 9 Part 4)
Radiation Tolerance S R Q Radiation Hard Processing 100 kRads (Si) Guaranteed 300 kRads (Si) Guaranteed Test Process (See Section 9 Part 3)
Package Type A F Pin Grid Array Flatpack (Solder Seal)
Assembly Process (See Section 9 Part 2)
Reliability Level L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S
For details of reliability, QA/QC, test and assembly options, see `Manufacturing Capability and Quality Assurance Standards' - SOS Handbook Section 9.
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HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: 00-44-(0)1522-500500 Fax: 00-44-(0)1522-500550 DYNEX POWER INC. Unit 7 - 58 Antares Drive, Nepean, Ontario, Canada K2E 7W6. Tel: 613.723.7035 Fax: 613.723.1518 Toll Free: 1.888.33.DYNEX (39639) CUSTOMER SERVICE CENTRES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 North America Tel: 011-800-5554-5554. Fax: 011-800-5444-5444 UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 SALES OFFICES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 Germany Tel: 07351 827723 North America Tel: (613) 723-7035. Fax: (613) 723-1518. Toll Free: 1.888.33.DYNEX (39639) / Tel: (831) 440-1988. Fax: (831) 440-1989 / Tel: (949) 733-3005. Fax: (949) 733-2986. UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. (c) Dynex Semiconductor 2000 Publication No. DS3748-8 Issue No. 8.0 January 2000 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM
Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand. No Annotation: The product parameters are fixed and the product is available to datasheet specification.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
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