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ISL6551
Data Sheet August 2003 FN9066.2
ZVS Full Bridge PWM Controller
The ISL6551 is a zero voltage switching (ZVS) full-bridge PWM controller designed for isolated power systems. This part implements a unique control algorithm for fixedfrequency ZVS current mode control, yielding high efficiency with low EMI. The two lower drivers are PWM-controlled on the trailing edge and employ resonant delay while the two upper drivers are driven at a fixed 50% duty cycle. This IC integrates many features in both 6x6 mm2 QFN and 28-lead SOIC packages to yield a complete and sophisticated power supply solution. Control features include programmable soft start for controlled start up, programmable resonant delay for zero voltage switching, programmable leading edge blanking to prevent false triggering of the PWM comparator due to the leading edge spike of the current ramp, adjustable ramp for slope compensation, drive signals for implementing synchronous rectification in high output current, ultra high efficiency applications, and current share support for paralleling up to 10 units, which helps achieve higher reliability and availability as well as better thermal management. Protective features include adjustable cycle-by-cycle peak current limiting for overcurrent protection, fast short-circuit protection (in hiccup mode), a latching shutdown input to turn off the IC completely on output over-voltage conditions or other extreme and undesirable faults, a non-latching enable input to accept an enable command when monitoring the input voltage and thermal condition of a converter, and VDD under voltage lockout with hysteresis. Additionally, the ISL6551 includes high current high-side and low-side totem-pole drivers to avoid additional external drivers for moderate gate capacitance (up to 1.6nF at 1MHz) applications, an uncommitted high bandwidth (10MHz) error amplifier for feedback loop compensation, a precision bandgap reference with 1.5% (ISL6551AB) or 1% (ISL6551IB) tolerance over recommended operating conditions, and an 5% "in regulation" monitor. In addition to the ISL6551, other external elements such as transformers, pulse transformers, capacitors, inductors and Schottky or synchronous rectifiers are required for a complete power supply solution. A detailed 200W telecom power supply reference design using the ISL6551 with companion Intersil ICs, Supervisor And Monitor ISL6550 and Half-bridge Driver HIP2100, is presented in Application Note AN1002. In addition, the ISL6551 can also be designed in push-pull converters using all of the features except the two upper drivers and adjustable resonant delay features.
Features
* High Speed PWM (up to 1MHz) for ZVS Full Bridge Control * Current Mode Control Compatible * High Current High-side and Low-side Totem-pole Drivers * Adjustable Resonant Delay for ZVS * 10MHz Error Amplifier Bandwidth * Programmable Soft Start * Precision Bandgap Reference * Latching Shutdown Input * Non-latching Enable Input * Adjustable Leading Edge Blanking * Adjustable Dead Time Control * Adjustable Ramp for Slope Compensation * Fast Short-circuit Protection (Hiccup Mode) * Adjustable Cycle-by-Cycle Peak Current Limiting * Drive Signals to Implement Synchronous Rectification * VDD Under-voltage Lockout * Current Share Support * 5% "In Regulation" Indication * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile
Applications
* Full-Bridge and Push-Pull Converters * Power Supplies for Off-line and Telecom/Datacom * Power Supplies for High End Microprocessors and Servers
Ordering Information
PART NUMBER ISL6551IB ISL6551IB-T ISL6551IR ISL6551IR-T ISL6551AB ISL6551AB-T ISL6551EVAL1 TEMP RANGE (oC) 0 to 85 0 to 85 0 to 85 0 to 85 -40 to 105 -40 to 105 PACKAGE 28 Lead SOIC Tape & Reel 28 Lead 6x6 QFN Tape & Reel 28 Lead SOIC Tape & Reel PKG. DWG. # M28.3 M28.3 L28.6x6 L28.6x6 M28.3 M28.3
Evaluation Platform (ISL6551IR only)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL6551 Pinouts
28 PIN WIDE BODY (SOIC) TOP VIEW
RD CT VSS CT RD R_RESDLY R_RA ISENSE PKILIM BGREF R_LEB CS_COMP CSS 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VDDP1 VDDP2 PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 ON/OFF DCOK LATSD CSS SHARE EAI EANI EAO LATSD DCOK SHARE 8 9 10 11 12 13 14 R_LEB CS_COMP 6 7 16 15 SYNC2 ON/OFF ISENSE PKILIM BGREF 3 4 5 19 18 17 LOWER1 LOWER2 SYNC1 R_RESDLY R_RA 1 2
28 PIN (QFN) TOP VIEW
VDDP1 VDDP2 23 PGND 22 21 20 UPPER1 UPPER2 VDD 25 VSS 26
28
27
24
EANI 12 EAI 13 EAO 14
Functional Pin Description
PACKAGE PIN # SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19, 20 21, 22 23, 24 25 26, 27 28 QFN 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16, 17 18, 19 20, 21 22 23, 24 25 PIN SYMBOL VSS CT RD R_RESDLY R_RA ISENSE PKILIM BGREF R_LEB CS_COMP CSS EANI EAI EAO SHARE LATSD DCOK ON/OFF SYNC2, SYNC1 LOWER2, LOWER1 UPPER2, UPPER1 PGND VDDP2, VDDP1 VDD FUNCTION Reference ground. All control circuits are referenced to this pin. Set the oscillator frequency, up to 1MHz. Adjust the clock dead time from 50ns to 1000ns. Program the resonant delay from 50ns to 500ns. Adjust the ramp for slope compensation (from 50mV to 250mV). The pin receives the current information via a current sense transformer or a power resistor. Set the over current limit with the bandgap reference as the trip threshold. Precision bandgap reference, 1.263V 2% overall recommended operating conditions. Program the leading edge blanking from 50ns to 300ns. Set a low current sharing loop bandwidth with a capacitor. Program the rise time and the clamping voltage with a capacitor and a resistor, respectively. Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp). Inverting input of Error Amp. It receives the feedback voltage. Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp). This pin is the SHARE BUS connecting with other unit(s) for current share operation. The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD. Power Good indication with a 5% window. This is an Enable pin that controls the states of all drive signals and the soft start. These are the gate control signals for the output synchronous rectifiers. Both lower drivers are PWM-controlled on the trailing edge. Both upper drivers are driven at a fixed 50% duty cycle. Power Ground. High current return paths for both the upper and the lower drivers. Power is delivered to both the upper and the lower drivers through these pins. Power is delivered to all control circuits including SYNC1 & SYNC2 via this pin.
2
ISL6551 Functional Block Diagram
18 ON/OFF 16 LATSD
28 VDD
BANDGAP REFERENCE
UVLO
SHUTDOWN SHUTDOWN LATCH LATCH SOFT SOFT START START
BGREF
8
PKILIM 7
SHUTDOWN
11 CSS
27 VDDP1
UPPER1 DRIVER R_LEB 9 RESODLY UPPER2 DRIVER
24 UPPER1
R_RESDLY 4
23 UPPER2
LEB ISENSE 6 R_RA 5 RAMP ADJUST
CT 2 RD 3
26 VDDP2 CLOCK GENERATOR PWM LOGIC LOWER1 DRIVER 22 LOWER1
EAO 14
ERROR AMP (See Fig. 4)
LOWER2 DRIVER EAI 13 EANI 12 DC OK CURRENT SHARE
21 LOWER2
CIRCUITS REFERENCED TO VSS
17 DCOK
10 CS_COMP
15 SHARE
19 SYNC2
20 SYNC1
25 PGND
1 VSS
CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
3
ISL6551
Absolute Maximum Ratings
Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . -0.3 to 16 V Enable Inputs (ON/OFF, LATSD) . . . . . . . . . . . . . . . . . . . . . . . VDD Power Good Sink Current (IDCOK) . . . . . . . . . . . . . . . . . . . . . . 5mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .3kV Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . .250V
Thermal Information
Thermal Resistance JA (oC/W) JC (oC/W) QFN Package (Note 1, 3). . . . . . . . . . . 30 2.5 SOIC Package (Note 2) . . . . . . . . . . . . 55 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range ISL6551IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC ISL6551AB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 105oC Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . 10.8V to 13.2V Supply Voltage Range, VDDP1 & VDDP2. . . . . . . . . . . . . . . <13.2V Maximum Operating Junction Temperature. . . . . . . . . . . . . . .125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER SUPPLY (VDD, VDDP1, VDDP2) Supply Voltage
These specifications apply for VDD = VDDP = 12V and TA = 0oC to 85 oC (ISL6551IB) or -40oC to 105oC (ISL6551AB), Unless Otherwise Stated SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VDD IDD IDD Icc VDD = 12V (not including drivers current at VDDP) VDD = 12V (not including drivers current at VDDP) VDD = VDDP = 12V, F = 1MHz, 1.6nF Load
10.8 5 3
12.0 13
13.2 18 20
V mA mA mA
Bias Current from VDD (ISL6551IB) Bias Current from VDD (ISL6551AB) Total Current from VDD and VDDP UNDER VOLTAGE LOCKOUT (UVLO) Start Threshold (ISL6551IB) Start Threshold (ISL6551AB) Stop Threshold (ISL6551IB) Stop Threshold (ISL6551AB) Hysteresis (ISL6551IB) Hysteresis (ISL6551AB) CLOCK GENERATOR (CT, RD) Frequency Range Dead Time Pulse Width (Note 4) BANDGAP REFERENCE (BGREF) Bandgap Reference Voltage (ISL6551IB) Bandgap Reference Voltage (ISL6551AB) Bandgap Reference Output Current
60
VDDON VDDON VDDOFF VDDOFF VDDHYS VDDHYS
9.2 9.16 8.03 7.98 0.3 0.27
9.6
9.9 9.94
V V V V V V
8.6
8.87 8.92
1
1.9 1.93
F DT
VDD = 12V (Figure 2) VDD = 12V (Figure 3)
100 50
1000 1000
kHz ns
VREF VREF IREF
VDD = 12V, 399k pull-up, 0.1F, after trimming VDD = 12V, 399k pull-up, 0.1F, after trimming VDD = 12V, see Block/Pin Functional Descriptions for details
1.250 1.244
1.263 1.263
1.280 1.287 100
V V A
4
ISL6551
Electrical Specifications
PARAMETER PWM DELAYS (Note 4) LOW1,2 delay "Rising" LOW1,2 delay "Falling" SYNC1,2 delay "Falling" SYNC1,2 delay "Rising" LOWR LOWF SYNCF SYNCR With respect to RESDLY rising Compare Delay @ Verror = Vramp With respect to RESDLY falling and with 20pF load With respect to CLK rising and with 20pF load 5 44 18 20 ns ns ns ns These specifications apply for VDD = VDDP = 12V and TA = 0oC to 85 oC (ISL6551IB) or -40oC to 105oC (ISL6551AB), Unless Otherwise Stated (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER (EANI, EAI, EAO) (Note 4) Unity Gain Bandwidth DC Gain Maximum Offset Error Voltage Input Common Mode Range Common Mode Rejection Ratio Power Supply Rejection Ratio Maximum Output Source Current Maximum Lower Saturation Voltage RAMP ADJUST (R_RA) (Note 4) Ramp Frequency Linear Voltage Ramp, Minimum Linear Voltage Ramp, Maximum Overall Variation PEAK CURRENT LIMIT (PKILIM) Peak Current Shutdown Threshold Peak Current Shutdown Delay (Note 4) SOFT-START (CSS) Charge Current Discharge Current Cycle-by-Cycle Current Limit (ISL6551IB) Cycle-by-Cycle Current Limit (ISL6551AB) Iss Idis Vclamp Vclamp Vcss = 0.6V 8 1.6 2 1.9 12 5.2 8 8.1 A mA V V IpkThr IpkDel BGREF = 0.1F, 399k pull-up 1.25 1.263 75 1.31 V ns F LVR 100 50 250 25 1000 kHz mV mV % UGBW DCG Vos Vcm CMMR PSSR ISRC Vsatlow Sinking 0.27mA 1mA load 2 125 VDD = 12V 0.4 82 95 10 79 3.1 9 MHz dB mV V dB dB mA mV
DRIVERS (UPPER1, UPPER2, LOWER1, LOWER2) Maximum Capacitive Load (each) Turn On Rise Time (ISL6551IB) Turn On Rise Time (ISL6551AB) Turn Off Fall Time (ISL6551IB) Turn Off Fall Time (ISL6551AB) Shutdown Delay (Note 4) Rising Edge Delay (Note 4) Falling Edge Delay (Note 4) CL Tr Tr Tf Tf TSD TRD TFD VDD = VDDP = 12V, F = 1MHz, Thermal Dependence 1.0nF Capacitive load 1.0nF Capacitive load 1.0nF Capacitive load 1.0nF Capacitive load 1.0nF Capacitive load 1.0nF Capacitive load 1.0nF Capacitive load 14.5 16.4 13.7 1600 8.9 9.2 6.4 16 17 10 12 pF ns ns ns ns ns ns ns
5
ISL6551
Electrical Specifications
PARAMETER Vsat_sourcing These specifications apply for VDD = VDDP = 12V and TA = 0oC to 85 oC (ISL6551IB) or -40oC to 105oC (ISL6551AB), Unless Otherwise Stated (Continued) SYMBOL Vsat_high TEST CONDITIONS Sourcing 20mA Sourcing 200mA Vsat_sinking (ISL6551IB) Vsat_low Sinking 20mA Sinking 200mA Vsat_sinking (ISL6551AB) Vsat_low Sinking 20mA Sinking 200mA SYNCHRONOUS SIGNALS (SYNC1, SYNC2) Maximum capacitive load (each) VDD = 12, F = 1MHz 20 pF MIN TYP MAX 1.00 1.35 0.035 0.31 0.04 0.5 UNITS V V V V V V
PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 4) Resonant Delay Adjust Range Resonant Delay tRESDLY (Figure 7) R_RESDLY = 10K R_RESDLY = 120K Leading Edge Blanking Adjust Range Leading Edge Blanking tLEB (Figure 8) R_LEB = 20K R_LEB = 140K R_LEB = 12V LATCHING SHUTDOWN (LATSD) Fault Threshold Fault_NOT Threshold Time to Set latch (Note 4) ON/OFF (ONOFF) Turn-off Threshold Turn-on Threshold OFF ON 2 0.8 V V VIN VINN TSET 415 3 1.9 V V ns 50 64 302 0 50 55 488 300 500 ns ns ns ns ns ns ns
CURRENT SHARE (SHARE, CS_COMP) (Note 4) Voltage Offset Between Error Amp Voltage of Master and Slave Maximum Source Current To External Reference Maximum Correctable Deviation In Reference Voltage Between Master and Slave Share/Adjust Loop Bandwidth DC OK (DCOK) Sink Current Saturation Voltage Input Reference Threshold (relative to Vref_in) Recovery (relative to Vref_in) Threshold (relative to Vref_in) Recovery (relative to Vref_in) IDCOK VSATDCOK IDCOK = 5mA Vref_in OV OV UV UV (Figure 11) (Figure 11) (Figure 11) (Figure 11) 1 5 3 -5 -3 5 0.4 5 mA V V % % % % CS BW Vcs_offset Ics_source SHARE = 30K SHARE = 30K SHARE = 30K, Rsource = 1K, OUTPUT REFERENCE = 1 to 5V, (See Figure 10) CS_COMP = 0.1F 30 190 190 mV A mV
500
Hz
6
ISL6551
Electrical Specifications
PARAMETER Transient Rejection (Note 4) NOTE: 4. Guaranteed by design. Not 100% tested in production. These specifications apply for VDD = VDDP = 12V and TA = 0oC to 85 oC (ISL6551IB) or -40oC to 105oC (ISL6551AB), Unless Otherwise Stated (Continued) SYMBOL TRej TEST CONDITIONS 100mV transient on Vout (system implicit rejection and feedback network dependence (Figure 12) MIN TYP 250 MAX UNITS s
Drive Signals Timing Diagrams
CLOCK
UPPER1
UPPER2
SYNC1
SYNC2
LOWER1 EAO ILOWER1
LOWER2 EAO ILOWER2 EAO
RAMP ADJUST OUTPUT TO PWM LOGIC
T1
T2
T3
T4
T5
NOTES:
T1 = Leading edge blanking T2 = T4 = Resonant delay T3 = T5 = dead time In the above figure, the values for T1 through T5 are exaggerated for demonstration purposes.
Timing Diagram Descriptions
The two upper drivers (UPPER1 and UPPER2) are driven at a fixed 50% duty cycle and the two lower drivers (LOWER1 and LOWER2) are PWM-controlled on the trailing edge, while the leading edge employs resonant delay (T2 and T4). In current mode control, the sensed switch (FET) current (ILOWER1 and ILOWER2) is processed in the Ramp Adjust and Leading Edge 7 Blanking (LEB) circuits and then compared to a control signal (EAO). Spikes, due to parasitic elements in the bridge circuit, would falsely trigger the comparator generating the PWM signal. To prevent false triggering, the leading edge of the sensed current signal is blanked out by T1, which can be programmed at the R_LEB pin with a resistor. Internal switches
ISL6551
gate the analog input to the PWM comparator, implementing the blanking function that eliminates response degrading delays which would be caused if filtering of the current feedback was incorporated. The dead time (T3 and T5) is the delay to turn on the upper FET (UPPER1/UPPER2) after its corresponding lower FET (LOWER1/LOWER2) is turned off when the bridge is operating at maximum duty cycle in normal conditions, or is responding to load transients or input line dipping conditions. Therefore, the upper and lower FETs that are located at the same side of the bridge can never be turned
C LATSD
on together, which eliminates shoot-through currents. SYNC1 and SYNC2 are the gate control signals for the output synchronous rectifiers. They are biased by VDD and are capable of driving capacitive loads up to 20pF at 1MHz clock frequency (500kHz switching frequency). External drivers with high current capabilities are required to drive the synchronous rectifiers, cascading with both synchronous signals (SYNC1 and SYNC2).
Shutdown Timing Diagrams
LATCH CANNOT BE RESET BY ON/OFF
D ON/OFF A E VDDON VDD PKILIM > BGREF B LATCH RESET BY REMOVING VDD
F VDDOFF
ILIM_OUT
PKILIM < BGREF
SOFT START
DRIVER ENABLE
FAULT
SOFT START SHUTDOWN
FAULT
OFF
OVER CURRENT
LATCHED
OFF/ON
LATCH RESET
UNDER VOLTAGE LOCKOUT
Shutdown Timing Descriptions
A (ON/OFF) - When the ON/OFF is pulled low, the soft start capacitor is discharged and all the drivers are disabled. When the ON/OFF is released without a fault condition, a soft start is initiated. B (OVER CURRENT) - If the output of the converter is over loaded, i.e., the PKILIM is above the bandgap reference voltage (BGREF), the soft-start capacitor is discharged very quickly and all the drivers are turned off. Thereafter, the soft start capacitor is charged slowly, and discharged quickly if the output is over loaded again. The soft start will remain in hiccup mode as long as the overload conditions persist. Once the overload is removed, the soft-start capacitor is charged up and the converter is then back to normal operation. C (LATCHING SHUTDOWN) - The IC is latched off completely as the LATSD pin is pulled high, and the softstart capacitor is reset. D (ON/OFF) - The latch cannot be reset by the ON/OFF. E (LATCH RESET) - The latch is reset by removing the VDD. The soft-start capacitor starts to be charged after VDD increases above the turn-on threshold VDDON. F (VDD UVLO) - The IC is turned off when the VDD is below the turn-off threshold VDDOFF. Hysteresis VDDHYS is incorporated in the under voltage lockout (UVLO) circuit.
8
ISL6551 Block/Pin Functional Descriptions
Detailed descriptions of each individual block in the functional block diagram on page 3 are included in this section. Application information and design considerations for each pin and/or each block are also included. * IC Bias Power (VDD, VDDP1, VDDP2) - The IC is powered from a 12V 10% supply. - VDD supplies power to both the digital and analog circuits and should be bypassed directly to the VSS pin with an 0.1F low ESR ceramic capacitor. - VDDP1 and VDDP2 are the bias supplies for the upper drivers and the lower drivers, respectively. They should be decoupled with ceramic capacitors to the PGND pin. - Heavy copper should be attached to these pins for a better heat spreading. * IC GNDs (VSS, PGND) - VSS is the reference ground, the return of VDD, of all control circuits and must be kept away from nodes with switching noises. It should be connected to the PGND in only one location as close to the IC as practical. For a secondary side control system, it should be connected to the net after the output capacitors, i.e., the output return pinout(s). For a primary side control system, it should be connected to the net before the input capacitors, i.e., the input return pinout(s). - PGND is the power return, the high-current return path of both VDDP1 and VDDP2. It should be connected to the SOURCE pins of two lower power switches or the RETURNs of external drivers as close as possible with heavy copper traces. - Copper planes should be attached to both pins. * Under Voltage Lockout (UVLO) - UVLO establishes an orderly start-up and verifies that VDD is above the turn-on threshold voltage (VDDON). All the drivers are held low during the lockout. UVLO incorporates hysteresis VDDHYS to prevent multiple startup/shutdowns while powering up. - UVLO limits are not applicable to VDDP1 and VDDP2. * Bandgap Reference (BGREF) - The reference voltage VREF is generated by a precision bandgap circuit. - This pin must be pulled up to VDD with a resistance of approximately 399k for proper operation. For additional reference loads (no more than 1mA), this pullup resistor should be scaled accordingly. - This pin must also be decoupled with an 0.1F low ESR ceramic capacitor. * Clock Generator (CT, RD) - This free-running oscillator is set by two external components as shown in Figure 1. A capacitor at CT is charged and discharged with two equal constant current sources and fed into a window comparator to set the clock frequency. A resistor at RD sets the clock dead time. RD and CT should be tied to the VSS pin on their other ends as close as possible. The corresponding CT for a particular frequency can be selected from Figure 2. - The switching frequency (Fsw) of the power train is half of the clock frequency (Fclock), as shown in Equation 1.
Fclock Fsw = -----------------2 (EQ. 1)
RD
SET CLOCK DEAD TIME (DT)
RD VDD
I_CT
VMAX
+
OUT
CLK
CT - OUT +
S R
Q Q Q Q
CT I_CT
VMIN
CLK
DT
DT
FIGURE 1. SIMPLIFIED CLOCK GENERATOR CIRCUIT
9
ISL6551
3,000 0oC 60oC 2,500 120oC 2,000 F (kHz) 1,500 1,000 500 0 10 2 1.6 1.2 0.8 0.4 0 0 20 40 60 80 RD (k) 100 CT (pF) 1,000 10,000 100 120 140 160
DEAD TIME (s) RECOMMENDED RANGE
FIGURE 3. RD vs. DEAD TIME (VDD = 12V)
FIGURE 2. CT vs. FREQUENCY
- Note that the capacitance of a scope probe (~12pF for single ended) would induce a smaller frequency at the CT pin. It can be easily seen at a higher frequency. An accurate operating frequency can be measured at the outputs of the bridge/synchronous drivers. - The dead time is the delay to turn on the upper FET (UPPER1/UPPER2) after its corresponding lower FET (LOWER1/LOWER2) is turned off when the bridge is operating at maximum duty cycle in normal conditions, or is responding to load transients or input line dipping conditions. This helps to prevent shoot through between the upper FET and the lower FET that are located at the same side of the bridge. The dead time can be estimated using Equation 2:
M x RD DT = ------------------k (ns) (EQ. 2)
* Error Amplifier (EAI, EANI, EAO) - This amplifier compares the feedback signal received at the EAI pin to a reference signal set at the EANI pin and provides an error signal (EAO) to the PWM Logic. The feedback loop compensation can be programmed via these pins. - Both EANI and EAO are clamped by the voltage (Vclamp) set at the CSS pin, as shown in Figure 4. Note that the diodes in the functional block diagram represent the clamp function of the CSS in a simplified way. * Soft-Start (CSS) - The voltage on an external capacitor charged by an internal current source ISS is fed into a control pin on the error amplifier. This causes the Error Amplifier to: 1) limit the EAO to the soft start voltage level; and 2) over-ride the reference signal at the EANI with the soft start voltage, when the EANI voltage is higher than the soft start voltage. Thus, both the output voltage and current of the power supply can be controlled by the soft start. - The clamping voltage determines the cycle-by-cycle peak current limiting of the power supply. It should be set above the EANI and EAO voltages and can be programmed by an external resistor as shown in Figure 4 using Equation 3. Vclamp = Rcss * Iss
(V) (EQ. 3)
where M=11.4(VDD=12V), 11.1(VDD=14V), and 12(VDD=10V), and RD is in k. This relationship is shown in Figure 3.
400mV
+ -
VDD
(See Fig. 9) SSL (TO BLANKING CIRCUIT)
EAI (-)
CSS
Iss EANI (+)
RCSS SHUTDOWN ERROR AMP EAO
FIGURE 4. SIMPLIFIED CLAMP/SOFTSTART
10
ISL6551
- Per Equation 3, the clamping voltage is a function of the charge current Iss. For a more predictable clamping voltage, the CSS pin can be connected to a referencebased clamp circuit as shown in Figure 5. To make the Vclamp less dependent on the soft start current (Iss), the currents flowing through R1 and R2 should be scaled much greater than Iss. The relationship of this circuit can be found in Equation 4.
VREF R1 CSS
in a short-circuit condition. The limit can be set with a resistor divider from the ISENSE pin. The resistor divider relationship is defined in Equation 7. - In general, the trip point is a little smaller than the BGREF due to the noise and/or ripple at the BGREF.
ISENSE
RUP
PKILIM
RDOWN
FIGURE 6. PEAK CURRENT LIMIT SET CIRCUIT
R2
Rdown BGREF -------------------------------------- = ----------------------------------------Rdown + Rup ISENSE ( max ) FIGURE 5. REFERENCE-BASED CLAMP CIRCUIT R1 x R2 R2 Vclamp Iss * --------------------- + Vref * ---------------------R1 + R2 R1 + R2
(EQ. 7)
(EQ. 4)
- The soft start rise time (Tss) can be calculated with Equation 5. The rise time (Trise) of the output voltage is approximated with Equation 6.
Vclamp x Css T ss = --------------------------------------Iss (s) (EQ. 5)
* Latching Shutdown (LATSD) - A high TTL level on LATSD latches the IC off. The IC goes into a low power mode and is reset only after the power at the VDD pin is removed completely. The ON/OFF cannot reset the latch. - This pin can be used to latch the power supply off on output over-voltage or other undesired conditions. * ON/OFF (ON/OFF) - A high standard TTL input (safe also for VDD level) signals the controller to turn on. A low TTL input turns off the controller and terminates all drive signals including the SYNC outputs. The soft start is reset. - This pin is a non-latching input and can accept an enable command when monitoring the input voltage and the thermal condition of a converter. * Resonant Delay (R_RESDLY) - A resistor tied between R_RESDLY and VSS determines the delay that is required to turn on a lower FET after its corresponding upper FET is turned off. This is the resonant delay, which can be estimated with Equation 8.
tRESDLY = 4.01 x R_RESDLY/k + 13 (ns) (EQ. 8)
EANI x Css T rise = -------------------------------Iss
(s)
(EQ. 6)
* Drivers (Upper1, Upper2, Lower1, Lower2) - The two upper drivers are driven at a fixed 50% duty cycle and the two lower drivers are PWM-controlled on the trailing edge while the leading edge employs resonant delay. They are biased by VDDP1 and VDDP2, respectively. - Each driver is capable of driving capacitive loads up to CL at 1MHz clock frequency and higher loads at lower frequencies on a layout with high effective thermal conductivity. - The UVLO holds all the drivers low until the VDD has reached the turn-on threshold VDDON. - The upper drivers require assistance of external levelshifting circuits such as Intersil's HIP2100 or pulse transformers to drive the upper power switches of a bridge converter. * Peak Current Limit (PKILIM) - When the voltage at PKILIM exceeds the BGREF voltage, the gate pulses are terminated and held low until the next clock cycle. The peak current limit circuit has a high-speed loop with propagation delay IpkDel. Peak current shutdown initiates a soft-start sequence. - The peak current shutdown threshold is usually set slightly higher than the normal cycle-by-cycle PWM peak current limit (Vclamp) and therefore will normally only be activated 11
- Figure 7 illustrates the relationship of the value of the resistor (R_RESDLY) and the resonant delay (tRESDLY). The percentages in the figure are the tolerances at the two end points of the curve.
ISL6551
500 450 400 tRESDLY (ns) 350 300 250 200 150 100 50 0 20 40 60 80 100 120 R_RESDLY (k) +37% +4% +18% -24%
incorporated. The current ramp is blanked out during the resonant delay period because no switching occurs in the lower FETs. The leading edge blanking function will not be activated until the soft start (CSS) reaches over 400mV, as illustrated in Figures 4 and 9. The leading edge blanking (LEB) function can be disabled by tying the R_LEB pin to VDD, i.e., LEB=1. Never leave the pin floating. - The blanking time can be estimated with Equation 9, whose relationship can be seen in Figure 8. The percentages in the figure are the tolerances at the two endpoints of the curve.
tLEB = 2 x R_LEB / k + 15 (ns) (EQ. 9)
FIGURE 7. R_RESDLY vs. RESDLY
300 250 200 tLEB (ns) 150 100 50 0 20 +51% -11%
+20% -18%
* Leading Edge Blanking (R_LEB) - In current mode control, the sensed switch (FET) current is processed in the Ramp Adjust and LEB circuits and then compared to a control signal (EAO voltage). Spikes, due to parasitic elements in the bridge circuit, would falsely trigger the comparator generating the PWM signal. To prevent false triggering, the leading edge of the sensed current signal is blanked out by a period that can be programmed with the R_LEB resistor. Internal switches gate the analog input to the PWM comparator, implementing the blanking function that eliminates response degrading delays which would be caused if filtering of the current feedback was
40
60
80 R_LEB (k)
100
120
140
FIGURE 8. R_LEB vs. tLEB
0.1 399K
VDD
ADJ_RAMP
ADJ_RAMP BGREF R_RA RAMP_OUT (TO PWM COMPARATOR)
200mV 0 ISENSE
RAMP_OUT 200mV
R_RA ADD RAMP ISENSE 200mV + BLANK
RESDLY 0
LEB X 0 1 X
SSL X 0 X 1
RAMP_OUT BLANK BLANK NO BLANK NO BLANK
R_LEB
SET BLANKING TIME
RESDLY LEB SSL (See Fig. 4)
X 1 1
R_LEB
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
12
ISL6551
* Ramp Adjust (R_RA, ISENSE) - The ramp adjust block adds an offset component (200mV) and a slope adjust component to the ISENSE signal before processing it at the PWM Logic block, as shown in Figure 9. This ensures that the ramp voltage is always higher than the OAGS (ground sensing opamp) minimum voltage to achieve a "zero" state. - It is critical that the input signal to ISENSE decays to zero prior to or during the clock dead time. The levelshifting and capacitive summing circuits in the RAMP ADJUST block are reset during the dead time. Any input signal transitions that occur after the rising edge of CLK and prior to the rising edge of RESDLY can cause severe errors in the signal reaching the PWM comparator. - Typical ramp values are hundreds of mV over the period on a 3V full scale current. Too much ramp makes the controller look like a voltage mode PWM, and too little ramp leads to noise issues (jitter). The amount of ramp (Vramp), as shown in Figure 9, is programmed with the R_RA resistor and can be calculated with Equation 10.
Vramp = BGREF x dt /(R_RA x 500E-12) (V) (EQ. 10)
synchronous rectifiers. When using these drive schemes, the user should understand the issues that might occur in his/her applications, especially the impacts on current share operation and light load operation. Refer to application note AN1002 for more details. - External high current drivers controlled by the synchronous signals are required to drive the synchronous rectifiers. A pulse transformer is required to pass the drive signals to the secondary side if the IC is used in a primary control system. * Share Support (SHARE, CS_COMP) - The unit with the highest reference is the master. Other units, as slaves, adjust their references via a source resistor to match the master reference sharing the load current. The source resistor is typically 1k connecting the EANI pin and the OUTPUT REFERENCE (external reference or BGREF), as shown in Figure 10. The share bus represents a 30k resistive load per unit, up to 10 units. - The output (ADJ) of "Operational Transconductance Amplifier (OTA)" can only pull high and it is floating while in master mode. This ensures that no current is sourced to the OUTPUT REFERENCE when the IC is working by itself. - The slave units attempt to drive their error amplifier voltage to be within a pre-determined offset (30mV typical) of the master error voltage (the share bus). The current-share error is nominally (30mV/EAO)*100% assuming no other source of error. With a 2.5V full load error amp voltage, the current-share error at full load would be -1.2% (slaves relative to master). - The bandwidth of the current sharing loop should be much lower than that of the voltage loop to eliminate noise pick-up and interactions between the voltage regulation loop and the current loop. A 0.1F capacitor is recommended between CS_COMP and VSS pins to achieve a low current sharing loop bandwidth (100Hz to 500Hz).
where dt = Duty Cycle / Fsw - tLEB (s). Duty cycle is discussed in detail in application note AN1002. - The voltage representation of the current flowing through the power train at ISENSE pin is normally scaled such that the desired peak current is less than or equal to Vclamp-200mV-Vramp, where the clamping voltage is set at the CSS pin. * SYNC Outputs (SYNC1, SYNC2) - SYNC1 and SYNC2 are the gate control signals for the output synchronous rectifiers. They are biased by VDD and are capable of driving capacitive loads up to 20pF at 1MHz clock frequency (500kHz switching frequency). These outputs are turned off sooner than the turn-off at UPPER1 and UPPER2 by the clock dead time, DT. - Inverting both SYNC signals or both LOWER signals is another possible way to control the drivers of the
CS_COMP 0.1F 30mV EAO + + + OTA ADJ EANI (+) SHARE 30K 1K OUTPUT REFERENCE
FIGURE 10. SIMPLIFIED CURRENT SHARE CIRCUIT
13
ISL6551
* Power Good (DCOK) - DCOK pin is an open drain output capable of sinking 5mA. It is low when the output voltage is within the UVOV window. The static regulation limit is 3%, while the 5% is the dynamic regulation limit. It indicates power good when the EAI is within -3% to +5% on the rising edge and within +3% to -5% on the falling edge, as shown in Figure 11.
EAI VOUT +5% +3% EANI -3% -5% 0.90V 1.05V EAI 1.00V 0.95V 1.00V 18K EAI VOUT 1K EANI R + 15N C EAO
1.10V
FIGURE 12. OUTPUT TRANSIENT REJECTION
DCOK FAULT
FIGURE 11. UNDERVOLTAGE-OVERVOLTAGE WINDOW
- The DCOK comparator might not be triggered even though the output voltage exceeds 5% limits at load transients. This is because the feedback network of the error amplifier filters out part of the transients and the EAI only sees the remaining portion that is still within the limits, as illustrated in Figure 12. The lower the "zero (1/RC)" of the error amplifier, the larger the portion of the transient is filtered out.
* Thermal Pad (in QFN only) - In the QFN package, the pad underneath the center of the IC is a "floating" thermal substrate. The PCB "thermal land" design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the QFN to achieve its full thermal potential. This pad should be connected to a low noise copper plane such as Vss. - Refer to TB389 for design guidelines.
14
ISL6551 Additional Applications Information
Table 1 highlights parameter setting for the ISL6551. Designers can use this table as a design checklist. For detailed operation of the ISL6551, see Block/Pin Functional Descriptions.
TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST VDD = 12V at room temperature, unless otherwise stated. PARAMETER Frequency Dead Time Resonant Delay Ramp Adjust Current Sense Peak Current Bandgap Reference Leading Edge Blanking Current Share Compensation Soft-Start & Output Rise Time Clamp Voltage (Vclamp) Error Amplifier Share Support Latching Shutdown Power Good IC Enable Reference Ground Power Ground Upper Drivers Lower Drivers Synchronous Drive Signals Bias for Control Circuits Biases for Bridge Drivers PIN NAME CT RD R_RESDLY R_RA ISENSE PKILIM BGREF R_LEB CS_COMP CSS CSS EANI, EAI, EAO SHARE LATSD DCOK ON/OFF VSS PGND FORMULA OR SETTING HIGHLIGHT Set 50% Duty Cycle Pulses with a fixed frequency DT = M x RD/k, where M=11.4 tRESDLY = 4.01 x R_RESDLY/k + 13 Vramp = BGREF/(R_RA x 500E-12) x dt < Vclamp-200mV-Vramp < BGREF and slightly higher than Vclamp 1.263V 2%, 399k pull-up, No more than 100A load tLEB = 2 x R_LEB / k + 15, never leave it floating 0.1 for a low current loop bandwidth (100 - 500 Hz) tss = Vclamp x Css / Iss, trise = EANI x CSS / Iss, Iss = 10A 20% Vclamp = Iss x Rcss, or Reference-based clamp EANI, EAO < Vclamp 30K load & a resistor (1K, typ.) between EANI and OUTPUT REF. Latch IC off at > 3V 5% with hysteresis, Sink up to 5mA, transient rejection Turn on/off at TTL level Connect to PGND in only one single point Single point to VSS plane UNIT kHz ns ns V V V V ns Hz S V V V V V V V FIGURE # 1, 2 3 7 6 8, 9 10 4 4, 5 11, 12 -
UPPER1, UPPER2 Capacitive load up to 1.6nF at Fsw = 500kHz LOWER1, LOWER2 Capacitive load up to 1.6nF at Fsw = 500kHz SYNC1, SYNC2 VDD VDDP1, VDDP2 Capacitive load up to 20pF at Fsw = 500kHz 12V 10%, 0.1F decoupling capacitor Need decoupling capacitors
15
ISL6551
Figure 13 shows the block diagram of a power supply system employing the ISL6551 full bridge controller. The ISL6551 not only is a full bridge PWM controller but also can be used as a push-pull PWM controller. Users can design a power supply by selecting appropriate blocks in the "System Blocks Chart" based on the power system requirements. Figures 13A, 14A, 15A, 16A, 17A, 18A, 19, 20A, 21, 22A, and 24A have been used in the 200W telecom power supply reference design, which can be found in the Application Note AN1002. To meet the specifications of the power supply, minor modifications of each block are required. To take full advantage of the integrated features of the ISL6551, "secondary side control" is recommended.
BIASES
PRIMARY BIAS SECONDARY BIAS
VIN
INPUT FILTER
PRIMARY FETs
MAIN TRANSFORMER
RECTIFIERS
OUTPUT FILTER
VOUT
CURRENT SENSE
PRIMARY FET DRIVERS
ISL6551 CONTROLLER
SECONDARY DRIVERS
SUPERVISOR CIRCUITS
FEEDBACK
FIGURE 13. BLOCK DIAGRAM OF A POWER SUPPLY SYSTEM USING ISL6551 CONTROLLER
16
ISL6551 System Blocks Chart
Input Filters
VIN VINF
Two-Leg Sense - Senses the current that flows through both lower primary FETs. Operates at the switching frequency. Top Sense - Senses the sum of the current that flows through both upper primary FETs. Operates at the clock frequency. Resistor Sense - This simple scheme is used in a primary side control system. The sum of the current that flows through both lower primary FETs is sensed with a low impedance power resistor. The sources of Q3 and Q4 and ISENSE should be tied at the same point as close as possible. BIASES
VINF CIN
CIN
FIGURE 13A. GENERAL
VIN
LIN
Linear Regulator - In a primary side control system, a linear regulator derived from the input line can be used for the start up purpose, and an extra winding coupled with the main transformer can provide the controller power after the start up. DCM Flyback - Use a PWM controller to develop both primary and secondary biases with discontinuous current mode flyback topology.
FIGURE 13B. EMI
General - Input capacitors are required to absorb the power switch (FET) pulsating currents. EMI - For good EMI performance, the ripple current that is reflected back to the input line can be reduced by an input L-C filter, which filters the differential-mode noises and operates at two times the switching frequency, i.e., the clock frequency (Fclock). In some cases, an additional common-mode choke might be required to filter the common-mode noises.
Primary FETs
VINF or CURRENT_SEN_P Q1_G P- Q1 Q2
Q2_G P+
Current Sense
ISENSE T_CURRENT Q3_S
Q3_G Q3_S
Q3
Q4_G Q4_S
Q4
FIGURE 15A. FULL BRIDGE
P1- Q4_S
P2-
FIGURE 14A. TWO-LEG SENSE
Q3_G
Q3
Q4_G
Q4
VINF
ISENSE
Q3_S
Q4_S
FIGURE 15B. PUSH-PULL
CURRENT_SEN_P
FIGURE 14B. TOP SENSE
ISENSE Q3_S & Q4_S RSENSE
Full Bridge - Four MOSFETs are required for full bridge converters. The drain to source voltage rating of the MOSFETs is Vin. Push-Pull - Only the two lower MOSFETs are required for push-pull converters. The two upper drivers are not used. The VDS of the MOSFETs is 2xVin.
FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL)
17
ISL6551
Feedback Rectifiers
SYNCHRONOUS FETs S+ SCHOTTKY S+ SYNP EAO EAI VOPOUT SYNN S-
S-
FIGURE 17A. CURRENT DOUBLER RECTIFIERS
FIGURE 16A. SECONDARY CONTROL
SYNCHRONOUS FETs S+ S+
SCHOTTKY
VREF = 5V VOPOUT IL207 SYNN SYNP
EAO TL431 EAI
S-
S-
FIGURE 17B. CONVENTIONAL RECTIFIERS
S+
FIGURE 16B. PRIMARY CONTROL
Secondary Control - In secondary side control systems, only a few resistors and capacitors are required to complete the feedback loop. Primary Control - This feedback loop configuration for primary side control systems requires an optocoupler for isolation. The bandwidth is limited by the optocoupler.
S-
FIGURE 17C. SELF-DRIVEN RECTIFIERS
Current Doubler Rectifiers 1. Synchronous FETs are used for low output voltage, high output current and/or high efficiency applications. 2. Schottky diodes are used for lower current applications. Pins S+ and S- are connected to the output filter and the main transformer with current doubler configurations. Conventional Rectifiers 1. Synchronous FETs are used for low output voltage, high output current and/or high efficiency applications. 2. Schottky diodes are used for lower current applications. Pins S+ and S- are connected to the main transformer with conventional configurations. Self-Driven Rectifiers - For low output voltage applications, both FETs can be driven by the voltage across the secondary winding. This can work with all kinds of main transformer configurations as shown in Figures 18A-D.
18
ISL6551
Main Transformers
P+ S+
Supervisor Circuits
(1) INTEGRATED SOLUTION * Intersil ISL6550 Supervisor And Monitor (SAM). Its QFN package requires less space than the SOIC package.
P-
S- VCC VOPP VOPM 1 2 3 4 5 6 7 8 9 20 UVDLY 19 OVUVSEN 18 PGOOD PGOOD 17 START START 16 PEN 15 VID0 14 VID1 13 VID2 12 VID3 11 VID4 PEN
FIGURE 18A. FULL BRIDGE AND CURRENT DOUBLER
P+
S+ VOUTF
VOPOUT VREF5
VOPOUT VREF5 GND
P-
S-
BDAC
BDAC OVUVTH DACHI
FIGURE 18B. CONVENTIONAL FULL BRIDGE
DACLO 10
P1-
VINF or CURRENT_SEN_P
S+
FIGURE 19. ISL6550 SOIC
S-
P2-
* Over temperature protection (discrete) * Input UV lockout (discrete) (2) DISCRETE SOLUTION
FIGURE 18C. PUSH-PULL AND CURRENT DOUBLER
P1-
VINF or CURRENT_SEN_P
S+ VOUTF S-
* Differential Amplifier * VCC undervoltage lockout * Programmable output OV and UV * Programmable output * Status indicators (PGOOD and START) * Precision Reference * Over temperature protection * Input UV lockout The Integrated Solution is much simpler than a discrete solution. Over temperature protection and input under voltage lockout can be added for better system protection and performance. The Discrete Solution requires a significant number of components to implement the features that the ISL6550 can provide.
P2-
FIGURE 18D. CONVENTIONAL PUSH-PULL
Full Bridge and Current Doubler - No center tap is required. The secondary winding carries half of the load, i.e., only half of the load is reflected to the primary. Conventional Full Bridge - Center tap is required on the secondary side, and no center tap is required on the primary side. The secondary winding carries all the load. i.e., all the load is reflected to the primary. Push-Pull and Current Doubler - Center tap is required on the primary side, and no center tap is required on the secondary side. The secondary winding carries half of the load, i.e., only half of the load is reflected to the primary. Conventional Push-Pull - Both primary and secondary sides require center taps. The secondary winding carries all the load, i.e., all the load is reflected to the primary.
19
ISL6551
Output Filter
S+ LOUT
Secondary Drivers
MIC4421BM VOUT COUT SYNC2 IN OUT /LOWER1 GND SYNC1 /LOWER2 MIC4421BM
SYNP
IN OUT GND
SYNN
S-
FIGURE 20A. CURRENT DOUBLER FILTER FIGURE 22A. INVERTING DRIVERS
LOUT VOUTF FCLOCK VOUT COUT SYNC1
MIC4422BM
MIC4422BM
IN OUT GND
SYNP
SYNC2
IN OUT GND
SYNN
FIGURE 20B. CONVENTIONAL FILTER
Current Doubler Filter - Two inductors are needed, but they can be integrated and coupled into one core. Each inductor carries half of the load operating at the switching frequency. Conventional Filter - One inductor is needed. The inductor carries all the load operating at two times the switching frequency.
FIGURE 22B. NON-INVERTING DRIVERS
IN OUT
T_SYN
SYNP
Controller
VSS 1 CT 2 RD 3 R_RESDLY 4 R_RA 5 ISENSE 6 PKILIM 7 BGREF 8 R_LEB 9 CS_COMP 10 OUTPUT REFERENCE CSS 11 (BDAC) EANI 12 EAI EAO EAI 13 EAO 14 ICL6551 SOIC 28 VDD 27 VDDP1 26 VDDP2 25 PGND 24 UPPER1 23 UPPER2 22 LOWER1 21 LOWER2 20 SYNC1 19 SYNC2 18 ON / OFF 17 DCOK 16 LSTSD 15 SHARE SHARE BUS LED LSTSD INPUT UV & OV SYN2 SYN1
GND
IN OUT FSW GND
SYNN
INVERTING SYN1 SYN2 IC SYNC2/LOWER1 SYNC1/LOWER2 MIC4421BM
NON INVERTING SYNC1 SYNC2 MIC4422BM
FIGURE 22C. PRIMARY CONTROL
FIGURE 21. ISL6551 CONTROLLER
Inverting Drivers - Inverting the SYNC signals or the LOWER signals with external high current drivers to drive the synchronous FETs. Non-inverting Drivers - Cascading SYNC signals with noninverting high current drivers to drive the synchronous FETs. There is a dead time between SYNC1 and SYNC2. For a higher efficiency, schottky diodes are normally in parallel with the synchronous FETs to reduce the conduction losses during the dead time in high output current applications. Primary Control - This requires a pulse transformer, operating at the switching frequency, for isolation. There are three options to drive the synchronous FETs, as described in previous lines.
ISL6551 Controller - It can be used as a full bridge or pushpull PWM controller. The QFN package requires less space than the SOIC package.
20
ISL6551
Primary FET Drivers
(1) PUSH-PULL DRIVERS
HIP2100IB Q3_G HI HO Q3_G Q3_S Q4_G Q4_S LOWER2
LOWER1 Q3_S Q4_S LOWER2 LOWER1
HS LI VSS LO
Q4_G
FIGURE 23A. PUSH-PULL MEDIUM CURRENT DRIVERS
FIGURE 23B. PUSH-PULL HIGH CURRENT DRIVERS
HIP2100IB LOWER1 HI LOWER2 LI HO HS Q3_G Q3_S Q4_G Q4_S
VSS LO PGND
FIGURE 23C. PUSH-PULL PRIMARY CONTROL
Push-Pull Medium Current Drivers - Upper drivers are not used. No external drivers are required. Secondary control. Operate at the switching frequency. Push-Pull High Current Drivers - Upper drivers are not used. External high current drivers are required and less power is dissipated in the ISL6551 controller. Secondary control. Operate at the switching frequency. Push-Pull Primary Control - Upper drivers are not used. Both lower drivers can directly drive the power switches. External drivers are required in high gate capacitance applications.
21
ISL6551
(2) FULL BRIDGE DRIVERS
HIP2100IB HI HO HS LI VSS LO UPPER1 Q3_S UPPER2 HIP2100IB UPPER2 Q1_G P- Q3_G UPPER1
Q1_G
P- P+
Q2_G HI HO HS Q2_G P+ Q4_G Q4_S LOWER1 LOWER2 LOWER2 Q4_G LOWER1 Q3_S Q4_S Q3_G
LI VSS LO
FIGURE 24A. FULL BRIDGE HIGH CURRENT DRIVERS
FIGURE 24B. FULL BRIDGE MEDIUM CURRENT DRIVERS
HIP2100IB UPPER1 LOWER1 HI HO HS Q1G P- Q3_G Q3_S
LI VSS LO
PGND
HIP2100IB UPPER2 LOWER2 HI HO HS Q2_G P+ Q4_G Q4_S
LI VSS LO
PGND
FIGURE 24C. FULL BRIDGE PRIMARY CONTROL
Full Bridge High Current Drivers - External high current drivers are required and less power is dissipated in the ISL6551 controller. Secondary control. Operate at the switching frequency. Full Bridge Medium Current Drivers - No external drivers are required. Secondary control. Operate at the switching frequency. Full Bridge Primary Control - Lower drivers can directly drive the power switches, while upper drivers require the assistance of level-shifting circuits such as a pulse transformer or Intersil's HIP2100 half-bridge driver. External high current drivers are not required in medium power applications, but level-shifting circuits are still required for upper drivers. Operate at the switching frequency.
22
Simplified Typical Application Schematics
SB+12V SB+48V SA+12V
LOWER1
VDD HB HO HS LO VSS LI HI VS VS OUT IN OUT NC GND GND
SYNC2
UPPER1
MIC4421
3.3Vout
HIP2100
UPPER2
V+
V-
23
SA+12V
LOWER2
LOWER1
SB+12V
VDD HB HO HS LO VSS LI HI
+
VS VS OUT IN OUT NC GND GND
SYNC1
MIC4421
LOWER2
HIP2100
SA+12V
-
PGOOD
20 19 18 17 16 15 14 13 12 11 UVDLY VCC OVU VSEN VOPP PGOOD VOPM START VOPOUT PEN VREF5 VID0 G ND BDAC VID1 OVUVTH VID2 DACHI VID3 DACLO VID4 1 2 3 4 5 6 7 8 9 10
ISL6551
SA+12V
+
OUT -
ISL6550
1.263V
PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2
28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS VDDP1 CT RD VDDP2 PGND R_RESDLY R_RA UPPER1 ISENSE UPPER2 PKILIM LOWER1 BGREF LOWER2 R_LEB SYNC1 SYNC2 CS_COMP ON/OFF CSS DCOK EANI LATSD EAI SHARE EAO 1 2 3 4 5 6 7 8 9 10 11 12 13 14
LED SHARE BUS
ISL6551
200W TELECOMMUNICATION POWER SUPPLY (SEE AN1002 FOR DETAILS)
ISL6551 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992
B C D E

A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
24
ISL6551 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 3.95 3.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 6.00 BSC 5.75 BSC 4.10 6.00 BSC 5.75 BSC 4.10 0.65 BSC 0.60 28 7 7 0.60 12 0.75 0.15 4.25 4.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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