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FEATURES +1.8 V to +5.5 V Single Supply 4 (Max) On Resistance Low On-Resistance Flatness -3 dB Bandwidth >200 MHz Rail-to-Rail Operation 8-Lead SOIC Package Fast Switching Times tON 20 ns tOFF 10 ns Low Power Consumption (<0.1 TTL/CMOS Compatible
CMOS Low Voltage 4 Dual SPST Switches ADG721/ADG722/ADG723
FUNCTIONAL BLOCK DIAGRAMS
ADG721
S1 IN1 D1 D2 IN2 S2 IN2 S2 D1 D2 S1 IN1
ADG722
W)
ADG723
S1 IN1 D1 D2 IN2 S2
APPLICATIONS Battery Powered Systems Communication Systems Sample Hold Systems Audio Signal Routing Video Switching Mechanical Reed Relay Replacement
SWITCHES SHOWN FOR A LOGIC "0" INPUT
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG721, ADG722 and ADG723 are monolithic CMOS SPST switches. These switches are designed on an advanced submicron process that provides low power dissipation yet gives high switching speed, low On resistance and low leakage currents. The ADG721, ADG722 and ADG723 are designed to operate from a single +1.8 V to +5.5 V supply, making them ideal for use in battery powered instruments and with the new generation of DACs and ADCs from Analog Devices. The ADG721, ADG722 and ADG723 contain two independent single-pole/single-throw (SPST) switches. The ADG721 and ADG722 differ only in that both switches are normally open and normally closed respectively. While in the ADG723, Switch 1 is normally open and Switch 2 is normally closed. Each switch of the ADG721, ADG722 and ADG723 conducts equally well in both directions when on. The ADG723 exhibits break-before-make switching action.
1. +1.8 V to +5.5 V Single Supply Operation. The ADG721, ADG722 and ADG723 offers high performance, including low on resistance and fast switching times and is fully specified and guaranteed with +3 V and +5 V supply rails. 2. Very Low RON (4 max at 5 V, 10 max at 3 V). At 1.8 V operation, RON is typically 40 over the temperature range. 3. Low On-Resistance Flatness. 4. -3 dB Bandwidth >200 MHz. 5. Low Power Dissipation. CMOS construction ensures low power dissipation. 6. Fast tON /tOFF. 7. 8-Lead SOIC.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
ADG721/ADG722/ADG723-SPECIFICATIONS1
(VDD = +5 V 10%, GND = 0 V. All specifications -40 C to +85 C, unless otherwise noted.)
B Version - 40 C to +25 C +85 C 0 V to VDD 5 Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD (ADG723 Only) Charge Injection Off Isolation Units V max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ pF typ pF typ pF typ VIN = VINL or VINH Test Conditions/Comments
4
VS = 0 V to VDD, IS = -10 mA, Test Circuit 1 VS = 0 V to VDD, IS = -10 mA VS = 0 V to VDD, IS = -10 mA VDD = +5.5 V VS = 4.5 V/1 V, VD = 1 V/4.5 V Test Circuit 2 VS = 4.5 V/1 V, VD = 1 V/4.5 V Test Circuit 2 VS = VD = 1 V, or VS = VD = 4.5 V Test Circuit 3
0.3 1.0 0.85 1.5 0.01 0.25 0.01 0.25 0.01 0.25
0.35 0.35 0.35 2.4 0.8
0.005
0.1
14 20 6 10 7 1 2 -60 -80 -77 -97 200 7 7 18
Channel-to-Channel Crosstalk
Bandwidth -3 dB CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD
RL = 300 , CL = 35 pF VS = 3 V, Test Circuit 4 RL = 300 , CL = 35 pF VS = 3 V, Test Circuit 4 RL = 300 , CL = 35 pF, VS1 = VS2 = 3 V, Test Circuit 5 VS = 2 V; RS = 0 , CL = 1 nF, Test Circuit 6 RL = 50 , CL = 5 pF, f = 10 MHz RL = 50 , CL = 5 pF, f = 1 MHz, Test Circuit 7 RL = 50 , CL = 5 pF, f = 10 MHz RL = 50 , CL = 5 pF, f = 1 MHz, Test Circuit 8 RL = 50 , CL = 5 pF, Test Circuit 9
0.001 1.0
A typ A max
VDD = +5.5 V Digital Inputs = 0 V or 5 V
NOTES 1 Temperature ranges are as follows: B Version, -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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SPECIFICATIONS (V
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON)
1
ADG721/ADG722/ADG723
DD
= +3 V
10%, GND = 0 V. All specifications -40 C to +85 C, unless otherwise noted.)
B Version - 40 C to +25 C +85 C 0 V to VDD 6.5 10 0.3 1.0 3.5 0.01 0.25 0.01 0.25 0.01 0.25
Units V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ pF typ pF typ pF typ
Test Conditions/Comments
VS = 0 V to VDD, IS = -10 mA Test Circuit 1 VS = 0 V to VDD, IS = -10 mA VS = 0 V to VDD, IS = -10 mA VDD = +3.3 V VS = 3 V/1 V, VD = 1 V/3 V Test Circuit 2 VS = 3 V/1 V, VD = 1 V/3 V Test Circuit 2 VS = VD = 1 V, or 3 V Test Circuit 3
On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD (ADG723 Only) Charge Injection Off Isolation
0.35 0.35 0.35 2.0 0.4
0.005
0.1
VIN = VINL or VINH
16 24 7 11 7 1 2 -60 -80 -77 -97 200 7 7 18
Channel-to-Channel Crosstalk
Bandwidth -3 dB CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD
RL = 300 , CL = 35 pF VS = 2 V, Test Circuit 4 RL = 300 , CL = 35 pF VS = 2 V, Test Circuit 4 RL = 300 , CL = 35 pF, VS1 = VS2 = 2 V, Test Circuit 5 VS = 1.5 V; RS = 0 , CL = 1 nF, Test Circuit 6 RL = 50 , CL = 5 pF, f = 10 MHz RL = 50 , CL = 5 pF, f = 1 MHz, Test Circuit 7 RL = 50 , CL = 5 pF, f = 10 MHz RL = 50 , CL = 5 pF, f = 1 MHz, Test Circuit 8 RL = 50 , CL = 5 pF, Test Circuit 9
0.001 1.0
A typ A max
VDD = +3.3 V Digital Inputs = 0 V or 3 V
NOTES 1 Temperature ranges are as follows: B Version, -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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ADG721/ADG722/ADG723
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
TERMINOLOGY
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog, Digital Inputs2 . . . . . . . . . . . -0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
Table I. Truth Table (ADG721/ADG722)
ADG721 In 0 1
ADG722 In 1 0
Switch Condition OFF ON
Table II. Truth Table (ADG723)
Most Positive Power Supply Potential. Ground (0 V) Reference. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Ohmic resistance between D and S. On resistance match between any two channels i.e., RON max - RON min. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. Source leakage current with the switch "OFF." IS (OFF) ID (OFF) Drain leakage current with the switch "OFF." ID, IS (ON) Channel leakage current with the switch "ON." VD (VS) Analog voltage on terminals D, S. CS (OFF) "OFF" Switch Source Capacitance. CD (OFF) "OFF" Switch Drain Capacitance. CD, CS (ON) "ON" Switch Capacitance. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tD "OFF" time or "ON" time measured between the 90% points of both switches, When switching from one address state to another. (ADG723 Only) Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an "OFF" switch. Charge A measure of the glitch impulse transferred Injection during switching.
PIN CONFIGURATION 8-Lead SOIC (RM-8)
S1 1 D1 2 IN2 3
8
VDD GND S D IN RON RON
Logic 0 1
Switch 1 OFF ON
Switch 2 ON OFF
VDD IN1
ADG721/ 722/723
7 6
D2 TOP VIEW GND 4 (Not to Scale) 5 S2
ORDERING GUIDE
Model ADG721BRM ADG722BRM ADG723BRM
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Brand* S6B S7B S8B
Package Description SOIC SOIC SOIC
Package Option RM-8 RM-8 RM-8
*Brand = Due to package size limitations, these three characters represent the part number.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG721/ADG722/ADG723 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Typical Performance Characteristics- ADG721/ADG722/ADG723
6.0 5.5 5.0 4.5 4.0 3.5 RON - 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 1n 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M 10n VDD = +5.0V ISUPPLY - A VDD = +3.0V VDD = +4.5V 10 VDD = +2.7V TA = +25 C 100 1m VDD = +5V
1
100n
Figure 1. On Resistance as a Function of VD (V S) Single Supplies
Figure 4. Supply Current vs. Input Switching Frequency
6.0 +85 C 5.0 OFF ISOLATION - dB VDD = +3V
-30 VDD = +3V, +5V -40
-50 -60 -70
4.0 +25 C RON - 3.0 -40 C
2.0
-80 -90 -100 10k
1.0
0 0 0.5 1.0 1.5 2.0 2.5 3.0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
100k
1M 10M FREQUENCY - Hz
100M
Figure 2. On Resistance as a Function of VD (VS) for Different Temperatures VDD = +3 V
Figure 5. Off Isolation vs. Frequency
6.0 5.5 5.0 4.5 +25 C +85 C CROSSTALK - dB 4.0 3.5 RON - 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V -40 C VDD = +5V
-30 VDD = +3V, +5V -40 -50 -60 -70 -80 -90 -100 -110 10k
100k
10M 1M FREQUENCY - Hz
100M
Figure 3. On Resistance as a Function of VD (VS) for Different Temperatures VDD = +5 V
Figure 6. Crosstalk vs. Frequency
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ADG721/ADG722/ADG723
-6 VDD = +5V -7 ON RESPONSE - dB
-8
-9
-10
-11
-12 100 1k 10k 100k 1M FREQUENCY - Hz 10M 100M
Figure 7. On Response vs. Frequency
Test Circuits
IDS V1 IS (OFF) S D A VS S D ID (OFF) A VD VS S D ID (ON) A VD
VS
RON = V1/IDS
Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
VDD 0.1 F VIN ADG721 VDD S VS D RL 300 GND VOUT VIN ADG722 IN CL 35pF VOUT 50% 90% 50% 90% 50% 50%
tON
tOFF
Test Circuit 4. Switching Times
VDD 0.1 F VIN D1 D2 RL2 300 GND VOUT2 CL2 35pF VOUT2 0V 90% 90% RL1 300 CL1 35pF VOUT1 VOUT1 0V
VDD VS1 VS2 S1 S2 IN1, IN2 VIN
0V
50% 90%
50% 90%
tD
tD
Test Circuit 5. Break-Before-Make Time Delay, tD (ADG723 Only)
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ADG721/ADG722/ADG723
VDD SW ON VDD RS VS S D CL 1nF VOUT GND QINJ = CL VOUT VOUT VOUT VIN SW OFF
IN
Test Circuit 6. Charge Injection
VDD 0.1 F 0.1 F VDD
VDD S D RL 50 VS VIN IN GND VS VIN IN VOUT S
VDD D RL 50 VOUT
GND
Test Circuit 7. Off Isolation
Test Circuit 9. Bandwidth
VDD 0.1 F
VDD S D 50
VS
VIN1 VIN2 S GND D RL 50 VOUT
NC
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VS/VOUT
Test Circuit 8. Channel-to-Channel Crosstalk
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ADG721/ADG722/ADG723
APPLICATIONS INFORMATION Off Isolation
The ADG721/ADG722/ADG723 belongs to Analog Devices' new family of CMOS switches. This series of general purpose switches have improved switching times, lower on resistance, higher bandwidths, low power consumption and low leakage currents.
ADG721/ADG722/ADG723 Supply Voltages
Off isolation is a measure of the input signal coupled through an off switch to the switch output. The capacitance, CDS, couples the input signal to the output load, when the switch is off as shown in Figure 9.
CDS S VIN D VOUT CD CLOAD RLOAD
Functionality of the ADG721/ADG722/ADG723 extends from +1.8 V to +5.5 V single supply, which makes it ideal for battery powered instruments, where important design parameters are power efficiency and performance. It is important to note that the supply voltage effects the input signal range, the on resistance and the switching times of the part. By taking a look at the typical performance characteristics and the specifications, the effects of the power supplies can be clearly seen. For VDD = +1.8 V, on resistance is typically 40 over the temperature range.
On Response vs. Frequency
Figure 9. Off Isolation Is Affected by External Load Resistance and Capacitance
Figure 8 illustrates the parasitic components that affect the ac performance of CMOS switches (the switch is shown surrounded by a box). Additional external capacitances will further degrade some performance. These capacitances affect feedthrough, crosstalk and system bandwidth.
CDS S RON VIN CD CLOAD D VOUT RLOAD
The larger the value of CDS, larger values of feedthrough will be produced. The typical performance characteristic graph of Figure 5 illustrates the drop in off isolation as a function of frequency. From dc to roughly 1 MHz, the switch shows better than -80 dB isolation. Up to frequencies of 10 MHz, the off isolation remains better than -60 dB. As the frequency increases, more and more of the input signal is coupled through to the output. Off isolation can be maximized by choosing a switch with the smallest CDS as possible. The values of load resistance and capacitance also affect off isolation, as they contribute to the coefficients of the poles and zeros in the transfer function of the switch when open. s(RLOAD CDS ) A(s) = s(RLOAD ) (CLOAD + CD + CDS ) + 1
Figure 8. Switch Represented by Equivalent Parasitic Components
The transfer function that describes the equivalent diagram of the switch (Figure 8) is of the form (A)s shown below. s(RON CDS ) + 1 A(s) = RT s(RON CT RT ) + 1 where: CT = CLOAD + CD + CDS RT = RLOAD/(R LOAD + R ON)
0.122 (3.10) 0.114 (2.90)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
8
5
The signal transfer characteristic is dependent on the switch channel capacitance, CDS. This capacitance creates a frequency zero in the numerator of the transfer function A(s). Because the switch on resistance is small, this zero usually occurs at high frequencies. The bandwidth is a function of the switch output capacitance combined with CDS and the load capacitance. The frequency pole corresponding to these capacitances appears in the denominator of A(s). The dominant effect of the output capacitance, CD, causes the pole breakpoint frequency to occur first. Therefore, in order to maximize bandwidth a switch must have a low input and output capacitance and low on resistance. The On Response vs. Frequency plot for the ADG721/ADG722/ADG723 can be seen in Figure 7. -8-
1
4
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27
0.028 (0.71) 0.016 (0.41)
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PRINTED IN U.S.A.
0.199 (5.05) 0.187 (4.75)
C3294-8-4/98

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