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(R)
TDA7345
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
1 STEREO INPUT VOLUME CONTROL IN 1.25dB STEP TREBLE AND BASS CONTROL THREE SURROUND MODES ARE AVAILABLE: - MOVIE, MUSIC AND SIMULATED FOUR SPEAKER ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7345 is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in car radio and Hi-Fi systems. It reproduces surround sound by using phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor netPIN CONNECTION
SO28
ORDERING NUMBER: TDA7345D
works and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
CREF PS2 PS1 LP1 HP1 HP2 L-in BASS-LA BASS-LB TREBLE-L REC_OUT_L REC_OUT_R Lout Rout
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D94AU191A
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vs PS3 PS4 LP REAR IN REAR OUT R-in BASS-RA BASS-RB TREBLE-R DIG GND SDA SCL AGND
November 1999
1/18
BASS-LB
100nF 5.6K
100nF
BASS-RB
2/18
100nF 100nF 22nF 22nF 5.6K 100nF 100nF 5.6nF PS1 3 RPS1 SPKR ATT 11 PS1 90Hz PHASE SHIFTER SPKR ATT SIM MUSIC + MOVIE/ MUSIC OFF MOVIE/SIM 16 17 I2C BUS DECODER + LATCHES 18 SCL SDA DIG GND L-R MIXING AMP VOL BASS TREBLE MUTE 13 LOUT PS2 4KHz PS3 400Hz PS4 400Hz MUTE REC_OUT_L RPS2 RPS3 RPS4 RB 2 27 26 8 9 10 PS2 PS3 PS4 BASS-LA TREBLE(L) + MIXING AMP VOL BASS TREBLE SPKR ATT 14 ROUT MUTE LPF 9KHz EFFECT CONTROL SPKR ATT 12 RB 1 AGND REAR OUT C5 22F 1.2nF CREF LP 25 23 24 REAR IN 21 BASS-RA 20 19 TREBLE(R)
D94AU192A
TDA7345
BLOCK DIAGRAM
5.6nF
680nF
LP1
HP1
HP2
4
5
6
0.47F
RLP1 RHP1
7
L-in
50K
R5
R6
-
+
+
0.47F
22
R-in MUTE
REC_ OUT_R
50K
SUPPLY
28
15
VS
5.6nF
TDA7345
TEST CIRCUIT
5.6nF C15 100nF C14 100nF C13 22F C3 10F C1 100nF C2 22nF C4 22nF C5
LP1 HP1 680nF C16 0.47F HP2 L-in 4 5 3
PS1 2
PS2 1
CREF 28
VS 27
PS3 26 25
PS4 LP 1.2nF C6 REAR IN 2.2F REAR OUT R-in 0.47F C7
6
24
7
C17
23
C20 100nF BASS-LA C21 100nF BASS-LB R2 5.6K TREBLE-L 5.6nF C22
D94AU193A
TDA7345
8
22
C10 100nF 21 BASS-RA C11 100nF
9
20
BASS-RB R1 5.6K TREBLE-R 5.6nF C12
10 11 REC OUT L 12 REC OUT R 13 LOUT 14 ROUT AGND 15 16 SCL 17 SDA 18
19
DIG GND
THERMAL DATA
Symbol Rth j-pins Thermal Resistance Junction-pins Description Max. Value 85 Unit C/W
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 11 -10 to 85 -55 to +150 Unit V C C
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio V out = 1Vrms (made = OFF) Channel Separation f = 1KHz Volume Control 1.25dB step Treble Control (2db step) Bass Control (2db step) Balance Control 1.25dB step REC-OUT L & R Balance Control 1.25dB step (LOUT, ROUT) Mute Attenuation -78.75 -14 -14 -38.75 -78.75 90 Parameter Min. 7 2 Typ. 9 0.02 106 70 0 +14 +14 0 0 Max. 10.5 0.1 Unit V Vrms % dB dB dB dB dB dB dB dB
3/18
TDA7345
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all controls flat (G = 0),Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection LCH / RCH out, Mode = OFF 7 20 60 9 25 80 10.5 35 V mA dB
INPUT STAGE
RII VCL CRANGE AVMIN AVMAX ASTEP VDC Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution DC Steps adjacent att. step -1 18.68 0.11 -3 THD = 0.3%; Lin or Rin THD = 0.3%; Rin + Lin (2) 35 2 50 2.5 3.0 19.68 0 19.68 0.31 0 1 20.68 0.51 3 65 K Vrms Vrms dB dB dB dB mV
VOLUME CONTROL
CRANGE AVMIN AVMAX ASTEP EA ET VDC Control Range Min. Attenuation Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps Av = 0 to -40dB Av = 0 to -20dB Av = -20 to -60dB adjacent attenuation steps 70 -1 70 0.5 -1.5 -3 -3 75 0 75 1.25 0 1 1.75 1.5 2 2 3 dB dB dB dB dB dB dB mV
0
BASS CONTROL (1)
Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +11.5 1 32 +14.0 2 44 +16.0 3 56 dB dB K
TREBLE CONTROL (1)
Gt TSTEP Control Range Step Resolution Max. Boost/cut +13 1 +14 2 +15 3 dB dB
EFFECT CONTROL
CRANGE SSTEP Control Range Step Resolution - 21 0.5 1 -6 1.5 dB dB
4/18
TDA7345
ELECTRICAL CHARACTERISTICS (continued) SURROUND SOUND MATRIX
Symbol GOFF Parameter In-phase Gain (OFF) Test Condition Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout Lin Lout Mode OFF, Input signal of 1kHz, 1.4 Vp-p (Rin Rout), (Lin Lout) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p Rin Rout, Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p Rin Rout, Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p Rin Rout, Lin Lout Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Rout Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Rout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Rout 7.5 13.5 0.30 13.6 13.6 45 7.5 Min. -1.5 Typ. 0 Max. 1.5 Unit dB
DGOFF
LR In-phase Gain Difference (OFF) In-phase Gain (Movie 1)
-1.5
0
1.5
dB
GMOV1
7
dB
GMOV2
In-phase Gain (Movie 2)
8
dB
DGMOV
LR In-phase Gain Diffrence (Movie) In-phase Gain (Music 1)
0
dB
GMUS1
6
dB
GMUS2
In-phase Gain (Music 2)
7.5
dB
DGMUS
LR In-phase Gain Difference (Music) Simulated L Output 1
0
dB
LMON1
4.5
dB
LMON2
Simulated L Output 2
- 4.0
dB
LMON3
Simulated L Output 3
7.0
dB
RMON1
Simulated R Output 1
- 4.5
dB
RMON2
Simulated R Output 2
3.8
dB
RMON3
Simulated R Output 3
- 20
dB
RLP1 RPS1 RPS2 RPS3 RPS2 RHPI RLPF
Low Pass Filter Resistance Phase Shifter 1 Resistance Phase Shifter 2 Resistance Phase Shifter 3 Resistance Phase Shifter 4 Resistance High Pass Filter Resistance LP Pin Impedance
10 17.95 0.40 18.08 18.08 60 10
12.5 22.5 0.50 22.6 22.6 75 12.5
K k K K K K K
5/18
TDA7345
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SPEAKER ATTENUATORS (REC_OUT_L, REC_OUT_R)
Crange SSTEP EA AMUTE VDC Control Range Step Resolution Attenuation set error Output Mute Attenuation DC Steps adjacent att. steps 35 0.5 -1.5 80 -3 90 0 37.5 1.25 40 1.75 1.5 3 dB dB dB dB mV
SPEAKER ATTENUATORS (LOUT, ROUT)
Crange SSTEP EA VDC AMUTE Control Range Step Resolution Attenuation set error DC Steps Output Mute Attenuation Av = 0 to -40dB Av = 0 to 20dB Av = -20 to -60dB adjacent att. steps 70 0.5 -1.5 -3 -3 80 75 1.25 0 0 0 90 1.75 1.5 2 3 dB dB dB dB mV dB
AUDIO OUTPUTS (LOUT, ROUT, REC_OUT_L, REC_OUT_R)
VOCL ROUT VOUT Clipping Level Output resistance DC Voltage Level d = 0.3% 2 100 4.2 2.5 200 4.5 300 4.8 Vrms V
GENERAL
NO(OFF) Output Noise (OFF) BW = 20Hz to 20KHz Output LOUT, ROUT, Output: REC-OUT-L, REC-OUT-R Mode =Movie , BW = 20Hz to 20KHz Rout and Lout measurement Mode = Music , BW = 20Hz to 20KHz, Rout and Lout measurement Mode = Simulated, BW = 20Hz to 20KHz Rout and Lout measurement Av = 0 ; Vin = 1Vrms 60 8 8 30 15 15 Vrms Vrms Vrms Vrms Vrms
NO(MOV)
Output Noise (Movie)
NO(MUS)
Output Noise (Music)
30
NO(MON)
Output Noise (Simulated)
30
d SC
Distorsion Channel Separation
0.02 70
0.1
% dB
BUS INPUTS
VIL VIH IIN VO
Note: (1) Bass and Treble response: The center frequency and the resonance quality can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network. (2) The peack voltage of the two input signals must be less then (Lin + Rin) peak * AVin < VS 2 VS : 2
Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA
1 3 -5 0.4 +5 0.8
V V A V
6/18
TDA7345
I C BUS INTERFACE Data transmission from microprocessor to the TDA7345 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS
2
knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
7/18
TDA7345
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7345 address (the 8th bit of the byte must be 0). The TDA7345 must always acknowledge at the end of each transmitted byte. A subaddress (function) bytes (identified by the MSB = 0) A sequence of dates and subaddresses (N bytes + achnowledge. The dates are identified by MSB = 1, subaddresses by MSB = 0) A stop condition (P)
TDA7345 ADDRESS MSB S 1 0 0 0 0 0 1 LSB 0 ACK MSB DATA LSB ACK MSB DATA LSB ACK S
D94AU194
Data Transferred (N-bytes + Acknowledge)
ACK = Achnowledge S = Start P = Stop INTERFACE FEATURES - Due to the fact that the MSB is used to select if the byte transmitted is a subaddress (function) or a data (value), between a start and stop condition, is possible to receive, how many subaddresses and datas as wanted. - The subaddress (function) is fixed until a new subaddress is transmitted, so the TDA7345 can receive how many data as wanted for the selected subaddress (without the need for a new start condition) - If TDA7345 receives a subaddress with the LSB = 1 the incremental bus is selected, so it enters in a loop condition that means that every acknowledge will increase automatically the subaddress (function) and it receives the data related to the new subaddress. EXAMPLES chip address, a subaddress with the LSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a new subaddress, N-data, a stop condition. So it can receive in a single transmission how many subaddress are necessary, and for each subaddress how many data are necessary. 2) INCREMENTAL BUS TDA7345 receives a start condition, the correct chip address a subaddress with the LSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress. The first data that it receives doesn't concern the subaddress sended but the next one, the second one concerns the subaddress sended plus two in the loop etc, and at the end it receives the stop condition. In the pictures there are some examples:
S = start ACK = acknowledge 1) NO INCREMENTAL BUS B = 1 incremental bus, B = 0 no incremental bus TDA7345 receives a start condition, the correct P = stop 1) one subaddress, with n data concerning that subaddress (no incremental bus)
CHIP ADDRESS MSB S 1 0 0 0 0 0 1 LSB 0 ACK MSB
SUBADDRESS LSB X 0 ACK MSB 1
DATA 1 ... DATA n LSB DATA ACK P
0 A0 A1 A2 A3 X
D94AU195
8/18
TDA7345
2) one subaddress, (with incremental bus) , with n data (data1 that concerns subaddress +1, data 2 that concerns subaddress + 2 etc.)
CHIP ADDRESS MSB S 1 0 0 0 0 0 1 LSB 0 ACK MSB
SUBADDRESS LSB X 1 ACK MSB 1
DATA 1 ... DATA n LSB DATA ACK P
0 A0 A1 A2 A3 X
D94AU196
3) more subaddress with more data
CHIP ADDRESS MSB S 1 0 0 0 0 0 1 LSB 0 ACK MSB
SUBADDRESS LSB X 0 ACK MSB 1
DATA 1 ... DATA n LSB DATA ACK MSB
SUBADDRESS LSB X 0 ACK MSB 1
DATA 1 ... DATA n LSB DATA ACK 1
0 A0 A1 A2 A3 X
0 A0 A1 A2 A3 X
D94AU197
DATA BYTES FUNCTION SELECTION FIRST BYTE (subaddress) The first byte select the function, it is identified by the MSB = 0
MSB A0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 A1 0 0 1 1 0 0 1 1 1 A2 0 0 0 0 1 1 1 1 1 A3 X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X LSB B B B B B B B B B B VOLUME ATTENUATION & LOUDNESS SURROUND & OUT & EFFECT CONTROL BASS TREBLE REC-OUT-R REC-OUT-L ROUT LOUT INPUT STAGE CONTROL SUBADDRESS
B = 1 yes incremental bus; B = 0 no incremental bus; X = indifferent 0,1
9/18
TDA7345
VALUE SELECTION The second byte select the value, it is identified by the MSB = 1
VOLUME ATTENUATION MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 1.25 dB STEPS 0 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75 10 dB STEPS 0 -10 -20 -30 -40 -50 -60 -70
ATT SPEAKER L AND R MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 1.25 dB STEPS 0 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75 10 dB STEPS 0 -10 -20 -30 -40 -50 -60 -70 MUTE OFF ON
10/18
TDA7345
ATT REC-OUT L AND R MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 1.25 dB STEPS 0 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75 10 dB STEPS 0 -10 -20 -30 MUTE
TREBLE/ BASS MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 LSB 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 2 dB STEPS 14 12 10 8 6 4 2 0 0 -2 -4 -6 -8 -10 -12 -14
11/18
TDA7345
SURROUND & OUT & EFFECT CONTROL MSB SELECTION 1 1 1 1 SELECTION 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 MUSIC MOVIE OFF EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 LSB SELECTION SURROUND SIMULATED
For example to select the music mode, out fix, effect control =-9dB: 10011101
12/18
TDA7345
INPUT CONTROL RANGE (0 TO -19.68dB) MSB 1 1 1 1 1 1 1 1 X Xx X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 0.3125 dB STEPS 0 -0.3125 -0.625 -0.9375 -1.25 -1.5625 -1.875 -2.1875 2.5 dB STEPS 1 1 1 1 1 1 1 1 X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -2.5 -5.0 -7.5 -10 -12.5 -15 -17.5
POWER ON RESET VOLUME ATTENUATION TREBLE BASS SURROUND + EFFECT CONTROL ATT SPEAKER R ATT SPEAKER L ATT REC-OUT L ATT REC-OUT R MAX ATTENUATION, -14dB -14dB OFF + MAX ATTENUATION MUTE MUTE MUTE MUTE
13/18
TDA7345
PIN: HP1 PIN: HP2
LP1
VS 10K
VS 20A 5.5K
60K GND
D94AU198
60K GND
D94AU199
HP2
HP1
5.5K
PIN: Lin, Rin
PIN: BASS - LA, BASS - RA
VS
VS
20A
20A
50K GND
BASS-LB BASS-RB GND 48K
VREF
D94AU200
D94AU201
PIN: BASS - LB, BASS - RB
PIN: TREBLE - L, TREBLE - R
VS 20A
VS 20A
GND BASS-LA BASS-RA
48K
25K
D94AU202
D94AU203
14/18
TDA7345
PIN: LOUT, ROUT, REC-OUT-1 REC-OUT-R PIN: SCL, SDA
VS 20A 100
20A
D94AU204
D94AU205
PIN: LP
VS 20A
PIN: PS3, PS2
VS 20A
10K
18.08K PS3A
GND
PS4A
D94AU206
D94AU207
PIN: CREF
PIN: PS2
VS
VS
20A
50K
20A
398
50K
D94AU208
PS2A
D94AU209
15/18
TDA7345
PIN: PS1
VS 20A
PIN: LP1
VS 20A
17.95K
PS1A
10K HP1
D94AU210
D94AU211
PIN: REAR OUT
PIN: REAR IN
VS 20A
VS 20A 20K
20K
D94AU214
D94AU215
16/18
TDA7345
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
17/18
TDA7345
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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