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CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
The CX28394/28395/28398 is a family of multiple framers for T1/E1/J1 and Integrated Service Digital Network (ISDN) primary rate interfaces operating at 1.544 Mbps or 2.048 Mbps. All framers are totally independent, and each combines a sophisticated framing synchronizer and transmit/receive slip buffers. Operations are controlled through a series of memory-mapped registers accessible via a parallel microprocessor port. Extensive register support is provided for alarm and error monitoring, signaling supervision (including ISDN D-channel/SS7 process), per-channel trunk conditioning, and Facility Data Link (FDL) maintenance. A flexible serial Time Division Multiplexed (TDM) system interface that supports bus rates from 1.536 to 8.192 MHz is featured. Extensive test and diagnostic functions include a full set of loopbacks, Pseudo Random Bit Sequence (PRBS) test pattern generation, Bit Error Rate (BER) meter, and forced error insertion.
Distinguishing Features
* * * * Up to 16 T1/E1/J1 Framers in one package Extensive support of various protocols T1: SF, ESF, SLC(R)96, T1DM, TTC JT(J1) E1: PCM-30, G.704, G.706, G.732, ISDN primary rate (ETS300 011, INS 500) Extracts and inserts signaling bits Dual HDLC controllers per framer for data link and LAPD/SS7 signaling Two-frame transmit and receive PCM slip buffers Separate or multiplexed system bus interfaces Parallel 8-bit microprocessor port supports Intel or Motorola buses BERT generation and counting B8ZS/HDB3/Bit 7 zero suppression (CX28394 and CX28398 only) Operates from a single +3.3 Vdc 5% power supply Low-power CMOS technology
* * *
Functional Block Diagram
*
Receive Dual Rail or NRZ RX Slip Buffer Receive System Bus
* * * * *
ZCS* Decode
T1/E1 Receive Framer
Receive Dual Rail or NRZ
ZCS* Encode Overhead Insertion
TX Slip Buffer T1/E1 Transmit Framer
Transmit System Bus
Applications * Multiline T1/E1 Channel Service Unit/Data Service Unit (CSU/DSU) Digital Access Cross-Connect System (DACS) T1/E1 Multiplexer (MUX) PBXs and PCM channel bank ISDN Primary Rate Access (PRA) Frame Relay Switches and Access Devices (FRADS) SONET/SDH add/drop multiplexers T3/E3 channelized access concentrators
Data Link Controllers DL1+DL2
* * * * * * *
. . .
Framer #1
External Data Link DL3*
Framer #N Control/Status Registers Framer #N
8394-8-5_019
JTAG
Test Port * CX28394 and CX28398 only.
Motorola/Intel Processor Bus
CX28394 - 4 Frames CX28398 - 8 Frames CX28395 - 16 Frames
Data Sheet
100054E June 2000
CX28398EVM--Evaluation Module, Octal T1/E1 ISDN PRI Board
T1 or E1 Connection at DSX Levels
Quad T1/E1 LIU (CX28380) Address Bus 12 Microprocessor Data Bus 8
Quad T1/E1 LIU (CX28380)
CX28398 (Octal T1/E1 Framer)
Local PCM Highway (i.e., 2 @ 8192 kbps)
8394-8-5_012
(c) 1999, 2000, Conexant Systems, Inc.
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100054E
Conexant
Typical Quad T1/E1 Application
T1 or E1 Connection at DSX Levels
CX28380 (Quad LIU) Address Bus 12 Microprocessor Data Bus 8 CX28394 (Octal T1/E1 Framer)
Local PCM Highway (8192 kbps)
8394-8-5_015
Typical x16 T1/E1 Application
T1 or E1 Line Interfaces, SONET/SDH Mapper or M13/E13 Mux
Address Bus 12 Microprocessor Data Bus 8 2 Chip Selects 2 CX28395 ( x16 T1/E1 Framer) CX28395 ( x16 T1/E1 Framer)
Local PCM Highways 32 at 1536 kbps to 8 at 8192 kbps)
8394-8-5_014
Ordering Information
Model Number CX28394-22 CX28398-22 CX28398-23 CX28395-19 CX28395-18 CX28398-24 BT00-D660-001 Number of Framers 4 8 8 16 16 8 Package 128-pin TQFP 208-pin PQFP 272-pin BGA 318-pin BGA 318-pin BGA 208-pin CABGA CX28398/CX28380 Evaluation Module Operating Temperature -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C 0 to 70 C -40 to 85 C
100054E
Conexant
Detailed Feature Summary
Frame Alignment * Framed formats: - Independent transmit and receive framing modes - T1: FT/SF/ESF/SLC/T1DM/TTC-JT(J1) - E1: FAS/MFAS/FAS+CAS/MFAS+CAS Maximum Average Reframe Time (MART) less than 50 ms Transmitter alignment modes: - Align to system bus data - Align to system bus sync - Align to buffer data (embedded framing) Unframed mode Out-of-Service Testing and Maintenance * Pseudo-Random Bit Sequence (PRBS): - Independent transmit and receive - 211; 215; 220; 223 patterns - Framed or unframed mode - Optional 7/14 zero limit - Bit Error Counter (BERR) Single error insertion: - PRBS error - Framing error - CRC error - BPV/LCV error (CX28394 and CX28398 only) - COFA error In-Service Performance Monitoring * * One-second timer I/O to synchronize reporting Receive error detectors with accumulators: - Bipolar/Line Code Violations (LCV) (CX28394 and CX28398 only) - Excessive Zeros (EXZ) - Loss of Frame (RLOF) - Framing Errors (FERR) - CRC Errors (CERR) - Far End Block Errors (FEBE) - Severely Errored Frames (SEF) - Change of Frame Alignment (COFA) Transmit error detectors: - Loss of Frame (TLOF) - Framing Errors (TFERR) - Multiframe Errors (TMERR) - CRC Errors (TCERR) - Loss of Transmit Clock (TLOC) Receive alarm detectors: - Alarm Indication Signal (AIS) - Loss of Signal (RLOS) - RAI/Yellow Alarm (YEL) - Multiframe Yellow (MYEL) - Lost Frame Alignment (FRED) - Lost Multiframe Alignment (MRED) - Carrier Failure Alarm (CFA) with 8:1 dual slope integration Controlled Frame Slip (RFSLIP) Uncontrolled Frame Slip (RUSLIP) Automatic and on-demand transmit alarms: - AIS following RLOS and/or TLOC - Automatic AIS clock switching - YEL following FRED - YEL following 100ms reframe timeout - MYEL following MRED - FEBE following CERR
* *
*
*
Signaling * * * * * * * * * * * T1: 2-, 4-, or 16-state robbed bit ABCD signaling E1: Channel Associated Signaling (CAS) Common Channel Signaling (CCS) in any time slot Per-channel receive signaling stack Signaling state change interrupt Automatic and manual signaling freeze Debounce signaling (2-bit integration) UNICODE detection Signaling reinsertion on PCM system bus Separate I/O for system bus signaling Per-channel transparent
System Bus Interface (SBI) * System bus data rates: - 1536 kbps (T1 without F-bits) - 1544 kbps (T1) - 2048 kbps (E1) - 4096 kbps (2E1) - 8192 kbps (4E1) Clock operation at 1x or 2x data rate Selectable I/O clock edges Master, slave, or mixed bus timing Bit and time slot frame sync offsets DS0 drop/insert indicators for external mux Embedded T1 framing transport per G.802 Receive and transmit slip buffers - Bypass, 2-frame, or 64-bit depth - Slip detection with directional status - Slip buffer phase status - Per-channel idle code insertion - Processor accessible data buffers Direct connection to upper layer devices: - Link layer: Bt8474 - ATM layer: CN8228 Direct connection to physical line interface - CX28380 Supported system bus formats: - ATT Concentration Highway Interface (CHI) - Multi-Vendor Integration Protocol (MVIP) - Mitel ST-bus Separate or internally multiplexed bus modes
*
*
* * * * * * *
* *
Loopbacks * Remote loopback toward line - Retains BPV transparency (CX28394 and CX28398 only) Payload loopback Per-channel DS0 remote loopback Local loopback towards system - Framer digital loopback - Per-channel DS0 local loopback Inband loopback code detection/ generation Simultaneous local and remote line loopbacks
* * *
*
* *
*
*
Processor Interface * * * * * Parallel 8-bit bus Data strobes (Motorola) or address latch enable (Intel) Multiplexed or non-multiplexed address/data bus Synchronous or asynchronous data transfers Open drain interrupt output with maskable sources
*
100054E
Conexant
Data Links * Two full-featured data link controllers (DL1 and DL2): - 64-octet transmit and receive FIFOs - HDLC Message Oriented Protocol (MOP) - Unformatted data transfer - Unformatted circular buffer - End of message/buffer interrupt - Near full/empty interrupts at selected depth Access any bit combination in any time slot: - ISDN D-channels at 16, 32, or 64 kbps - National/spare bits (SA-bits) in 4 kbps increments - CCS/SS7 - T1DM R-bits Access T1 F-bits in even, odd, or all frames: - Automatic Performance Report Message (PRM) generator - ESF Facility Data Link (FDL) - Unformatted SLC-96 overhead - Bit-Oriented Protocol (BOP) priority codeword generation and detection Separate I/O for external data link (DL3) on CX28394 and CX28398 devices
*
*
*
100054E
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100054E
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Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii 1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 1.1.2 1.1.3 1.1.4 1.2 External Datalink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 RINDO/TINDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 LIU Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Transmit/Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2.0
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.1 2.2.2 2.2.3 ZCS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 In-Band Loopback Code Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3.1 Frame Bit Error Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.3.2 CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.3.3 LCV Error Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.3.4 FEBE Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Error Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4.1 Frame Bit Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4.2 MFAS Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.4.3 CAS Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.4.4 CRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.4.5 Pulse Density Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.4
100054E
Conexant
vii
Table of Contents
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.2.5
2.2.6 2.2.7 2.2.8 2.2.9 2.2.10
Alarm Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.5.1 Loss of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5.2 Loss of Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5.3 Receive Analog Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5.4 Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5.5 Yellow Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5.6 Multiframe YEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.5.7 Severely Errored Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.5.8 Change of Frame Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.5.9 Receive Multiframe AIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Test Pattern Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Receive Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 External Receive Data Link (CX28394 and CX28398 Only) . . . . . . . . . . . . . . . . . . . . . . . 2-15 Sa-Byte Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Receive Data Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.10.1 Data Link Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.10.2 RBOP Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Non-Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Externally Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Internally Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Receive System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.4.1 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.3.4.2 Slip Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.3.4.3 Signaling Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.3.4.4 Signaling Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.3.4.5 Embedded Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 Transmit System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.3.5.1 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 2.3.5.2 Slip Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 2.3.5.3 Signaling Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2.3.5.4 Transmit Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2.3.5.5 Embedded Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 External Transmit Data Link (CX28394 and CX28398 Only) . . . . . . . . . . . . . . . . . . . . . . 2-41 Transmit Data Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.4.2.1 Data Link Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.4.2.2 Circular Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.4.2.3 Time Slot and Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.4.2.4 Transmit Data Link FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.4.2.5 End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.4.2.6 Programming the Data Link Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 2.4.2.7 PRM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 2.4.2.8 TBOP Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.3
System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.1 2.3.2 2.3.3 2.3.4
2.3.5
2.4
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.4.1 2.4.2
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100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers 2.4.3 2.4.4
Table of Contents
2.4.5 2.4.6 2.4.7 2.4.8 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.7 2.8
Sa-Byte Overwrite Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 Overhead Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.4.4.1 Framing Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.4.4.2 Alarm Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.4.4.3 CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.4.4.4 Far-End Block Error Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Transmit Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 In-Band Loopback Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 ZCS Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 Address/Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
2-56 2-56 2-56 2-58
Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 Remote Line Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 Remote Payload Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 Remote Per-Channel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 Local Framer Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60 Local Per-Channel Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 Joint Test Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 2.8.1 2.8.2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
3.0
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 3.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Global Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 000--Device Identification (DID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 080--Framer Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 081--Master Interrupt Request (MIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 082--Master Interrupt Enable (MIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 083--Test Configuration (TEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3 3.4 Primary Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 001--Primary Control Register (CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 003--Interrupt Request Register (IRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
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3.5
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 004--Alarm 1 Interrupt Status (ISR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 005--Alarm 2 Interrupt Status (ISR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 006--Error Interrupt Status (ISR5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 007--Counter Overflow Interrupt Status (ISR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 008--Timer Interrupt Status (ISR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 009--Data Link 1 Interrupt Status (ISR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 00A--Data Link 2 Interrupt Status (ISR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 00B--Pattern Interrupt Status (ISR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.6
Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 00C--Alarm 1 Interrupt Enable Register (IER7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 00D--Alarm 2 Interrupt Enable Register (IER6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 00E--Error Interrupt Enable Register (IER5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 00F--Count Overflow Interrupt Enable Register (IER4) . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 010--Timer Interrupt Enable Register (IER3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 011--Data Link 1 Interrupt Enable Register (IER2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 012--Data Link 2 Interrupt Enable Register (IER1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 013--Pattern Interrupt Enable Register (IER0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.7
Primary Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 014--Loopback Configuration Register (LOOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 015--External Data Link Time Slot (DL3_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 016--External Data Link Bit (DL3_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 017--Offline Framer Status (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 018--Programmable Input/Output (PIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 019--Programmable Output Enable (POE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 01A--Clock Input Mux (CMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 020--Receive Alarm Configuration (RAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 021--Receive Line Code Status (RSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.8
Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 022--Serial Control (SER_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 023--Serial Data (SER_DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 024--Serial Status (SER_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 025--Serial Configuration (SER_CONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 026--RAM Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-36 3-36 3-36 3-37 3-37 3-38 3-39 3-40 3-41 3-41 3-42 3-44 3-45 3-47 3-48
3.9
Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 040--Receiver Configuration (RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 041--Receive Test Pattern Configuration (RPATT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 042--Receive Loopback Code Detector Configuration (RLB) . . . . . . . . . . . . . . . . . . . . . 043--Loopback Activate Code Pattern (LBA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 044--Loopback Deactivate Code Pattern (LBD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 045--Receive Alarm Signal Configuration (RALM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 046--Alarm/Error/Counter Latch Configuration (LATCH) . . . . . . . . . . . . . . . . . . . . . . . . 047--Alarm 1 Status (ALM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 048--Alarm 2 Status (ALM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 049--Alarm 3 Status (ALM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.10 Performance Monitoring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 050--Framing Bit Error Counter LSB (FERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 051--Framing Bit Error Counter MSB (FERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 052--CRC Error Counter LSB (CERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 053--CRC Error Counter MSB (CERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 054--Line Code Violation Counter LSB (LCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 055--Line Code Violation Counter MSB (LCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 056--Far End Block Error Counter LSB (FEBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 057--Far End Block Error Counter MSB (FEBE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 058--PRBS Bit Error Counter LSB (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 059--PRBS Bit Error Counter MSB (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 05A--SEF/FRED/COFA Alarm Counter (AERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 3.11 Receive Sa-Byte Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 05B--Receive Sa4 Byte Buffer (RSA4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 05C--Receive Sa5 Byte Buffer (RSA5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 05D--Receive Sa6 Byte Buffer (RSA6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 05E--Receive Sa7 Byte Buffer (RSA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 05F--Receive Sa8 Byte Buffer (RSA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 070--Transmit Framer Configuration (TCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 071--Transmitter Configuration (TCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 072--Transmit Frame Format (TFRM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 073--Transmit Error Insert (TERROR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 074--Transmit Manual Sa-Byte/FEBE Configuration (TMAN) . . . . . . . . . . . . . . . . . . . . . 076--Transmit Test Pattern Configuration (TPATT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 077--Transmit Inband Loopback Code Configuration (TLB). . . . . . . . . . . . . . . . . . . . . . 078--Transmit Inband Loopback Code Pattern (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . 07B--Transmit Sa4 Byte Buffer (TSA4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 07C--Transmit Sa5 Byte Buffer (TSA5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 07D--Transmit Sa6 Byte Buffer (TSA6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 07E--Transmit Sa7 Byte Buffer (TSA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 07F--Transmit Sa8 Byte Buffer (TSA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-52 3-52 3-53 3-53 3-54 3-55 3-59 3-61 3-62 3-63 3-65 3-66 3-67 3-68 3-68 3-69 3-69 3-70
3.12 Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
3.13 Transmit Sa-Byte Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
3.14 Bit-Oriented Protocol Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 0A0--Bit Oriented Protocol Transceiver (BOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 0A1--Transmit BOP Codeword (TBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 0A2--Receive BOP Codeword (RBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 0A3--BOP Status (BOP_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
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3.15 Data Link Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 0A4--DL1 Time Slot Enable (DL1_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 0A5--DL1 Bit Enable (DL1_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76 0A6--DL1 Control (DL1_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76 0A7--RDL #1 FIFO Fill Control (RDL1_FFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 0A8--Receive Data Link FIFO #1 (RDL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79 0A9--RDL #1 Status (RDL1_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80 0AA--Performance Report Message (PRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81 0AB--TDL #1 FIFO Empty Control (TDL1_FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82 0AC--TDL #1 End Of Message Control (TDL1_EOM). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 0AD--Transmit Data Link FIFO #1 (TDL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 0AE--TDL #1 Status (TDL1_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 0AF--DL2 Time Slot Enable (DL2_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84 0B0--DL2 Bit Enable (DL2_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85 0B1--DL2 Control (DL2_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85 0B2--RDL #2 FIFO Fill Control (RDL2_FFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87 0B3--Receive Data Link FIFO #2 (RDL2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88 0B4--RDL #2 Status (RDL2_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 0B6--TDL #2 FIFO Empty Control (TDL2_FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90 0B7--TDL #2 End Of Message Control (TDL2_EOM). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90 0B8--Transmit Data Link FIFO #2 (TDL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91 0B9--TDL #2 Status (TDL2_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91 0BA--DLINK Test Configuration (DL_TEST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92 0BB--DLINK Test Status (DL_TEST2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92 0BC--DLINK Test Status (DL_TEST3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92 0BD--DLINK Test Control #1 or Configuration #2 (DL_TEST4) . . . . . . . . . . . . . . . . . . . 3-92 0BE--DLINK Test Control #2 or Configuration #2 (DL_TEST5). . . . . . . . . . . . . . . . . . . . 3-93 3.16 System Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94 0D0--System Bus Interface Configuration (SBI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94 0D1--Receive System Bus Configuration (RSB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96 0D2--RSB Sync Bit Offset (RSYNC_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97 0D3--RSB Sync Time Slot Offset (RSYNC_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98 0D4--Transmit System Bus Configuration (TSB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99 0D5--TSB Sync Bit Offset (TSYNC_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100 0D6--TSB Sync Time Slot Offset (TSYNC_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101 0D7--Receive Signaling Configuration (RSIG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102 0D8--Signaling Reinsertion Frame Offset (RSYNC_FRM) . . . . . . . . . . . . . . . . . . . . . . 3-104 0D9--Slip Buffer Status (SSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105 0DA--Receive Signaling Stack (STACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107 0DB--RSLIP Phase Status (RPHASE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108 0DC--TSLIP Phase Status (TPHASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108 0DD--RAM Parity Status (PERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109 0E0-0FF--System Bus Per-Channel Control (SBCn; n = 0 to 31) . . . . . . . . . . . . . . . . . 3-109 100-11F--Transmit Per-Channel Control (TPCn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . 3-110 120-13F--Transmit Signaling Buffer (TSIGn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . . . . 3-112
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140-15F--Transmit PCM Slip Buffer (TSLIP_LOn; n = 0 to 31) . . . . . . . . . . . . . . . . . . 3-112 160-17F--Transmit PCM Slip Buffer (TSLIP_HIn; n = 0 to 31). . . . . . . . . . . . . . . . . . . 3-113 180-19F--Receive Per-Channel Control (RPCn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . . 3-113 1A0-1BF--Receive Signaling Buffer (RSIGn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . . . . 3-115 1C0-1DF--Receive PCM Slip Buffer (RSLIP_LOn; n = 0 to 31) . . . . . . . . . . . . . . . . . . 3-115 1E0-1FF--Receive PCM Slip Buffer (RSLIP_HIn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . 3-116 3.17 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117
4.0
Electrical/Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 MPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 System Bus Interface (SBI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 A.2 A.3 A.4 A.5 A.6 Superframe Format (SF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 T1DM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 SLC 96 Format (SLC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Extended Superframe Format (ESF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 E1 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 IRSM CEPT Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Appendix C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1 System Bus Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C.1.1 C.1.2 AT&T Concentration Highway Interface (CHI): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 CHI Programming Options:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Appendix D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
D.1 D.2 Notation and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.1 Arithmetic Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Acronyms and Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
Appendix E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
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List of Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 2-17. Figure 2-18. Figure 2-19. Figure 2-20. Figure 2-21. Figure 2-22. Figure 2-23. Figure 2-24. Figure 2-25. Figure 2-26. Figure 2-27. CX28395 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 CX28394 128-pin TQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 CX28395 318-pin BGA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 CX28398 208-pin PQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 CX28398 208-pin CABGA Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 CX28398 272-pin BGA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 CX28394 Logic Diagram (Non-Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 1-25 CX28394 Logic Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . . . . . 1-26 CX28398 Logic Diagram (Non-Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 1-27 CX28398 Logic Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . . . . . 1-28 CX28395 Logic Diagram (Non-Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 1-29 CX28395 Logic Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Detailed Framer Block Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 2-2 Detailed Framer Block Diagram (Non-multiplexed System Bus Mode) . . . . . . . . . . . . . . . . 2-3 RCVR Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Receive External Data Link Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Polled Receive Data Link Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Interrupt-Driven Receive Data Link Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Externally Multiplexed Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Internally Multiplexed Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 RSB Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 RSB 4096K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 RSB 8192K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 RSB Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 T1 Line to E1 System Bus Time Slot Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 G.802 Embedded Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 TSB Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 Transmit System Bus Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 TSB 4096K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 TSB 8192K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Transmit Framing and Timebase Alignment Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 XMTR Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 Transmit External Data Link Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 Polled Transmit Data Link Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 Interrupt-Driven Transmit Data Link Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 Zero Code Substitution Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 NRZ Mode Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54 Microprocessor Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
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Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-28. Figure 2-29. Figure 2-30. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. Figure 4-18. Figure 4-19. Figure 4-20. Figure 4-21. Figure 4-22. Figure 4-23. Figure 4-24. Figure 4-25. Figure 4-26. Figure 4-27. Figure A-1. Figure A-2. Figure A-3.
Interrupt Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 Test Access Port (TAP) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Minimum Clock Pulse Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Input Data Setup/Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Output Data Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 One-Second Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Motorola Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Motorola Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Intel Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Intel Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Motorola Synchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Motorola Synchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Intel Synchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Intel Synchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Serial Control Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Serial Control Port Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Serial Control Port Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 SBI Timing--1536K Mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 SBI Timing--1544K Mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 SBI Timing--2048K Mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 SBI Timing--4096K Mode(1),(5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 SBI Timing--8192K Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 SBI Timing--Eight Clock Edge Combinations (Applicable to Any SBI Mode) . . . . . . . . . . 4-23 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 318-Pin Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 272-Pin Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 208-Pin Ball Grid Array (CABGA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 208-Pin Plastic Quad Flat Pack (PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 128-Pin (TQFP) Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 T1 Superframe PCM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 T1 Extended Superframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 E1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
xvi
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
List of Tables
List of Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 3-20. Table 3-21. Table 3-22. Pin Assignments (SBI1, SBI2, SBI3, SBI4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Pin Assignments (SBI5, SBI6, SBI7, SBI8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Pin Assignments (SBI9, SBI10, SBI11, SBI12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Pin Assignments (SBI13, SBI14, SBI15, SBI16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Receive Framer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Criteria for Loss/Recovery of Receive Framer Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Commonly Used Data Link Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 RSB Interface Time Slot Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Commonly Used Data Link Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 Yellow Alarm Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 Microprocessor Interface Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 CX28394 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 CX28395 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 CX28398 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Address Offset Map (CX28394). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Address Offset Map (CX28398). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Address Offset Map (CX28395). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Receive Framer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Interrupt Status Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Counter Overflow Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Maximum Average Reframe Time (MART) and Framer Timeout . . . . . . . . . . . . . . . . . . . . . 3-30 System Bus Sync Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Common TFSYNC and TMSYNC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Common RFSYNC and RMSYNC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 Receive PRBS Test Pattern Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 Receive Yellow Alarm Set/Clear Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 Receive Yellow Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 E1 Transmit Framer Modes (T1/E1N = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56 T1 Transmit Framer Modes (T1/E1N = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 Criteria for E1 Loss/Recovery of Transmit Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . . 3-57 Criteria for T1 Loss/Recovery of Transmit Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . . 3-58 Transmit Framer Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 Transmit Zero Code Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60 Transmit PRBS Test Pattern Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66 DLI Configuration for T1-ESF, FDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
100054E
Conexant
xvii
List of Tables
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-23. Table 3-24. Table 3-25. Table 3-26. Table 3-27. Table 3-28. Table 3-29. Table 3-30. Table 3-31. Table 3-32. Table 3-33. Table 3-34. Table 3-35. Table 3-36. Table 3-37. Table 3-38. Table 3-39. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 4-14. Table 4-15. Table 4-16. Table 4-17. Table 4-18. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table B-1. Table E-1.
Remote DS0 Channel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111 Signaling Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111 Global Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117 Primary Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118 Interrupt Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118 Primary Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119 Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119 Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120 Performance Monitoring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121 Receive Sa-Byte Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121 Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122 Transmit Sa-Byte Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122 Bit-Oriented Protocol Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123 Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123 System Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-124 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Input Data Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Output Data Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 One-Second Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Motorola Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Motorola Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Intel Asynchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Intel Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Motorola Synchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Motorola Synchronous Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Intel Synchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Intel Synchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Host Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Test and Diagnostic Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Test and Diagnostic Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Superframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 T1DM Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 SLC-96 Fs Bit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Extended Superframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Performance Report Message Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 ITU-T CEPT Frame Format Time Slot 0 Bit Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 IRSM CEPT Frame Format Time Slot 0 Bit Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 CEPT (ITU-T and IRSM) Frame Format Time Slot 16 Bit Allocations . . . . . . . . . . . . . . . . . A-11 Applicable Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
xviii
Conexant
100054E
1
1.0 Product Description
1.1 Overview
The CX2839x devices each contain multiple T1/E1 framers which provide the data access and framing portion of T1 and E1 physical layer interfaces: Device CX28394 CX28398 CX28395 Number of Framers 4 8 16
While the framers are identical, there are minor differences among the devices due to the pins provided. These differences are summarized below.
1.1.1 External Datalink
The CX28394 and CX28398 devices include an External Datalink (DL3) which provides signal access to any bit(s) in any time slot of all frames, odd frames, or even frames, including T1 framing bits. Refer to Section 2.2.8, External Receive Data Link (CX28394 and CX28398 Only), and 2.4.1, External Transmit Data Link (CX28394 and CX28398 Only). The DL3 signals are not available on the CX28395 device.
1.1.2 RINDO/TINDO
Receive and Transmit Time Slot Indicator signals are provided by each framer to mark selected (programmable) receive and transmit system bus time slots. On the CX28394 and CX28398 devices, these signals appear on different pins depending on whether Multiplexed System Bus mode or Non-Multiplexed System Bus mode is selected. On the CX28395, they are available only in Multiplexed Bus mode.
100054E
Conexant
1-1
1.0 Product Description
1.1 Overview
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
1.1.3 LIU Serial Port
The CX28394 and CX28398 devices include a serial interface which allows a microprocessor to indirectly communicate with a line interface unit such as the CX28380 Quad T1/E1 LIU. This interface allows the microprocessor to control and query the LIU status. This serial interface is not available on the CX28395.
1.1.4 Transmit/Receive Line Interface
The CX28394 and CX28398 devices include line interfaces which can operate in either of two modes: bipolar NRZ or unipolar NRZ. In bipolar NRZ mode, receiver signals RPOSI, RNEGI, and RCKI are used; and transmitter signals TPOSO, TNEGO, and TCKO are used. In unipolar NRZ mode, receiver signals RNRZ and RCKI are used, and transmitter signals TNRZO and TCKO are used. The CX28395 device provides only unipolar NRZ operation and signals. Figure 1-1 illustrates the CX28395 Functional Block Diagram (single framer).
Figure 1-1. CX28395 Functional Block Diagram
Receive NRZ Data Receive NRZ Clock T1/E1 Receive Framer
RX Slip Buffer
Receive System Bus
Transmit NRZ Data
TX Slip Buffer Overhead Insertion T1/E1 Transmit Framer
Transmit System Bus
Transmit NRZ Clock
1-2
Conexant
8394-8-5_011
Data Link Controllers DL1 + DL2
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
1.0 Product Description
1.2 Pin Assignments
1.2 Pin Assignments
The CX28394 is packaged in a 128-pin Quad Flat Pack (TQFP). The CX28395 is packaged in a 318-pin Ball Grid Array (BGA) multi-chip module (MCM). The CX28398 has two package alternatives: a 208-pin Quad Flat Pack (MQFP) and a 272-pin BGA. Pinout diagrams are provided in Figures 1-2 through 1-6 and Tables 1-1 through 1-4 summarize pin assignments for system bus pins. Table 1-5 lists all other pin assignments. Figures 1-7 through 1-12 illustrate the devices' logic, and Table 1-6 defines the hardware signals. The following input pins contain an internal pullup resistor (>50 k) and may remain unconnected if the active high input state is desired: A[7:0] MOTO* SYNCMD TDI (CX28394/28398) TDI1, TDI2 (CX28395) TMS TCK TRST* RST* SERDI Address lines unused in INTEL bus mode. Pullup selects INTEL bus mode if unconnected. Pullup selects synchronous processor interface. JTAG unused if not connected. JTAG unused if not connected. JTAG unused if not connected. Disables JTAG if not connected. Disables JTAG reset if not connected. Disables hardware reset if not connected. May be left unconnected if not used.
100054E
Conexant
1-3
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-2. CX28394 128-pin TQFP Pinout Diagram
TNEGO[3] / MSYNCO[3] TPOSO[3] / TNRZO[3] TCK0[3] VDD TCKI[2] TNEGO[2] / MSYNCO[2] TCKI[1] TNEGO[1] / MSYNCO[1] TPOSO[1] / TNRZO[1]
TPOSO[4] / TNRZO[4]
TPOSO[2] / TNRZO[2] TCK0[2] VDD
128 127 126 125 124 123 122 121 120 119 118
117 116
115
114 113 112
111 110 109
108 107 106
105 104
103
TCK0[1] SERCS1*
TCK0[4] RNEGI[3] RPOSI[3] RCKI[3] TCKI[3]
RNEGI[2] RPOSI[2]
RNEGI[1] RPOSI[1] RCKI[1]
RCKI[2]
TNEGO[4] / MSYNCO[4] TCKI[4] RCKI[4] RPOSI[4] RNEGI[4] EIACKI VSS T1ACKI VSS SYSCKI VSS VDD RPCMO[4] / RSIGO[4] RFSYNC[4] / RMSYNC[4] RSBCKI[4] / RFSYNC SIGFRZ[4] RSIGO[4] / RDLO[4] RINDO[4] / RDLCKO[4] TPCMI[4] / TSIGI[4] TFSYNC[4] / TMSYNC[4] TSBCKI[4] / TFSYNC TSIGI[4] / TDLI[4] TINDO[4] / TDLCKO[4] VDD RPCMO[3]/RSIGO[3] RFSYNC[3] / RMSYNC[3] RSBCKI[3] / RINDO SIGFRZ[3] RSIGO[3] / RDLO[3] RINDO[3] / RDLCKO[3] TPCMI[3] / TSIGI[3] TFSYNC[3] / TMSYNC[3] TSBCKI[3] / TINDO TSIGI[3] / TDLI[3] TINDO[3] / TDLCKO[3] VGG VSS TRST*
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 TSB3 / RSB3 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CLKs XMTR3 / RCVR3 XMTR2 / RCVR2 XMTR1 / RCVR1 SERIO XMTR4 / RCVR4
102 101 100 99 98 97 96
SERDI SERDO SERCKO TINDO[1] / TDLCKO[1] TSIGI[1] / TDLI[1] TSBCKI[1] / TSBCKI TFSYNC[1] / TMSYNC[1] TPCMI[1] / TSIGI[1] RINDO[1] / RDLCKO[1] RSIGO[1] / RDLO[1] SIGFRZ[1] RSBCKI[1] / RSBCKI RFSYNC[1] / RMSYNC[1] RPCMO[1] / RSIGO[1] VSS VDD VSS TINDO[2] / TDLCKO[2] TSIGI[2] / TDLI[2] TSBCKI[2] / TPCMI TFSYNC[2] / TMSYNC[2] TPCMI[2] / TSIGI[2] RINDO[2] / RDLCKO[2] RSIGO[2] / RDLO[2] SIGFRZ[2] RSBCKI[2] / RPCMO RFSYNC[2] / RMSYNC[2] RPCMO[2] / RSIGO[2] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] VSS A[0]
TSB1 / RSB1
95 94 93 92 91 90 89 88 87
TSB4 / RSB4
CX28394
TSB2 / RSB2
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
JTAG
MPU
VDD ONESEC INTR* DTACK* R/W* / WR* DS* / RD*
A[10] A[9]
A[8] A[7] A[6]
A[5] A[4] A[3]
CS* AS* / ALE MCLK
TMS TDI TDO TCK
SYNCMD MOTO* RST*
A[2] A[1]
1-4
Conexant
100054E
8394-8-5_016
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-3. CX28395 318-pin BGA Pinout Diagram
1 A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1.0 Product Description
1.2 Pin Assignments
20 A B C D E F G H J
Top View
K L M N P R T U V W Y 17 18 19 20
8394-8-5_013
100054E
Conexant
1-5
1-6
RINDO[7] / RDLCKO[7] TSBCKI[8] / TFSYNC[B] FSYNC[7] / TMSYNC[7] FSYNC[8] / TMSYNC[8] TINDO[7] / TDLCKO[7] TINDO[8] / TDLCKO[8] R/W* / WR* DTACK* TPCMI[7] / TSIGI[7] RPCMO[7] / RSIGO[7] TSBCKI[7] / TINDO[B] RSIGO[7] / RDLO[7] TSIGI[7] / TDLI[7] TSIGI[8] / TDLI[8] MOTO* SIGFRZ[7] TRST* A[10] A[11] VSS VSS TDO TDI TCK A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] VSS FSYNC[7] / RMSYNC[7] RSBCKI[7] / RINDO[B] INTR* ONESEC DS* / RD* AS* / ALE MCLK SYNCMD AD[5] RST* TMS VGG CS* VDD VDD 52 8 6 7 5 4 3 2 1 50 51 49 48 46 47 45 44 43 41 42 40 38 39 37 36 35 33 34 32 30 31 29 28 27 25 26 24 22 23 21 20 19 17 18 16 14 15 13 12 11 9 10 AD[6] AD[7]
1.2 Pin Assignments
AD[4] AD[3] 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
CLKs JTAG MPU MPU
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
SERIO
208
TINDO[3] / TDLCKO[3] TSIGI[3] / TDLI[3] TSBCKI[3] / TINDO[A] TFSYNC[3] / TMSYNC[3] TPCMI[3] / TSIGI[3] RINDO[3] / RDLCKO[3] RSIGO[3] / RDLO[3] SIGFRZ[3] RSBCKI[3] / RINDO[A] RFSYNC[3] / RMSYNC[3 RPCMO[3]/RSIGO[3] VDD VSS TPCMI[8] / TSIGI[8] RINDO[8] / RDLCKO[8] RSIGO[8] / RDLO[8] SIGFRZ[8] RSBCKI[8] / RFSYNC[B] RFSYNC[8] / RMSYNC[8 RPCMO[8] / RSIGO[8] TINDO[4] / TDLCKO[4] TSIGI[4] / TDLI[4] TSBCKI[4] / TFSYNC[A] TFSYNC[4] / TMSYNC[4] TPCMI[4] / TSIGI[4] RINDO[4] / RDLCKO[4] RSIGO[4] / RDLO[4] SIGFRZ[4] RSBCKI[4] / RFSYNC[A] RFSYNC[4] / RMSYNC[4 RPCMO[4] / RSIGO[4] RNEGI[8] RPOSI[8] RCKI[8] TCKI[8] TNEGO[8] / MSYNCO[8] TPOSO[8] / TNRZO[8] TCK0[8] RNEGI[7] RPOSI[7] RCKI[7] TCKI[7] TNEGO[7] / MSYNCO[7] TPOSO[7] / TNRZO[7] TCK0[7] VDD VSS SYSCKI VSS
AD[2] AD[1] AD[0] RPCMO[6] / RSIGO[6] RFSYNC[6] / RMSYNC[6] RSBCKI[6] / RPCMO[B] SIGFRZ[6] RSIGO[6] / RDLO[6] RINDO[6] / RDLCKO[6] TPCMI[6] / TSIGI[6] TFSYNC[6] / TMSYNC[6] TSBCKI[6] / TPCMI[B] TSIGI[6] / TDLI[6] TINDO[6] / TDLCKO[6] RPCMO[2] / RSIGO[2] RFSYNC[2] / RMSYNC[2] RSBCKI[2] / RPCMO[A] SIGFRZ[2] RSIGO[2] / RDLO[2] RINDO[2] / RDLCKO[2] TPCMI[2] / TSIGI[2] TFSYNC[2] / TMSYNC[2] TSBCKI[2] / TPCMI[A] TSIGI[2] / TDLI[2] TINDO[2] / TDLCKO[2] VSS RPCMO[5] / RSIGO[5] RFSYNC[5] / RMSYNC[5] RSBCKI[5] / RSBCKI[B] SIGFRZ[5] RSIGO[5] / RDLO[5] RINDO[5] / RDLCKO[5] TPCMI[5] / TSIGI[5] TFSYNC[5] / TMSYNC[5] TSBCKI[5] / TSBCKI[B] TSIGI[5] / TDLI[5] TINDO[5] / TDLCKO[5] VDD VSS RPCMO[1] / RSIGO[1] RFSYNC[1] / RMSYNC[1] RSBCKI[1] / RSBCKI[A] SIGFRZ[1] RSIGO[1] / RDLO[1] RINDO[1] / RDLCKO[1] TPCMI[1] / TSIGI[1] TFSYNC[1] / TMSYNC[1] TSBCKI[1] / TSBCKI[A] TSIGI[1] / TDLI[1] TINDO[1] / TDLCKO[1] 104
105 106 108 107 109 TSB1 / RSB1 TSB5 / RSB5 TSB2 / RSB2 TSB6 / RSB6 TSB8 / RSB8 TSB4 / RSB4 TSB3 / RSB3
1.0 Product Description
Figure 1-4. CX28398 208-pin PQFP Pinout Diagram
TSB7 / RSB7 TSB8 / RSB8
CX28398
Conexant
103
XMTR1 / RCVR1 110 111 112 113 114 115 116 117 VSS 118 VDD 119 120 XMTR5 / RCVR5 121 123 122 124 125 126 XMTR2 / RCVR2 128 127 129 131 130 132 133 134 XMTR6 / RCVR6 135 136 137 138 SERDI TCKI[1] TCKI[5] TCKI[2] TCKI[6] RCKI[1] RCKI[5] RCKI[2] RCKI[6] SERDO TCK0[1] TCK0[5] TCK0[2] TCK0[6] SERCKO RPOSI[1] RPOSI[5] RPOSI[2] RPOSI[6] RNEGI[1] RNEGI[5] RNEGI[2] SERCS1* SERCS2* TNEGO[1] / MSYNCO TNEGO[5] / MSYNCO TNEGO[2] / MSYNCO TNEGO[6] / MSYNCO TPOSO[1] / TNRZO[1] TPOSO[5] / TNRZO[5] TPOSO[2] / TNRZO[2] TPOSO[6] / TNRZO[6]
XMTR8 / RCVR8 XMTR7 / RCVR7
159 158 157
140 139 VSS RNEGI[6] 141 VDD 143 142 TCK0[3] TPOSO[3] / TNRZO[3] 144 TNEGO[3] / MSYNCO 145 TCKI[3] 146 RCKI[3] 148 147 149 151 150 152 153 154 155 156
T1ACKI VSS EIACKI
XMTR3 / RCVR3 VDD TCK0[4] RPOSI[3] RNEGI[3] TPOSO[4] / TNRZO[4]
XMTR4 / RCVR4 TCKI[4] RCKI[4] TNEGO[4] / MSYNCO
RPOSI[4]
RNEGI[4]
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
100054E
8394-8-5_023
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-5. CX28398 208-pin CABGA Pinout Diagram
1.0 Product Description
1.2 Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A B C D E F G H J K L M N P R T U
A B C D E F G H
Top View
J K L M N P R T U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
100054_001
100054E
Conexant
1-7
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-6. CX28398 272-pin BGA Pinout Diagram
1 A B C D E F G H J K L M N P R T U V W Y 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19
20 A B C D E
Top View
F G H J K L M N P R T U V W Y
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19
20
1-8
Conexant
8394-8-5_005
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4) (1 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
System Bus Interface Pin Functions
Non-Multiplexed Mode SBIMODE[0] = 0 [FCR; addr 080]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 080]
89 90 91 92 93 -- 94 95 96 97 98 -- 99 -- 75 76 77 78 79 -- 80 81 82 83 84 -- 85 -- 25 26
94 95 96 97 98 -- 99 100 101 102 103 -- 104 -- 69 70 71 72 73 -- 74 75 76 77 78 -- 79 -- 198 199
R12 P11 U14 T14 R13 -- P12 U15 U16 R14 P13 -- T15 -- R6 T6 U7 P7 R7 -- T7 U8 P8 R8 T8 -- U9 -- C6 D6
V15 W16 Y17 V16 W17 -- Y18 V17 W18 Y19 V18 -- W19 -- W8 Y8 V9 W9 Y9 -- W10 V10 Y10 Y11 W11 -- V11 -- C6 B5
J3 J4 J2 -- -- J1 -- K4 K1 K3 -- K2 -- K5 E4 E3 E2 -- -- F4 -- F3 F2 E1 -- F1 -- H5 U9 Y9
RPCMO[1] RFSYNC[1]/RMSYNC[1] RSBCKI[1] SIGFRZ[1] RSIGO[1] / RDLO[1] RSIGO[1] RINDO[1] / RDLCKO[1] TPCMI[1] TFSYNC[1]/TMSYNC[1] TSBCKI[1] TSIGI[1] / TDLI[1] TSIGI[1] TINDO[1] / TDLCKO[1] TINDO[1] RPCMO[2] RFSYNC[2]/RMSYNC[2] RSBCKI[2] SIGFRZ[2] RSIGO[2] / RDLO[2] RSIGO[2] RINDO[2] / RDLCKO[2] TPCMI[2] TFSYNC[2]/TMSYNC[2] TSBCKI[2] TSIGI[2] / TDLI[2] TSIGI[2] TINDO[2] / TDLCKO[2] TINDO[2] RPCMO[3] RFSYNC[3]/RMSYNC[3]
RSIGO[1] RMSYNC[1] RSBCKI[A] SIGFRZ[1] RDLO[1] TSTO[1] RDLCKO[1] TSIGI[1] TMSYNC[1] TSBCKI[A] TDLI[1] TSTI[1] TDLCKO[1] -- RSIGO[2] RMSYNC[2] RPCMO[A] SIGFRZ[2] RDLO[2] TSTO[2] RDLCKO[2] TSIGI[2] TMSYNC[2] TPCMI[A] TDLI[2] TSTI[2] TDLCKO[2] -- RSIGO[3] RMSYNC[3]
100054E
Conexant
1-9
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4) (2 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA System Bus Interface Pin Functions
Non-Multiplexed Mode SBIMODE[0] = 0 [FCR; addr 080]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 080]
27 28 29 -- 30 31 32 33 34 -- 35 -- 13 14 15 16 17 -- 18 19 20 21 22 -- 23 --
200 201 202 -- 203 204 205 206 207 -- 208 -- 178 179 180 181 182 -- 183 184 185 186 187 -- 188 --
C5 D5 B5 -- A4 A3 B3 C4 A2 -- B4 -- A11 B10 C10 D10 A10 -- A9 B9 C9 D9 A8 -- C8 --
A4 C5 B4 -- A3 C4 B3 B2 A2 -- C3 -- B11 C11 A11 A10 B10 -- C10 A9 B9 C9 A8 -- B8 --
U10 -- -- Y10 -- V9 W10 V10 -- W9 -- T10 U5 W5 V6 -- -- Y5 -- W6 V5 U6 -- Y6 -- T8
RSBCKI[3] SIGFRZ[3] RSIGO[3] / RDLO[3] RSIGO[3] RINDO[3] / RDLCKO[3] TPCMI[3] TFSYNC[3]/TMSYNC[3] TSBCKI[3] TSIGI[3] / TDLI[3] TSIGI[3] TINDO[3] / TDLCKO[3] TINDO[3] RPCMO[4] RFSYNC[4]/RMSYNC[4] RSBCKI[4] SIGFRZ[4] RSIGO[4] / RDLO[4] RSIGO[4] RINDO[4] / RDLCKO[4] TPCMI[4] TFSYNC[4]/TMSYNC[4] TSBCKI[4] TSIGI[4] / TDLI[4] TSIGI[4] TINDO[4] / TDLCKO[4] TINDO[4]
RINDO[A] SIGFRZ[3] RDLO[3] TSTO[3] RDLCKO[3] TSIGI[3] TMSYNC[3] TINDO[A] TDLI[3] TSTI[3] TDLCKO[3] -- RSIGO[4] RMSYNC[4] RFSYNC[A] SIGFRZ[4] RDLO[4] TSTO[4] RDLCKO[4] TSIGI[4] TMSYNC[4] TFSYNC[A] TDLI[4] TSTI[4] TDLCKO[4] --
1-10
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8) (1 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
System Bus Interface Pin Functions Pin Functions
Non-Multiplexed Mode SBIMODE[0] = 0 [FCR; addr 080]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 080]
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
81 82 83 84 85 -- 86 87 88 89 90 -- 91 -- 58 59 60 61 62 -- 63 64 65 66 67 -- 68 -- 25 26
U10 R9 P9 T10 R10 -- U11 T11 R11 T12 U12 -- P10 -- P4 U3 U4 R4 T4 -- U5 P5 R5 T5 U6 -- P6 -- J4 H2
Y12 W12 V12 Y13 W13 -- V13 Y14 W14 Y15 V14 -- W15 -- Y4 V5 W5 Y5 V6 -- W6 Y6 V7 W7 Y7 -- V8 -- L1 L2
G4 G2 G3 -- -- G1 -- H3 H4 H1 -- H2 -- J5 C2 C4 C1 -- -- D4 -- D2 D3 D1 -- C3 -- G5 U12 Y11
RPCMO[5] RFSYNC[5] / RMSYNC[5] RSBCKI[5] SIGFRZ[5] RSIGO[5] / RDLO[5] RSIGO[5] RINDO[5] / RDLCKO[5] TPCMI[5] TFSYNC[5] / TMSYNC[5] TSBCKI[5] TSIGI[5] / TDLI[5] TSIGI[5] TINDO[5] / TDLCKO[5] TINDO[5] RPCMO[6] RFSYNC[6] / RMSYNC[6] RSBCKI[6] SIGFRZ[6] RSIGO[6] / RDLO[6] RSIGO[6] RINDO[6] / RDLCKO[6] TPCMI[6] TFSYNC[6] / TMSYNC[6] TSBCKI[6] TSIGI[6] / TDLI[6] TSIGI[6] TINDO[6] / TDLCKO[6] TINDO[6] RPCMO[7] RFSYNC[7] / RMSYNC[7]
RSIGO[5] RMSYNC[5] RSBCKI[B] SIGFRZ[5] RDLO[5] TSTO[5] RDLCKO[5] TSIGI[5] TMSYNC[5] TSBCKI[B] TDLI[5] TSTI[5] TDLCKO[5] -- RSIGO[6] RMSYNC[6] RPCMO[B] SIGFRZ[6] RDLO[6] TSTO[6] RDLCKO[6] TSIGI[6] TMSYNC[6] TPCMI[B] TDLI[6] TSTI[6] TDLCKO[6] -- RSIGO[7] RMSYNC[7]
100054E
Conexant
1-11
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8) (2 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA System Bus Interface Pin Functions Pin Functions
Non-Multiplexed Mode SBIMODE[0] = 0 [FCR; addr 080]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 080]
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
27 28 29 -- 30 31 32 33 34 -- 35 -- 189 190 191 192 193 -- 194 195 9 10 11 -- 12 --
H1 J1 J3 -- J2 K4 K1 K2 L1 -- K3 -- D8 B8 C7 A7 D7 -- B7 A6 E4 E3 D2 -- D1 --
L3 M1 M2 -- M3 N1 N2 N3 P1 -- P2 -- C8 A7 B7 A6 C7 -- B6 A5 E1 F3 F2 -- F1 --
Y12 -- -- W11 -- W12 V11 V12 -- U11 -- T11 W7 V7 Y7 -- -- V8 -- Y8 W8 U8 -- U7 -- T9
RSBCKI[7] SIGFRZ[7] RSIGO[7] / RDLO[7] RSIGO[7] RINDO[7] / RDLCKO[7] TPCMI[7] TFSYNC[7] / TMSYNC[7] TSBCKI[7] TSIGI[7] / TDLI[7] TSIGI[7] TINDO[7] / TDLCKO[7] TINDO[7] RPCMO[8] RFSYNC[8] / RMSYNC[8] RSBCKI[8] SIGFRZ[8] RSIGO[8] / RDLO[8] RSIGO[8] RINDO[8] / RDLCKO[8] TPCMI[8] TFSYNC[8] / TMSYNC[8] TSBCKI[8] TSIGI[8] / TDLI[8] TSIGI[8] TINDO[8] / TDLCKO[8] TINDO[8]
RINDO[B] SIGFRZ[7] RDLO[7] TSTO[7] RDLCKO[7] TSIGI[7] TMSYNC[7] TINDO[B] TDLI[7] TSTI[7] TDLCKO[7] -- RSIGO[8] RMSYNC[8] RFSYNC[B] SIGFRZ[8] RDLO[8] TSTO[8] RDLCKO[8] TSIGI[8] TMSYNC[8] TFSYNC[B] TDLI[8] TSTI[8] TDLCKO[8] --
1-12
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12) (1 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
System Bus Interface Pin Functions
Non-Multiplexed Mode SBIMODE[0] = [FCR; addr 001]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 001]
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
F20 F18 F19 F17 E20 E18 E19 E17 F16 K17 K19 K18 K20 J17 J20 J18 J19 H16 A4 A3 B4 B3 A2 A1 B2 B1 E5 A10 D10 B10
RPCMO[9] RFSYNC[9]/RMSYNC[9] RSBCKI[9] RSIGO[9] TPCMI[9] TFSYNC[9]/TMSYNC[9] TSBCKI[9] TSIGI[9] TINDO[9] RPCMO[10] RFSYNC[10]/RMSYNC[10] RSBCKI[10] RSIGO[10] TPCMI[10] TFSYNC[10]/TMSYNC[10] TSBCKI[10] TSIGI[10] TINDO[10] RPCMO[11] RFSYNC[11]/RMSYNC[11] RSBCKI[11] RSIGO[11] TPCMI[11] TFSYNC[11]/TMSYNC[11] TSBCKI[11] TSIGI[11] TINDO[11] RPCMO[12] RFSYNC[12]/RMSYNC[12] RSBCKI[12]
RSIGO[9] RMSYNC[9] RSBCKI[C] TSTO[9] TSIGI[9] TMSYNC[9] TSBCKI[C] TSTI[9] -- RSIGO[10] RMSYNC[10] RPCMO[C] TSTO[10] TSIGI[10] TMSYNC[10] TPCMI[C] TSTI[10] -- RSIGO[11] RMSYNC[11] RINDO[C] TSTO[11] TSIGI[11] TMSYNC[11] TINDO[C] TSTI[11] -- RSIGO[12] RMSYNC[12] RFSYNC[C]
100054E
Conexant
1-13
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12) (2 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA System Bus Interface Pin Functions
Non-Multiplexed Mode SBIMODE[0] = [FCR; addr 001]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 001]
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
D9 A9 C9 B9 C10 E7
RSIGO[12] TPCMI[12] TFSYNC[12]/TMSYNC[12] TSBCKI[12] TSIGI[12] TINDO[12]
TSTO[12] TSIGI[12] TMSYNC[12] TFSYNC[C] TSTI[12] --
Table 1-4. Pin Assignments (SBI13, SBI14, SBI15, SBI16) (1 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA System Bus Interface Pin Functions
Non-Multiplexed Mode SBIMODE[0] = [FCR; addr 001]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 001]
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
H18 H19 H17 H20 G17 G20 G18 G19 G16 M18 M17 M19 L19 L20 L17 M20
RPCMO[13] RFSYNC[13]/RMSYNC[13] RSBCKI[13] RSIGO[13] TPCMI[13] TFSYNC[13]/TMSYNC[13] TSBCKI[13] TSIGI[13] TINDO[13] RPCMO[14] RFSYNC[14]/RMSYNC[14] RSBCKI[14] RSIGO[14] TPCMI[14] TFSYNC[14]/TMSYNC[14] TSBCKI[14]
RSIGO[13] RMSYNC[13] RSBCKI[D] TSTO[13] TSIGI[13] TMSYNC[13] TSBCKI[D] TSTI[13] -- RSIGO[14] RMSYNC[14] RPCMO[D] TSTO[14] TSIGI[14] TMSYNC[14] TPCMI[D]
1-14
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-4. Pin Assignments (SBI13, SBI14, SBI15, SBI16) (2 of 2) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
System Bus Interface Pin Functions
Non-Multiplexed Mode SBIMODE[0] = [FCR; addr 001]
Multiplexed Mode SBIMODE[0] = 1 [FCR; addr 001]
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
L18 K16 B7 B8 D7 C8 A7 A8 C7 D8 M16 A6 A5 B6 D6 C6 B5 C5 D5 J16
TSIGI[14] TINDO[14] RPCMO[15] RFSYNC[15]/RMSYNC[15] RSBCKI[15] RSIGO[15] TPCMI[15] TFSYNC[15]/TMSYNC[15] TSBCKI[15] TSIGI[15] TINDO[15] RPCMO[16] RFSYNC[16]/RMSYNC[16] RSBCKI[16] RSIGO[16] TPCMI[16] TFSYNC[16]/TMSYNC[16] TSBCKI[16] TSIGI[16] TINDO[16]
TSTI[14] -- RSIGO[15] RMSYNC[15] RINDO[D] TSTO[15] TSIGI[15] TMSYNC[15] TINDO[D] TSTI[15] -- RSIGO[16] RMSYNC[16] RFSYNC[D] TSTO[16] TSIGI[16] TMSYNC[16] TFSYNC[D] TSTI[16] --
100054E
Conexant
1-15
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (1 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
Pin Functions
7 9 11 37 66 86 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 111
117 140 158 160 162 196 2 24 49 80 93 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 118
B2 G1 P3 T9 T13 N17 F17 B16 A16 D14 B6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C1
A1 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 N4 N17 U4 U8 U13 U17 D6
N6 N7 N8 P6 P7 P8 R6 R7 R8 F13 F14 F15 G13 G14 G15 H13 H14 H15 T13 T14 -- -- -- -- -- -- -- -- -- E6
VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VSS (GND) VDD
1-16
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (2 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
Pin Functions
119 12 24 43 87 -- -- -- -- -- -- 36 38 39 40 -- -- 41 -- -- 42 6 8 10 44 -- -- 45 -- --
141 149 163 197 8 48 92 -- -- -- -- 1 3 4 5 -- -- 6 -- -- 7 157 159 161 13 -- -- 14 -- --
P2 U13 M15 G15 F14 C14 A5 -- -- -- -- A1 C3 B1 D4 -- -- D3 -- -- C2 A17 B15 C15 F4 -- -- F3 -- --
D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 B1 D2 D3 C1 -- -- D1 -- -- E3 A19 B17 A18 G3 -- -- G2 -- --
F5 N20 R16 T15 Y20 -- -- -- -- -- -- Y14 Y16 W20 -- Y15 T20 -- Y19 P19 W17 P20 N19 U13 -- V13 Y13 -- Y18 N17
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VGG TRST* TMS TDI TDI1 TDI2 TD0 TDO1 TDO2 TCK E1ACKI T1ACKI SYSCKI ONESEC ONESEC1 ONESEC2 INTR* INTR1* INTR2*
100054E
Conexant
1-17
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (3 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
Pin Functions
46 -- -- 47 48 49 -- -- 50 51 52 53 54 -- 55 56 57 58 59 60 61 62 63 64 65 67 68 69 70 71
15 -- -- 16 17 18 -- -- 19 20 21 22 23 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54
E2 -- -- E1 G4 G3 -- -- F2 F1 H4 H3 G2 L3 M2 M1 L4 N2 L2 N1 M4 M3 N4 P1 N3 R2 R1 T1 U1 T2
G1 -- -- H3 H2 H1 -- -- J3 J2 J1 K2 K3 R1 P3 R2 T1 R3 T2 U1 T3 U2 V1 U3 V2 V3 W2 Y1 W3 Y2
-- W13 T18 Y17 W14 -- W19 N18 V14 U14 W15 W18 W16 V15 V18 U15 V16 V20 V19 U20 V17 U16 U19 U17 T17 R17 U18 R18 R20 P18
DTACK* DTACK1* DTACK2* R/W*/WR* DS*/RD* CS* CSI* CS2* AS*/ALE MCLK SYNCMD MOTO* RST* A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] AD[7] AD[6] AD[5] AD[4] AD[3]
1-18
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (4 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
Pin Functions
72 73 74 100 101 102 103 -- 104 107 105 106 108 109 110 112 115 113 114 116 117 118 120 123 121 122 124 125 126 127
55 56 57 105 106 107 108 109 110 113 111 112 114 115 116 126 129 127 128 130 131 132 142 145 143 144 146 147 148 150
U2 T3 R3 U17 T16 T17 R16 R17 R15 P16 N15 P17 P15 P14 N16 K15 K16 K17 L14 J16 J17 J15 H14 G14 F16 E17 F15 E16 D17 E15
W4 V4 Y3 W20 V19 U19 U18 V20 U20 T20 T18 T19 R18 R19 R20 L19 K20 L18 L20 K19 K18 J20 F19 E19 E20 F18 D20 E18 D19 C20
R19 P17 T19 -- -- -- -- -- L3 M3 L4 L5 L1 L2 -- N1 P3 N2 N5 P1 P2 -- T1 T4 T3 R5 T2 U1 -- U2
AD2] AD[1] AD[0] SERCLKO SERDO SERDI SERCS1* (SERCS*) SERCS2* TCKO[1] TCKI[1] TPOSO[1]/TNRZO[1] TNEGO[1]/MSYNCO[1] RCKI[1] RPOSI[1]/RNRZI[1] RNEGI[1] TCKO[2] TCKI[2] TPOSO[2]/TNRZO[2] TNEGO[2]/MSYNCO[2] RCKI[2] RPOSI[2]/RNRZI[2] RNEGI[2] TCKO[3] TCKI[3] TPOSO[3]/TNRZO[3] TNEGO[3]/MSYNCO[3] RCKI[3] RPOSI[3]/RNRZI[3] RNEGI[3] TCKO[4]
100054E
Conexant
1-19
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (5 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
Pin Functions
2 128 1 3 4 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
153 151 152 154 155 156 119 122 120 121 123 124 125 133 136 134 135 137 138 139 164 167 165 166 168 169 170 171 174 172
E14 D16 C17 D15 C16 B17 N14 L15 M16 M17 M14 L16 L17 H17 H15 K14 H16 G17 J14 G16 B14 C13 A15 D13 A14 B13 D12 C12 A12 A13
B20 D18 C19 C18 B19 A20 P20 N20 N18 N19 M18 M19 M20 J19 H19 J18 H20 H18 G20 G19 B16 B15 A16 C15 A15 C14 B14 A14 A13 C13
U3 U4 T5 V1 V2 -- M4 M2 M1 M5 N3 N4 -- P4 R2 R1 P5 R3 R4 -- V3 Y1 W1 T6 W2 Y2 -- Y3 W3 V4
TCKI[4] TPOSO[4]/TNRZO[4] TNEGO[4]/MSYNCO[4] RCKI[4] RPOSI[4]/RNRZI[4] RNEGI[4] TCKO[5] TCKI[5] TPOSO[5]/TNRZO[5] TNEGO[5]/MSYNCO[5] RCKI[5] RPOSI[5]/RNRZI[5] RNEGI[5] TCKO[6] TCKI[6] TPOSO[6]/TNRZO[6] TNEGO[6]/MSYNCO[6] RCKI[6] RPOSI[6] /RNRZI[6] RNEGI[6] TCKO[7] TCKI[7] TPOSO[7]/TNRZO[7] TNEGO[7]/MSYNCO[7] RCKI[7] RPOSI[7] /RNRZI[7] RNEGI[7] TCKO[8] TCKI[8] TPOSO[8]/TNRZO[8]
1-20
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (6 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
Pin Functions
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
173 175 176 177 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
B12 C11 B11 D11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
B13 C12 B12 A12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
T7 W4 Y4 -- D20 B20 C20 E16 D19 C19 B18 D17 C17 E14 A18 A17 A15 D15 C15 E12 B15 A14 B14 D14 C14 E11 A13 B13 B19 A19
TNEGO[8]/MSYNCO[8] RCKI[8] RPOSI[8] /RNRZI[8] RNEGI[8] TCKO[9] TCKI[9] TPOSO[9]/TNRZO[9] TNEGO[9]/MSYNCO[9] RCKI[9] RPOSI[9]/RNRZI[9] TCKO[10] TCKI[10] TPOSO[10]/TNRZO[10] TNEGO[10]/MSYNCO[10] RCKI[10] RPOSI[10]/RNRZI[10] TCKO[11] TCKI[11] TPOSO[11]/TNRZO[11] TNEGO[11]/MSYNCO[11] RCKI[11] RPOSI[11]/RNRZI[11] TCKO[12] TCKI[12] TPOSO[12]/TNRZO[12] TNEGO[12]/MSYNCO[12] RCKI[12] RPOSI[12]/RNRZI[12] TCKO[13] TCKI[13]
100054E
Conexant
1-21
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (7 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
Pin Functions
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E2 G4 E4 J4 C2 K1 L4 M4
A20 E15 C18 D18 B17 B16 A16 E13 C16 D16 C12 A12 B12 E10 C13 D13 B11 C11 D12 E8 A11 D11 E9 T12 L16 N16 P16 T16 -- --
TPOSO[13]/TNRZO[13] TNEGO[13]/MSYNCO[13] RCKI[13] RPOSI[13]/RNRZI[13] TCKO[14] TCKI[14] TPOSO[14]/TNRZO[14] TNEGO[14]/MSYNCO[14] RCKI[14] RPOSI[14] /RNRZI[14] TCKO[15] TCKI[15] TPOSO[15]/TNRZO[15] TNEGO[15]/MSYNCO[15] RCKI[15] RPOSI[15] /RNRZI[15] TCKO[16] TCKI[16] TPOSO[16]/TNRZO[16] TNEGO[16]/MSYNCO[16] RCKI[16] RPOSI[16] /RNRZI[16] NC NC NC NC NC NC NC NC
1-22
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (8 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
1.0 Product Description
1.2 Pin Assignments
Pin Functions
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
T4 P4 W1 U5 U7 U9 U11 U12 Y16 U14 U16 Y20 T17 P17 P18 P19 M17 F20 E17 G17 G18 B18 C17 D16 A17 C16 D14 K17 J17 D12
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
100054E
Conexant
1-23
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-5. Pin Assignments (9 of 9) Pin Number CX28398 208-pin CABGA CX28398 208-pin PQFP CX28394 128-pin TQFP CX28398 272-pin BGA CX28395 318-pin BGA
Pin Functions
-- -- -- --
-- -- -- --
-- -- -- --
D10 D9 D7 D5
-- -- -- --
NC NC NC NC
1-24
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-7. CX28394 Logic Diagram (Non-Multiplexed System Bus Mode)
1.0 Product Description
1.2 Pin Assignments
Hardware Reset I System Clock I Processor Clock I Synchronous Bus mode I Motorola Bus mode I Address Strobe I Chip Select I Data or Read Strobe I Read/Write or Write Strobe I Data or Multiplexed I/O Address/Data Bus Address Bus I
RST* SYSCKI MCLK SYNCMD MOTO* AS*(ALE*) CS* DS*(RD*) R/W*(W*) AD[7:0] A[10:0]
Microprocessor Interface and Control (MPU)
DTACK* INTR* ONESEC
O Data Transfer Acknowledge O Interrupt Request PIO One-Second Timer
Serial Data In I
SERDI
LIU Serial Port Interface (SERIO)
SERCKO SERDO SERCS*
O Serial Clock Out O Serial Data Out O Serial Port Chip Select
Transmit Clock In I 1544 KHz All Ones Clock I 2048 KHz All Ones Clock I
TCKI[4:1] T1ACKI E1ACKI
Transmitter (XMTR)
TCKO{4:1]
O Transmit Clock Out O Transmit Positive/Transmit NRZ Out O Transmit Negative/Transmit Multiframe Sync Out
TPOSO[4:1]/TNRZO[4:1] TNEGO[4:1]/MSYNCO[4:1] Receiver (RCVR)
Receive Clock In I Receive Positive In I Receive Negative In I
RCKI[4:1] RPOSI[4:1] RNEGI[4:1]
Bused TSB Clock In I Bused TSB PCM Data In I TSB Signalling In I Transmit Datalink Data In I
Transmit System Bus (TSB) TSBCKI TPCMI TSIGI[4:1] TDLI[4:1] Receive System Bus (RSB)
TINDO TFSYNC TMSYNC[4:1] TDLCKO[4:1]
O Bused Time Slot Indicator PIO Bused TSB Frame Sync PIO TSB Multiframe Sync O Transmit Datalink Clock Out
RPCMO RINDO RFSYNC RMSYNC RSIGO RDLCKO RDLO SIGFRZ
O Bused RSB PCM Data Out O Bused Time Slot Indicator PIO Bused RSB Frame Sync PIO RSB Multiframe Sync PIO RSB Signalling O Receive Datalink Clock Out O Receive Datalink Data Out O Signalling Freeze
Bused RSB Clock In I
RSBCKI
Test Clock In I Test mode Select I Test Data In I Test Reset In I
TCK TMS TDI TRST*
Boundary Scan (JTAG) TDO O Test Data Out
I= Input, O= Output PIO = Programmable I/O; controls located at PIO (address 018)
100054E
Conexant
8394-8-5_017
1-25
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-8. CX28394 Logic Diagram (Multiplexed System Bus Mode)
Microprocessor Interface and Control (MPU)
Hardware Reset I System Clock I Processor Clock I Synchronous Bus mode I Motorola Bus mode I Address Strobe I Chip Select I Data or Read Strobe I Read/Write or Write Strobe I Data or Multiplexed I/O Address/Data Bus Address Bus I
RST* SYSCKI MCLK SYNCMD MOTO* AS*(ALE*) CS* DS*(RD*) R/W*(W*) AD[7:0] A[10:0]
DTACK* INTR* ONESEC
O
Data Transfer Acknowledge
O Interrupt Request PIO One-Second Timer
LIU Serial Port Interface (SERIO) Serial Data In I SERDI
SERCKO SERDO SERCS*
O O O
Serial Clock Out Serial Data Out Serial Port Chip Select
Transmit Clock In 1544 KHz All Ones Clock 2048 KHz All Ones Clock
I I I
TCKI[4:1] T1ACKI E1ACKI
Transmitter (XMTR)
TCKO[4:1] TPOSO[8:1]/TNRZO[4:1] TNEGO[8:1]/MSYNCO[4:1]
O O O
Transmit Clock Out Transmit Positive/Transmit NRZ Out Transmit Negative/Transmit Multiframe Sync Out
Receive Clock In Receive Positive In Receive Negative In
I I I
RCKI[4:1] RPOSI[4:1] RNEGI[4:1]
Receiver (RCVR)
Bused TSB Clock In Bused TSB PCM Data In TSB Signalling In/ Transmit Datalink Data In
I I I I
Transmit System Bus (TSB) TSBCKI[A] TINDO[A] TPCMI[A] TFSYNC[A] TSIGI[4:1] TMSYNC[4:1] TDLI[4:1] TDLCKO[4:1] Receive System Bus (RSB) RPCMO[A] RSBCKI[8:1] RINDO[A] RFSYNC[A] RMSYNC[4:1] RSIGO[4:1] RDLCKO[4:1] RDLO[4:1] SIGFRZ[4:1] Boundary Scan (JTAG) TDO
O PIO PIO O
Bused Time Slot Indicator Bused TSB Frame Sync TSB MUltiframe Sync Transmit Datalink Clock Out
Bused RSB Clock In
I
O O PIO PIO PIO O O O
Bused RSB PCM Data Out Bused Time Slot Indicator Bused RSB Frame Sync RSB Multiframe Sync RSB Signalling Receive Datalink Clock Out Receive Datalink Data Out Signalling Freeze
Test Clock In Test mode Select Test Data In Test Reset In
I= Input, O= Output PIO = Programmable I/O; controls located at PIO (address 018)
1-26
Conexant
100054E
8394-8-5_018a
I I I I
TCK TMS TDI TRST*
O
Test Data Out
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-9. CX28398 Logic Diagram (Non-Multiplexed System Bus Mode)
1.0 Product Description
1.2 Pin Assignments
Hardware Reset I System Clock I Processor Clock I Synchronous Bus mode I Motorola Bus mode I Address Strobe I Chip Select I Data or Read Strobe I Read/Write or Write Strobe I Data or Multiplexed I/O Address/Data Bus Address Bus I
RST* SYSCKI MCLK SYNCMD MOTO* AS*(ALE*) CS* DS*(RD*) R/W*(W*) AD[7:0] A[11:0]
Microprocessor Interface and Control (MPU)
DTACK* INTR* ONESEC
O
Data Transfer Acknowledge
O Interrupt Request PIO One-Second Timer
LIU Serial Port Interface (SERIO) Serial Data In I SERDI
SERCKO SERDO SERCS*[2:1]
O O O
Serial Clock Out Serial Data Out Serial Port Chip Select
Transmit Clock In 1544 KHz All Ones Clock 2048 KHz All Ones Clock
I I I
TCKI[8:1] T1ACKI E1ACKI
Transmitter (XMTR)
TCKO[8:1] TPOSO[8:1]/TNRZO[8:1] TNEGO[8:1]/MSYNCO[8:1]
O O O
Transmit Clock Out Transmit Positive/Transmit NRZ Out Transmit Negative/Transmit Multiframe Sync Out
Receive Clock In Receive Positive In Receive Negative In
I I I
RCKI[8:1] RPOSI[8:1] RNEGI[8:1]
Receiver (RCVR)
TSB Clock In TSB PCM Data In TSB Signalling In/ Transmit Datalink Data In
I I I
Transmit System Bus (TSB) TSBCKI[8:1] TFSYNC[8:1]/TMSYNC[8:1] TPCMI[8:1] TINDO[8:1]/TDLCKO[8:1] TSIGI[8:1]/TDLI[8:1] Receive System Bus (RSB) RPCMO[8:1] RFSYNC[8:1]/RMSYNC[8:1] RSBCKI[8:1] RINDO[8:1]/RDLCKO[8:1] RSIGO[8:1]/RDLO[8:1] SIGFRZ[8:1]
PIO TSB Frame/Multiframe Sync O Time Slot Indicator/Transmit Datalink Clock Out
O
RSB PCM Data Out
RSB Clock In
I
PIO RSB Frame/Multiframe Sync O Time Slot Indicator/Receive Datalink Clock Out O RSB Signalling/Receive Datalink Data Out PIO Signalling Freeze
Test Clock In Test mode Select Test Data In Test Reset In
I I I I
TCK TMS TDI TRST*
Boundary Scan (JTAG) TDO O Test Data Out
I= Input, O= Output PIO = Programmable I/O; controls located at PIO (address 018)
100054E
Conexant
1-27
8394-8-5_020
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-10. CX28398 Logic Diagram (Multiplexed System Bus Mode)
Microprocessor Interface and Control (MPU)
Hardware Reset I System Clock I Processor Clock I Synchronous Bus mode I Motorola Bus mode I Address Strobe I Chip Select I Data or Read Strobe I Read/Write or Write Strobe I Data or Multiplexed I/O Address/Data Bus Address Bus I
RST* SYSCKI MCLK SYNCMD MOTO* AS*(ALE*) CS* DS*(RD*) R/W*(W*) AD[7:0] A[11:0]
DTACK* INTR* ONESEC
O
Data Transfer Acknowledge
O Interrupt Request PIO One-Second Timer
LIU Serial Port Interface (SERIO) Serial Data In I SERDI
SERCKO SERDO SERCS*[2:1]
O O O
Serial Clock Out Serial Data Out Serial Port 1 and 2 Chip Selects Transmit Clock Out Transmit Positive/Transmit NRZ Out Transmit Negative/Transmit Multiframe Sync Out
Transmit Clock In 1544 KHz All Ones Clock 2048 KHz All Ones Clock
I I I
TCKI[8:1] T1ACKI E1ACKI
Transmitter (XMTR)
TCKO[8:1] TPOSO[8:1]/TNRZO[8:1] TNEGO[8:1]/MSYNCO[8:1]
O O O
Receive Clock In Receive Positive In Receive Negative In
I I I
RCKI[8:1] RPOSI[8:1] RNEGI[8:1]
Receiver (RCVR)
Bused TSB Clock In Bused TSB PCM Data In TSB Signalling In/ Transmit Datalink Data In
I I I I
Transmit System Bus (TSB) TSBCKI[A:B] TINDO[A:B] TPCMI[A:B] TFSYNC[A:B] TSIGI[8:1] TMSYNC[8:1] TDLI[8:1] TDLCKO[8:1] Receive System Bus (RSB) RPCMO[A:B] RSBCKI[A:B] RINDO[A:B] RFSYNC[A:B] RMSYNC[8:1] RSIGO[8:1] RDLCKO[8:1] RDLO[8:1] SIGFRZ[8:1] Boundary Scan (JTAG) TDO
O PIO PIO O
Bused Time Slot Indicator Bused TSB Frame Sync TSB MUltiframe Sync Transmit Datalink Clock Out
Bused RSB Clock In
I
O O PIO PIO PIO O O O
Bused RSB PCM Data Out Bused Time Slot Indicator Bused RSB Frame Sync RSB Multiframe Sync RSB Signalling Receive Datalink Clock Out Receive Datalink Data Out Signalling Freeze
Test Clock In Test mode Select Test Data In Test Reset In
I I I I
TCK TMS TDI TRST*
O
Test Data Out
8394-8-5_021
I= Input, O= Output PIO = Programmable I/O; controls located at PIO (address 018)
1-28
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-11. CX28395 Logic Diagram (Non-Multiplexed System Bus Mode)
Microprocessor Interface and Control (MPU)
1.0 Product Description
1.2 Pin Assignments
Hardware Reset System Clock Processor Clock Synchronous Bus mode Motorola Bus mode Address Strobe Chip Select 1 Chip Select 2
I I I I I I I I
RST* SYSCKI MCLK SYNCMD MOTO* AS*(ALE*) CS1* CS2* DS*(RD*) R/W*(W*) AD[7:0] A[11:0]
DTACK* INTR* ONESEC
O
Data Transfer Acknowledge
O Interrupt Request PIO One-Second Timer
Data or Read Strobe I Read/Write or Write Strobe I Data or Multiplexed I/O Address/Data Bus Address Bus I
Transmit Clock In 1544 KHz All Ones Clock 2048 KHz All Ones Clock
Transmitter (XMTR) I I I TCKI[16:1] T1ACKI E1ACKI Receiver (RCVR) TCKO[16:1] TNRZO[16:1] O O Transmit Clock Out Transmit Transmit NRZ Out
Receive Clock In Receive NRZ In Receive Negative In
I I I
RCKI[16:1] RNRZ[16:1] RNEGI[16:1]
Transmit System Bus (TSB) TSB Clock In TSB PCM Data In TSB Signalling In/ I I I TSBCKI[16:1] TPCMI[16:1] TFSYNC[16:1]/TMSYNC[16:1] TSIGI[16:1] PIO TSB Frame/Multiframe Sync
RSB Clock In
I
Receive System Bus (RSB) RPCMO[16:1] RSBCKI[16:1] RFSYNC[16:1]/RMSYNC[16:1] RSIGO[16:1] Boundary Scan (JTAG) TDO1 TDO2
O RSB PCM Data Out PIO RSB Frame/Multiframe Sync O RSB Signalling
Test Clock In Test mode Select Test Data In 1 Test Data In 2 Test Reset In
I I I I I
TCK TMS TDI1 TDI2 TRST*
O O
Test Data Out 1 Test Data Out 2
100054E
Conexant
1-29
8394-8-5_006
I= Input, O= Output PIO = Programmable I/O; controls located at PIO (address 018)
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 1-12. CX28395 Logic Diagram (Multiplexed System Bus Mode)
Hardware Reset I System Clock I Processor Clock I Synchronous Bus Mode I Motorola Bus Mode I Address Strobe I Chip Select 1 I Chip Select 2 I Data or Read Strobe I Read/Write or Write Strobe I Data or Multiplexed I/O Address/Data Bus Address Bus I
RST* SYSCKI MCLK SYNCMD MOTO* AS* (ALE*) CS1* CS2* DS* (RD*) R/W* (W*) AD[7:0]
Microprocessor Interface and Control (MPU)
DTACK* INTR1* INTR2* ONESEC1 ONESEC2
O O O
Data Transfer Acknowledge Interrupt Request 1 Interrupt Request 2
PIO One-Second Timer 1 PIO One-Second Timer 2
A[11:0] Transmitter (XMTR)
Transmit Clock In I 1544 KHz All Ones Clock I 2048 KHz All Ones Clock I
TCKI[16:1] T1ACKI E1ACKI
TCKO[16:1] TNRZO[16:1]
O O
Transmit Clock Out Transmit Positive / Transmit NRZ Out
Receive Clock In I Receive NRZ In I
RCKI[16:1] RNRZ[16:1]
Receiver (RCVR)
Bused TSB Clock In I Bused TSB PCM Data In I TSB Signalling In I
TSBCKI[A:D] TPCMI[A:D] TSIGI[16:1]
Transmit System Bus (TSB) TINDO[A:D] TFSYNC[A:D] TMSYNC[16:1]
O
Bused Timeslot Indicator
PIO Bused TSB Frame Sync PIO TSB Multiframe Sync
Bused RSB Clock In I
Receive System Bus (RSB) RPCMO[A:D] RSBCKI[A:D] RINDO[A:D] RFSYNC[A:D] RMSYNC[16:1] RSIGO[16:1]
O O
Bused RSB PCM Data Out Bused Timeslot Indicator
PIO Bused RSB Frame Sync PIO RSB Multiframe Sync O RSB Signalling
Test Clock In I Test Mode Select I Test Data In 1 I Test Data In 2 I Test Reset In I
TCK TMS TDI1 TDI2 TRST*
Boundary Scan (JTAG) TDO1 TDO2 O O Test Data Out 1 Test Data Out 2
I = Input, O = Output PIO = Programmable I/O; controls located at PIO (address 018)
1-30
Conexant
100054E
8394-8-5_022
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (1 of 9) Pin Label Signal Name Device (1) I/O
1.0 Product Description
1.2 Pin Assignments
Definition
Microprocessor Interface (MPU) RST* Hardware Reset 4, 5, 8 I High-to-low-to-high cycle forces registers to their power-up state and all PIO pins to the input state. RST* is not mandatory since power-on reset circuit performs an identical function. RST* must remain asserted for a minimum of 2 processor clock cycles (MCLK or SYSCKI, depending on SYNCMD selection). Required 32.768 MHz clock for internal use. Supplied from external source. System applies MCLK in the range of 8-36 MHz for use with synchronous MPU applications. MCLK is used when SYNCMD = 1 and ignored when SYNCMD = 0. Selects synchronous or asynchronous read/write timing with respect to MCLK. Supports Intel- or Motorola-style buses: 0 = Asynchronous Bus; read and write latches are asynchronously controlled by CS*, DS*, and R/W* signals. 1 = Synchronous Bus; MCLK rising edge samples CS*, DS*, and R/W* to determine valid read/write cycle timing. Selects Intel- or Motorola-style microprocessor interface. DS*, R/W*, A[11:0], and AD[7:0] functions are affected. 0 = Motorola; AD[7:0] is data, A[11:0] is address, DS* is data strobe, and R/W* indicates read (high) or write (low) data direction. 1 = Intel; AD[7:0] is multiplexed address/data, A[7:0] is ignored, A[11:8] is address, DS* is read strobe (RD*), and R/W* is write strobe (WR*). Address used to identify a register for subsequent read/write data transfer cycle. In Motorola bus mode, all eleven address bits (A[10:0]) are valid. In Intel bus mode, only upper three bits (A[10:8]) are used. Address used to identify a register for subsequent read/write data transfer cycle. In Motorola bus mode, all twelve address bits (A[11:0]) are valid. In Intel bus mode, only upper four bits (A[11:8]) are used. Multiplexed address/data (Intel) or data only(Motorola). Refer to MOTO* signal definition. For all processor bus modes, AS* falling edge asynchronously latches address from A[11:0] (Motorola) or A[11:8], AD[7:0] (Intel) to identify one register for subsequent read/write data transfer cycle. Active-low enables read/write decoder. Active high ends current read or write cycle and places data bus output in high impedance. CS1* is the chip select pin for framers 1 to 8, CS2* is the chip select for framers 9 to 16.
SYSCKI MCLK
System Clock Processor Clock
4, 5, 8 4, 5, 8
I I
SYNCMD
Sync mode
4, 5, 8
I
MOTO*
Motorola Bus Mode
4, 5, 8
I
A[10:0]
Address Bus
4
I
A[11:0]
Address Bus
5, 8
I
AD[7:0] AS*(ALE)
Data Bus or Address Data Address Strobe
4, 5, 8 4, 5, 8
I/O I
CS1*, CS2*
Chip Select
5
I
100054E
Conexant
1-31
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (2 of 9) Pin Label Signal Name Device (1) I/O Definition
Microprocessor Interface (MPU) (Continued) CS* Chip Select 4, 8 I Active-low enables read/write decoder. Active high ends current read or write cycle and places data bus output in high impedance. Active-low read data strobe (RD*) for MOTO* = 1, or data strobe (DS*) for MOTO* = 0. Active-low write data strobe (WR*) for MOTO* = 1, or data select (R/W*) for MOTO* = 0. Controls or marks one-second interval used for status reporting. When input, the timer is aligned to ONESEC rising edge. When output, rising edge indicates start of each one-second interval. Controls or marks one-second interval used for status reporting. When input, the timer is aligned to ONESEC rising edge. When output, rising edge indicates start of each one-second interval. ONESEC1 is the one second timer for framers 1 to 8, ONESEC2 is the one second timer for framers 9 to 16. Open drain active low output signifies one or more pending interrupt requests. INTR* goes to high-impedance state with weak (>50 k) internal pullup resistance after processor has serviced all pending interrupt requests. Open drain active low output signifies one or more pending interrupt requests. INTRn* goes to high-impedance state with weak (>50k) internal pullup resistance after processor has serviced all pending interrupt requests. INTR1* is the interrupt request for framers 1 to 8, INTR2* is the interrupt request for framers 9 to 16. Open drain active low output signifies in-progress data transfer cycle. DTACK* remains asserted (low) for as long as AS* and CS* are both active-low. Open drain active low output signifies in-progress data transfer cycle. DTACKn* remains asserted (low) for as long as AS* and CSn* are both active-low.
DS*(RD*) R/W*(WR*)
Data Strobe or Read Strobe Read/Write Direction or Write Strobe One Second Timer
4, 5, 8 4, 5, 8
I I
ONESEC
4, 8
PIO
ONESEC1 ONESEC2
One Second Timer
5
PIO
INTR*
Interrupt Request
4, 8
O
INTR1* INTR2*
Interrupt Request
5
O
DTACK*
Data Transfer Acknowledge Data Transfer Acknowledge
4, 8
O
DTACK1* DTACK2*
5
O
1-32
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (3 of 9) Pin Label Signal Name Device (1) I/O
1.0 Product Description
1.2 Pin Assignments
Definition
LIU Serial Interface SERDI Serial Data Input 4, 8 I Serial data input from an LIU is sampled on rising edge of SERCKO and written into Serial Data Register; addr 023. Serial bit clock provided for transmitting and receiving serial LIU data on SERDI and SERDO. SERCKO frequency is 1.024 MHz or 8.192 MHz selectable. Address and data is output to an LIU serially on SERDO. Data changes on falling edge of SERCKO. Chip select line used to select an LIU's serial port for communication. SERCS is controlled in Serial Configuration Register; addr 025. Chip select lines used to select an LIU's serial port for communication. SERCS1* and SERCS2* are independently controlled in Serial Configuration Register; addr 025.
SERCKO
Serial Clock
4, 8
O
SERDO SERCS*
Serial Data Output Serial Chip Select Serial Chip Selects
4, 8 4
O O
SERCS1* SERCS2*
8
O
Transmitter (XMTR) TCKI[4:1] TCKI[8:1] TCKI[16:1] T1ACKI TX Clock Input 4 8 5 4, 5, 8 I Primary TX line rate clocks for transmitter signals: TPOSO, TNEGO, TNRZO, MSYNCO, TDLI, and TDLCKO. If TSLIP is bypassed, TCKI also clocks TSB signals. System optionally applies T1ACKI to use for T1 AIS transmission in case the selected primary transmit clock source fails. T1ACKI is either manually or automatically switched to replace TCKI (see [AISCLK; addr 075]). Systems without a T1 AIS clock should tie T1ACKI to ground. System optionally applies E1ACKI to use for E1 AIS transmission in case the selected primary transmit clock source fails. E1ACKI is either manually or automatically switched to replace TCKI (see [AISCLK; addr 075]). Systems without an E1 AIS clock should tie E1ACKI to ground. Line rate data output from ZCS encoder changes on rising edge of TCKO. Active-high marks transmission of a positive AMI pulse. Line-rate data output from ZCS encoder changes on rising edge of TCKO. Active high marks transmission of a negative AMI pulse. Selected time slot bits are sampled on TDLCKO falling edge for insertion into the transmit output stream during external data link applications. Gapped version of TCKI for external data link applications. TDLCKO high clock pulse coincides with low TCKI pulse interval during selected time slot bits, else TDLCKO low (see [DL3_TS; addr 015]).
T1 All Ones Clock
I
E1ACKI
E1 All Ones Clock
4, 5, 8
I
TPOSO[4:1] TPOSO[8:1] TNEGO[4:1] TNEGO[8:1] TDLI[4:1] TDLI[8:1] TDLCKO[4:1] TDLCKO[8:1]
TX Positive Rail Output TX Negative Rail Output TX Data Link Input TX Data Link Clock
4 8 4 8 4 8 4 8
O
O
I
O
100054E
Conexant
1-33
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (4 of 9) Pin Label Signal Name Device (1) I/O Definition
Transmitter (XMTR) (Continued) TCKO[4:1] TCKO[8:1] TCKO[16:1] TNRZO[4:1] TNRZO[8:1] TNRZO[16:1] MSYNCO[4:1] MSYNCO[8:1] MSYNCO[16:1] TX Clock Output 4 8 5 4 8 5 4 8 5 O Line rate clock. TCKO equals selected TCKI or T1ACKI (E1ACKI). Line-rate data output from transmitter on rising edge of TCKO. TNRZO does not include ZCS encoded bipolar violations. Active high for one TCKI clock cycle to mark the first bit of TX multiframe coincident with TNRZO. Output on rising edge of TCKO.
TX Non Return to Zero Data TX Multiframe Sync
O
O
Receiver (RCVR) RCKI[4:1] RCKI[8:1] RCKI[16:1] RNRZI[4:1] RNRZI[8:1] RNRZI[16:1] RPOSI[4:1] RPOSI[8:1] RX Clock Input 4 8 5 4 8 5 4 8 I Line rate clock samples RPOSI and RNEGI or RNRZ.
RX Positive Rail Input RX Positive Rail Input
I
Line rate data input on rising edge of RCKI. Non-return to zero (NRZ) receive data. Line rate data input on rising edge of RCKI. RPOSI and RNEGI levels are interpreted as received AMI pulses, encoded as follows: RPOSI 0 0 1 1 RNEGI 0 1 0 1 RX Pulse Polarity No pulse Negative AMI pulse Positive AMI pulse Invalid (decoded as a pulse)
I
Unipolar. Non-return to zero (NRZ) data may be connected to RPOSI or RNEGI in which case the other input should be connected to ground. In this configuration RAMI [RCR0; addr 040] should be set to 1 (receive AMI line format) and DIS_LCV [RALM; addr 045] should be set to 1 (disable LCV counting and reporting). RNEGI[4:1] RNEGI[8:1] RDLO[4:1] RDLO[8:1] RX Negative Rail Input RX Data Link Output 4 8 4 8 I O Line rate data input on rising edge of RCKI. See RPOSI signal definition. Line rate NRZ data output from receiver on falling edge of RCKI. All receive data is represented at the RDLO pin. However, selective RDLO bit positions are also marked by RDLCKO for external data link applications. Gapped version of RCKI for external data link applications. RDLCKO high clock pulse coincides with low RCKO pulse interval during selected time slot bits, otherwise RDLCKO is low (see Figure 2-4, Receive External Data Link Waveforms).
RDLCKO[4:1] RDLCKO[8:1]
RX Data Link Clock Output
4 8
O
1-34
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (5 of 9) Pin Label Signal Name Device (1) I/O
1.0 Product Description
1.2 Pin Assignments
Definition
Transmit System Bus (TSB) TSBCKI[4:1] TSBCKI[8:1] TSBCKI[16:1] TSBCKI[A] TSBCKI[B] TSBCKI[C] TSBCKI[D} TSB Clock Input 4 8 5 4,5,8 5,8 5 5 I Bit clock and I/O signal timing for TSB according to system bus mode (see [SBI_CR; addr 0D0]). System chooses from one of two different clocks to act as TSB clock source (see [CMUX; addr 01A]). Rising or falling edge clocks are independently configurable for data signals TPCMI, TSIGI, TINDO and sync signals TFSYNC and TMSYNC (see [TPCM_NEG and TSYN_NEG; addr 0D4]). When configured to operate at twice the data rate, TSB clock is internally divided by 2 before clocking TSB data signals. Serial data formatted into TSB frames consisting of DS0 channel time slots and optional F-bits. One group of 24 T1 time slots or 32 E1 time slots is selected from up to four available groups; data from the group is sampled by TSBCKI, then sent towards transmitter output. Time slots are routed through transmit slip buffer (see [TSLIPn; addr 140-17F]) according to TSLIP mode (see [TSBI; addr 0D4]). F-bits are taken from the start of each TSB frame or from within an embedded time slot (see [EMBED; addr 0D0]) and optionally inserted into the transmitter output (see [TFRM; addr 072] register). Serial data formatted into TSB frames containing ABCD signaling bits for each system bus time slot. Four bits of TSIGI time slot carry signaling state for each accompanying TPCMI time slot. Signaling state of every time slot is sampled during first frame of the TSB multiframe and then transferred into transmit signaling buffer [TSIGn; addr 120-13F]. Active-high output pulse marks selective transmit system bus time slots as programmed by SBCn [addr 0E0-0FF], TINDO occurs on TSBCKI rising or falling edges as selected by TPCM_NEG (see [TSBI; addr 0D4]).
Bused TSB Clock Inputs
TPCMI[4:1] TPCMI[8:1] TPCMI[16:1] TPCMI[A] TPCMI[B] TPCMI[C] TPCMI[D]
TSB Data Input
Bused TSB Data Input
4 8 5 4,5,8 5,8 5 5
I
TSIGI[4:1] TSIGI[8:1] TSIGI[16:1]
TSB Signaling Input
4 8 5
I
TINDO[4:1] TINDO[8:1] TINDO[16:1] TINDO[A] TINDO[B] TINDO[C] TINDO[D] TFSYNC[4:1] TFSYNC[8:1] TFSYNC[16:1] TFSYNC[A] TFSYNC[B] TFSYNC[C] TFSYNC[D]
TSB Time Slot Indicator Bused TSB Time Slot Indicator
4 8 5 4,5,8 5,8 5 5 4 8 5 4,5,8 5,8 5 5
O
TSB Frame Sync
PIO
Bused TSB Frame Sync
Input or output TSB frame sync (see [TFSYNC_IO; addr 018]). TFSYNC output is active high for one TSB clock cycle at programmed offset bit location (see [TSYNC_BIT; addr 0D5]), marking offset bit position within each TSB frame and repeating once every 125 s. When transmit framer is also enabled, TSB timebase and TFSYNC output frame alignment are established by transmit framer's examination of TPCMI serial data input. When TFSYNC is programmed as an input, the low-to-high signal transition is detected and is used to align TSB timebase to programmed offset bit value. TSB timebase flywheels at 125 s frame interval after the last TFSYNC is applied.
100054E
Conexant
1-35
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (6 of 9) Pin Label Signal Name Device (1) I/O Definition
Transmit System Bus (TSB) (Continued) TMSYNC[4:1] TMSYNC[8:1] TMSYNC[16:1] TSB Multiframe Sync 4 8 5 PIO Input or output TSB multiframe sync (see [TMSYNC_IO; addr 018]). TMSYNC output is active high for one TSB clock cycle at programmed offset bit location (see [TSYNC_BIT; addr 0D5]), marking offset bit position within each TSB multiframe and repeating once every 6 ms coincident with TFSYNC. When transmit framer is also enabled, TSB timebase and TMSYNC output multiframe alignment are established by transmit framer's examination of TPCMI serial data input. When TMSYNC is programmed as an input, the low-to-high signal transition is detected and is used to align TSB timebase to programmed offset bit value and first frame of the multiframe. TSB timebase flywheels at 6 ms multiframe intervals after the last TMSYNC is applied. If system bus applies TMSYNC input, TFSYNC input is not needed.
Receive Systetm Bus (RSB) RSBCKI[4:1] RSBCKI[8:1] RSBCKI[16:1] RSBCKI[A] RSBCKI[B]} RSBCKI[C]} RSBCKI[D]} RSB Clock Input 4 8 5 4,5,8 5,8 5 5 I Bit clock and I/O signal timing for RSB according to system bus mode (see [SBI_CR; addr 0D0]). System chooses from one of two different clocks to act as RSB clock source (see [CMUX; addr 01A]). Rising or falling edge clocks are independently configurable for data signals RPCMO, RSIGO, RINDO and sync signals RFSYNC, RMSYNC (see [RPCM_NEG and RSYN_NEG; addr 0D1]). When configured to operate at twice the data rate, RSB clock is internally divided by 2 before clocking RSB data signals. Serial data formatted into RSB frames consisting of DS0 channel time slots, optional F-bits and optional ABCD signaling. Time slots are routed through receive slip buffer (see [RSLIPn; addr 1C0-1FF]) according to RSLIP mode (see [RSBI; addr 0D1]). Data for each output time slot is assigned sequentially from received time slot data according to system bus channel programming (see [ASSIGN; addr 0E0-0FF]). F-bits are output at the start of each RSB frame or at the embedded time slot location (see [EMBED; addr 0D0]). ABCD signaling is optionally inserted on a per-channel basis (see [INSERT; addr 0E0-0FF]) from the local signaling buffer (see [RLOCAL; addr 180-19F]) or from the receive signaling buffer [RSIGn; addr 1A0-1BF]. When enabled, robbed bit signaling or CAS reinsertion is performed according to T1/E1 mode: The eighth time slot bit of every sixth T1 frame is replaced, or the 4-bit signaling value in the E1 time slot 16 is replaced. Active high output pulse marks selective receive system bus time slots as programmed by SBCn [addr 0E0-0FF]. RINDO occurs on RSBCKI rising or falling edges as selected by RPCM_NEG (see [RSBI; addr 0D1]). Only available in Multiplexed System Bus mode on CX28395 (see [FCR; addr 080]).
Bused RSB Data Input
RPCMO[4:1] RPCMO[8:1] RPCMO[16:1] RPCMO[A] RPCMO[B] RPCMO[C] RPCMO[D]
RSB Data Output
Bused RSB Data Output
4 8 5 4,5,8 5,8 5 5
O
RINDO[4:1] RINDO[8:1] RINDO[A] RINDO[B] RINDO[C] RINDO[D]
RSB Time Slot Indicator Bused RSB Time Slot Indicator
4 8 4,5,8 5,8 5 5
O
1-36
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (7 of 9) Pin Label Signal Name Device (1) I/O
1.0 Product Description
1.2 Pin Assignments
Definition
Receive Systetm Bus (RSB) (Continued) RSIGO[4:1] RSIGO[8:1] RSIGO[16:1] RSB Signaling Output 4 8 5 O Serial data formatted into RSB frames consisting of ABCD signaling bits for each system bus time slot. Four bits of RSIGO time slot carry signaling state for each accompanying RPCMO time slot. Local or through signaling bits are output in every frame for each time slot and updated once per RSB multiframe, regardless of per-channel RPCMO signaling reinsertion. Input or output RSB frame sync (see [RFSYNC_IO; addr 018]). RFSYNC output is active high for one RSB clock cycle at programmed offset bit location (see [RSYNC_BIT; addr 0D2]), marking offset bit within each RSB frame and repeating once every 125 s. RSB timebase and RFSYNC output frame alignment begins at an arbitrary position and changes alignment according to RSLIP mode (see [RSBI; addr 0D1]). When RFSYNC is programmed as an input, the low-to-high signal transition is detected and used to align RSB timebase to the programmed offset. RSB timebase flywheels at 125 s frame interval after the last RFSYNC is applied. Input or output RSB multiframe sync (see [RMSYNC_IO; addr 018]). RMSYNC output is active high for one RSB clock cycle at programmed offset bit location (see [RSYNC_BIT; addr 0D2]), marking offset bit within each RSB multiframe and repeating once every 6 ms coincident with RFSYNC. RSB timebase and RMSYNC output multiframe alignment begins at an arbitrary position and changes alignment according to RSLIP mode (see [RSBI; addr 0D1]). When RMSYNC is programmed as an input, the low-to-high signal transition is detected and is used to align the RSB timebase to programmed offset and first frame of the multiframe. RSB timebase flywheels at 6 ms multiframe interval after the last RMSYNC is applied. Active high indicates that signaling bit updates are suspended for both receive signaling buffer [RSIGn; addr 1A0-1BF] and stack [STACK; addr 0DA] register. SIGFRZ is clocked by RSB clock, goes high coincident with receive loss of frame alignment (see RLOF; addr 047) and returns low 6-9 ms after recovery of frame alignment.
RFSYNC[4:1] RFSYNC[8:1] RFSYNC[16:1] RFSYNC[A] RFSYNC[B] RFSYNC[C] RFSYNC[D]
RSB Frame Sync
Bused RSB Frame Sync
4 8 5 4,8,5 5,8 5 5
PIO
RMSYNC[4:1] RMSYNC[8:1] RMSYNC[16:1]
RSB Multiframe Sync
4 8 5
PIO
SIGFRZ[4:1] SIGFRZ[8:1]
Signaling Freeze
4 8
O
100054E
Conexant
1-37
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (8 of 9) Pin Label Signal Name Device (1) I/O Definition
Joint Test Access Group (JTAG) TCK TDI1, TDI2 JTAG Clock JTAG Test Data Input 4, 5, 8 5 I I Clock input samples TDI on rising edge and outputs TDO on falling edge. Test data input per IEEE Std 1149.1-1990. Used for loading all serial instructions and data into internal test logic. Sampled on the rising edge of TCK. TDI can be left unconnected if it is not being used because it is pulled up internally. TDI1 is the test data input for framers 1 to 8, TDI2 is the test data input for framers 9 to 16. Test data input per IEEE Std 1149.1-1990. Used for loading all serial instructions and data into internal test logic. Sampled on the rising edge of TCK. TDI can be left unconnected if it is not being used because it is pulled up internally. Active low test mode select input per IEEE Std 1149.1-1990. Internally pulled-up input signal used to control the test-logic state machine. Sampled on the rising edge of TCK. TMS can be left unconnected if it is not being used because it is pulled up internally. Test data output per IEEE Std 1149.1-1990. TDO is a three-state output used for reading all serial configuration and test data from internal test logic. Updated on the falling edge of TCK. Test data output per IEEE Std, 1149.1-1990. TDO is a three-state output used for reading all serial configuration and test data from internal test logic. Updated on the falling edge of TCK. TDO1 is the test data output for framers1 to 8, TDO2 is the test data output for framers 9 to 16. Active low input to initialize Tap Controller.
TDI
JTAG Test Data Input
4, 8
I
TMS
JTAG Test mode Select
4, 5, 8
I
TDO
JTAG Test Data Output
4, 8
O
TDO1, TDO2
JTAG Test Data Output
5
O
TRST*
JTAG Reset
4, 5, 8
I Power Supply
VDD VSS VGG
Power Ground High Voltage Power
4, 5, 8 4, 5, 8 4, 5, 8
I I I
+3.3 Vdc 5%. 0 Vdc. +3.3 Vdc 5%. Connect to +5 Vdc 5% to ensure 5 V tolerance in applications which include 5 V logic driving signals.
1-38
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (9 of 9) Pin Label Signal Name Device (1) I/O
Test TSTO[16:1] TSTI[16:1]
NOTE(S):
(1)
1.0 Product Description
1.2 Pin Assignments
Definition
Test Output Test Input
5 5
O I
Test output. Leave disconnected for normal operation. Test input. Connect through 50k ohm pull-up resistor to VDD for normal operation.
1. 2. 3. 4.
4 = CX28394 5 = CX28395 8 = CX28398 All RSB and TSB outputs can be placed in high-impedance state (see SBI_OE; addr 0D0). I = Input, O = Output PIO = Programmable I/O; controls located at address 018. Multiple signal names show mutually exclusive pin functions.
100054E
Conexant
1-39
1.0 Product Description
1.2 Pin Assignments
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
1-40
Conexant
100054E
2
2.0 Circuit Description
2.1 Functional Block Diagram
Figures 2-1 and 2-2 illustrate detailed framer block diagrams for non-multiplexed and multiplexed system bus modes. To show the details of these circuits, individual block diagrams of the functions listed below have been created and are placed, along with descriptions, throughout this section: * * * * * * * Receiver (RCVR) Receive System Bus (RSB) Transmit System Bus (TSB) Transmitter (XMTR) Microprocessor Interface (MPU) Joint Test Access Group Port (JTAG) Serial Port (SERIO)
100054E
Conexant
2-1
2.0 Circuit Description
2.1 Functional Block Diagram
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-1. Detailed Framer Block Diagram (Multiplexed System Bus Mode)
MCLK MOTO* SYNCMD SYSCKI CS* Microprocessor Port AS* DS* R/W* DTACK* AD[7:0] A[11:0] INTR* ONESEC RST* RCKI[1] TCKO[1] Framer Loopback Line Loopback RNRZI[1]
RDLO[1] (1)
RDLCKO[1] (1) RSIG Buffer RSIG Local RSLIP Buffer AIS
Per-Channel Remote Loopback
(1) (1)
RPOSI[1] RNEGI[1]
External DLINK PRBS/Inband LB DLINK2 Buffer DLINK1 Buffer Sa-Byte/BOP PDV Monitor RZCS Decoder Error Counters Alarm Monitor Receiver Framer Receive Timebase
RSIG Stack RSIGO[1]
RPCMO[A]
Per-Channel Local Loopback
SIGFRZ[1] RINDO[A] RFSYNC[A] RMSYNC[1] RSBCKI[A] TCKI E1ACKI TIACKI
RPHASE
RSB Timebase
Clock Monitor Transmitter Timebase TPHASE TSB Timebase Transmit Framer TSLIP Buffer TSIG Buffer TSIG Buffer
TSBCKI[A] TFSYNC[A] TMSYNC[1] TINDO[A]
(1)
SERCS[1:0] SERCLK SERDO SERI Serial Port
T1/E1 Frame Insert External Dlink DLINK2 Buffer DLINK1 Buffer Sa-Byte/BOP PRBS Inband LB Alarm/Error Insert PDV Enforcer
(1) TPOSO[1] (1) TNEGO[1]
TNRZO[1] MSYNCO [1]
TZCS Encoder
TPCMI[A]
TCK JTAG Port TMS TDI TDO TRST*
TSIGI[1]
(1) (1) TDLI[1] TDLCKO[1]
FRAMER 1 FRAMER 2
8394-8-5_001
NOTE(S):
(1)
Not available on CX28395.
2-2
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-2. Detailed Framer Block Diagram (Non-multiplexed System Bus Mode)
2.0 Circuit Description
2.1 Functional Block Diagram
MCLK MOTO* SYNCMD SYSCKI CS*
Microprocessor Port
RDLO[1] (1)
RDLCKO[1] (1) RSIG Buffer RSIG Local RSLIP Buffer AIS
Per-Channel Remote Loopback
RNRZI[1]
(1) (1)
AS* DS* R/W* DTACK* AD[7:0] A[11:0] INTR* ONESEC RST*
RPOSI[1] RNEGI[1]
External DLINK PRBS/Inband LB DLINK2 Buffer DLINK1 Buffer Sa-Byte/BOP PDV Monitor RZCS Decoder Error Counters Alarm Monitor Receiver Framer Receive Timebase
RSIG Stack RSIGO[1]
RPCMO[1]
Per-Channel Local Loopback
SIGFRZ[1] RINDO[1] RFSYNC[1] RMSYNC[1] RSBCKI[1]
RPHASE
RSB Timebase
RCKI[1] TCKO[1]
Framer Loopback Line Loopback
TCKI[1] E1ACKI TIACKI Clock Monitor Transmitter Timebase TPHASE TSB Timebase Transmit Framer TSLIP Buffer TSIG Buffer TSIG Buffer FRAMER 1 FRAMER N
8394-8-5_001a
TSBCKI[1] TFSYNC[1] TMSYNC[1] TINDO[1]
(1)
SERCS[1:0] SERCLK SERDO SERI
Serial Port
T1/E1 Frame Insert External Dlink DLINK2 Buffer DLINK1 Buffer Sa-Byte/BOP PRBS Inband LB Alarm/Error Insert PDV Enforcer
(1) (1)
TPOSO[1] TNEGO[1] TNRZO[1]
TZCS Encoder
TPCMI[1]
TCK
JTAG Port
MSYNCO [1]
TSIGI[1]
TMS TDI TDO TRST*
(1) (1) TDLI[1] TDLCKO[1]
NOTE(S):
(1)
Not available on CX28395.
100054E
Conexant
2-3
2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.2 Receiver
The Receiver (RCVR) inputs single rail NRZ data or decodes positive and negative rail NRZ data into single rail NRZ data. The RCVR, illustrated in Figure 2-3, consists of the following elements: Receive Zero Code Suppression (RZCS) Decoder, In-Band Loopback Code Detector, Error Counters, Error Monitor, Alarm Monitor, Test Pattern Receiver, Receive Framer, External Receive Data Link, and Receive Data Links.
Figure 2-3. RCVR Diagram
RDLCKO MPU Registers
RDLO
RNRZI
External DLINK PRBS/Inband LB Sa-Byte RPDV Monitor RZCS Decoder Error Monitor Error Counters Alarm Monitor Receive Framer Receiver Timebase
DLINK1 MOP/BOP
DLINK2 MOP
RPOSI RNEGI
RNRZ
To RSB
Line Loopback
Framer Loopback
RCKI
2.2.1 ZCS Decoder
The Receive Zero Code Suppression (RZCS) decoder is applicable only to the CX28394 and CX28398. The decoder decodes the dual rail data (bipolar) into single rail data (unipolar). The Receive AMI bit (RAMI) in the Receiver Configuration register [RCR0; addr 040] controls whether the received signal is B8ZS/HDB3 decoded, depending on T1/E1N [addr 001] line rate selection, or if the RZCS decoder is bypassed. If the line code is unknown, the ZCSUB bit in Receive Line Code Status [RSTAT; addr 021] indicates the RPOSI/RNEGI input received one or more B8ZS/HDB3 substitution patterns. If the line code is B8ZS/HDB3-encoded, the RZCS bit in RCR0 should be set to keep the LCV counter from counting BPVs that are part of the B8ZS/HDB3 code.
2-4
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.2 Receiver
2.2.2 In-Band Loopback Code Detection
The in-band loopback code detector circuitry detects receive data with in-band codes of configurable value and length. These codes can be used to request loopback of terminal equipment signals or other user specified applications. The two codes are referred to as loopback-activate and loopback-deactivate, although the detectors need not be used only for loopback codes. Generally, any repeating 1-7 bit pattern can be selected. The loopback application is described in Section 9.3.1 of ANSI T1.403-1995. The loopback activate code is set in the Loopback Activate Code Pattern [LBA; addr 043]. The loopback deactivate code is set in the Loopback Deactivate Code Pattern [LBD; addr 044]. The sequence length for the loopback activate and deactivate codes can be programmed for 4, 5, 6, or 7 bits by setting the code length bits of the Receive Loopback Code Detector Configuration register [RLB; addr 042]. Shorter codes can be programmed by repeating the expected pattern (e.g. 3+3 bit code programmed as 6-bit code).
T1 In-Band Loopback Codes Activate 00001 Deactivate 001
When a loopback code is detected, the LOOPUP or LOOPDN status bit is set in Alarm 2 register [ALM2; addr 048], and the corresponding LOOPUP or LOOPDN bit in Alarm 2 Interrupt Status register (ISR6; addr 005] is set. The loopback detection interrupt can be enabled using the Alarm 2 Interrupt Enable register [IER6; addr 00D]. When enabled, a loop-up or loop-down code detection causes the Alarm 2 Interrupt bit [ALARM2] to be set in the Interrupt Request register [IRR; addr 003] and generates an interrupt. Since loopbacks are not automatically initiated, the processor must intercept and interpret the interrupt status condition to determine when it must enable or disable the loopback control mechanism (e.g., LLOOP; addr 014).
2.2.3 Error Counters
The following Performance Monitoring (PM) counters are available in the RCVR: * * * * Framing Bit Errors (FERR) CRC Errors (CERR) Line Code Violations (LCV) Far End Block Errors (FEBE)
All PM count registers are reset on read unless LATCH_CNT is set in the Alarm/Error/Counter Latch Configuration register [LATCH; addr 046]. LATCH_CNT enables the one-second latching of counts coincident with the one-second timer interrupt [ISR6; addr 005]. One-second latching of PM counts is required if AUTO_PRM responses are enabled. All PM counters can be disabled during RLOF, RLOS, and RAIS, using the STOP_CNT bit in the LATCH register. Note that if STOP_CNT is negated, error monitoring during RLOF conditions will detect FERR, CERR, and FEBE according to the last known frame alignment.
100054E
Conexant
2-5
2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.2.3.1 Frame Bit Error Counter
The 12-bit Framing Bit Error Counter [FERR; addr 050 and 051] increments every time a receive Ft, Fs, T1DM, FPS, or FAS error is detected. Fs (T1) and NFAS (E1) errors can be included in the FERR count by setting FS_NFAS in Receive Alarm Signal Configuration [RALM; addr 045]. An interrupt is available to indicate that the FERR counter overflowed in the Counter Overflow Interrupt Status register [ISR4; addr 007]. The 10-bit Cyclic Redundancy Check Error Counter [CERR; addr 052 and 053] increments each time a receive CRC4 (E1) or CRC6 (T1) error is detected. An interrupt is available to indicate that CERR counter overflowed in ISR4. The 16-bit Line Code Violation Error Counter [LCV; addr 054 and 055] increments each time a receive Bipolar Violation (BPV)--not including line coding--is detected. The LCV count can include EXZ if EXZ_LCV in the Receive Alarm Signal Configuration register [RALM; addr 045] is set. EXZ can be configured [RZCS; addr 040] to be 8 or 16 successive zeros, following a one. An interrupt is available to indicate that the LCV counter overflowed in ISR4. The 10-bit Far End Block Error (FEBE) counter [FEBE; addr 056 and 057] increments every time the RCVR encounters an E1 far-end block error. An interrupt is available to indicate that the FEBE counter overflowed in ISR4.
2.2.3.2 CRC Error Counter 2.2.3.3 LCV Error Counter
2.2.3.4 FEBE Counter
2.2.4 Error Monitor
The following signal errors are detected in the RCVR: * * * * * Frame Bit Error (FERR) MFAS Error (MERR) CAS Error (SERR) CRC Error (CERR) Pulse Density Violation (PDV)
Each error type has an interrupt enable bit that enables an interrupt to occur marking the event, and an interrupt register bit that is read by the interrupt service routine to determine which event caused the interrupt. All error status registers are reset on read unless the LATCH_ERR bit is set in the Alarm/Error/Counter Latch Configuration register [LATCH; addr 046]. LATCH_ERR enables the one-second latching of alarms coincident with the one-second timer interrupt [ISR6; addr 005]. With LATCH_ERR enabled, any error detected during the one second interval is latched and held during the following one-second interval. LATCH_ERR allows the processor to gather error statistics based on the one-second interval. 2.2.4.1 Frame Bit Error FERR is reported for the receive direction in the Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0; addr 00B]. FERR indicates that one or more Ft/Fs/FPS frame-bit errors or FAS-pattern errors occurred since the last time the interrupt status was read. The FERR type is determined by the receive framer's configuration [CR0; address 001].
2-6
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.2 Receiver
2.2.4.2 MFAS Error
When CRC4 framing is enabled, MERR is reported for the receive direction in the Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0; addr 00B]. MERR is applicable only in E1 mode, and indicates that one or more MFAS pattern errors occurred since the interrupt status was last read. When CAS framing is enabled, SERR is reported for the receive direction in the Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0; addr 00B]. SERR is only applicable in E1 mode, and indicates that one or more errors were received in the TS16 Multiframe Alignment Signal (MAS) since the interrupt status was last read. CERR is reported for the receive direction in the Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0; addr 00B]. CERR is only applicable in T1 ESF and E1 MFAS modes, and indicates that one or more bit errors were found in the CRC4/CRC6 pattern block since the interrupt status was last read. PDV is reported when the receive signal does not meet the pulse density requirements of ANSI T1.403-1995 (Section 5.6). A PDV is declared when more than 15 consecutive zeros or the average ones density falls below 12.5%. RPDV is reported for the receive direction in the Alarm 1 Interrupt Status register [ISR7; addr 004].
2.2.4.3 CAS Error
2.2.4.4 CRC Error
2.2.4.5 Pulse Density Violation
2.2.5 Alarm Monitor
The following signal alarms are detected in the RCVR: * * * * * * * * * Loss Of Frame (LOF) Loss Of Signal (LOS) Receive Analog Loss Of Signal (RALOS) Alarm Indication Signal (AIS) Remote Alarm Indication (RAI) or Yellow Alarm (YEL) Multiframe Yellow Alarm (MYEL) Severely Errored Frame (SEF) Change Of Frame Alignment (COFA) Multiframe AIS (MAIS)
Each alarm has the following: a status register bit that reports the real-time status of the event; an interrupt enable bit that enables an interrupt to mark the event; and an interrupt register bit read by the interrupt service routine to identify the event that caused the interrupt. All alarm status registers are reset on read unless the LATCH_ALM bit is set in the Alarm/Error/Counter Latch Configuration register [LATCH; addr 046]. LATCH_ALM enables the one-second latching of alarms coincident with the one-second timer interrupt [ISR6; addr 005]. With LATCH_ALM enabled, any alarm detected during the one-second interval is latched and held during the following one-second interval.
100054E
Conexant
2-7
2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.2.5.1 Loss of Frame
Receive Loss Of Frame (RLOF) is declared when the receive data stream does not meet the framing criteria specified in the Receiver Configuration register [RCR0; addr 040]. If the line rate is E1 [T1/E1N; addr 001], RLOF is the logically OR'ed status of FAS, MFAS, and CAS alignment. These alignments, FRED, MRED and SRED, respectively, are available separately in the Alarm 3 Status register [ALM3; addr 049]. Once RLOF is declared the LOF[1:0] bits in ALM3 report the reason for E1 loss of frame alignment. In T1 mode, RLOF is equal to FRED. The RLOF real-time status is available in Alarm 1 Status register [ALM1; addr 047], and the interrupt status is set in the Alarm 1 Interrupt Status register [ISR7; addr 004]. The RLOF interrupt is enabled by setting RLOF in the Alarm 1 Interrupt Enable register [IER7; addr 00C]. An FRED count [FRED[3:0]; addr 05A] is also available in the SEF/LOF/COFA Alarm Counter [AERR; addr 05A]. An interrupt in Counter Overflow Interrupt Status [ISR4; addr 007] indicates that the FRED counter overflowed. While T1 framing mode is enabled, the RLOF status and RLOF interrupt status are integrated over 2.0 to 2.5 seconds if the RLOF_INTEG bit is set in the Receive Alarm Signal Configuration register [RALM; addr 045]. The FRED count is unaffected by RLOF_INTEG. If the line rate is T1, the criteria for Receive Loss Of Signal (RLOS) is 100 contiguous zeros (consistent with the standard requirement of 175 75 zeros). If the line rate is E1, the criteria for RLOS is 32 contiguous zeros. RLOS is cleared upon detecting an average pulse density of at least 12.5% (occurring during a period of 175 75 bits starting with the receipt of a pulse, and where no occurrences of 100/32 contiguous zeros are detected). The RLOS real-time status is available in ALM1, and the interrupt is available in ISR7. The XMTR can be configured to automatically generate an Alarm Indication Signal (AIS) in the transmit direction when RLOS is declared (see AUTO_AIS [TALM; addr 075]). RALOS [ALM1; addr 047] can be configured to report loss of receive clock (RCKI) or loss of receive signal [RLOS; addr 047] for 1 msec depending on the RALOS configuration bit [RAL_CON; addr 020]. RALOS status is provided for compatibility with ANSI T1.431 loss of signal detection requirements; and works in conjunction with LIUs which detect loss of signal if the received signal level falls below a certain threshold and which have a signal `squelch' feature. If RAL_CON is set for loss of signal, RALOS indicates that all zeros have been received for at least 1 msec (RLOS is active for 1 msec). If RAL_CON is set for loss of clock, RALOS becomes active (1) if the receive clock on the RCKI pin is not present, and inactive (0) if the clock is present. If the line rate is T1 [T1/E1N; addr 001], the criteria for Receive Alarm Indication Signal (RAIS) is the reception of four or fewer zeros in a period of 3 ms (4632 bits) and assertion of RLOF. If the line rate is E1, RAIS is set if two consecutive double frames each contain two or fewer zeros out of 512 bits and FAS alignment is lost [FRED; addr 049]. The RAIS real-time status is available in ALM1. The RAIS interrupt is available in ISR7. The criteria for Yellow Alarm (YEL) is described in Table 3-13, Receive Yellow Alarm Set/Clear Criteria. YEL real-time status is available in ALM1; YEL interrupt is available in ISR7.
2.2.5.2 Loss of Signal
2.2.5.3 Receive Analog Loss of Signal
2.2.5.4 Alarm Indication Signal
2.2.5.5 Yellow Alarm
2-8
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.2 Receiver
2.2.5.6 Multiframe YEL
The criteria for Multiframe Yellow Alarm is described in Table 3-13, Receive Yellow Alarm Set/Clear Criteria. The MYEL real-time status is available in ALM1, and the interrupt is available in ISR7. A SEF is reported when the receive signal does not meet the requirements of ANSI T1.231. SEF real-time status is available in ALM3. A 2-bit counter is also available [SEF; addr 05A]. An interrupt is available in ISR4 to indicate that the SEF counter overflowed. Each COFA increments a 2-bit counter [COFA; addr 05A]. An interrupt is available in ISR4 to indicate that the COFA counter overflowed. Receive Multiframe AIS (RMAIS) is reported when the receive TS16 signal contains three or fewer zeros out of 128 bits in each multiframe over two consecutive multiframes, according to the requirements of ITU-T Recommendation G.775. RMAIS is only checked in E1 CAS mode. RMAIS real-time status is available in ALM3 [addr 049].
2.2.5.7 Severely Errored Frame
2.2.5.8 Change of Frame Alignment 2.2.5.9 Receive Multiframe AIS
2.2.6 Test Pattern Receiver
The test pattern receiver circuitry can sync on framed or unframed PRBS patterns and count bit errors. This feature is particularly useful for system diagnostics, production testing, and test equipment applications. The PRBS patterns available include 2E11-1, 2E15-1, 2E20-1, and 2E23-1. Each pattern can optionally include Zero Code Suppression (ZCS). The Receive Test Pattern Configuration register [RPATT; addr 041] controls the test pattern receiver circuit. The BSTART control bit (in RPATT) must be active to enable the test pattern receiver and to begin counting bit errors. RPATT controls the PRBS pattern, ZCS setting (ZLIMIT), and T1/E1 framing (FRAMED). RPATT selects which PRBS pattern the receiver should hunt for pattern sync. ZLIMIT selects the maximum number of consecutive zeros the pattern is allowed to contain. FRAMED mode informs the PRBS pattern receiver not to search for the pattern in the frame bit in T1 mode or search for the pattern in time slot 0 (and time slot 16 if CAS framing is selected) in E1 mode. CAS framing is selected by setting RFRAME[3] to 1 in the Primary Control register [CR0; addr 001]. If FRAMED is disabled, the PRBS pattern receiver searches all time slots for the test pattern. The RESEED bit in RPATT informs the receive PRBS sync circuit to begin a PRBS pattern search. Once the search begins, any additional writes to RESEED restarts the pattern sync search at a different point in the pattern. The time to sync depends on the pattern and number of bit errors in the pattern. Pattern sync is reported (when found) in PSYNC status of the Pattern Interrupt Status register [ISR0; addr 00B]. Next, the PRBS Pattern Error counter [BERR; addr 058 and 059] counts bit errors detected on the incoming pattern, provided that BSTART remains active. Error counting stops if the BSTART bit is cleared. The BERR counter is reset to zero after every read, or latched on every ONESEC interrupt as selected by LATCH_CNT [addr 046]. An interrupt is available to indicate the BERR counter overflowed in ISR4.
100054E
Conexant
2-9
2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.2.7 Receive Framing
Two framers are in the receive data stream: an offline framer and an online frame status monitor. The offline framer recovers receive frame alignment; the online framer monitors frame alignment patterns and recovers multiframe alignment in E1 modes. Table 2-1 lists supported RCVR framing modes. Frame and multiframe synchronization criteria used by the framers, as well as the monitoring criteria of the online framer, are selected in RFRAME[3:0] of the Primary Control register [CR0; addr 001]. Table 2-2 details framing loss/recovery criteria. Receive frame synchronization is initiated by the online framer's activation of the Receive Loss Of Frame (RLOF) status bit in the Alarm 1 Status register [ALM1; addr 047]. The RLOF criteria is set in the RLOFA, RLOFB, RLOFC, and RLOFD bits of the Receiver Configuration register [RCR01; addr 040]. The online framer supports the following LOF criteria for T1: 2 out of 4, 2 out of 5, and 2 out of 6. For E1, the online framer supports 3 out of 3, with or without 915 out of 1000 CRC errors. When RLOF is asserted, the offline framer automatically starts searching the receive data stream for a new frame alignment, provided that receive framing is enabled [RABORT; addr 040]. If receive framing is disabled, the offline framer does not automatically search for the frame alignment, but waits for a reframe command [RFORCE; addr 040] to start a frame alignment search. If RLOF integration is enabled [RLOF_INTEG; addr 045] the RLOF status [ALM1; addr 047] and RLOF interrupt status [ISR7; addr 004] is integrated for 2.0 to 2.5 seconds. The online framer continuously monitors for loss of frame (RLOF) condition [ALM1; addr 047] and searches for E1 multiframe alignment after basic frame alignment is recovered by the offline framer. Receive multiframe alignment is declared when multiframe alignment criteria are met. The receive online framer reports multiframe errors, as well as frame errors and CRC errors in the Error Interrupt Status [ISR5; addr 006]. The offline framer is shared between the RCVR and XMTR and can search only in one direction at any time. Consequently, the processor arbitrates which direction is searched by enabling the reframe request (RLOF and TLOF) for that direction.
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Quad/x16/Octal--T1/E1/J1 Framers
Table 2-1. Receive Framer Modes T1/E1N
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
2.0 Circuit Description
2.2 Receiver
RFRAME[3:0]
000X 001X 010X 011X 100X 101X 110X 111X 0000 0001 0100 0101 0110 1000 1001 1100 1101 FAS Only
Receive Framer Mode
FAS Only + BSLIP FAS + CRC FAS + CRC + BSLIP FAS + CAS FAS + CAS + BSLIP FAS + CRC + CAS FAS + CRC + CAS + BSLIP FT Only ESF + No CRC (FPS only) SF SF + JYEL SF + T1DM SLC + FSLOF SLC ESF + Mimic CRC ESF + Force CRC
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2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 2-2. Criteria for Loss/Recovery of Receive Framer Alignment Mode
FAS
Description
Basic Frame Alignment (BFA) is recovered when the following search criteria are satisfied: * FAS pattern (0011011) is found in frame N. * Frame N+1 contains bit 2 equal to 1. * Frame N+2 also contains FAS pattern (0011011). During FAS-only modes, BFA is recovered when the following search criteria are satisfied: * FAS pattern (0011011) is found in frame N. * No mimics of the FAS pattern are present in frame N+1. * FAS pattern (0011011) is found in frame N+2.
NOTE(S): If FAS pattern is not found in frame N+2, or if FAS mimic is found in frame N+1, the search restarts in
frame N+2. Loss of FAS frame alignment (FRED) is declared when one of the following criteria is met: * Three consecutive FAS pattern errors are detected when the FAS pattern consists of a 7-bit (x0011011) pattern in FAS frames and--if FS_NFAS is also active [addr 045]--the FAS pattern includes bit 2 of NFAS frames. * Loss of MFAS (MRED) is due to 915 or more CRC errors out of 1000. * Failure to locate two valid MFAS patterns within 8 ms after BFA.
NOTE(S): In all cases, FRED causes next search for FAS alignment to begin 1 bit after the current FAS location.
BSLIP
FAS Bit Slip Enable. Applicable only for Dutch PTT national applications. If BSLIP is enabled, the online framer is allowed to change RX timebase by 1 bit when a 1-bit FAS pattern slip is detected. BSLIP does not affect the offline framer's search criteria. CRC4 Multiframe Alignment is recovered when the following search criteria are satisfied: * BFA is recovered, identifying FAS and NFAS frames. * Within 8 ms after BFA, bit 1 of NFAS frames contains two MFAS patterns (001011xx). The second MFAS must be aligned with respect to first MFAS, but the second MFAS pattern is not necessarily received in consecutive frames. * Within 8 ms after BFA, bit 1 of NFAS frames contains the second MFAS pattern (001011xx), aligned to first MFAS. Loss of MFAS alignment (MRED) declared when one of the following criteria is met: * 915 or more CRC4 errors out of 1000 (submultiframe) blocks. * Loss of FAS (FRED).
NOTE(S): If Disable 915 CRC Reframe is set [RLOFD; addr 040], then MRED is activated only by FRED.
MFAS
CAS
CAS Multiframe Alignment is recovered when the following search criteria are satisfied: * BFA is recovered, identifying TS0 through TS31. * MAS (0000xxxx) multiframe alignment signal pattern is found in the first 4 bits of TS16, and 8 bits of TS16 in preceding frame contains nonzero value. Loss of CAS alignment (SRED) is declared when one of the following criteria is met: * Two consecutive MAS pattern errors are detected. * TS16 contains all zeros in two multiframes (32 consecutive frames). * Loss of FAS (FRED).
FT Only
Terminal frame alignment is recovered when: The first valid Ft pattern (1010) is found in 12 alternate F-bit locations (3 ms), where F-bits are separated by 193 bits. During Ft-only mode, loss of frame alignment (FRED) is declared when: Number of Ft bit errors detected meets selected loss of frame criteria [RLOFA-RLOFC; addr 040].
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Table 2-2. Criteria for Loss/Recovery of Receive Framer Alignment Mode
SF
2.0 Circuit Description
2.2 Receiver
Description
Superframe alignment is recovered when: * Terminal frame alignment is recovered, identifying Ft bits. * Depends on SF submode: If JYEL, only Ft bits are used, Fs bits are ignored. If no JYEL, SF pattern (001110) found in Fs bits. During any SF mode, loss of frame alignment (FRED) is declared when: Number of frame errors detected--either Ft or Fs bit errors--meets selected loss of frame criteria [RLOFA-RLOFC; addr 040]. FS_NFAS [addr 045] determines whether Fs bits are included in error count.
SLC
Superframe alignment is recovered when: Terminal frame alignment is recovered, identifying Ft bits. SLC pattern (refer to Table A-3, SLC-96 Fs Bit Contents) is found in 16 of 36 Fs bits, according to Bellcore TR-TSY-000008. During SLC modes without FSLOF, loss of frame alignment (FRED) is declared when: Number of Ft bit errors detected meets selected reframe criteria [RLOFA-RLOFC; addr 040].
FSLOF
FSLOF instructs the online framer to monitor 16 of 36 Fs bits (SLC multiframe pattern) for loss of frame alignment criteria. FS_NFAS [addr 045] must also be set to include Fs bits in loss of frame. FSLOF does not affect the offline framer's search criteria. Extended Superframe alignment is recovered when: A valid FPS candidate is located (001011). Candidate bits are each separated by 772 digits and are received without pattern errors. If there is only one valid FPS candidate and the mode is one of the following: No CRC mode--align to FPS, regardless of CRC6 comparison. Mimic CRC mode--align to FPS, regardless of CRC6 comparison. Force CRC mode--align to FPS, only if CRC6 is correct. If there are two or more valid FPS candidates and the mode is one of the following: No CRC mode--do not align (INVALID status). Mimic CRC mode--align to first FPS with correct CRC6. Force CRC mode--align to first FPS with correct CRC6. During any ESF mode, loss of frame alignment (FRED) is declared when: Number of FPS pattern errors detected meets selected loss of frame criteria [RLOFA-RLOFC; addr 040].
ESF
T1DM
During T1DM mode, frame alignment is recovered in two steps: 1. A 6-bit T1DM pattern (10111xx0) is found. 2. A valid F-bit pattern (Ft, Fs, or FPS) is found in the first six consecutive frames of the 12-frame cycle aligned to the T1DM pattern. During T1DM mode, loss of frame alignment (FRED) is declared when: Number of frame errors detected, either Ft, Fs, or T1DM errors, meets selected loss of frame criteria [RLOFA-RLOFC; addr 040]. FS_NFAS [addr 046] does not affect T1DM mode.
NOTE(S): To be compatible with Bellcore TA-TSY-000278, the processor must select SF + T1DM framer mode
and reframe criteria = 2 out of 6 F-bit errors [RLOFA-RLOFC; addr 040].
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2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
The offline framer waits until the current search is complete (see [FSTAT; addr 017]) before checking for pending LOF reframe requests. If both online framers have pending reframe requests, the offline framer aligns to the direction opposite from that which was most recently searched. For example, if TLOF is pending at the conclusion of a receive search which timed out without finding alignment, the offline framer switches to search in the transmit direction. The TLOF switchover is prevented in the preceding example if the processor asserts TABORT to mask the transmit reframe request. TABORT does not affect TLOF status reporting. For applications that frame in only one direction, the opposite direction should be masked. If, at the conclusion of a receive search, TLOF status is asserted but masked by TABORT, the offline framer continues to search in the receive direction. For applications that frame in both directions, the processor can allow the offline framer to automatically arbitrate among pending reframe requests, or may elect to manually control reframe precedence. An example of manual control follows:
1 2 3 4 5 Initialize RABORT = 1 and TABORT = 1 Enable RLOF and TLOF interrupts Read clear pending ISR interrupts Release RABORT = 0 Call LOF Service Routine if either RLOF or TLOF interrupt; { (check current LOF status [ALM1, 2; addr 047, 048] If RLOF recovered and TLOF lost --Assert RABORT = 1 --Release TABORT = 0 If RLOF lost or TLOF recovered --Assert TABORT = 1 --Release RABORT = 0 }
The status of the offline framer can be monitored for diagnostic purposes using the Offline Framer Status register [FSTAT; addr 017]. The register reports the following: whether the offline framer is looking at the receive or transmit data streams (RX/TXN); whether the framer is actively searching for a frame alignment (ACTIVE); whether the framer found multiple framing candidates (TIMEOUT); whether the framer found frame sync (FOUND); and whether the framer found no frame alignment candidates (INVALID). Note that these status bits are updated in real time and might be active for only very short (1-bit) periods of time. Table 2-1 lists the receive framer modes.
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2.0 Circuit Description
2.2 Receiver
2.2.8 External Receive Data Link (CX28394 and CX28398 Only)
The External Data Link (DL3) provides signal access to any bit(s) in any time slot of all frames, odd frames, or even frames, including T1 framing bits. Pin access to the DL3 receiver is provided through RDLCKO and RDLO. These two pins serve as the DL3 clock output (RDLCKO) and data output (RDLO). The data link mode of the pins is selected using the RDL_IO bit in the Programmable Input/Output register [PIO; addr 018]. Control of DL3 is provided in two registers: External Data Link Channel [DL3_TS; add 015] and External Data Link Bit [DL3_BIT; addr 016]. RDL3 is set up by selecting the bit(s) (DL3_BIT) and time slot [TS[4:0]; addr 015] to be monitored, and then enabling the data link [DL3EN; addr 015], which starts the RDLCKO and TDLCKO gapped clock outputs that mark the selected bits, as shown in Figure 2-4.
NOTE:
DL3 signals are not provided on the CX28395. Therefore, DL3_TS must be written to 00 to disable the DL3 transmitter and prevent transmit data corruption.
Figure 2-4. Receive External Data Link Waveforms
RDLO (T1: ESF) Frame 1 F12 23 24 F 1 Frame 2 2 Frame 3 23 24 F 1 2 Frame 4 23 24 F 1 2 23 24 F 1 2 Frame 5 23 24 F 1 2
RDLCKO
RCKi RDLO RDLCKO
TS24 F TS1
8394-8-5_074
NOTE(S): This waveform represents ESF FDL extraction; any combination of bits can alternatively be selected.
2.2.9 Sa-Byte Receive Buffers
The Sa-Byte buffers give read access to the odd frame Sa bits in E1 mode. Five receive Sa-Byte buffers [RSA4 to RSA8; addr 05B to 05F] are available. As a group, the buffers are updated every multiframe from Sa-bits received in TS0. This gives the processor up to 2 ms after the receive multiframe interrupt [RMF; addr 008] occurs to read any Sa-Byte buffer before the buffer content changes.
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2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.2.10 Receive Data Link
The RCVR contains two independent data link controllers (DL1 and DL2) and a Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to send and receive HDLC formatted messages in the Message-Oriented Protocol (MOP) mode. Alternatively, unformatted serial data can be sent and received over any combination of bits within a selected time slot or F-bit channel. The BOP transceiver can preemptively receive and transmit BOP messages, such as ESF Yellow Alarm. 2.2.10.1 Data Link Controllers DL1 and DL2 control two serial data channels operating at multiples of 4 kbps up to the full 64 kbps time slot rate by selecting a combination of bits from odd, even, or all frames. Both DL1 and DL2 support ESF Facilities Data Link (FDL), SLC-96 Data Link, Sa Data Link, Common Channel Signaling (CCS), Signaling System #7 (SS7), ISDN LAPD channels, Digital Multiplexed Interface (DMI) Signaling in TS24, as well as the latest ETSI V.51 and V.52 signaling channels. DL1 and DL2 each contain a 64-byte receive FIFO buffer. Both data link controllers are configured identically, except for their offset in the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address range is 0AF to 0B9. From this point on, DL1 is used to describe the operation of both data link controllers. DL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6]. DL1 will not function until it is enabled. DL1_CTL also controls the format of the data. The following data formats [DL1[1:0]; addr 0A6] are supported on the data link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and non-FCS are HDLC formatted messages. Pack8 and Pack6 are unformatted messages with 8 bits per FIFO access, or 6 bits per FIFO access, respectively (see Table 2-3).
Table 2-3. Commonly Used Data Link Settings Data Link
ESF FDL T1DM R Bit SLC-96 ISDN LAPD Sa4
Frame
Odd All Even All Odd
Time Slot
0 (F-bits) 24 0 (F-bits) N 1
Time Slot Bits
Don't Care 00000010 Don't Care 11111111 00001000
Mode
FCS FCS Pack6 FCS FCS
NOTE(S): N represents any T1/E1 time slot.
The time slot and bit selection are performed through the DL1 Time Slot Enable register [DL1_TS; addr 0A4] and the DL1 Bit Enable register [DL1_BIT; addr 0A5]. The DL1 Time Slot Enable register selects the frames and time slot to extract the data link. The frame select tells the receiver to extract the time slot in all frames, odd frames, or even frames. The time slot enable is a value between 0 and 31 that selects which time slot to extract. The DL1 Bit Enable register selects which bits will be extracted in the selected time slot. Refer to Table 2-3 for the common frame, time slot, time slot bits, and modes used.
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2.0 Circuit Description
2.2 Receiver
The Receive Data Link FIFO #1 [RDL1; addr 0A8] is 64 bytes. The Receive FIFO buffer is formatted differently than the transmit FIFO buffer. The Receive buffer contains not only received messages, but also a status byte preceding each message that specifies the size of the received message and the status of that message. The message status reports if the message was aborted, received with a correct or incorrect FCS, or continued. A continued message means the byte count represents a partial message. When all message bytes are read, the buffer contains another status byte. Message bytes can be differentiated from status bytes in the buffer by reading the RSTAT1 bit in the RDL #1 Status register [RDL1_STAT; addr 0A9]. RSTAT1 reports whether the next byte read from the buffer will be a status byte or some number of message bytes. The receive data link controller has a versatile microprocessor interface that can be tuned to the system's CPU bandwidth. For systems with one dedicated CPU, the data link status can be polled. For systems where a single CPU controls multiple devices, the data link can be interrupt-driven. See Figures 2-5 and 2-6 for a high-level description of polling and interrupt driven Receive Data Link Controller software. Using the Receive FIFO buffer, an entire block of data can be received with very little microprocessor interrupt overhead. Block transfers from the buffer can be controlled by the Near Full Threshold in the FIFO Fill Control register [RDL1_FFC; addr 0A7]. The Near Full Threshold is a user programmable value between 0 and 63. This value represents the maximum number of bytes that can be placed in the Receive buffer without the near full being declared. Once the threshold is set, the Near Full Status (RNEAR1) in RDL #1 Status [RDL1_STAT; addr 0A9] is asserted when the Near Full Threshold is reached. An interrupt, RNEAR, in Data Link 1 Interrupt Status [ISR2; addr 009], is also available to mark this event. The device uses a hierarchical interrupt structure, with one top-level interrupt request register directing software to the lower levels (see Master Interrupt Request register; addr 081 and Interrupt Request register; addr 003). Of all the interrupt sources, the two most significant bandwidth requirements are signaling and data link interrupts. Each data link controller has a top-level interrupt status register that reports data link operations (see Data Link 1 and 2 Interrupt Status registers [ISR2, ISR1; addr 009 and 00A). The processor uses a three-step interrupt scheme for the data link: 1. Read the Master Interrupt Request register to determine which framer interrupted. 2. Read the Interrupt Request register for that framer. 3. Use that register value to read the corresponding Data Link Interrupt Status register.
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2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-5. Polled Receive Data Link Processing
Receive Message
Read Data Link Status
Wait N Milliseconds If FIFO EMPTY Yes
Wait N Milliseconds
No
Read Message Byte from FIFO and Discard No
If Message Status on FIFO Yes
Read Message Status from FIFO
Read X Message Bytes from FIFO
Yes
If Message Status is Continue No
If Message Status is Good No Error Receiving Message
Yes
Return
Return
NOTE(S): Message status contains number of message bytes (X) in FIFO.
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Figure 2-6. Interrupt-Driven Receive Data Link Processing
Interrupt Service Routine Interrupt Occurred
2.0 Circuit Description
2.2 Receiver
Read Interrupt Status
Complete MSG or Near Full Interrupt Yes
No
Read Data Link Status Read Message Byte from FIFO and Discard No If Message Status on FIFO Yes Read Message Status from FIFO
Process Other Interrupt
Return
Read X Message Bytes from FIFO
If Message Status is Good or Continue No Error Receiving Message
Yes
Return
Return
NOTE(S): Message status contains number of message bytes (X) in FIFO.
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2.0 Circuit Description
2.2 Receiver
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.2.10.2 RBOP Receiver
The Receive Bit-Oriented Protocol (RBOP) receiver receives BOP messages, including the ESF Yellow Alarm, which consists of repeated 16-bit patterns with an embedded 6-bit codeword as shown in this example:
0xxxxxx0 11111111 (received right to left) [543210] RBOP = 6-bit codeword
The BOP message channel is configured to operate over the same channel selected by Data Link #1 [DL1_TS; addr 0A4]. It must be configured to operate over the FDL channel so RBOP can detect priority, command, and response codeword messages according to ANSI T1.403, Section 9.4.1. RBOP is enabled using the RBOP_START bit in Bit Oriented Protocol Transceiver register [BOP; address 0A0]. BOP codewords are received in the Receive BOP Codeword register [RBOP; addr 0A2], which contains the 6-bit codeword, a valid flag (RBOP_VALID), and a lost flag (RBOP_LOST). The valid flag is set each time a new codeword is put in RBOP, and is cleared on reading the codeword. The lost flag indicates a new codeword overwrote a valid codeword before being read by the processor. The BOP receiver can be configured to update RBOP using a message length filter and integration filter. The receive BOP message length filter [RBOP_LEN; addr 0A40] sets the number of successive identical messages required before RBOP is updated. RBOP_LEN can be set to 1, 10, or 25 messages. When enabled, the RBOP integration filter [RBOP_INTEG; add 0A0] requires receipt of two identical consecutive 16-bit patterns, without gaps or errors between patterns, to validate the first codeword. RBOP integration is needed to meet the codeword detection criteria while receiving 1/1000 bit error ratio. The real-time status of the codeword reception can be monitored using the RBOP_ACTIVE bit in the BOP Status register [BOP_STAT; addr 0A3]. Each time a message is put in RBOP register, an interrupt is generated, and the RBOP bit is set in the Data Link 2 Interrupt Status register [ISR1; addr 00A].
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2.0 Circuit Description
2.3 System Bus
2.3 System Bus
Each framer provides high-speed, transmit and receive serial TDM interfaces. These interfaces can be configured as non-multiplexed, individual system buses, or they can be multiplexed internally or externally to provide 2xE1 (4096 Mbps) and 4xE1 (8192 Mbps) buses. The system bus is compatible with the Mitel ST-Bus, the Siemens PEB Bus, and the AT&T CHI Bus and directly connects to other Conexant serial TDM bus devices without the need for any external circuitry. The following five bus rates are supported: * * * * * 1.536 MHz--T1 rate, 24 time slots, without framing bit 1.544 MHz--T1 rate with framing bit 2.048 MHz--E1 rate, 32 time slots 4.096 MHz--twice the E1 rate, 64 time slots 8.192 MHz--four times the E1 rate, 128 time slots
2.3.1 Non-Multiplexed Mode
In Non-Multiplexed mode, each framer has a separate system bus interface consisting of the following pin functions: Receive System Bus (RSB) RSBCKI RPCMO RFSYNC/RMSYNC RINDO/RDLCKO RSIGO/RDLO SIGFRZ Transmit System Bus (TSB) TSBCKI TPCMI TFSYNC/TMSYNC TINDO/TDLCKO TSIGI/TDLI --
The signal available on dual function pins is controlled using register PIO [addr 018]. To use Non-Multiplexed mode, SBIMODE[0] and/or SBIMODE[1] in the Framer Control register [FCR; addr 080] must be zero to disable Internally Multiplexed mode. The system bus rate is independent of the line rate and must be selected using SBI[3:0] in the System Bus Interface Configuration register [SBI_CR; addr 0D0]. Register bit SBI_OE [SBI_CR; addr 0D0] must also be set to 1 to enable system bus outputs.
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2.0 Circuit Description
2.3 System Bus
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.3.2 Externally Multiplexed Mode
Externally Multiplexed mode allows any two, three, or four framers (in the same or different devices) to share a common high speed system bus (see Figure 2-7). The 4.096 and 8.192 MHz bus modes contain multiple bus members (bus groups A, B, C, D) which allow multiple T1/E1 signals to share the same system bus. This is done by interleaving the time slots from up to four framers (see Figures 2-10 and 2-11). To use Externally Multiplexed mode, SBIMODE[0] and/or SBIMODE[1] in the Framer Control register [FCR; addr 080] must be zero to disable Internally Multiplexed mode. The system bus rate is independent of the line rate and must be selected using SBI[3:0] in the System Bus Interface Configuration register [SBI_CR; addr 0D0]. SBI[3:0] is also used to assign each framer to a different bus group. Register bits SBI_OE [SBI_CR; addr 0D0], BUS_RSB [RSB_CR; addr 0D1], and BUS_TSB [TSB_CR; addr 0D4] must be set to 1 to allow system bus outputs to share common connections.
Figure 2-7. Externally Multiplexed Configuration Examples
Possible Externally Multiplexed Configurations 8.192 Mbps 4.096 Mbps
Framer 1 Framer 2 Framer 3 Framer 4 Framer 5 Framer 6 Framer 7 Framer 8 CX28398
Framer 1 Framer 2 Framer 3 Framer 4
8.192 Mbps Any 2, 3, or 4 framers from a device (or from different devices) can be externally multiplexed with no additional circuitry.
4.096 Mbps
Framer 5 Framer 6
4.096 Mbps
Framer 7 Framer 8 CX28398
2.048 Mbps 1.544 Mbps
8394-8-5_003
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Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.3 System Bus
2.3.3 Internally Multiplexed Mode
Internally Multiplexed mode operation is very similar to Externally Multiplexed mode. The framers in each device are internally grouped into four-framer groups to allow an internally multiplexed mode (see Figure 2-8). In the CX28398, framers 1 through 4 form a group (lower group or group A) and framers 5 through 8 form another (upper group or group B). The CX28395 supports four groups: A, B, C, and D. The CX28394's four framers are also grouped in the same manner. In this mode, system bus signals from all four framers are internally connected and the interface pin functions are redefined. The advantage of this mode is that all system bus signals which are normally available on dual function pins, are now available on separate pins. In Internally Multiplexed mode, the following signals are available for each four-framer group (lower group shown): Receive System Bus (RSB) Transmit System Bus (TSB) RSBCKI[A] RPCMO[A] RFSYNC[A] RINDO[A] RSIGO[1:4] RMSYNC[1:4] RDLCKO[1:4](1) RDLO[1:4](1) SIGFRZ[1:4]
NOTE(S):
(1)
TSBCKI[A] TPCMI[A] TFSYNC[A] TINDO[A] TSIGI[1:4] TMSYNC[1:4] TDLCKO[1:4](1) TDLI[1:4](1) --
Common, internally connected to all four framers.
Separate signals.
These signals are not provided on the CX28395.
To use Internally Multiplexed mode, SBIMODE[0] and/or SBIMODE[1] in the Framer Control register [FCR; addr 080] must be set to 1. The system bus rate is independent of the line rate and must be selected using SBI[3:0] in the System Bus Interface Configuration register [SBI_CR; addr 0D0]. SBI[3:0] is also used to assign each framer to a different bus group. Register bits SBI_OE [SBI_CR; addr 0D0], BUS_RSB [RSB_CR; addr 0D1], and BUS_TSB [TSB_CR; addr 0D4] must be set to 1 to allow system bus outputs to share common connections. Because RFSYNC (and TFSYNC) signals are bused, all four framers' RFSYNC (and TFSYNC) signals must be configured as inputs and driven externally or, alternatively, three framers' sync signals can be configured as inputs and one as an output [PIO; addr 018].
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2.0 Circuit Description
2.3 System Bus
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-8. Internally Multiplexed Configuration Examples
Possible Internally Multiplexed Configurations 8.192 Mbps Two separte 8.192 Mbps buses is the typical application for Internally Multiplexed mode. 4.096 Mbps In this application, Framers 3 and 4 are used as back-up line interfaces and are connected to the system bus; but are disabled.
Framer 1 Framer 2 Framer 3 Framer 4 Framer 5 Framer 6 Framer 7 Framer 8 CX28398
Framer 1 Framer 2 Framer 3 Framer 4
8.192 Mbps
Framer 5 Framer 6 Framer 7 Framer 8 CX28398
8.192 Mbps In this application, Framer 8 is used as a back-up line interface and is connected to the system bus; but is disabled.
2.3.4 Receive System Bus
The Receive System Bus (RSB) provides a high-speed, serial interface between the RCVR and the system bus. The RSB has the following pins: Pin Name RSBCKI RPCMO RFSYNC/RMSYNC RINDO/RDLCKO RSIGO/RDLO SIGFRZ Function Receive System Bus Clock Receive PCM Data Receive Frame Sync or Receive Multiframe Sync Receive Time Slot Indicator or Receive Datalink Clock Receive Signaling Data or Receive Datalink Data Signaling Freeze
2-24
Conexant
8394-8-5_004
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.3 System Bus
Figure 2-9 illustrates the relationship between these signals. Signal definitions are provided in Table 1-6, Hardware Signal Definitions. RSB data outputs can be configured to output on the rising or falling edge of RSBCKI (see the Receive System Bus Configuration register [RSB_CR; addr 0D1]).
Figure 2-9. RSB Waveforms
RSBCKI Frame 48 TS 31 RPCMO E1 RINDO RSIGO Frame 1 TS 0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
A 1
B 2
C 3
D 4
A 5
B 6
C 7
D 8
A F
B 1
C 2
D 3
A 4
B 5
C 6
D 7
A 8
B 1
Frame 48 TS 24 RPCMO
Frame 1 TS 1
T1
RINDO
RSIGO
A
B
C
D
A
B
C
D
X
A
B
C
D
A
B
C
D
A
SIGFRZ RFSYNC
RMSYNC
NOTE(S): The Receive Multiframe Sync (RMSYNC) occurs every 6 ms, 48 T1 or 48 E1 frames.
The RSB supports five different system bus rates (MHz): * * * * * 1.536 MHz--T1 rate, 24 time slots, without framing bit 1.544 MHz--T1 rate with framing bit 2.048 MHz--E1 rate, 32 time slots 4.096 MHz--twice the E1 rate, 64 time slots 8.192 MHz--four times the E1 rate, 128 time slots
100054E
Conexant
2-25
2.0 Circuit Description
2.3 System Bus
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
The 4.096 and 8.192 MHz bus modes contain multiple bus members (A, B, C, D) which allow multiple T1/E1 signals to share the same system bus. This is done by interleaving the time slots from up to four framers, without external circuitry (see Figures 2-10 and 2-11). The system bus rate is independent of the line rate and must be selected using the System Bus Interface Configuration register [SBI_CR; addr 0D0].
Figure 2-10. RSB 4096K Bus Mode Time Slot Interleaving
RSBCKI RPCMO RSIGO RFSYNC NOTE(S): A and B time slot comes from different framers. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1]. TS31A SIG31A TS31B SIG31B TS0A SIG0A TS0B SIG0B
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate.
Figure 2-11. RSB 8192K Bus Mode Time Slot Interleaving
RSBCKI RPCMO RSIGO RFSYNC NOTE(S): A, B, C, and D data comes from different framers. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1]. TS31A SIG31A TS31B SIG31B TS31C SIG31C TS31D SIG31D TS0A SIG0A TS0B SIG0B TS0C SIG0C TS0D SIG0D
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate. RSB.OFFSET equals zero.
2-26
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.3 System Bus
The RSB maps line rate time slots to system bus time slots. The 24 (DS1) or 32 (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus time slots as listed in Table 2-4. The system bus rate must be greater than or equal to the line rate, except for 1536K bus mode.
Table 2-4. RSB Interface Time Slot Mapping Line Rate (MHz)
1.544
Source Channels
24 24 24 24 24
System Bus Rate (MHz)
1.536 1.544 2.048 4.096 8.192 2.048 4.096 8.192
Destination Time Slots
24 24 32 64 128 32 64 128
2.048
32 32 32
The RSB, Figure 2-12, consists of a timebase, slip buffer, a signaling buffer, and a signaling stack.
Figure 2-12. RSB Diagram
RSIG Buffer RSIG Local RSLIP Buffer AIS From Receive Timebase
RSIG STACK RSIGO RPCMO SIGFRZ RSB Timebase RSBCK RINDO RFSYNC RMSYNC RSBCKI TSBCKI
RNRZ
RPHASE
Remote Channel Loopback
Local Channel Loopback
}
I/O From Pins
100054E
Conexant
2-27
2.0 Circuit Description
2.3 System Bus
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.3.4.1 Timebase
The RSB timebase synchronizes RFSYNC, RMSYNC, and RINDO with the Receive System Bus Clock (RSBCKI). The RSBCK can be slaved to two different clock sources: Receive System Bus Clock Input (RSBCKI), or Transmit System Bus Clock Input (TSBCKI). The RSB clock selection is made through the Clock Input Mux register [CMUX; addr 01A]. The system bus clock can also be configured to run at twice the data rate by setting the X2CLK bit in the System Bus Interface Configuration register [SBI_CR; addr 0D0]. In Non-Multiplexed mode, the RFSYNC/RMSYNC dual function pin is configured for either RFSYNC or RMSYNC using the RMSYNC_EN register bit [PIO; addr 018]. RFSYNC and RMSYNC can be configured as inputs or outputs [PIO; addr 018]. RFSYNC and RMSYNC should be configured as inputs when the RSB timebase is slaved to the system bus [SBI_OE; addr 0D0]. RFSYNC and RMSYNC should be configured as outputs when the RSB timebase is master of the system bus. RFSYNC and RMSYNC can be also configured as rising or falling edge outputs [RSB_CR; addr 0D1]. In addition to having RFSYNC and RMSYNC active on the frame boundary, a programmable offset is available to select the time slot and bit offset in the frame. See the Receive System Bus Sync Time Slot Offset [RSYNC_TS; addr 0D3] and the Receive System Bus Sync Bit Offset [RSYNC_BIT; addr 0D2]. The 64-byte Receive PCM Slip Buffer [RSLIP; addr 1C0 to 1FF] resynchronizes the Receiver Clock (RCKI) and data (RNRZ), to the Receive System Bus Clock (RSBCK) and data (RPCMO). RSLIP acts like an elastic store by clocking RNRZ data in with RCKI and clocking PCM data out on RPCMO with RSBCK. If the system bus rate is greater than the line rate (i.e., T1 line rate and E1 system bus rate), there will be a mismatched number of time slots. The mapping of line rate time slots to system bus time slots is done by time slot assignments with the ASSIGN bit in the System Bus Per-Channel Control register [SBC0 to SBC31; addr 0E0 to 0FF]. ASSIGN selects which system bus time slots are used to transport line rate time slots. Time slot mapping is done by mapping the first line rate time slot to the first assigned system bus time slot. For example, T1 to E1 mapping might make every fourth time slot unassigned (i.e., 3, 7, 11, 15, 19, 23, 27, 31); see Figure 2-13. This distribution of unassigned time slots averages out the idle time slots and optimizes the use of the slip buffer.
2.3.4.2 Slip Buffer
2-28
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-13. T1 Line to E1 System Bus Time Slot Mapping
Frame A RNRZ FA 1 2 3 4 5 6 22 23 24 FB 1 2 3 Frame B 4
2.0 Circuit Description
2.3 System Bus
RPCMO
u 0 1 2 3 4 5 6
u 7
u u 27 28 29 30 31
0
1
2
NOTE(S):
(1) (2) (3)
u = unassigned time slots FA = T1 frame bit, frame A FB = T1 frame bit, frame B
Two-Frame Normal
RSLIP has four modes of operation: Two Frame Normal, 64-bit Elastic, Two-Frame Short, and Bypass. RSLIP mode is set in the Receive System Bus Configuration register [RSB_CR; addr 0D1]. RSLIP is organized as a two-frame buffer. This allows MPU access to frame data, regardless of the RSLIP mode selected. Each byte offset into the frame buffer is a different time slot: offset 0 in RSLIP is always time slot 0 (TS0), offset 1 is always TS1, and so on. The slip buffer has processor read/write access. In Normal mode, the slip buffer total depth is two 193-bit frames (T1) or two 256-bit frames (E1). Data is written to the slip buffer using RXCLK, and read from the slip buffer using RSBCK. If a slight rate difference between the clocks occurs, the slip buffer changes from its initial condition--approximately half full--by either adding or removing frames. If RXCLK writes to the slip buffer faster than RSBCK reads the data, the buffer will fill up. When the slip buffer in Normal mode is full, an entire frame of data is deleted. Conversely, if RSBCK reads the slip buffer faster than RXCLK writes the data, the buffer will become empty. When the slip buffer in Normal mode is empty, an entire frame of data is duplicated. When an entire frame is deleted or duplicated it is known as a Frame Slip (FSLIP), which is always one full frame of data. The FSLIP status is reported in the Slip Buffer Status register [SSTAT; addr 0D9]. In T1 mode, the F-bit is treated as part of the frame and can slip accordingly.
100054E
Conexant
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2.0 Circuit Description
2.3 System Bus 64-Bit Elastic
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Two-Frame Short
Bypass
In 64-bit Elastic mode, the slip buffer total depth is 64 bits, and the initial throughput delay is 32 bits, one-half of the total depth. Similar to Normal mode, Elastic mode allows the system bus to operate at any of the programmable rates, independent of the line rate. The advantage of this mode over the Normal mode is that throughput delay is reduced from one frame to an average of 32 bits, and the output multiframe always retains its alignment with respect to the output data. The disadvantage of this mode is handling the full and empty buffer conditions. In Elastic mode, an empty or full buffer condition causes an Uncontrolled Slip (USLIP). Unlike an FSLIP, a USLIP is of unknown size within the range of 1 to 256 bits of data. The USLIP status is reported in SSTAT. The Two-Frame Short mode combines the depth of the Normal mode with the throughput delay of the Elastic mode. The Two-Frame Short mode begins in the Elastic mode with a 32-bit initial throughput delay, and switches to the Normal mode when the buffer becomes empty or full; thereafter the Two-Frame Short and normal mode perform identically. If the slip buffer is full (two frames) in the Two-Frame Short mode, an FSLIP is reported, after which the slip buffer and Two-Frame mode perform identically. In Bypass mode, data is immediately clocked through RSLIP from the RCVR to RSB, and RCKI internally replaces the system bus clock. The 32-byte Receive Signaling Buffer [RSIG; addr 1A0 to 1BF] stores a single multiframe of signaling data. Each byte offset into RSIG contains signaling data for a different time slot: offset 0 stores TS0 signaling data, offset 1 stores TS1 signaling data and so on. The signaling data is stored in the least significant 4 bits of RSIG. The output signaling data is stored in the most significant 4 bits of RSIG. Similar to RSLIP, the RSIG buffer has read/write processor access to read or overwrite signaling information. RMSYNC extracts robbed-bit signaling from RSIG onto RPCMO; RFSYNC extracts ABCD signaling from RSIG onto RSIGO. The RSIG buffer has the following configurable features: transparent, robbed-bit signaling; signaling freeze; debounce signaling; and unicode detection. Each feature is available in the Receive Signaling Configuration register [RSIG; addr 0D7]. See the registers section for more details.
2.3.4.3 Signaling Buffer
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Conexant
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CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.3 System Bus
2.3.4.4 Signaling Stack
The Receive Signaling Stack (RSTACK) allows the processor to quickly extract signaling changes without polling every channel. RSTACK is activated on a per-channel basis by setting the Received Signaling Stack (SIG_STK) control bit in the Receive Per-Channel Control register [RPC0 to RPC31; addr 180 to 19F]. The signaling stack stores the channel and the A, B, C, and D signaling bits that changed in the last multiframe. The stack has the capacity to store signaling changes for all 24 (T1) or 30 (E1) PCM channels. At the end of any multiframe where one or more ABCD signaling values have changed, an interrupt occurs with RSIG set in the Timer Interrupt Status register [ISR3; addr 008]. The processor then reads the Receive Signaling Stack [STACK; addr 0DA] twice to retrieve the channel number (WORD = 0) and the new ABCD value (WORD = 1), and continues to read from STACK until the MORE bit in STACK is cleared, indicating the RSIG stack is empty. Optionally, the processor can select RSIG interrupt (SET_RSIG; addr 0D7) to occur at each multiframe boundary in T1 modes, regardless of signaling change. This mode provides an interrupt aligned to the multiframe to read the RSIG buffer, rather than to read RSTACK.
2.3.4.5 Embedded Framing
Embedded framing mode bit (EMBED; addr 0D0) instructs the RSB to embed framing bits in RPCMO while in T1 mode. The Embedded mode supports ITU-T Recommendation G.802, which describes how 24 T1 time slots and one framing bit (193 bits) are mapped to 32 E1 time slots (256 bits). This mapping is done by leaving TS0 and TS16 unassigned; by storing the 24 T1 time slots in TS1 to TS15, and TS17 to TS25; and by storing the frame bit in bit 1 of TS26 (see Figure 2-14). TS26 through TS31 are also unassigned.
Figure 2-14. G.802 Embedded Framing
Frame A RNRZ
FA 1 2 14 15 16 17 23 24 FB 1 2
Frame B
23 24 FC 1 2
RPCMO
u 0
1
2
u 14 15 16 17 18
uu 24 25 26 27
u 31
0
1
2
FB
X
X
X
X
X
X
X
E1 Framing Time Slot NOTE(S):
(1) (2) (3) (4) (5)
E1 Multiframe/Signalling Time Slot
X = unused bits u = unassigned time slot (see ASSIGN bit [addr 0E0 to 0FF]) FA = T1 frame bit, frame A FB = T1 frame bit, frame B FC = T1 frame bit, frame C
100054E
Conexant
2-31
2.0 Circuit Description
2.3 System Bus
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.3.5 Transmit System Bus
The Transmit System Bus (TSB) consists of a timebase, slip buffer, signaling buffer, and transmit framer (Figure 2-15). It provides a high-speed serial interface between the XMTR and the system bus.
Figure 2-15. TSB Interface Block Diagram
Remote Channel Loopback Local Channel Loopback
RSBCKI TSBCKI TSB Timebase Transmit Framer TINDO TFSYNC TMSYNC
From Transmit Timebase
TPHASE
TXDATA TNRZ
TSLIP Buffer TSIG Local TSIG Local
TPCMI
TSIGI
8394-8-5_035
The TSB contains the following five pins: Pin Name TSBCKI TPCMI TFSYNC/TMSYNC TINDO/TDLCKO TSIGI/TDLI Function Transmit System Bus Clock Transmit PCM Data Transmit Frame Sync or Transmit Multiframe Sync Transmit Time Slot Indicator or Transmit Datalink Clock Transmit Signaling Data or Transmit Datalink Data
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Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.3 System Bus
Refer to Figure 2-16 for the relationship between these signals. Signal definitions are provided in Table 1-6, Hardware Signal Definitions. TSB data outputs can be configured to input data on the rising or falling edge of TSBCKI (see the Transmit System Bus Configuration register [TSB_CR; addr 0D4].
Figure 2-16. Transmit System Bus Waveforms
TSBCKI Frame 48 TS 31 TPCMO E1 TINDO TSIGI Frame 1TS 0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
X 1
X 2
X 3
X 4
A 5
B 6
C 7
D 8
X F
X 1
X 2
X 3
A 4
B 5
C 6
D 7
X 8
X 1
Frame 48 TS 24 TPCMI
Frame 0 TS 1
T1
TINDO
TSIGI TFSYNC
X
X
X
X
A
B
C
D
X
X
X
X
X
A
B
C
D
X
TMSYNC
The TSB supports five different system bus rates (MHz): * * * * * 1.536 MHz--T1 rate, 24 time slots, without framing bits 1.544 MHz--T1 rate with framing bits 2.048 MHz--E1 rate, 32 time slots 4.096 MHz--twice the E1 rate, 64 time slots 8.192 MHz--four times the E1 rate, 128 time slots.
100054E
Conexant
2-33
2.0 Circuit Description
2.3 System Bus
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
The 4.096 and 8.192 MHz bus modes contain multiple bus members (A, B, C, and D) of which one bus member is selected by the SBI [3:0] bits in the System Bus Interface Configuration register [SBI_CR; 0D0] (see Figures 2-17 and 2-18). The system bus rate is independent of the line rate and must be selected using the System Bus Interface Configuration register.
Figure 2-17. TSB 4096K Bus Mode Time Slot Interleaving
TSBCKI TPCMI TSIGI TFSYNC NOTE(S): A and B time slot data comes from different framers. TSBCKI can be operated at 1 or 2 times the data rate. TS31A SIG31A TS31B SIG31B TS0A SIG0A TS0B SIG0B
Figure 2-18. TSB 8192K Bus Mode Time Slot Interleaving
TSBCKI TPCMI TSIGI TFSYNC NOTE(S): A, B, C, and D time slot data comes from different framers. TSBCKI can be operated at 1 or 2 times the data rate. TS31A SIG31A TS31B SIG31B TS31C SIG31C TS31D SIG31D TS0A SIG0A TS0B SIG0B TS0C SIG0C TS0D SIG0D
2-34
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.3 System Bus
2.3.5.1 Timebase
The TSB timebase synchronizes TPCMI, TFSYNC, TMSYNC, and TINDO with the Transmit System Bus Clock (TSBCK). The TSBCK can be slaved to three different clock sources: Transmit Clock Input (TCKI), Transmit System Bus Clock Input (TSBCKI), and Receive System Bus Clock Input (RSBCKI). The TSB clock selection is made through the Clock Input Mux register [CMUX; addr 01A]. TCKI is automatically selected when the transmit slip buffer is bypassed. The system bus clock can also be configured to run at twice the data rate by setting the X2CLK bit in the System Bus Interface Configuration register [SBI_CR; addr 0D0] when TSLIP is not in Bypass mode. In Non-Multiplexed mode, the TFSYNC/TMSYNC dual function pin is configured for either TFSYNC or TMSYNC using the TMSYNC_EN register bit [PIO; addr 018]. TFSYNC and TMSYNC can be individually configured as inputs or outputs, [PIO; addr 018]. TFSYNC and TMSYNC should be configured as inputs when the TSB timebase is slaved to the system bus, the transmit framer is disabled [TABORT; addr 071], or TSB carries embedded T1 framing. TFSYNC and TMSYNC should be configured as outputs when the TSB timebase is master of the system bus, or the transmit framer is enabled. TFSYNC and TMSYNC can be also configured as rising or falling edge outputs [TSB_CR; addr 0D4]. In addition to having TFSYNC and TMSYNC active on the frame boundary, a programmable offset is available to select the time slot and bit offset in the frame (see Transmit System Bus Sync Time Slot Offset [TSYNC_TS; addr 0D6] and Transmit System Bus Sync Bit Offset [TSYNC_BIT; addr 0D5]). The 64-byte Transmit PCM Slip Buffer [TSLIP; addr 140 to 17F] resynchronizes the Transmit System Bus Clock (TSBCK) and data (TPCMI) to the Transmit Clock (TXCLK) and data (TNRZ). TSLIP acts like an elastic store by clocking PCM data in on TPCMI with TSBCK and clocking TNRZ data out with TXCLK. TPCMI can be configured to sample on the rising or falling edge of TSBCKI (see the Transmit System Bus Configuration register [TSB_CR; addr 0D4]). TSLIP has four modes of operation: Two Frame Normal, 64-bit Elastic, Two Frame Short, and Bypass. TSLIP mode is set in the Transmit System Bus Configuration register [TSB_CR; addr 0D4]. It is organized as a two-frame buffer, with high frame and low frame buffers. This allows MPU access to frame data, regardless of the TSLIP mode selected. Each byte offset into the frame buffer is a different time slot, offset 0 in TSLIP is always time slot 0 (TS0); offset 1 is always TS1, and so on. The slip buffer has processor read/write access. In Normal mode, the slip buffer total depth is two 193-bit frames (T1), or two 256-bit frames (E1). Data is written to the slip buffer using TSBCK and read from the slip buffer using TXCLK. If there is a slight rate difference between the two clocks, the slip buffer changes from its initial condition--approximately half full--by either adding or removing frames. If TSBCK writes to the slip buffer faster than TXCLK reads the data, the buffer becomes full. When the slip buffer in Normal mode is full, an entire frame of data is deleted. Conversely, if TXCLK is reading the slip buffer at a faster rate than TSBCK is writing the data, the buffer will eventually empty, and an entire frame of data is duplicated. When an entire frame is deleted or duplicated, it is known as a Frame Slip (FSLIP). An FSLIP is always one full frame of data. The FSLIP status is reported in the Slip Buffer Status register [SSTAT; addr 0D9].
2.3.5.2 Slip Buffer
Two-Frame Normal
100054E
Conexant
2-35
2.0 Circuit Description
2.3 System Bus 64-Bit Elastic
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
In 64-bit Elastic mode, the slip buffer total depth is 64 bits and the initial throughput delay is 32 bits, or one-half of the total depth. Similar to Normal mode, Elastic mode allows the system bus to operate at any of the programmable bus rates, independent of the line rate. The advantage of this mode over the two-frame mode is that throughput delay is reduced from one frame to an average of 32 bits, and the transmit multiframe can retain its alignment with respect to the transmit data. The disadvantage of this mode is handling the full and empty buffer conditions. In 64-bit Elastic mode, an empty or full buffer condition causes an Uncontrolled Slip (USLIP). Unlike an FSLIP, a USLIP is of unknown size, ranging from 1 to 256 bits of data. The USLIP status is reported in SSTAT. The Two-Frame Short mode combines the depth of the Normal mode with the throughput delay of the Elastic mode. This mode begins in Elastic mode with a 32-bit initial throughput delay, and switches to Normal modes when the buffer is empty or full; thereafter, the Two-Frame Short and Normal modes perform identically. If the slip buffer is full (two frames) in the Two-Frame Short and normal modes, an FSLIP is reported; thereafter, the slip buffer performs exactly like Normal mode. In Bypass mode, data is clocked through TSLIP from the TSB to the XMTR using TXCLK as selected by the TXCLK input clock mux. The 32-byte Transmit Signaling Buffer [TSIG; addr 120-13F] stores a single multiframe of signaling data input from TSIGI pin and is updated as each time slot is received in every TSB frame. Each byte offset into TSIG is a different time slot's signaling data: offset 0 stores TS0 signaling data, offset 1 stores TS1 signaling data, etc. The signaling data is stored in the least significant 4 bits of the signaling buffer. Similar to TSLIP, TSIG has read/write processor access for accessing or overwriting signaling information. TFSYNC is used by the signaling buffer to identify the frame boundaries in the TSIGI data stream. A transmit framing option is provided to allow the transmitter to automatically align to the transmit PCM data on TPCMI. In this mode, the Transmit Framer searches transmit data for a valid E1 or T1 framing pattern. The transmit data stream has two framing functions: offline framer and an online framer. The offline framer recovers the transmit frame alignment (TFSYNC). The online framer monitors the frame alignment found by the offline framer and recovers multiframe alignment (TMSYNC). Transmit frame resynchronization is initiated by activating the Transmit Loss Of Frame (TLOF) status bit in the Alarm 2 status [ALM2; addr 048] register by the online framer. The TLOF criteria is set in the TLOFA, TLOFB, and TLOFC bits of the Transmitter Configuration register [TCR1; addr 071]. The online framer supports the following LOF criteria for T1: 2 frame bit errors out of 4, 2 out of 5, or 2 out of 6; for E1, it supports 3 out of 3. Figure 2-19 illustrates transmit framing and timebase alignment options.
Two-Frame Short
Bypass
2.3.5.3 Signaling Buffer
2.3.5.4 Transmit Framing
Transmit Frame Alignment
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Conexant
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CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-19. Transmit Framing and Timebase Alignment Options
2.0 Circuit Description
2.3 System Bus
TPCMI
TSLIP Buffer TPHASE Recenter (TUSLIP) MFAS CAS On-Line On-Line
TNRZ
A
01 Off-Line Framer
C
TFSYNCI TMSYNCI TSB Offset FSYNC MSYNC TSB Timebase Pass MF B Pass MF D FSYNC FAS CAS MSYNC
TFSYNCO TMSYNCO
TX Timebase
A TSB Aligns to TPCMI (EMBED = 0) B TSB Aligns to TX (TSB_ALIGN = 1)
C TSB Aligns to TNRZ (EMBED = 1) D TX Aligns to TSB (TX_ALIGN = 1)
NOTE(S):
(1) (2)
EMBED located in SBI_CR (addr 0D0). TSB_ALIGN and TX_ALIGN located in TSB_CR (addr 0D4).
When TLOF is asserted, the offline framer searches the transmit data stream for a new frame alignment, provided that transmit framing is enabled [TABORT; addr 071]. If embedded framing is enabled [EMBED; addr 0D0], the offline framer examines the TSLIP buffer output--TNRZ--for transmit frame alignment. If embedded framing is disabled, the offline framer examines the slip buffer input (TPCMI) for transmit frame alignment. This case (EMBED = 0) is only applicable if TPCMI is configured to operate at the line rate--2,048 kbps E1, or 1,544 kbps T1. If transmit framing is disabled, the offline framer waits for a reframe command [TFORCE; addr 071] before beginning a frame alignment search.
Transmit Multiframe Alignment
After the offline framer recovers frame alignment, the online framer monitors TLOF and searches for multiframe alignment using criteria defined by the Transmit Frame mode [TFRAME; addr 070]. The online framer conducts a multiframe alignment search each time the offline framer recovers transmit frame alignment--as reported by high-to-low transition of transmit loss of frame status [TLOF; addr 048]. After TLOF recovery, the online framer searches continuously for multiframe alignment until the correct pattern sequence is located, or until basic frame alignment is lost (TLOF goes active-high). After multiframe alignment recovery, the online framer checks subsequent multiframes for errored alignment patterns, but does not use those errors as part of the criteria for loss of basic frame alignment.
100054E
Conexant
2-37
2.0 Circuit Description
2.3 System Bus
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Note that the online framer's multiframe search status is not directly reported to the processor, but instead is monitored by examination of transmit error status: TMERR, TSERR, and TCERR [addr 00B]. If the system incorporates a certain number of multiframe pattern errors (or a certain error ratio) into the loss of transmit frame alignment criteria, the processor must count multiframe pattern errors to determine when to force a transmit reframe [TFORCE; addr 071].
Transmit Frame Alignment Criteria
The frame synchronization criteria used by the offline framer is set in the TFRAME[3:0] of the Transmit Framer Configuration register [TCR0; addr 070]. (Tables 3-15 and 3-16 illustrate supported transmit framing formats. Also, see Tables 3-17 and 3-18, Criteria for Loss/Recovery of Transmit Frame Alignment.) The offline framer is shared between the RCVR and XMTR and can only search in one direction at a time. Consequently, the host processor can manually arbitrate between RCVR and XMTR reframe requests by manipulating the ABORT and FORCE controls, or by allowing the framer to automatically arbitrate LOF requests. The offline framer waits until the current search is complete [FSTAT; addr 017] before checking for pending LOF reframe requests. If both online framers have pending reframe requests, the offline framer aligns to the opposite direction of that most recently searched. For example, if TLOF is pending at the conclusion of a receive search which timed out without finding alignment, the offline framer switches to search in the transmit direction. The TLOF switchover is prevented in the preceding example if the processor asserts TABORT to mask the transmit reframe request. TABORT does not affect TLOF status reporting. For applications that frame in only one direction, framing in the opposite direction must be masked. If, at the conclusion of a receive search timeout, TLOF status is asserted but masked by TABORT, the offline framer continues to search in the receive direction. For applications that frame in both directions, the processor can manually arbitrate among pending reframe requests by controlling the reframe precedence. An example of manual control follows:
1 2 3 4 5 Initialize RABORT = 1 and TABORT = 1. Enable RLOF and TLOF interrupts. Read clear pending ISR interrupts. Release RABORT = 0. Call LOF Service Routine if either RLOF or TLOF interrupt; { (check current LOF status (ALMI, 2; addr 047, 048) If RLOF recovered and TLOF lost --Assert RABORT = 1 --Release TABORT = 0 If RLOF lost or TLOF recovered --Assert TABORT = 1 --Release RABORT = 0 }
Transmit/Receive Framer Arbitration
2-38
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.3 System Bus
The status of the offline framer can be monitored using the Offline Framer Status register [FSTAT; addr 017]. The register reports the following: whether the offline framer is looking at the receive or transmit data streams (RX/TXN); whether the framer is actively searching for frame alignment (ACTIVE); whether the framer found multiple framing candidates (TIMEOUT); whether the framer found frame sync (FOUND); and whether the framer found no frame alignment candidates (INVALID). 2.3.5.5 Embedded Framing Embedded framing mode [EMBED; addr 0D0] instructs the transmit framer to search TSLIP buffer output (TNRZ) for framing bits while in T1 mode, or for MFAS and CAS in E1 mode. Embedded framing allows the transmit timebase to align with the transmit framer multiframe alignment of the PCM signal transported across the system bus. The Embedded mode supports ITU-T Recommendation G.802, which describes how 24 T1 time slots and framing bit (193 bits) are mapped to the 32 E1 time slots (256 bits): by leaving TS0 and TS16 unassigned; by storing the 24 T1 time slots in TS1 to TS15, and in TS17 to TS25; and by storing the frame bit in Bit 1 of TS26 (see Figure 2-14, G.802 Embedded Framing).
100054E
Conexant
2-39
2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.4 Transmitter
The Transmitter (XMTR) inserts T1/E1 overhead data and outputs single rail NRZ data from the TSB or ZCS-encoded P and N rail NRZ data. The CX28395 only provides single rail NRZ transmit signals. The XMTR, Figure 2-20, consists of the following elements: two Transmit Data Links, Test Pattern Generator, In-Band Loopback Code Generator, Overhead Pattern Generator, Alarm Generator, Zero Code Suppression (ZCS) Encoder, External Transmit Data Link (CX28394 and CX28398 only), CRC Generation, Framing Pattern Insertion, and Far End Block Error Generator.
Figure 2-20. XMTR Diagram
TXCLK Line Framer Loopback Loopback Transmitter Timebase To TSBI
TPOSO/TNRZO TNEGO/MSYNCO AIS Generator ZCS Encoder
Data Link 2 Buffer External DL3 T1/E1 Frame Insert
TPDV Enforcer Alarm/Error Insert PRBS/Inband LB Sa-Byte/BOP Data Link 1 Buffer
TNRZ
2-40
Conexant
TDLI TDLCKO
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.4 Transmitter
2.4.1 External Transmit Data Link (CX28394 and CX28398 Only)
The External Data Link (DL3) allows the system to externally supply any bit(s) in any time slot in all frames, odd frames or even frames, including T1 framing bits. Pin access to the DL3 transmitter is provided through TDLCKO and TDLI. These two pins serve as the TDL3 clock output (TDLCKO) and data input (TDLI). The mode of the pins is selected using the TDL_IO bit in the Programmable Input/Output register [PIO; addr 018]. Control of DL3 format is provided in two registers: External Data Link Channel [DL3_TS; add 015] and External Data Link Bit [DL3_BIT; addr 016]. Transmit DL3 is set up by selecting the bit(s) [DL3_BIT], time slot [TS[4:0]; addr 015], and frames [EVEN/ODD; addr 015] to be overwritten, then enabling the data link [DL3EN; addr 015]. Enabling the data link will start TDLCKO gating the NRZ data provided on TDLI (see Figure 2-21).
NOTE:
DL3 signals are not provided on the CX28395. Therefore, DL3_TS must be written to 00 to disable the DL3 transmitter and prevent transmit data corruption.
Figure 2-21. Transmit External Data Link Waveforms
TDLCKO TS8 TDLI 1 2 TS9 7 8 TS10
NOTE(S): This example shows bits 1, 2, 7, and 8 of TS9 selected. Any combination of time slot bits can be selected.
2.4.2 Transmit Data Links
The XMTR contains two independent data link controllers (DL1, DL2), a Performance Report Message (PRM) generator, and a Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to send and receive HDLC formatted messages in the Message Oriented Protocol (MOP) mode or unformatted serial data over any combination of bits within a selected time slot or F-bit channel. The PRM message generator can immediately or automatically send one-second performance reports. The BOP transceiver can preemptively transmit BOP messages, such as ESF Yellow Alarm. 2.4.2.1 Data Link Controllers DL1 and DL2 control serial data channels operating at multiples of 4 kbps up to the full 64 kbps time slot rate by selecting a combination of bits from odd, even, or all frames. Both data link controllers support ESF Facilities Data Link (FDL), SLC-96 data link, Sa data link, Common Channel Signaling (CCS), Signaling System #7 (SS7), ISDN LAPD channels, Digital Multiplexed Interface (DMI) signaling in TS24, as well as the latest ETSI V and V signaling channels. .51 .52 DL1 and DL2 each contain a 64-byte transmit buffer which function either as programmable length circular buffers in transparent (unformatted) mode, or as full-length data FIFOs in formatted (HDLC) mode.
100054E
Conexant
2-41
2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
DL1 and DL2 are configured identically, except for their offset in the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address range is 0AF to 0B9. From this point on, the DL1 is used to describe the operation of both data link controllers. Transmit Data Link 1 (TDL1) can be viewed as having a higher priority than Transmit Data Link 2 (TDL2) because TDL1 overwrites the primary rate channel after TDL2. Thus, any data that TDL2 writes to the primary rate channel can be overwritten by TDL1, if TDL1 is configured to transmit in the same time slot as TDL2. The TDL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6]. TDL1 will not overwrite time slot data until it is enabled. DL1_CTL also controls the data format and the circular buffer/FIFO mode. The following data formats [DL1[1,0]; addr 0A6] are supported on the data link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and non-FCS are HDLC-formatted messages. Pack8 and Pack6 are unformatted messages with 8 bits per FIFO access, and 6 bits per FIFO access, respectively. 2.4.2.2 Circular Buffer The Circular Buffer/FIFO control bit [TDL1_RPT; addr 0A6] allows the FIFO to act as a circular buffer; in this mode, a message can be transmitted repeatedly. This feature is available only for unformatted transmit data link applications. The processor can repeatedly send fixed patterns on the selected channel by writing a 1- to 64-byte message into the circular buffer. The programmed message length repeats until the processor writes a new message. The first byte of each unformatted message is output automatically, aligned to the first frame of a 24-, or 16-frame transmit multiframe (SF/ESF/MFAS). This allows the processor to source overhead or data elements aligned to the TX timebase. In both SF and ESF T1 modes, unformatted messages are aligned on 24-frame boundaries. Therefore, in SF applications the repeating message must be designed to span two SF multiframes. Each unformatted message written is output-aligned only after the preceding message completes transmission. Therefore, data continuity is retained during the linkage of consecutive messages, provided that the contents of each message consists of a multiple of the multiframe length.
2-42
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.4 Transmitter
2.4.2.3 Time Slot and Bit Selection
Time slot and bit selection is done through the DL1 Time Slot Enable [DL1_TS; addr 0A4] and DL1 Bit Enable [DL1_BIT; addr 0A5] registers. DL1_TS selects which frames and which time slot will be overwritten. The frame select allows TDL1 to overwrite the time slot in either all frames, odd frames, even frames, or in a special 2 kbps mode. The time slot word enable is a value between 0 and 31 that selects which time slot will be filled with data from the transmit data link buffer. DL1_BIT selects which bits will be overwritten in the time slot selected. Table 2-5 lists commonly used data link settings.
Table 2-5. Commonly Used Data Link Settings Data Link
ESF FDL T1DM R Bit SLC-96 ISDN LAPD CEPT Sa4
Frame
Odd All Even All Odd
Time Slot
0 (F-bits) 24 0 (F-bits) N 1
Time Slot Bits
Don't Care 00000010 Don't Care 11111111 00001000
Mode
FCS FCS Pack6 FCS FCS
NOTE(S): N represents any T1/E1 time slot.
2.4.2.4 Transmit Data Link FIFO Buffer
The Transmit Data Link FIFO #1 [TDL1; addr 0AD] is a versatile, 64-byte buffer that can be used as a single-byte transmit buffer or for any number of bytes up to 64. As a single-byte FIFO, the Transmit FIFO Empty Status (TMPTY1) in TDL #1 Status [TDL1_STAT; addr 0AE] and Transmit FIFO Empty Interrupt (TEMPTY) in Data Link 1 Interrupt Status (ISR2; addr 009] can be used to do byte-by-byte transmissions. Using the Transmit Data FIFO, an entire block of data can be transmitted with very little microprocessor interrupt overhead. Block transfers to the FIFO can be controlled by the Near Empty Threshold in the FIFO Empty Control register [TDL1_FEC; addr 0AB]. The Near Empty Threshold is a user-programmable value between 0 and 64 that represents the minimum number of bytes that can be left in the transmit FIFO before near empty is declared. Once the threshold is set, the Near Empty Status (TNEAR1) in TDL #1 Status [TDL1_STAT; addr 0AE] will be asserted whenever the Near Empty Threshold is reached. An interrupt, TNEAR in the Data Link 1 Interrupt Status register [ISR2; addr 009], is also available to mark this event. Once an entire message is written to the transmit FIFO or circular buffer, the processor must indicate the end of message by writing any value to the TDL #1 End Of Message (EOM) Control [TDL1_EOM; addr 0AC]. In FCS mode, the EOM indicates that the FCS is to be calculated and transmitted following the last byte in the FIFO. In the circular buffer mode, the EOM indicates the end of the transmit circular buffer.
2.4.2.5 End of Message
100054E
Conexant
2-43
2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.4.2.6 Programming the Data Link Controller
The Transmit Data Link Controller can be programmed according to the system CPU bandwidth. For systems with sufficient CPU bandwidth, the data link status can be polled, and the 64-byte transmit FIFO buffer can be used as a single-byte transmit buffer. For systems with limited CPU bandwidth, the data link can be interrupt-driven, and the entire 64-byte transmit FIFO buffer can be used to store entire messages. See Figures 2-22 and 2-23 for a high level description of polling and interrupt-driven Transmit Data Link Controller software. The device uses a hierarchical interrupt structure, with one top-level interrupt request register directing software to the lower levels (see Master Interrupt Request register; addr 081 and Interrupt Request register; addr 003). Of all the interrupt sources, the two most significant bandwidth requirements are signaling and data link interrupts. Each data link controller has a top-level interrupt status register that reports data link operations (see Data Link 1 and 2 Interrupt Status registers [ISR2; addr 009, and ISR1; 00A]). The processor uses a three-step interrupt scheme for the data link: 1. Read the Master Interrupt Request register to determine which framer is interrupted. 2. Read the Interrupt Request register for that framer. 3. Use that register value to read the corresponding Data Link Interrupt Status register.
Figure 2-22. Polled Transmit Data Link Processing
Transmit Message 0x00 Write Block/Byte to FIFO 0x20 0x40 If End of Message No Yes Message Block 1 Block 2 Block 3
Wait N Milliseconds
Write End of Message Register
Read FIFO Status
Return
No
If FIFO Empty or Near Empty Yes
2-44
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-23. Interrupt-Driven Transmit Data Link Processing
Main Line Code Message Transmit Message 0x00 0x20 0x40 0x60 Block 1 Block 2 Block 3 Block 4 Return Write Block/Byte to FIFO
2.0 Circuit Description
2.4 Transmitter
Interrupt Service Routine Interrupt Occurred
Read Interrupt Status
If Transmit Data Link Near Empty Interrupt Yes Write Block/Byte to FIFO
No
Process Other Interrupt
If End of Message
Return No
Yes Write End of Message Register Return
Return
100054E
Conexant
2-45
2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.4.2.7 PRM Generator
In T1 applications, Performance Report Messages (PRMs) are HDLC messages containing path identification and performance monitoring information. If automatic performance report insertion is selected [AUTO_PRM; addr 0AA], a performance report is generated each second and begins transmitting coincident with the one-second timer interrupt [ONESEC; addr 005]. The PRM is sent immediately if the processor sets SEND_PRM bit in the Performance Report Message register [PRM; addr 0AA]. All performance monitoring fields of the message are automatically filled in when a PRM is generated. The remaining PRM bit fields are application-specific and can be configured using the Performance Report Message register. For limited systems, the automatic PRM generation off-loads a significant portion of CPU bandwidth. The Transmit Bit-Oriented Protocol (TBOP) transceiver sends BOP messages in T1 applications, including ESF Yellow Alarm. These messages consist of repeated 16-bit patterns with an embedded 6-bit codeword, as shown in this example:
0xxxxxx0 11111111 (transmitted right to left) [543210] TBOP = 6-bit codeword
2.4.2.8 TBOP Transceiver
The TBOP is configured to operate over the same channel selected by Data Link #1 [DL1_TS; addr 0A4]. The TBOP channel must be configured to operate over the FDL channel in order for TBOP to convey Priority, Command, and Response codeword messages according to ANSI T1.403, Section 9.4.1. The precedence of transmitted BOP messages with respect to current DL1 transmit activity is configurable using the Transmit BOP mode bits [TBOP_MODE[1,0]; addr 0A0]. BOP messages can also be transmitted during E1 mode, although the 16-bit codeword pattern has not currently been adopted as an E1 standard. The length of the BOP message [TBOP_LEN[1,0]; addr 0A0] can be set to a single pattern, 10 patterns, 25 patterns, or continuous. BOP codewords are transmitted by writing to the Transmit BOP Codeword [TBOP; addr 0A1]. The real-time status of the codeword transmission can be monitored using TBOP_ACTIVE in the BOP Status register [BOP_STAT; addr 0A3]. A TBOP Transmit interrupt is available in the Data Link 1 Interrupt Status register [ISR2; addr 009] to indicate that a codeword has begun transmission and the next codeword may be written to TBOP.
2.4.3 Sa-Byte Overwrite Buffer
There are five transmit Sa-Byte buffers [TSA4 to TSA8; addr 07B to 07F]. The Sa-Byte buffers insert Sa-bits into the odd frames of TS0. The entire group of 40 bits is sampled every 16 frames coincident with the Transmit Multiframe bit interrupt boundary [TMF; addr 008]. Bit 0 from each TSA register is then inserted during frame 1, bit 1 is inserted during frame 3, bit 2 during frame 5, and so on, which gives the processor up to 2 ms after TMF interrupt to write new Sa-Byte buffer values. Transmit Sa-bits maintain a fixed relationship to the transmit CRC multiframe. Each of the 5 Sa-Byte transmit buffers can be individually enabled using the Manual Sa-Byte Transmit Enable in Transmit Manual Sa-Byte/FEBE Configuration register [TMAN; addr 074].
2-46
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.4 Transmitter
2.4.4 Overhead Pattern Generation
The transmit overhead generation circuitry provides the ability to insert all of the overhead associated with the Primary Rate Channel. The following types of overhead pattern generation are supported: Framing patterns, Alarm patterns, Cyclic Redundancy Check (CRC), and Far-End Block Error (FEBE). 2.4.4.1 Framing Pattern Generation The framing pattern generation circuitry inserts the 2-bit terminal framing (Ft) pattern, the 6-bit signaling frame (Fs) pattern, the 6-bit FPS pattern, the 8-bit FAS/NFAS pattern, and the 6-bit MFAS pattern into the transmit data stream. The Ft pattern in SF, SLC-96, and T1DM is inserted into the transmit data stream by enabling the INS_FBIT in the Transmit Frame Format register [TFRM; addr 072]. The Fs pattern in SF is inserted by enabling the INS_MF bit. The FPS pattern in T1-ESF and the FAS/NFAS pattern in E1 mode are inserted by enabling the INS_FBIT bit. The MFAS pattern is inserted by enabling the INS_MF bit. The Transmit Alarm Generation circuitry generates Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI/Yellow Alarm). AIS is an unframed all-ones pattern and is normally transmitted when the data source is lost. AIS transmission can be enabled:
1. 2. 3.
2.4.4.2 Alarm Generation
AIS Generation
manually, automatically upon detection of transmit loss of clock, and automatically upon loss of received signal.
Typical applications require transmission of AIS toward the line when DTE transmit data or clock is not present. In most applications, DTE data and clock are isolated from the transmitter requiring manual AIS transmission under software control. Manual insertion of AIS is controlled by the TAIS bit in Transmit Alarm Signal Configuration register [TALM; addr 075]. Setting this bit overwrites the currently transmitted data with the AIS pattern. If AISCLK [TLIU_CR; addr 068] is also set, AIS is transmitted using an alternate transmit line rate clock supplied on E1ACKI (for E1) or T1ACKI (for T1) pins. Automatic transmission of AIS can be controlled by detection of transmit loss of clock [TLOC; addr 048]. This mode is enabled by setting AISCLK and providing an alternate transmit line rate clock on the E1ACKI or T1ACKI pin. If no transitions are detected on the TCKI pin for eight cycles of E1ACKI or T1ACKI, TLOC is set and AIS is transmitted. AIS is terminated and TLOC cleared when TCKI returns. By setting AUTO_AIS in the TALM register, automatic transmission of AIS can also be controlled by detection of Receiver Loss Of Signal [RLOS; addr 047]. This mode is typically used to transmit AIS (keep-alive) during line loopback if the received signal is lost. Setting AUTO_AIS simultaneously with setting LLOOP [LOOP; addr 014] enables this operation.
100054E
Conexant
2-47
2.0 Circuit Description
2.4 Transmitter Yellow Alarm Generation
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Yellow Alarm, also referred to as RAI (Remote Alarm Indication), is a bit pattern inserted into the transmit stream to alert far-end equipment that the local receiver cannot recover data. Yellow Alarm/RAI is typically transmitted during receive loss of frame and is defined differently depending upon the transmit frame format configured [TFRAME; addr 070]. Table 2-6 describes the Yellow Alarm/RAI transmitted for each frame format.
Table 2-6. Yellow Alarm Generation Frame Format
SF ESF(1) SLC-96 SF/JYEL T1DM E1
NOTE(S):
(1)
Yellow Alarm Transmitted
Bit 2 of every time slot set to zero Bit 2 of every time slot set to zero Bit 2 of every time slot set to zero F-bit 12 of every superframe set to one Y bit of the sync byte set to zero The A bit of TS0 set to one
Mode
YB2 YB2 YB2 YJ Y24 Y0
Yellow Alarm/RAI for T1-ESF framing is defined as a BOP priority codeword in the FDL channel. T1-ESF Yellow Alarm/RAI is not transmitted using the procedure described below. Instead, T1- ESF Yellow Alarm/RAI is generated by configuring DL1 to continuously transmit an all zeros BOP priority codeword. Refer to Section 2.4.2, Transmit Data Links.
Transmission of Yellow Alarm/RAI is controlled by these register bits: Bit Name INS_YEL TYEL AUTO_YEL RLOF RLOF_INTEG Register TFRM; addr 072] TALM; addr 075] TALM; addr 075] ALM1; addr 047] RALM; addr 045]
Insertion of Yellow Alarm/RAI into the transmit stream is controlled by INS_YEL. Yellow Alarm/RAI is inserted only when INS_YEL is set, otherwise these bit positions are supplied by data from TPCMI. Yellow Alarm/RAI generation can be done manually or automatically. Manual generation of Yellow Alarm/RAI is controlled by TYEL. Setting this bit will immediately and unconditionally overwrite the Yellow Alarm/RAI signal bit(s) in the transmitted data stream with the appropriate pattern. Automatic generation of Yellow Alarm/RAI is controlled by AUTO_YEL, RLOF, and RLOF_INTEG. If AUTO_YEL is set, Yellow Alarm/RAI is generated during a receive loss of frame alignment (RLOF = 1). Optionally, RLOF integration can be enabled by setting RLOF_INTEG. In this case, both RLOF indication and Yellow Alarm/RAI generation are delayed for approximately 2.5 seconds if a continuous out-of-frame condition exists. Yellow Alarm/RAI generation continues for at least 1 second after RLOF clears.
2-48
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Multiframe Yellow Alarm Generation
2.0 Circuit Description
2.4 Transmitter
In E1 CAS framing modes, Multiframe Yellow Alarm is inserted into the transmit stream to alert far-end equipment that local received multiframe alignment is not recovered. E1 Multiframe Yellow Alarm is transmitted by setting the Y bit in time slot 16, frame 0. Transmission of Multiframe Yellow Alarm is controlled by these register bits: Bit Name INS_MYEL TMYEL AUTO_MYEL SRED Register [TFRM; addr 072] [TALM; addr 075] [TALM; addr 075] [ALM3; addr 049]
Insertion of E1 Multiframe Yellow Alarm is controlled by INS_MYEL and inserted only when INS_MYEL is set. Multiframe Yellow Alarm generation can be initiated manually or automatically. Manual insertion of Multiframe Yellow Alarm is controlled by TMYEL. Setting this bit will unconditionally overwrite the Multiframe Yellow Alarm signal bit in the transmitted data stream. Automatic insertion of Multiframe Yellow Alarm is controlled by AUTO_MYEL in the TALM register. When set, the AUTO_MYEL mode will send yellow alarm for the duration of a receive loss of CAS multiframe alignment [SRED; addr 049] 2.4.4.3 CRC Generation The CRC generation circuitry computes the value of the CRC6 code in T1 mode or the CRC4 code in E1 mode. Once computed, it is inserted into the appropriate position of the transmitted data stream. CRC overwrite is enabled by INS_CRC [TFRM; addr 072]. In T1 mode, CRC6 may be computed on only the payload data or on all data including the F-bit. Setting TINCF [TCR0; addr 070] selects CRC6 computation on all data. If the transmit frame format is configured as ESF and INS_CRC is active, the 2 kbps CRC sequence is inserted. The position of the CRC-6 bits is shown in Table A-4, Extended Superframe Format. If the transmit frame format is configured as E1, and INS_CRC is active, the 4 kbps CRC sequence is inserted. The position of the CRC-4 bits is shown in Table A-6, ITU-T CEPT Frame Format Time Slot 0 Bit Allocations. The register bits that control FEBE are INS_FE [TFRM; addr 072], TFEBE [TMAN; addr 074], FEBE_I [TMAN; addr 074], and FEBE_II [TMAN; addr 074]. The Far-End Block Error (FEBE) generation circuitry inserts FEBE bits automatically or manually. Automatic FEBE generation is enabled by INS_FE. If the transmit frame format is configured as E1 and INS_FE bit is set, a FEBE is generated in response to an incoming CRC-4 error by setting an E-bit of TS0 to zero. Refer to Table A-6, ITU-T CEPT Frame Format Time Slot 0 Bit Allocations, for the location of the E-bits within the E1 frame. Manual FEBE generation is enabled by TFEBE. If the transmit frame format is configured as E1 and TFEBE is set, the FEBE bits are supplied by the processor in FEBE_I and FEBE_II.
2.4.4.4 Far-End Block Error Generation
100054E
Conexant
2-49
2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.4.5 Test Pattern Generation
The transmit test pattern generation circuitry overwrites the transmit data with various test patterns and permits logical and frame-bit error insertion. This feature is particularly useful for system diagnostics, production testing, and test equipment applications. The test pattern can be a framed or unframed PRBS pattern. The PRBS patterns available include 2E11-1, 2E15-1, 2E20-1, and 2E23-1. Each pattern can optionally include Zero Code Suppression (ZCS). Error insertion includes LCV, BPV, Ft, CRC4, CRC6, COFA, PRBS, Fs, MFAS, and CAS. The Transmit Test Pattern Configuration register [TPATT; addr 076] controls the test pattern insertion circuit. TPATT controls the PRBS pattern (TPATT[1:0]) bits), ZCS setting (ZLIMIT bit), T1/E1 framing (FRAMED bit), and starting and stopping transmission (TPSTART bit). Patterns are generated in accordance with ITU-T O.150 (10/92), O.151 (10/92), and O.152 (10/92). Enabling ZLIMIT modifies the inserted pattern by limiting the number of consecutive zeros. For the 2E11-1 or 2E15-1 PRBS patterns, eight or more zeros will not occur with ZLIMIT enabled. For the 2E20-1 or 2E23-1 PRBS patterns, 15 or more zeros will not occur with ZLIMIT enabled. Note that the QRSS pattern is a 2E20-1 PRBS with ZLIMIT enabled. This function is performed according to ANSI T1.403 and ITU-T O.151 (10/92). Frame bit positions can be preserved in the output pattern by enabling FRAMED. In T1 mode, this prevents the test pattern from overwriting the frame bit which occurs every 193 bits. In E1 mode with FRAMED enabled, the test pattern does not overwrite time slot 0 data (FAS and NFAS words) and time slot 16 (CAS signalling word) if CAS framing is also selected. CAS framing is selected by setting TFRAME[3] to 1 in the Transmit Configuration register [TCR0; addr 070]. The test pattern is stopped during these bit periods according to ITU-T O.151, (10/92). If FRAMED is disabled, the test pattern is transmitted in all time slots.
2.4.6 Transmit Error Insertion
The Transmit Error Insert register [TERROR; addr 073] controls error insertion during pattern generation. Writing one to a TERROR bit injects a single occurrence of the respective error on TPOSO/TNEGO and XTIP/XRING outputs; writing a zero has no effect. Multiple transmit errors can be generated simultaneously. Periodic or random bit error rates can also be emulated by software control of the error control bit. Note that injected errors affect the data sent during a Framer or Analog Loopback [FLOOP or ALOOP; addr 014]. Line Code Violations (LCV) are inserted via the TVERR bit of the TERROR register. In T1 mode, if TVERR is set, a BPV is inserted between two consecutive ones. TVERR is latched until the BPV is inserted into the transmit data stream, and then cleared. In E1 mode with HDB3 selected, two consecutive BPVs of the same polarity are inserted. This is registered as a single LCV for the receiving E1 equipment. Ft, FPS, and FAS bit errors are inserted using the TFERR bit in the TERROR register. TFERR commands a logical inversion of the next frame bit transmitted. CRC4 (E1) and CRC6 (T1) bit errors are inserted using the TCERR bit in the TERROR register. TCERR commands a logical inversion of the next CRC bit transmitted.
2-50
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.4 Transmitter
Change Of Frame Alignments (COFAs) are controlled by the TCOFA and BSLIP bits in the TERROR register. TCOFA commands a 1-bit shift in the location of the transmit frame alignment by deleting (or inserting) a 1-bit position from the transmit frame. During E1 modes, BSLIP determines which direction the bit slip occurs. In T1 modes, only 1-bit deletion is provided. Note that TCOFA alters extraction rate of data from transmit slip buffer; thus, repeated TCOFAs eventually cause a controlled frame slip where one frame of data is repeated (T1/BSLIP = 0), or where one frame of data is deleted (BSLIP = 1). PRBS test pattern errors are inserted by TBERR in the TERROR register. TBERR commands a single PRBS error by logically inverting the next PRBS generator output bit. Fs and MFAS errors are controlled by the TMERR bit in the TERROR register. TMERR commands a single Fs bit error in T1, or MFAS bit error in E1 by logically inverting the next multiframe bit transmitted. CAS Multiframe (MAS) errors are controlled by the TSERR bit in the TERROR register. TSERR commands a single MAS pattern error by logically inverting the first MAS bit transmitted.
2.4.7 In-Band Loopback Code Generation
The in-band loopback code generator circuitry overwrites the transmit data with in-band codes of configurable value and length. These codes are sequences with periods of 1 to 7 bits and may, in some applications, overwrite the framing bit. The Transmit Inband Loopback Code Configuration register [TLB; addr 077] controls the functions required for this operation. A loopback code is generated in the transmit data stream by writing the loopback code to the Transmit Inband Loopback Code Pattern register [LBP; addr 078], and then setting the Start Inband Loopback (LBSTART) and Loopback Length (LB_LEN) bits in the Transmit Inband Loopback Code Configuration register [TLB; addr 077]. The TLB register optionally allows the loopback code to overwrite framing bits using the UNFRAMED bit. The LB_LEN provides loopback code pattern lengths of 4 to 7 bits. Patterns of 2 or 3 bits can be achieved by repeating the pattern in 4- or 6-bit modes, respectively. Framed or unframed all ones or all zeros can also be achieved by setting the pattern to all zeros or all ones.
2.4.8 ZCS Encoder
The ZCS encoder encodes the single rail clock and data (unipolar) into dual rail data (bipolar). The Transmit Zero Code Suppression Bits (TZCS[1,0]) in the Transmitter Configuration register [TCR1; addr 071] selects ZCS and Pulse Density Violation (PDV) enforcement options for TPOSO/TNEGO output pins. TZCS supports the following: Alternate Mark Inversion (AMI); High Density Bipolar of order 3 (HDB3); Bipolar with 8 Zero Suppression (B8ZS); Pulse Density Violation (PDV); Unassigned Mux Code (UMC); and Bipolar with 7 Zero Suppression (B7ZS). Note that ZCS encoding, which alters data content, is performed prior to the CRC calculation so the outgoing CRC is always correct. The AMI line code requires at least 12.5 percent average ones density and no more than 15 consecutive zeros. A one is encoded as either a positive or negative pulse; a zero is the absence of a pulse. Two consecutive pulses of the same polarity are referred to as a Bipolar Violation (BPV).
100054E
Conexant
2-51
2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
The HDB3 line code replaces four consecutive zeros by 000V or B00V code, where B is an AMI pulse and V is a bipolar violation (see Figure 2-24). ZCS encoder selects the code that will force the BPV output polarity opposite to the prior BPV .
Figure 2-24. Zero Code Substitution Formats
Zero Code Substitution Formats Octet
1
1
0
0
0
0
0
0
0
0
1
1
AMI
BPV B8ZS
BPV
BPV HDB3
BPV
B7ZS
UMC
UMC forces DS0 channels containing 8 zeros to be replaced with the 10011000 code, per Bellcore TA-TSY-000278. Note that RCVR's ZCS decoder cannot recover original data content from a UMC or B7ZS encoded signal, or from a PDV-enforced one.
2-52
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.4 Transmitter
The output on TPOSO/TNEGO can be changed from dual rail bipolar to NRZ unipolar data (TNRZO) and to multiframe sync clock (MSYNCO), using the Transmit NRZ Data (TNRZ) bit in TCR1[addr 071]. Figures 2-25 and 2-26 illustrate transmit signal timing for both bipolar and unipolar operation.
Figure 2-25. Transmit Signals
TCKO
TPOSO (Bipolar) TNEGO (Bipolar)
TNRZO (Unipolar) 1 1 0 1 1 0 0 1
8394-8-5_077
100054E
Conexant
2-53
2.0 Circuit Description
2.4 Transmitter
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 2-26. NRZ Mode Transmit Signals
MSYNCO
TCKO
TNRZO
Bit 8
F-bit
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Time Slot 24, Frame 12 (SF) or Frame 24 (ESF)
Time Slot 1, Frame 1 T1 Mode
In E1 mode, MSYNCO is output during bit 7 of time slot 31 in frame 15 of the multiframe. MSYNCO
TCKO
TNRZO
Bit 6
Bit 7
Bit 8
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Time Slot 31, Frame 15 E1 Mode
Time Slot 0, Frame 0
8394-8-5_078
2-54
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.5 Microprocessor Interface
2.5 Microprocessor Interface
The Microprocessor Interface (MPU) provides the capability to configure the device, read status registers and counters, and respond to interrupts (see Figure 2-27). The interface supports both the Intel 8051 and Motorola 68000-type processors. In the Intel mode, the address and data are multiplexed; in the Motorola mode, the address and data are separate pins. Both synchronous and asynchronous Read and Write modes are supported. The synchronous mode is optimized for Motorola 68000-type processors with a maximum clock rate of 36 MHz. The asynchronous mode runs internally at 32 MHz, which limits the processor speed to 30 MHz for 68302 processors, and 16 MHz for 8051 processors. The microprocessor interface is made up of the following pins: MCLK, MOTO*, SYNCMD, CS*, AS*/ALE, DS*/RD*, R/W*/WR*, DTACK*, AD[7:0], A[11:0], INTR*, ONESEC, RST*. A detailed description of the MPU signals is provided in Table 1-6, Hardware Signal Definitions.
Figure 2-27. Microprocessor Interface Block Diagram
MCLK MOTO* SYNCMD CS* AS*/ALE DS*/RD* R/W*(WR*) DTACK* AD[7:0] A[11:0] INTR* ONESEC RST* Microprocessor Interface
100054E
Conexant
2-55
2.0 Circuit Description
2.5 Microprocessor Interface
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.5.1 Address/Data Bus
In Non-Multiplexed Address Mode, A[11:0] (A[10:0] for CX28394) provides the address for the register access. In Multiplexed Address Mode, A[11:8] (A[10:8] for CX28394) and AD[7:0] provide the address. In both modes, the data bytes flow over the shared bidirectional, byte-wide bus, AD[7:0].
2.5.2 Bus Control Signals
Four signals control operation of the interface port. The control signals are AS*/ALE, CS*, DS*/RD*, and R/W*(WR*). An additional pin, MOTO*, selects whether the interface signals are of a Motorola or Intel style. When MOTO* is low, indicating a Motorola-style interface, CS*, AS*, R/W*, and DS* signals are expected. When MOTO* is high, indicating an Intel-style interface, CS*, ALE, RD*, and WR* signals are expected. When MOTO* is high, the address lines are multiplexed with the data. This pin should usually be tied high for Intel devices and tied low for Motorola devices. SYNCMD puts the interface into the Synchronous Processor Interface Mode. Motorola 68000 processors typically have SYNCMD tied high if MCLK is connected to the MPU clock source; Intel 8051 processors have SYNCMD tied low (see Table 2-7).
Table 2-7. Microprocessor Interface Operating Modes MOTO*
0 0 1 1
SYNCMD
0 1 0 1
Description
Asynchronous Motorola, internal clock Synchronous Motorola, external clock Asynchronous Intel, internal clock Synchronous Intel, external clock
2.5.3 Interrupt Requests
Figure 2-28, Interrupt Generation Block Diagram, details the interrupt generation process. The INTR* output pin is an active low, open-drain type output which provides a common interrupt request for all eight framers and the LIU serial interface. Each framer includes interrupt status registers (ISR[7:0]), interrupt enable registers (IER[7:0]), and an interrupt request register (IRR). Events such as alarm status changes and sync signals are latched in ISR registers until read by the microprocessor. Each ISR bit has a corresponding IER bit used to enable or disable interrupt generation. If enabled, an ISR event is reported in the appropriate IRR bit.
2-56
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.5 Microprocessor Interface
The IRR bits from each framer are gated with the corresponding enable bit in the master interrupt enable register [MIE; addr 01E] and are routed to the master interrupt register [MIR; addr 01D]. MIE provides a convenient location to enable or disable interrupts for an entire framer. The serial done bit [SER_STAT; addr 024] is gated with the serial interrupt enable bit [SER_CONFIG; addr 025] to produce an additional interrupt request. Finally, MIR bits and the LIU serial interface interrupt request are combined to generate a single interrupt request signal on the INTR* pin. Using these registers, the microprocessor can process interrupts as follows: Interrupt service routine Read MIR and SER_STAT registers to determine which framer or framers caused the interrupt or whether LIU serial operation occurred. 2. For each interrupting framer, read IRR to determine which ISR contains the interrupt event or events. 3. Read the ISR and mask the interrupt event bit using the corresponding IER to determine which event or events caused the interrupt. 4. Enter the appropriate service routine.
1.
Figure 2-28. Interrupt Generation Block Diagram
SER_DONE SER_IER
Framer 8 Framer 7 Framer 6 Framer 5 Framer 4 Framer 3 Framer 2 Framer 1
INTR*
MIR Register
ISR Latches IRR Register IER Registers MIE Register
Events
NOTE(S):
(1)
In CX28395, INTR1* is provided for Framers 1-8, and INTR2* is provided for Framers 9-16.
100054E
Conexant
2-57
2.0 Circuit Description
2.5 Microprocessor Interface
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.5.4 Device Reset
The device contains four reset methods: Internal Power-On Reset (POR), Hardware Reset which uses the RST* pin, Global Software Reset which uses the GRESET bit in register FCR [addr 080], and 4. Software Reset which uses the RESET bit in register CR0 [addr 001].
1. 2. 3.
All four methods result in device outputs placed in a high-impedance state and configuration registers set to default values as shown in Table 3-4, Address Map. In all reset methods, SYSCKI must be present during the reset process for proper operation. MCLK (internal or external) performs the actual register initialization. Therefore, if the SYNCMD pin is connected high to enable external MCLK, the external MCLK must be applied during reset, and if the SYNCMD pin is low during reset, the internal clock (33 MHz) is used and external MCLK is not required. After hardware reset, software reset, or internal power-on reset, the microprocessor must initialize the configuration registers to the desired state. An internal POR process is initiated during power-up. When VDD has reached approximately 2.0 V, the internal reset process begins and continues for 100 SYSCKI cycles if SYSCKI is applied. If SYSCKI is not present, the device remains in the reset state and does not terminate until detecting 100 SYSCKI cycles. GRESET or RESET can be monitored to determine when POR is complete. MCLK (internal or external) must be present during the POR concurrent with SYSCKI to allow register initialization. Hardware reset is initiated by bringing the RST* pin active (low) for a minimum of 4 s. If SYNCMD is high (using external MCLK), external MCLK must be present while RST* is low to allow register initialization. After RST* is deactivated, the internal reset process continues for 5 s and register access should be avoided. GRESET can be monitored to determine when the reset process is complete.
2-58
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.6 Loopbacks
2.6 Loopbacks
The device provides a complete set of loopbacks for diagnostics, maintenance, and troubleshooting for each framer. All loopbacks perform clock and data switching, if necessary.
2.6.1 Remote Line Loopback
The line loopback loops the RCVR inputs to the XMTR outputs. The loopback provides BPV transparency and the ability to override the looped data with AIS. The RCVR data path is not affected by the activation of this loopback. Remote line loopback is activated by setting the Remote Line Loopback (LLOOP) bit in the Loopback Configuration register [LOOP; addr 014]. It is possible to operate the remote line loopback simultaneously with the local framer loopback.
2.6.2 Remote Payload Loopback
The payload loopback loops all DS0 channels from the RCVR input to the XMTR output. Payload loopback retains time slot integrity, so that numbered time slots from each receive frame are transferred to the same numbered time slots in the transmit frame. Transmit overhead bits--F-bits in T1 mode or TS0 in E1 mode--are supplied by transmit frame formatter or by TSB according to TFRM [addr 072] settings. Existing transmit frame alignment and clock timing are not altered by [PLOOP; addr 014] activation or deactivation, allowing system operation with independent receive and transmit timing. Controlled frame slips are performed in the payload loopback path if receive and transmit clocks are asynchronous, although these slips are not reported to the processor as slip buffer errors. Multiframe integrity is not maintained during PLOOP; therefore, DS0 and signaling channel loopbacks [TPCn; addr 100-11F] must be used to implement payload loopback if transparent or forced signaling is desired. PLOOP overrides transmit per-channel remote loopback selection (TLOOP bit in TPCn).
2.6.3 Remote Per-Channel Loopback
The remote per-channel loopback loops the RCVR input DS0 channel to the XMTR output DS0 channel. The remote per-channel loopback is activated by setting TLOOP in the Transmit Per-Channel Control register [TPC0 to TPC31; addr 100 to 11F].
100054E
Conexant
2-59
2.0 Circuit Description
2.6 Loopbacks
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.6.4 Local Framer Loopback
The local framer loopback loops the transmit line encoder outputs to the receive line decoder inputs. Transmitter output is not affected by the activation of this loopback. The local framer loopback is activated by setting the Local Framer Loopback (FLOOP) bit in the Loopback Configuration register [LOOP; addr 014]. It is possible to operate the local framer loopback simultaneously with the remote line loopback.
2.6.5 Local Per-Channel Loopback
The local per-channel loopback loops the TSB PCM and signaling inputs to the RSB PCM and signaling outputs on a per-channel basis. The local per-channel PCM loopback is activated by setting RLOOP in the System Bus Per-Channel Control registers [SBC0 to SBC31; addr 0E0 to 0FF]. The local per-channel signaling loopback is activated by setting SIG_LP in System Bus Per-Channel Control registers.
2-60
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.7 Serial Interface
2.7 Serial Interface
The device provides a serial interface that allows the microprocessor to indirectly communicate with an attached LIU (such as the Conexant CX28380 Quad T1/E1 LIU). This interface allows the microprocessor to control and query the LIU status. One 8-bit register in the LIU can be written via the SERDO pin or read from the SERDI pin at the clock rate determined by the SERCKO clock output. The serial interface supports a glueless interface to two quad LIUs by supplying two independently controlled external chip select lines on the CX28398: SERCS1* and SERCS2*. The CX28394 provides a single SERCS* chip select line. On the CX28395, the serial interface is not accessable. The serial interface uses a 16-bit process for each write or read operation. During a write operation, a 16-bit word--consisting of [SER_CTRL; addr 022] and [SER_DAT; addr 023]--is transmitted to the LIU. The SER_CTL register contains the LIU register address for the current operation and a read/write control bit. During a read operation, SER_CTL is transmitted and 8-bit data from the LIU is received and placed in SER_DAT register. Writing to SER_CTL initiates a serial interface read or write operation. The Data register contains either write or read data. For the write operation, its content is written to the SERDO serial port on the eight SERCKO cycles immediately following the Address/Command byte. Likewise, for the read operation, data on the SERDI serial port is input immediately on the eight SERCKO clock cycles following the Address/Command byte. Figure 2-29 illustrates serial interface timing.
Figure 2-29. Serial Interface Timing Diagram
SERCS*
SERCLK
SERDO
SERDI
SERCS*
SERCLK
SERDO
SERDI
100054E
; ;;; ;; ;;; ;; ; ;; ;;;;;;
Read Timing
R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
Write Timing
R/W A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
Conexant
2-61
2.0 Circuit Description
2.8 Joint Test Access Group
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.8 Joint Test Access Group
The device incorporates printed circuit board testability circuits in compliance with IEEE Std. P1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture, commonly known as JTAG (Joint Test Action Group). The JTAG includes a Test Access Port (TAP) and several data registers. The TAP provides a standard interface through which instructions and test data are communicated (see Figure 2-30). A Boundary Scan Description Language (BSDL) file is available from Conexant upon request. The test access port consists of TDI, TCK, TMS, TDO and TRST* pins.
Figure 2-30. Test Access Port (TAP) Diagram
TCK TMS TRST* TDI (CX28394, CX28398) TDO JTAG Port TDO1 (CX28395) TDO2
100054_003
2.8.1 Instructions
In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST instructions, IDCODE instruction is supported. There is also one private instruction. Table 2-8 lists the JTAG instructions along with their codes.
Table 2-8. JTAG Instructions Instruction
BYPASS SAMPLE/PRELOAD EXTEST IDCODE Private
Code
111 001 000 010 xxx
2-62
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2.0 Circuit Description
2.8 Joint Test Access Group
2.8.2 Device Identification Register
JTAG ID register consists of a 4-bit version, 16-bit part number, and 11-bit manufacturer number (see Tables 2-11 and 2-9).
Table 2-9. CX28394 Device Identification JTAG Register Version(1)
0 0 0x0 4 bits
NOTE(S):
Part Number
0 1 0 00 0 0 1 1 1 0 0 10 1 0 0 0 0 0
Manufacturer ID
0 00 1 0 0 1 1 1
TDO
0
0x8394 16 bits
0X013 11 bits
(1) Consult factory for current version number.
Table 2-10. CX28395 Device Identification JTAG Register Version(1)
0 0 0x0 4 bits
NOTE(S):
Part Number
0 1 0 00 0 0 1 1 1 0 0 10 1 0 1 0 0 0
Manufacturer ID
0 00 1 0 0 1 1 1
TDO1 TDO2
0
0x8395 16 bits
0X013 11 bits
(1) Consult factory for current version number.
Table 2-11. CX28398 Device Identification JTAG Register Version(1)
0 0 0x0 4 bits
NOTE(S):
Part Number
0 1 0 00 0 0 1 1 1 0 0 11 0 0 0 0 0 0
Manufacturer ID
0 00 1 0 0 1 1 1
TDO
0
0x8398 16 bits
0X013 11 bits
(1) Consult factory for current version number.
100054E
Conexant
2-63
2.0 Circuit Description
2.8 Joint Test Access Group
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
2-64
Conexant
100054E
3
3.0 Registers
3.1 Address Map
Registers shown with a default setting are reset to the indicated value following power up, software RESET (CRO; addr 001), GRESET (FCR; addr 080), or hardware reset (RST* pin). Addresses 000 (hex) to 1FF (hex) are offset by the upper 3 bits of address lines A[11:0] and chip selects as listed in Tables 3-1 through 3-3.
Table 3-1. Address Offset Map (CX28394) Framer
1 2 3 4
NOTE(S):
Chip Select CS*
0 0 0 0
Offset Address A[10:0] (hex)
000 200 400 600
1. Global registers at 000 and 080-083 may be accessed at any offsets.
Table 3-2. Address Offset Map (CX28398) Framer
1 2 3 4 5 6 7 8
NOTE(S):
Chip Select CS*
0 0 0 0 0 0 0 0
Offset Address A[11:0] (hex)
000 200 400 600 800 A00 C00 E00
1. Global registers at 000 and 080-083 may be accessed at any offsets.
100054E
Conexant
3-1
3.0 Registers
3.1 Address Map
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-3. Address Offset Map (CX28395) Chip Select Framer CS1*
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NOTE(S):
CS2*
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Offset Address A[11:0] (hex)
000 200 400 600 800 A00 C00 E00 000 200 400 600 800 A00 C00 E00
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1. Global registers at 000 and 080-083 for framers 1-8 may be accessed at any of the first 8 offsets. 2. Global registers at 000 and 080-083 for framers 9-16 may be accessed at any of the second 8 offsets.
3-2
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-4. Address Map (1 of 5) Block Address (Hex)
000 080 Global 081 082 083 Primary Control 001 003 004 005 Interrupt Status 006 007 008 009 00A 00B 00C 00D Interrupt Enable 00E 00F 010 011 012 013 014 015 016 Primary 017 018 019 01A 020 021 DID FCR MIR MIE TEST CR0 IRR ISR7 ISR6 ISR5 ISR4 ISR3 ISR2 ISR1 ISR0 IER7 IER6 IER5 IER4 IER3 IER2 IER1 IER0 LOOP DL3_TS DL3_BIT FSTAT PIO POE CMUX RAC RSTAT
3.0 Registers
3.1 Address Map
Acronym
R/W
R R/W R R/W R/W R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W
Description
Device Identification Framer Control Register Master Interrupt Request Master Interrupt Enable Test Configuration Primary Control Register Interrupt Request Register Alarm 1 Interrupt Status Alarm 2 Interrupt Status Error Interrupt Status Counter Overflow Interrupt Status Timer Interrupt Status Data Link 1 Interrupt Status Data Link 2 Interrupt Status Pattern Interrupt Status Alarm 1 Interrupt Enable Register Alarm 2 Interrupt Enable Register Error Interrupt Enable Register Count Overflow Interrupt Enable Register Timer Interrupt Enable Register Data Link 1 Interrupt Enable Register Data Link 2 Interrupt Enable Register Pattern Interrupt Enable Register Loopback Configuration Register External Data Link Channel External Data Link Bit Offline Framer Status Programmable Input/Output Programmable Output Enable Clock Input Mux Receive Alarm Configuration Receive Line Code Status
Default Register Setting (Hex)
28 00 00 00 00 00 -- -- -- -- -- -- -- -- 00 00 00 00 00 00 00 00 00 -- -- -- -- 00 3C 00 -- --
100054E
Conexant
3-3
3.0 Registers
3.1 Address Map
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-4. Address Map (2 of 5) Block Address (Hex)
022 Serial Interface 023 024 025 026 040 041 Digital Receiver (RCVR) 042 043 044 045 046 047 048 049 050 051 052 Error/Alarm Counters 053 054 055 056 057 058 059 05A 05B Receive Sa-Byte 05C 05D 05E 05F
Acronym
SER_CTL SER_DAT SER_STAT SER_CONFIG RAM TEST RCR0 RPATT RLB LBA LBD RALM LATCH ALM1 ALM2 ALM3 FERR FERR CERR CERR LCV LCV FEBE FEBE BERR BERR AERR RSA4 RSA5 RSA6 RSA7 RSA8
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R R Serial Control Serial Data Serial Status
Description
Default Register Setting (Hex)
-- -- -- 00 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Serial Configuration Ram Test Receiver Configuration Receive Test Pattern Configuration Receive Loopback Code Detector Configuration Loopback Activate Code Pattern Loopback Deactivate Code Pattern Receive Alarm Signal Configuration Alarm/Error/Counter Latch Configuration Alarm 1 Status Alarm 2 Status Alarm 3 Status Framing Bit Error Counter LSB Framing Bit Error Counter MSB CRC Error Counter LSB CRC Error Counter MSB Line Code Violation Counter LSB Line Code Violation Counter MSB Far End Block Error Counter LSB Far End Block Error Counter MSB PRBS Bit Error Counter LSB PRBS Bit Error Counter MSB SEF/LOF/COFA Alarm Count Receive Sa4 Byte Buffer Receive Sa5 Byte Buffer Receive Sa6 Byte Buffer Receive Sa7 Byte Buffer Receive Sa8 Byte Buffer
3-4
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-4. Address Map (3 of 5) Block Address (Hex)
070 Digital Transmitter (XMTR) 071 072 073 074 075 076 077 078 07B Transmit Sa-Byte 07C 07D 07E 07F 0A0 BOP 0A1 0A2 0A3 0A4 0A5 0A6 0A7 Data Link #1 0A8 0A9 0AA 0AB 0AC 0AD 0AE
3.0 Registers
3.1 Address Map
Acronym
TCR0 TCR1 TFRM TERROR TMAN TALM TPATT TLB LBP TSA4 TSA5 TSA6 TSA7 TSA8 BOP TBOP RBOP BOP_STAT DL1_TS DL1_BIT DL1_CTL RDL1_FFC RDL1 RDL1_STAT PRM TDL1_FEC TDL1_EOM TDL1 TDL1_STAT
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R R R/W R/W W R/W R
Description
Transmit Framer Configuration Transmitter Configuration Transmit Frame Format Transmit Error Insert Transmit Manual Sa-Byte/FEBE Configuration Transmit Alarm Signal Configuration Transmit Test Pattern Configuration Transmit Inband Loopback Code Configuration Transmit In-Band Loopback Code Pattern Transmit Sa4 Byte Buffer Transmit Sa5 Byte Buffer Transmit Sa6 Byte Buffer Transmit Sa7 Byte Buffer Transmit Sa8 Byte Buffer Bit Oriented Protocol Transceiver Transmit BOP Code Word Receive BOP Code Word BOP Status DL1 Time Slot Enable DL1 Bit Enable DL1 Control RDL #1 FIFO Fill Control Receive Data Link FIFO #1 RDL #1 Status Performance Report Message TDL #1 FIFO Empty Control TDL #1 End Of Message Control Transmit Data Link FIFO #1 TDL #1 Status
Default Register Setting (Hex)
-- -- -- 00 -- -- -- -- -- -- -- -- -- -- 00 00 -- -- 00 00 00 00 -- -- 00 00 -- -- --
100054E
Conexant
3-5
3.0 Registers
3.1 Address Map
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-4. Address Map (4 of 5) Block Address (Hex)
0AF 0B0 0B1 Data Link #2 0B2 0B3 0B4 0B6 0B7 0B8 0B9 0BA 0BB Test 0BC 0BD 0BE 0D0 0D1 0D2 0D3 0D4 System Bus Interface (SBI) 0D5 0D6 0D7 0D8 0D9 0DA 0DB 0DC 0DD 0E0-0FF
Acronym
DL2_TS DL2_BIT DL2_CTL RDL2_FFC RDL2 RDL2_STAT TDL2_FEC TDL2_EOM TDL2 TDL2_STAT DL_TEST1 DL_TEST2 DL_TEST3 DL_TEST4 DL_TEST5 SBI_CR RSB_CR RSYNC_BIT RSYNC_TS TSB_CR TSYNC_BIT TSYNC_TS RSIG_CR RSYNC_FRM SSTAT STACK RPHASE TPHASE PERR SBCn: n = 0 to 31
R/W
R/W R/W R/W R/W R R R/W W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W
Description
DL2 Time-Slot Enable DL2 Bit Enable DL2 Control RDL #2 FIFO Fill Control Receive Data Link FIFO #2 RDL #2 Status TDL #2 FIFO Empty Control TDL #2 End Of Message Control Transmit Data Link FIFO #2 TDL #2 Status DLINK Test Configuration DLINK Test Status DLINK Test Status DLINK Test Control #1 or Configuration #2 DLINK Test Control #2 or Configuration #2 System Bus Interface Configuration Receive System Bus Configuration Receive System Bus Sync Bit Offset Receive System Bus Sync Time Slot Offset Transmit System Bus Configuration Transmit System Bus Sync Bit Offset Transmit System Bus Sync Time Slot Offset Receive Signaling Configuration Signaling Reinsertion Frame Offset Slip Buffer Status Receive Signaling Stack RSLIP Phase Status TSLIP Phase Status RAM Parity Status System Bus Per-Channel Control
Default Register Setting (Hex)
00 00 00 00 -- -- 00 -- -- -- 00 00 00 00 00 00 00 -- -- 00 -- -- -- -- -- -- -- -- -- --
3-6
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-4. Address Map (5 of 5) Block Address (Hex)
100-11F 120-13F 140-15F Buffer Memory 160-17F 180-19F 1A0-1BF 1C0-1DF 1E0-1FF
3.0 Registers
3.1 Address Map
Acronym
TPCn: n = 0 to 31 TSIGn: n = 0 to 31 TSLIP_LOn: n = 0 to 31 TSLIP_HIn: n = 0 to 31 RPCn: n = 0 to 31 RSIGn: n = 0 to 31 RSLIP_LOn: n = 0 to 31 RSLIP_HIn: n = 0 to 31
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Description
Transmit Per-Channel Control Transmit Signaling Buffer Transmit PCM Slip Buffer Transmit PCM Slip Buffer Receive Per-Channel Control Receive Signaling Buffer Receive PCM Slip Buffer Receive PCM Slip Buffer
Default Register Setting (Hex)
-- -- -- -- -- -- -- --
100054E
Conexant
3-7
3.0 Registers
3.2 Global Control and Status Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.2 Global Control and Status Registers
Global registers are applicable to all framers in the CX28394 and CX28398. There are two sets of global registers for the CX28395, one for each 8-framer group.
000--Device Identification (DID)
Read only value.
7 DID[7] 6 DID[6] 5 DID[5] 4 DID[4] 3 DID[3] 2 DID[2] 1 DID[1] 0 DID[0]
DID[7:4] DID[3:0]
Device Revision--A value of 0x4 indicates the current revision. Device ID--A value of 0x8 indicates the CX28398 or CX28395. A value of 0x4 indicates the CX28394.
080--Framer Control Register (FCR)
Unused bits are reserved and should be written to 0.
7 GRESET 6 - 5 - 4 - 3 - 2 ONESEC_IO 1 SBIMODE[1] 0 SBIMODE[0]
GRESET
Global Reset --When written to 1 by the microprocessor, GRESET initiates an internal global reset process which initializes all global control registers and certain control registers for all framers to their default settings (see Table 3-4). The internal reset process takes a maximum of 15 sec. The processor must not write to the control registers until the reset process is complete. GRESET remains active (1) during the reset process to allow the microprocessor to detect reset completion. GRESET also indicates a reset operation triggered by power-up or by an active low RST* pin. After GRESET initialization, the following is true: * System bus outputs (RSIGO, RPCMO, and SIGFRZ) for all framers are three-stated. * Programmable I/O pins are configured as inputs. * Global control and framer control registers are set to their default values.
ONESEC_IO
Bidirectional ONESEC Input/Output Mode--Selects input or output mode for ONESEC signal pin and controls the internal timer interval used for one-second status latching [LATCH; addr 046]. When ONESEC is an output, SYSCLK is used to develop the one-second timer interval output with an arbitrarily defined initial starting location. When ONESEC is an input, the timer/latch interval is aligned to rising edge of ONESEC input. The system can apply ONESEC input to define any length timer/latch interval up to 1 second, but not greater than 1 second. 0 = ONESEC input 1 = ONESEC output
3-8
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
SBIMODE[1:0]
3.0 Registers
3.2 Global Control and Status Registers
The processor writes FCR at power-up to configure the system bus interface mode. Each group of four framers can be configured as separate system bus interfaces or as an internally multiplexed group. The group consisting of framers 1 through 4 (9 through 12) can be configured to share a common system bus interface, SBI Bus A. The group consisting of framers 5 through 8 (13 through 16) can also be configured to share a common system bus interface, SBI Bus B. SBIMODE[1]: SBIMODE[0]: 0= 1= 0= 1= Separate system bus interface mode for framer group 5-8 (13-16). Common, multiplexed system bus interface mode. Separate system bus interface mode for framer group 1-4 (9-12). Common, multiplexed system bus interface mode.
081--Master Interrupt Request (MIR)
CX28394
7 -- 6 -- 5 -- 4 -- 3 MIR[3] 2 MIR[2] 1 MIR[1] 0 MIR[0]
CX28398 and CX28395
7 MIR[7] 6 MIR[6] 5 MIR[5] 4 MIR[4] 3 MIR[3] 2 MIR[2] 1 MIR[1] 0 MIR[0]
MIR[7:0]
An active MIR bit indicates which framer has active interrupts. An MIR bit is latched active (high) whenever any bit in the Interrupt Request Register (IRR[7:0]; addr 003-0B) is set to report an interrupt event. MIR0: MIR1: MIR2: MIR3: MIR4: MIR5: MIR6: MIR7: 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= no interrupt event in framer 0 active interrupt event in framer 0 no interrupt event in framer 1 active interrupt event in framer 1 no interrupt event in framer 2 active interrupt event in framer 2 no interrupt event in framer 3 active interrupt event in framer 3 no interrupt event in framer 4 active interrupt event in framer 4 no interrupt event in framer 5 active interrupt event in framer 5 no interrupt event in framer 6 active interrupt event in framer 6 no interrupt event in framer 7 active interrupt event in framer 7
100054E
Conexant
3-9
3.0 Registers
3.2 Global Control and Status Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
082--Master Interrupt Enable (MIE)
CX28394
7 -- 6 -- 5 -- 4 -- 3 MIE[3] 2 MIE[2] 1 MIE[1] 0 MIE[0]
CX28398 and CX28395
7 MIE[7] 6 MIE[6] 5 MIE[5] 4 MIE[4] 3 MIE[3] 2 MIE[2] 1 MIE[1] 0 MIE[0]
MIE[7:0]
MIE is a global interrupt enable for each framer. Writing a one to an MIE bit enables the corresponding framer's IRR bit to be latched in MIR (addr 081) and to activate the INTR* output. MIE0: MIE1: MIE2: MIE3: MIE4: MIE5: MIE6: MIE7: 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= 0= 1= Disable framer 0 IRR interrupt Enable framer 0 IRR interrupt Disable framer 1 IRR interrupt Enable framer 1 IRR interrupt Disable framer 2 IRR interrupt Enable framer 2 IRR interrupt Disable framer 3 IRR interrupt Enable framer 3 IRR interrupt Disable framer 4 IRR interrupt Enable framer 4 IRR interrupt Disable framer 5 IRR interrupt Enable framer 5 IRR interrupt Disable framer 6 IRR interrupt Enable framer 6 IRR interrupt Disable framer 7 IRR interrupt Enable framer 7 IRR interrupt
083--Test Configuration (TEST)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 TEST 0 --
TEST
Global Test Enable--Reserved for Conexant production test.
3-10
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.3 Primary Control and Status Register
3.3 Primary Control and Status Register
001--Primary Control Register (CR0)
Unused bits are reserved and should be written to 0.
7 RESET 6 -- 5 RINCF 4 RFRAME[3] 3 RFRAME[2] 2 RFRAME[1] 1 RFRAME[0] 0 T1/E1N
RESET
Framer Reset--When written to 1 by the microprocessor, RESET initiates an internal reset process which initializes certain control registers to their default settings (see Table 3-4). The internal reset process takes a maximum of 15 sec. The processor must not write to the control registers until the reset process is complete. RESET remains active (1) during the reset process to allow the microprocessor to detect reset completion. RESET also indicates a reset operation triggered by power-up, GRESET [FCR; addr 080], or by an active low RST* pin. After RESET initialization, the following is true: * System bus outputs (RSIGO, RPCMO, and SIGFRZ) are three-stated. * Programmable I/O pins are configured as inputs. * Framer control registers are set to their default values.
RINCF
Receiver Framer CRC6 include F-bit--Determines if the F-bit is included in the CRC6 remainder calculation in T1 mode (T1/E1N = 1). This bit is ignored in E1 mode (T1/E1N = 0). 0 = T1 ESF CRC6 calculation is performed on the receive data including a 1 in place of the F-bit. 1 = TI ESF CRC6 transmit calculation is performed on receive data including the F-bit.
100054E
Conexant
3-11
3.0 Registers
3.3 Primary Control and Status Register
RFRAME[3:0]
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Receiver Framer Mode--Establishes the offline framer's search criteria for recovery of frame alignment (reframe). Also works in conjunction with the RLOFA-RLOFD bits [addr 040] to establish the online framer's criteria for loss of frame alignment. Refer to Tables A-1 through A-6 to find which frame bits are monitored and Table 2-2, Criteria for Loss/Recovery of Receive Framer Alignment, for frame alignment loss/recovery criteria during the selected mode. Mode descriptions are given in Table 3-5. Online framer's SF, SLC, CAS and MFAS criteria for loss/recovery of multiframe alignment are also selected by RFRAME[3:0].
Table 3-5. Receive Framer Modes RFRAME[3:0]
000X 001X 010X 011X 100X 101X 110X 111X 0000 0001 0100 0101 0110 1000 1001 1100 1101
T1/E1N
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 FAS Only
Receive Framer Mode
FAS Only + BSLIP FAS + CRC FAS + CRC + BSLIP FAS + CAS FAS + CAS + BSLIP FAS + CRC + CAS FAS + CRC + CAS + BSLIP FT Only ESF + No CRC (FPS only) SF SF + JYEL SF + T1DM SLC + FSLOF SLC ESF + Mimic CRC ESF + Force CRC
T1/E1N
Global T1/E1 Select--Affects all functions by enabling receive and transmit circuits to operate at either the T1 or E1 line rate. The processor should reinitialize all control register settings after changing the T1/E1N control bit. T1/E1N selects the nominal line rate (shown below) while the exact receive and transmit line rate frequencies are independently determined by their respective input clock or input data references. The actual receive and transmit line frequency can vary within defined tolerances. 0 = 2.048 MHz line rate (E1) 1 = 1.544 MHz line rate (T1)
3-12
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.4 Interrupt Control Register
3.4 Interrupt Control Register
003--Interrupt Request Register (IRR)
An IRR bit is latched active (high) whenever an enabled interrupt source reports an interrupt event in the corresponding Interrupt Status Register [ISR7-ISR0; addr 004-00B]. IRR is latched until the corresponding ISR register is read by the processor. Reading ISR clears the respective IRR bit, independent of clearing ISR bits. Therefore, persistently active ISR bits won't affect INTR* deactivation. All IRR bits are logically OR'ed to activate a corresponding MIR bit and INTR*, so the processor must read IRR = 00 before exiting its interrupt service routine in order to confirm the MIR bit has been deasserted.
7 ALARM1 6 ALARM2 5 ERROR 4 COUNT 3 TIMER 2 DL1 1 DL2 0 PATT
ALARM1
Alarm 1 Interrupt Request--Indicates one or more receiver errors. Processor reads ISR7 [addr 004] to locate specific source. 0 = no event 1 = active interrupt request Alarm 2 Interrupt Request--Indicates one-second timer expiry, or detection of one or more transmitter errors, or detection of inband loopback codeword. Processor reads ISR6 [addr 005] to locate specific source. 0 = no event 1 = active interrupt request Error Interrupt--Indicates one or more errors detected by receive framer, RSLIP, or TSLIP circuits. Processor reads ISR5 [addr 006] to locate specific source. 0 = no event 1 = active interrupt request Counter Overflow Interrupt--Indicates one or more error counts [addr 050-05A] have issued an overflow interrupt. Processor reads ISR4 [addr 007] to locate specific source. 0 = no event 1 = active interrupt request Timer Interrupt Request--Indicates that the transmit, receive, or system bus timebase has reached a frame count terminus or that the receive signaling stack [STACK; addr 0DA] has been updated with new signaling during the prior multiframe. Processor reads ISR3 [addr 008] to locate specific source. 0 = no event 1 = active interrupt request Data Link Controller 1 or BOP Transmit--Indicates that a transmit or receive interrupt issued by DL1 or BOP transceiver has begun transmitting a priority codeword from TBOP [addr 0A1]. Processor reads ISR2 [addr 009] to locate specific source. 0 = no event 1 = active interrupt request
ALARM2
ERROR
COUNT
TIMER
DL1
100054E
Conexant
3-13
3.0 Registers
3.4 Interrupt Control Register
DL2
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Data Link Controller 2 or BOP Receive--Indicates that a transmit or receive interrupt issued by DL2 or BOP transceiver has received a valid priority codeword and updated RBOP [addr 0A2]. Processor reads ISR1 [addr 00A] to locate specific source. 0 = no event 1 = active interrupt request PRBS Pattern or Transmit Framer Error--Indicates detection of PRBS test pattern sync or detection of one or more transmit frame alignment pattern errors. Processor reads ISR0 [addr 00B] to locate specific source. 0 = no event 1 = active interrupt request
PATT
3-14
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.5 Interrupt Status Registers
3.5 Interrupt Status Registers
An Interrupt Status Register (ISR) bit is latched active (high) whenever its corresponding interrupt source reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding interrupt enable is active (high), each interrupt event forces the associated IRR bit active (high). Interrupt sources fall into two categories: * Rising-edge source reports an interrupt event when status changes from inactive to active state. Unless specifically noted otherwise, all ISR bits are rising-edge sources. * Dual-edge source reports an interrupt event when status changes from inactive to active (rising edge), or from active to inactive (falling edge). The processor must read the associated real-time status to determine which edge occurred. Interrupt events are reported in real time in the MIR register and on the INTR* output pin if interrupt enable is active (high). Otherwise, the interrupt status is latched and reported according to the selected latching mode [LATCH; addr 046] without asserting the MIR bit or the INTR* output pin. Table 3-6 summarizes the interrupt status registers.
Table 3-6. Interrupt Status Register Summary Bit
0 1 2 3 4 5 6 7
004 ISR7 ALARM1
SIGFRZ RLOF RLOS RALOS RAIS RPDV RYEL RMYEL
005 ISR6 ALARM2
ONESEC TLOF -- TLOC -- TPDV LOOPUP LOOPDN
006 ISR5 ERROR
FERR MERR SERR CERR -- -- RSLIP TSLIP
007 ISR4 COUNT
FERR[12] CRC[10] LCV[16] FEBE[10] BERR[12] SEF[2] COFA[2] FRED[4]
008 ISR3 TIMER
RFRAME RMF RMSYNC RSIG TFRAME TMF TMSYNC TSIG
009 ISR2 DL1
TMSG TNEAR TEMPTY TDLERR RMSG RNEAR RFULL TBOP
00A ISR1 DL2
TMSG TNEAR TEMPTY TDLERR RMSG RNEAR RFULL RBOP
00B ISR0 PATT
TFERR TMERR TSERR TCERR PSYNC BSLIP -- --
100054E
Conexant
3-15
3.0 Registers
3.5 Interrupt Status Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
004--Alarm 1 Interrupt Status (ISR7)
All events reported in ISR7 are from dual-edge sources, except Receive Pulse Density Violation [RPDV]. Any transition of real-time status in Alarm 1 Status Register [ALM1; addr 047] forces the corresponding ISR7 status bit active (high). Active high status is latched and held according to the LATCH_ALM bit [addr 046]. Each event triggers an interrupt if the corresponding IER7 bit is enabled [addr 00C].
7 RMYEL 6 RYEL 5 RPDV 4 RAIS 3 RALOS 2 RLOS 1 RLOF 0 SIGFRZ
RMYEL
Loss/Recovery of Multiframe Yellow Alarm--Reports any change in real-time status of Multiframe Yellow (E1) or ESF Yellow (T1) alarm detector. 0 = no event 1 = multiframe yellow alarm transition Loss/Recovery of Yellow Alarm--Reports any change in real-time status of Remote Alarm Indication (RAI), also referred to as yellow alarm. 0 = no event 1 = yellow alarm transition Receive Pulse Density Violation--Reports each occurrence of a receive pulse density violation according to ANSI T1.403 sliding window criteria. RPDV is latched active upon detection of any window of 8 (N+1) bits which does not contain at least N pulses. For example, RPDV reports each occurrence of 16 consecutive zeros. 0 = no error 1 = receive pulse density violation Loss/Recovery of Alarm Indication Signal--Reports any change in real-time status of the AIS detector. 0 = no event 1 = AIS transition Loss/Recovery of Receive Signal or Clock--Reports any change in RALOS [ALM1; addr 047] status. RALOS can be configured to report receive loss of clock or a continuous loss of signal for 1 msec. Loss/Recovery of Receive Signal--Reports any change in real-time status of digital receive signal detector. 0 = no event 1 = receive signal transition Loss/Recovery of Frame Alignment--Reports any change in real-time or integrated status of receive online frame status monitor. 0 = no event 1 = receive frame status transition Loss/Recovery of Signaling Freeze--Reports any change in real-time status of the SIGFRZ receiver status, which is also available on the SIGFRZ output pin. 0 = no event 1 = SIGFRZ transition
RYEL
RPDV
RAIS
RALOS
RLOS
RLOF
SIGFRZ
3-16
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.5 Interrupt Status Registers
005--Alarm 2 Interrupt Status (ISR6)
All events reported in ISR6 are from dual-edge sources, except the one-second timer [ONESEC] and Transmit Pulse Density Violation [TPDV]. Any transition of real-time status in the Alarm 2 Status Register [ALM2; addr 048] forces the corresponding ISR6 status bit active (high). Active-high status is latched and held according to the LATCH_ALM bit [addr 046]. Each event triggers an interrupt if the corresponding IER6 bit is enabled [addr 00D].
7 LOOPDN 6 LOOPUP 5 TPDV 4 -- 3 TLOC 2 -- 1 TLOF 0 ONESEC
LOOPDN
Loss/Recovery of Inband Loopback Deactivate Code--Reports any change in real-time status of inband loopback deactivate code detector. 0 = no event 1 = LOOPDN code transition Loss/Recovery of Inband Loopback Activate Code--Reports any change in real-time status of inband loopback activate code detector. 0 = no event 1 = LOOPUP code transition Transmit PDV Monitor/Enforcer--Applicable only if TZCS [addr 071] enables PDV enforcement. When enabled, TPDV is latched active if one or more PDV-enforced ones were output in order to meet ANSI T1.403 minimum pulse density requirements. 0 = no error 1 = PDV-enforced one Loss/Recovery of Transmit Clock--Reports any change in real-time status of TCKI clock monitor. 0 = No alarm 1 = clock monitor transition Loss/Recovery of Transmit Frame Alignment--Reports any change in real-time status of transmit framer's basic alignment. 0 = no alarm 1 = transmit framer transition One Second Timer Event--ONESEC is derived from the internal 1-second timer or the rising edge of ONESEC input signal according to the selected I/O mode [PIO; addr 018]. 0 = no timer event 1 = ONESEC timer expired or rising edge of ONESEC input
LOOPUP
TPDV
TLOC
TLOF
ONESEC
100054E
Conexant
3-17
3.0 Registers
3.5 Interrupt Status Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
006--Error Interrupt Status (ISR5)
All events in ISR5 are from rising edge sources. Each event is latched active high and held according to the LATCH_ERR bit [addr 046] and triggers an interrupt if the corresponding IER5 bit is enabled [addr 00E].
7 TSLIP 6 RSLIP 5 -- 4 -- 3 CERR 2 SERR 1 MERR 0 FERR
TSLIP
Transmit Slip Error--Two types of TSLIP buffer errors are reported: TFSLIP or TUSLIP. Error type is reported separately in slip status [SSTAT; 0D9]. 0 = no error 1 = TSLIP error Receive Slip Error--Two types of RSLIP buffer errors are reported: RFSLIP or RUSLIP. Error type is reported separately in slip status [SSTAT; 0D9]. 0 = no error 1 = RSLIP error CRC6/CRC4 Block Error--Applicable to ESF and MFAS modes only, read zero in other modes. CERR indicates one or more bit errors found in received CRC-6 or CRC-4 checksum block pattern. 0 = no error 1 = CRC error CAS Pattern Error--Applicable only in E1 mode, read zero in T1 mode. SERR indicates one or more bit errors in received TS16 Multiframe Alignment Signal (MAS). 0 = no error 1 = CAS error MFAS Pattern Error--Applicable only in E1 mode (read zero in T1 mode)--Indicates one or more bit errors in received MFAS alignment pattern. 0 = no error 1 = MFAS error Frame Error--Ft/Fs/T1DM/FPS/FAS Pattern Error--Indicates one or more Ft/Fs/FPS frame bit errors or FAS pattern errors. Refer to Tables A-1 through A-6 for a description of which frame bits are monitored according to the selected receive framer mode. 0 = no error 1 = frame error
RSLIP
CERR
SERR
MERR
FERR
3-18
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.5 Interrupt Status Registers
007--Counter Overflow Interrupt Status (ISR4)
All count overflow events in ISR4 are from rising edge sources. Each event is latched active high when the respective error counter [addr 050-05A] reaches its maximum count value, but only while the respective IER4 [addr 00F] interrupt enable bit is active. If the corresponding interrupt is masked, then no overflow status is reported. Active overflow status bits are held until the processor read clears ISR4. Each event triggers an interrupt if the corresponding IER4 bit is enabled.
7 FRED[4] 6 COFA[2] 5 SEF[2] 4 BERR[12] 3 FEBE[10] 2 LCV[16] 1 CRC[10] 0 FERR[12]
FRED[4] COFA[2] SEF[2] BERR[12] FEBE[10] LCV[16] CRC[10] FERR[12]
Out of Frame Error Count Overflow Change of Alignment Count Overflow Severely Errored Frame Count Overflow Test Pattern Bit Error Count Overflow FEBE Error Count Overflow LCV (BPV+EXZ) Error Count Overflow CRC6/CRC4 Error Count Overflow Ft/Fs/FPS/FAS Error Count Overflow
008--Timer Interrupt Status (ISR3)
All events in ISR3 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR3. Each event triggers an interrupt if corresponding IER3 bit is enabled [addr 010].
7 TSIG 6 TMSYNC 5 TMF 4 TFRAME 3 RSIG 2 RMSYNC 1 RMF 0 RFRAME
TSIG
Transmit Signaling Multiframe--Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (CAS) coincident with the first bit of a transmit signaling multiframe. 0 = no timer event 1 = transmit signaling multiframe TX System Bus MF Sync--Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (CAS) coincident with the first bit of transmit system bus multiframe input on TPCMI. 0 = no timer event 1 = TSB multiframe Transmit Multiframe--TMF is activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (MFAS) coincident with the first bit of a transmit multiframe. 0 = no timer event 1 = transmit multiframe Transmit Frame--Activated every 193 bits (T1) or 256 bits (E1) coincident with first bit of a transmit frame. Processor may read TPHASE [addr ODC] to determine which TSLIP buffer half can be accessed. 0 = no timer event 1 = transmit frame
TMSYNC
TMF
TFRAME
100054E
Conexant
3-19
3.0 Registers
3.5 Interrupt Status Registers
RSIG
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Receive Signaling Stack--Indicates that one or more signaling bit changes were detected during the prior receive multiframe, and that new ABCD (robbed bit or CAS) signaling is available on the Receive Signaling Stack Register [addr 0DA]. RSIG is cleared by processor read of ISR3, independent of STACK contents. 0 = no stack update 1 = new ABCD signaling Receive System Bus MF Sync--Activated every 3 ms (SF/SLC/ESF), or 2 ms (CAS) coincident with the first bit of receive system bus multiframe output on RPCMO. 0 = no timer event 1 = RSB multiframe Receive Multiframe Boundary--RMF is activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (MFAS) coincident with the first bit of a received multiframe. If MAS is not included in the receive framer criteria, then RMF is activated at 2 ms interval. 0 = no timer event 1 = receive multiframe Receive Frame Boundary--Activated every 193 bits (T1) or 256 bits (E1) coincident with the first bit of a received frame. Processor may read RPHASE [addr 0DB] to determine which RSLIP buffer half can be accessed. 0 = no timer event 1 = receive frame
RMSYNC
RMF
RFRAME
009--Data Link 1 Interrupt Status (ISR2)
All events in ISR2 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR2. Each event triggers an interrupt if the corresponding IER2 bit is enabled [addr 011].
7 TBOP 6 RFULL1 5 RNEAR1 4 RMSG1 3 TDLERR1 2 TEMPTY1 1 TNEAR1 0 TMSG1
TBOP
BOP Codeword Transmitted--Set when a valid Bit Oriented Codeword has been transmitted and a new TBOP value can be written [TBOP; addr 0A1]. Receive FIFO Full--In HDLC modes, RFULL is set when the data link receiver attempts to write received data to a full FIFO causing the receive data link FIFO to overrun. In unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the MSG_FILL Limit selected in register RDL1_FFC [addr 0A7]. Receive FIFO Near Full--Set when the receive FIFO fill level reaches the near full threshold selected in register RDL1_FFC [addr 0A7]. Message Received--Set when a complete message or a partial message is received and available in the receiver FIFO. Transmit FIFO Error--Set when the FIFO underruns as a result of the internal logic emptying the FIFO without encountering an end of message [TDL1_EOM; addr 0AC]. The underrun condition also forces transmission of an HDLC abort code. Transmit FIFO Empty--Set when the FIFO overflows as a result of the processor attempting to write to a full FIFO. Overflow data is ignored by the transmit FIFO. Transmit FIFO Near Empty --Set when the transmit FIFO level falls below the threshold selected in register TDL1_FEC [addr 0AB]. Message Transmitted--Set when a complete message has been transmitted and the closing flag is just beginning transmission.
RFULL1
RNEAR1
RMSG1
TDLERR1
TEMPTY1
TNEAR1
TMSG1
3-20
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.5 Interrupt Status Registers
00A--Data Link 2 Interrupt Status (ISR1)
All events in ISR1 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR1. Each event triggers an interrupt if the corresponding IER1 bit is enabled [addr 012].
7 RBOP 6 RFULL2 5 RNEAR2 4 RMSG2 3 TDLERR2 2 TEMPTY2 1 TNEAR2 0 TMSG2
RBOP
BOP Codeword Received--Set when a valid Bit Oriented Codeword is received and available in the RBOP register [addr 0A2]. Receive FIFO Full--In HDLC modes, RFULL is set when the data link receiver attempts to write received data to a full FIFO causing the receive data link FIFO to overrun. In unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the MSG_FILL limit selected in register RDL2_FFC [addr 0B2]. Receive FIFO Near Full--Set when the receive FIFO fill level reaches the near full threshold selected in register RDL2_FFC [addr 0B2]. Message Received--Set when a complete message or a partial message is received and available in the receiver FIFO. Transmit FIFO Error--Set when the FIFO underruns as a result of the internal logic emptying the FIFO without encountering an end of message [TDL2_EOM; addr 0B7]. The underrun condition also forces transmission of an HDLC abort code. Transmit FIFO Empty--Set when the FIFO overflows as a result of the processor attempting to write to a full FIFO. Overflow data is ignored by the transmit FIFO. Transmit FIFO Near Empty--Set when the transmit FIFO level falls below the threshold selected in register TDL2_FEC [addr 0B6]. Message Transmitted--Set when a complete message has been transmitted and the closing flag is just beginning transmission.
RFULL2
RNEAR2
RMSG2
TDLERR2
TEMPTY2
TNEAR2
TMSG2
100054E
Conexant
3-21
3.0 Registers
3.5 Interrupt Status Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
00B--Pattern Interrupt Status (ISR0)
All events in ISR0 are from rising edge sources. Each event is latched active high and held until the processor read clears ISR0. Each event triggers an interrupt if the corresponding IER0 bit is enabled [addr 013].
7 -- 6 -- 5 BSLIP 4 PSYNC 3 TCERR 2 TSERR 1 TMERR 0 TFERR
BSLIP
Online Framer Bit Slip--Active high, indicates receive online framer adjusted receive frame sync by 1 bit. When BSLIP occurs, the apparent FAS error is not reported elsewhere (not to FERR count, RLOF circuit, or SEF circuit). Applicable only to receive framer modes with BSLIP enabled (see Table 3-5). 0 = no error 1 = frame bit slip Receive PRBS Test Pattern Sync--Forced to inactive (low) status when the processor requests RESEED [addr 041] of the PRBS sync detector and remains low while the detector searches for test pattern sync. PRBS bit errors [BERR; addr 058, 059] are not counted while PSYNC is low. PSYNC remains low for a minimum of 128 bits following RESEED and for as long as the received bit error ratio (BER) exceeds 10E-2. PSYNC is latched active (high) and the PRBS sync detector stops searching when no bit errors are found for a period of 96 bits. The sync detector remains disabled until the processor requests another RESEED. Therefore, any range of BER can be measured after initial pattern sync. The processor must determine criteria for loss of pattern sync based on its accumulation of bit errors over the desired time interval. 0 = no sync 1 = PRBS test pattern sync Transmit CRC Error--Reports occurrences of CRC-6 or CRC-4 errors detected on TPCMI data according to the selected T1/E1 mode. 0 = no error 1 = CRC error Transmit CAS Error--Reports occurrences of MAS pattern errors detected on TPCMI data if CAS transmit framer mode is selected. 0 = no error 1 = CAS error Transmit Multiframe Error--Reports occurrences of Fs or MFAS errors detected on TPCMI data according to the selected transmit framer mode. 0 = no error 1 = transmit multiframe error Transmit Frame Error--Reports occurrences of Ft, FPS, or FAS errors detected on TPCMI data according to the selected transmit framer mode. 0 = no error 1 = transmit frame error
PSYNC
TCERR
TSERR
TMERR
TFERR
3-22
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.6 Interrupt Enable Registers
3.6 Interrupt Enable Registers
Writing a one to an IER bit allows that specific interrupt source to activate its respective ISR bit, the associated MIR bit. While cleared, each IER bit allows that source to activate its respective ISR bit, but prevents activation of the MIR bit.
00C--Alarm 1 Interrupt Enable Register (IER7)
7 RMYEL 6 RYEL 5 RPDV 4 RAIS 3 RALOS 2 RLOS 1 RLOF 0 SIGFRZ
RMYEL RYEL RPDV RAIS RALOS RLOS RLOF SIGFRZ
Enable RMYEL Interrupt Enable RYEL Interrupt Enable RPDV Interrupt Enable RAIS Interrupt Enable RALOS Interrupt Enable RLOS Interrupt Enable RLOF Interrupt Enable SIGFRZ Interrupt
00D--Alarm 2 Interrupt Enable Register (IER6)
Unused bits are reserved and should be written to 0.
7 LOOPDN 6 LOOPUP 5 TPDV 4 -- 3 TLOC 2 -- 1 TLOF 0 ONESEC
LOOPDN LOOPUP TPDV TLOC TLOF ONESEC
Enable LOOPDN Interrupt Enable LOOPUP Interrupt Enable TPDV Interrupt Enable TLOC Interrupt Enable TLOF Interrupt Enable ONESEC Interrupt
100054E
Conexant
3-23
3.0 Registers
3.6 Interrupt Enable Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
00E--Error Interrupt Enable Register (IER5)
Unused bits are reserved and should be written to 0.
7 TSLIP 6 RSLIP 5 -- 4 -- 3 CERR 2 SERR 1 MERR 0 FERR
TSLIP RSLIP CERR SERR MERR FERR
Enable TSLIP Interrupt Enable RSLIP Interrupt Enable CERR Interrupt Enable SERR Interrupt Enable MERR Interrupt Enable FERR Interrupt
00F--Count Overflow Interrupt Enable Register (IER4)
7 LOF 6 COFA 5 SEF 4 BERR 3 FEBE 2 LCV 1 CRC 0 FERR
LOF COFA SEF BERR FEBE LCV CRC FERR
Enable LOF Count Overflow Interrupt Enable COFA Count Overflow Interrupt Enable SEF Count Overflow Interrupt Enable BERR Count Overflow Interrupt Enable FEBE Count Overflow Interrupt Enable LCV Count Overflow Interrupt Enable CRC Count Overflow Interrupt Enable FERR Count Overflow Interrupt
Table 3-7. Counter Overflow Behavior IER4 Addr 00F
0 1 0 1
LATCH_CNT Addr 046
0 0 1 1
Count (addr 050-05A) Saturate
Hold all Ones Rollover Hold all Ones Rollover
MIR* Clear
hi @rd_MSB hi @rd_MSB None none None @rollover None @rollover
Latch
hi @rd_LSB hi @rd_LSB onesec onesec
Active
3-24
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.6 Interrupt Enable Registers
010--Timer Interrupt Enable Register (IER3)
7 TSIG 6 TMSYNC 5 TMF 4 TFRAME 3 RSIG 2 RMSYNC 1 RMF 0 RFRAME
TSIG TMSYNC TMF TFRAME RSIG RMSYNC RMF RFRAME
Enable TSIG Interrupt Enable TMSYNC Interrupt Enable TMF Interrupt Enable TFRAME Interrupt Enable RSIG Interrupt Enable RMSYNC Interrupt Enable RMF Interrupt Enable RFRAME Interrupt
011--Data Link 1 Interrupt Enable Register (IER2)
7 TBOP 6 RFULL1 5 RNEAR1 4 RMSG1 3 TDLERR1 2 TEMPTY1 1 TNEAR1 0 TMSG1
TBOP RFULL1 RNEAR1 RMSG1 TDLERR1 TEMPTY1 TNEAR1 TMSG1
Enable TBOP Interrupt Enable RFULL Interrupt Enable RNEAR Interrupt Enable RMSG Interrupt Enable TDLERR Interrupt Enable TEMPTY Interrupt Enable TNEAR Interrupt Enable TMSG Interrupt
100054E
Conexant
3-25
3.0 Registers
3.6 Interrupt Enable Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
012--Data Link 2 Interrupt Enable Register (IER1)
7 RBOP 6 RFULL2 5 RNEAR2 4 RMSG2 3 TDLERR2 2 TEMPTY2 1 TNEAR2 0 TMSG2
RBOP RFULL2 RNEAR2 RMSG2 TDLERR2 TEMPTY2 TNEAR2 TMSG2
Enable RBOP Interrupt Enable RFULL Interrupt Enable RNEAR Interrupt Enable RMSG Interrupt Enable TDLERR Interrupt Enable TEMPTY Interrupt Enable TNEAR Interrupt Enable TMSG Interrupt
013--Pattern Interrupt Enable Register (IER0)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 BSLIP 4 PSYNC 3 TCERR 2 TSERR 1 TMERR 0 TFERR
BSLIP PSYNC TCERR TSERR TMERR TFERR
Enable BSLIP Interrupt Enable PSYNC Interrupt Enable TCERR Interrupt Enable TSERR Interrupt Enable TMERR Interrupt Enable TFERR Interrupt
3-26
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.7 Primary Control and Status Registers
3.7 Primary Control and Status Registers
014--Loopback Configuration Register (LOOP)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 PLOOP 2 LLOOP 1 FLOOP 0 --
PLOOP
Enable Remote Payload Loopback--Payload from receiver replaces payload on transmitter output. Loopback payload retains time slot and frame integrity, such that numbered time slots from each receive frame are transferred to the same numbered time slots in the transmit frame. Transmit overhead bits, Fbits in T1 mode or TS0 in E1 mode, are supplied by transmit frame formatter or by transmit system bus according to TFRM [addr 072] settings. Existing transmit frame alignment and clock timing is not altered by PLOOP activation or deactivation, thus allowing system operation with independent receive and transmit timing. Controlled frame slips are performed in the payload loopback path if receive and transmit clocks are asynchronous, although these slips are not reported to the processor as slip buffer errors. Multiframe integrity is not maintained during PLOOP. This means that DS0 channel loopbacks [TPCn; addr 100-11F] must be used to implement payload loopbacks when transparent or forced signaling is desired. Note that TIDLE (in TPCn) overrides PLOOP. 0 = no loopback 1 = payload loopback Enable Remote Line Loopback--Received dual-rail unipolar data (RPOSI, RNEGI) is internally connected to transmit dual-rail unipolar data (TPOSO, TNEGO). The receive clock must also be looped when LLOP is selected in CMUX [addr 01A]; TXCLK must be set to 01 to select RCKI as the transmit clock. Loopback data retains BPV transparency. Data input from transmit system bus continues to pass through the transmitter, but is ignored at ZCS encoder outputs. Received data to RSB block is unaffected. LLOOP and FLOOP can be active simultaneously to support both line and network loopbacks at the same time. 0 = no loopback 1 = line loopback Enable Local Framer Loopback--Dual-rail unipolar data from transmit ZCS encoder is internally connected to receive ZCS decoder inputs. Clock switching is automatic during FLOOP loopback mode. 0 = no loopback 1 = framer loopback
LLOOP
FLOOP
100054E
Conexant
3-27
3.0 Registers
3.7 Primary Control and Status Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
015--External Data Link Time Slot (DL3_TS)
DL3_TS works in conjunction with the DL3_BIT Register [addr 016] to determine which transmit time slots are supplied from the TDLI pins and which receive and transmit time slots are accompanied by a gated RDLCKO and TDLCKO output. Refer to Figure 2-21, Transmit External Data Link Waveforms. Note that RDLO outputs the entire receive data bit stream, and only selective time slots are marked by RDLCKO. DL3 is not accessible on the CX28395 device, therefore, DL3_TS must be written to 00. CX28394, CX28398
7 DL3EN 6 ODD 5 EVEN 4 TS[4] 3 TS[3] 2 TS[2] 1 TS[1] 0 TS[0]
CX28395
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
DL3EN
Enable External Data Link--Active high enables data insertion from TDLI and clock gating on TDLCKO and RDLCKO outputs according to the selected external data link mode. PIO [addr 018] must select TDL_IO and/or RDL_IO to enable external data link signals. 0 = external data link pins inactive 1 = TDLI/TDLCKO and RDLO/RDLCKO active Odd/Even Frame Select--The external data link is programmed to source and sink data bits during all frames or odd or even frames only. ODD/EVEN also controls gating of RDLCKO and TDLCKO external data link clocks. Frames are counted from 0 through 15 in E1 mode and 1 through 24 in T1 mode, where frames 1, 3, 5 etc., are always considered ODD frames. ODD/EVEN is ignored if T1 Fbits are selected in DL3_TS.
ODD 0 0 1 1 EVEN 0 1 0 1 Frame Select None. Equivalent to disabling external data link. Even frames only. Frame 0, 2, 4, 6, etc. Odd frames only. Frame 1, 3, 5, 7, etc. All frames
ODD/EVEN
TS[4:0]
External Data Link Time Slot Select--Picks one 8-bit time slot for input and output over the external data link pins. Any time slot can be chosen from TS0 to TS31 in E1 mode, or TS1 to TS24 in T1 mode. In T1 mode, TS0 selects Fbits instead of a channel time slot.
00000 00001 | 11110 11111 T1 Fbits or E1 Time Slot 0 Time Slot 1 | Time Slot 30 Time Slot 31
3-28
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.7 Primary Control and Status Registers
016--External Data Link Bit (DL3_BIT)
7 DL3_BIT[7] 6 DL3_BIT[6] 5 DL3_BIT[5] 4 DL3_BIT[4] 3 DL3_BIT[3] 2 DL3_BIT[2] 1 DL3_BIT[1] 0 DL3_BIT[0]
DL3_BIT[7:0]
External Data Link Bit Select--Enables receive (RDLCKO) and transmit (TDLCKO) clock pulse outputs during the selected time slot bits. DL3_BIT and the DL3_TS Register [addr 015] select any combination of bits for input and output on the external data link pins by writing the corresponding DL3_BIT active (high). LSB enables clock pulses coincident with the first bit transmitted or received. Full T1/E1 data stream is output on RDLO as long as the RDL_IO bit [addr 018] is active and regardless of which bits are accompanied by RDLCKO clock pulses. The selected transmit data link bits are sampled from the TDLI pin on the falling edge of TDLCKO to replace normal transmitted data. DL3_BIT has no effect when DL3_TS selects T1 Fbits or when the DL3EN bit is inactive. DL3 is not accessible on the CX28395 device. 0 = disable DL3 bit 1 = enable DL3 bit
017--Offline Framer Status (FSTAT)
Each framer contains a single offline framer that acts as a shared resource for both receive and transmit channels. Current alignment status for receive and transmit channels are reported separately in Alarm Status Registers (ALM1, ALM2; addr 047, 048). FSTAT is thus used primarily for diagnostic purposes to monitor the progress of an alignment search or to verify acknowledgment of a processor-generated forced reframe request. These status bits may only be reported for a very short period of time (i.e., 1 clock cycle) since the RLOF and TLOF reframe requests may immediately request another offline framer search.
7 -- 6 -- 5 -- 4 INVALID 3 FOUND 2 TIMEOUT 1 ACTIVE 0 RX/TXN
INVALID
No Candidate--Active high at the conclusion of a search during which no frame alignment candidates were located. 0 = search active, aborted, timed out, or found 1 = alignment not found (no candidate) Frame Search Successful--Active high indicates the offline framer located frame alignment according to the selected receive or transmit framer mode. Refer to Table 3-8 for Maximum Average Reframe Time. Upon detection of frame alignment, the following occurs: FOUND goes active high, RLOF or TLOF is cleared by the online framer (depending on RX/TX direction), offline framer goes inactive (if no pending reframe requests), and RX, TX, or TSB timebase is realigned (depending on RX/TX direction and the embedded framing mode). If the reframe pulse causes the receive timebase to align to a position that differs from its existing alignment, the change of frame alignment error counter [COFA; addr 05A] will increment. Changes of the transmit frame alignment are not detected. 0 = no candidate: search active, aborted, or timed out 1 = frame alignment found (one and only one candidate)
NOTE:
FOUND
In E1 receive framer modes, the offline framer also reports intermediate FRED, MRED, and SRED status [ALM3; addr 049] while searching for FAS/MFAS/CAS alignment, respectively.
100054E
Conexant
3-29
3.0 Registers
3.7 Primary Control and Status Registers
TIMEOUT
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Framer Search Timeout--Cleared when the offline framer transitions to its ACTIVE state. If multiple frame candidates exist over the entire mode-dependent timeout interval (refer to Table 3-8), TIMEOUT is latched active high. Processor-generated reframe requests (RFORCE or TFORCE) initiate a single search that extends for up to 24 ms before TIMEOUT. After reporting TIMEOUT, the offline framer starts another search if the reframe request (RLOF or TLOF) is active. 0 = no candidate; search active, aborted, or found 1 = framer search timeout (multiple candidates)
Table 3-8. Maximum Average Reframe Time (MART) and Framer Timeout Framer Mode
Ft Ft + T1DM SF SF + JYEL SF + TIDM SLC ESF ESF + CRC ESF + MIMIC FAS CAS MFAS
MART
3.5 ms 1.0 ms 3.5 ms 4.5 ms 2.0 ms 15.0 ms 10.0 ms 15.0 ms 15.0 ms 0.5 ms 2.0 ms 10.0 ms
TIMEOUT (addr 017)
12 ms 1 bit 12 ms 1 bit 12 ms 1 bit 12 ms 1 bit 12 ms 1 bit 24 ms 1 bit 24 ms 1 bit 24 ms 1 bit 24 ms 1 bit 8 ms 125 s 8 ms 125 s 8 ms 125 s
NOTE(S): MART is defined (per Bellcore TA-0278) as the difference between the time that
known good pseudo-random DS1 input is applied and the time that a valid DS0 signal is observed at the output.
ACTIVE
Framer Active--Offline framer transitions to its ACTIVE state in response to RFORCE or TFORCE reframe request from the processor or in response to RLOF or TLOF reframe request from an online framer. Offline framer remains ACTIVE until alignment is found (FOUND), search is aborted [see RABORT, addr 040; or TABORT, addr 071], search reaches its timeout interval (TIMEOUT), or all possible frame candidates are eliminated (INVALID). 0 = offline framer inactive; search completed, aborted or timed out 1 = offline framer actively searching for alignment
NOTE:
RFORCE or TFORCE don't change current RLOF or TLOF status. RFORCE or TFORCE is cleared by framer transition to ACTIVE.
RX/TXN
RX/TX Reframe Operation--Indicates which direction the offline framer is actively searching or most recently searched for frame alignment. RX/TXN status is updated when offline framer transitions to its ACTIVE state in response to a reframe request. 0 = search data from Transmit System Bus PCM Input (TPCMI) 1 = search data from receive line interface unit
3-30
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.7 Primary Control and Status Registers
018--Programmable Input/Output (PIO)
7 RMSYNC_EN 6 RDL_IO 5 TMSYNC_EN 4 TDL_IO 3 RFSYNC_IO 2 RMSYNC_IO 1 TFSYNC_IO 0 TMSYNC_IO
RMSYNC_EN
Enable RMSYNC--Select which signal is present on bimodal pin, RFSYNC/RMSYNC. When active, receiver multiframe sync (RMSYNC) is enabled. Otherwise, receiver frame sync RFSYNC is enabled. Enable Receiver Data Link--Select which signals are present on bimodal RDLCKO and RDLO. When active Receiver Data Link Clock Out (RDLCKO) and Receive Data Link Data Out (RDLO) are enabled. Otherwise RINDO and RSIGO are as follows: 0 = select RINDO and RSIGO 1 = select Receive Data Link Enable TMSYNC--Select which signal is present on bimodal pin, TFSYNC/TMSYNC. When active, transmit multiframe sync (TMSYNC) is enabled. Otherwise, receiver frame sync TFSYNC is enabled. Enable Transmit Data Link--Select which signals are present on bimodal TDLCKO and TDLI. When active Transmit Data Link Clock Out (TDLCKO) and Transmit Data Link Data Out (TDLO) are enabled. On the CX28395 device, TDL3 is not available and TDL_IO must be written to 0. 0 = select TINDO and TSIGI 1 = select Transmit Data Link Bidirectional RFSYNC Input/Output Mode--Refer to the system bus sync mode summary in Tables 3-9 and 3-11. When RFSYNC is an input, its low to high transition aligns the RSB timebase to the programmed RSB.OFFSET. Refer to RSYNC_BIT, RSYNC_TS, and RSYNC_FRM offset registers [addr 0D2, 0D3, and 0D8] for a complete description of the RSB Sync Bits Time Slot and Frame Offset. Once aligned, the RSB timebase internally flywheels at a 125 s interval (8 kHz) until a new RFSYNC pulse is applied. When RFSYNC is programmed as an output, it operates continuously at a 8 kHz frame rate, marking the RSB sync bits and time slot offset position of each frame. Initial RFSYNC alignment and subsequent realignment depends upon RSB Mode [RSBI; addr 0D1] and RSB manual center [RSB_CTR; addr 0D1]. RFSYNC must be programmed as an output when RSLIP is in bypass mode. RFSYNC and RMSYNC are supplied either by the RSB timebase (output) or receive system bus (input) at a programmable RSB sync bit offset, time slot location and frame offset location. 0 = RFSYNC input 1 = RFSYNC output Bidirectional RMSYNC Input/Output Mode--Refer to the system bus sync mode summary in Table 3-9. When RMSYNC is an input, its low-to-high transition aligns the RSB timebase to the programmed RSB.OFFSET. Once aligned, the RSB timebase internally flywheels at a 3 ms (T1) or 2 ms (E1) interval until a new RMSYNC pulse is applied. Note that RMSYNC input signal must always coincide with RFSYNC. When RMSYNC is an output, it operates continuously at the 6 ms multiframe rate, marking the RSB.OFFSET position of every second multiframe (T1) or every third multiframe (E1). Initial RMSYNC alignment and subsequent realignment depends upon RSB mode [RSBI; addr 0D1] and RSB manual center [RSB_CTR; addr 0D1]. RMSYNC must be programmed as an output when RSLIP is in bypass mode or transparent signaling mode [THRU; addr 0D7]. 0 = RMSYNC input 1 = RMSYNC output
RDL_IO
TMSYNC_EN
TDL_IO
RFSYNC_IO
RMSYNC_IO
100054E
Conexant
3-31
3.0 Registers
3.7 Primary Control and Status Registers
TFSYNC_IO
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Bidirectional TFSYNC Input/Output Mode--TFSYNC_IO programming is dependent on transmit framer and system bus modes as shown in Tables 3-9 and 3-10. 0 = TFSYNC input 1 = TFSYNC output Bidirectional TMSYNC Input/Output mode--TMSYNC_IO programming is dependent on transmit framer and system bus modes as shown in Tables 3-9 and 3-10. 0 = TMSYNC input 1 = TMSYNC output
TMSYNC_IO
Table 3-9. System Bus Sync Mode Summary FSYNC
IN IN IN IN-GND OUT OUT
MSYNC
IN IN-GND OUT OUT IN OUT
SBI Alignment Mode
SBI supplies multiframe and 8 kHz frame alignment. FSYNC must be aligned with MSYNC if both are provided. SBI supplies 8 kHz frame alignment. Multiframe alignment is arbitrary and MSYNC is unused. SBI supplies 8 kHz frame alignment. Multiframe alignment is supplied by the framer. Framer supplies multiframe alignment. FSYNC is unused. SBI supplies multiframe and frame alignment. Framer supplies frame and multiframe alignment.
Table 3-10. Common TFSYNC and TMSYNC Configurations Conditions
Transmit framer disabled. (TABORT = 1)
TFSYNC
IN IN-GND IN IN OUT OUT
TMSYNC
IN IN IN-GND OUT OUT IN OUT
Explanation
TSB timebase slaved to system bus TFSYNC or TMSYNC. TSB timebase slaved to system bus TMSYNC. TFSYNC is unused. TSB timebase slaved to system bus TFSYNC. TMSYNC is unused and multiframe alignment is arbitrary. SB timebase slaved to system bus TFSYNC. TMSYNC alignment is arbitrary. TSB timebase alignment is arbitrary. TSB timebase slaved to system bus TMSYNC. TFSYNC aligns to TMSYNC input. TSB timebase is aligned to embedded framing on TPCMI. TPCMI must be configured to line rate for this case.
Transmit framer enabled to search TPCMI for embedded framing. (EMBED = 0, TABORT = 0) Transmit framer enabled to search TNRZ (after TSLIP buffer) for embedded framing. (EMBED = 1, TABORT = 0)
OUT
OUT
IN-GND
TSB timebase is aligned to embedded framing on TNRZ data. TMSYNC is unused. TPCMI may be configured for 1,544 kbps or a multiple of 2,048 kbps.
3-32
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-11. Common RFSYNC and RMSYNC Configurations Conditions
Thru = 0 [RSIG_CR; addr 0D7]
3.0 Registers
3.7 Primary Control and Status Registers
RFSYNC
IN IN OUT OUT
RMSYNC
IN OUT IN OUT OUT
Explanation
RSB timebase slaved to system bus RFSYNC or RMSYNC. RSB timebase slaved to system bus RFSYNC. RMSYNC alignment is arbitrary. RSB timebase slaved to system bus RMSYNC. RFSYNC aligns to TMSYNC input. RFSYNC and RMSYNC alignment is arbitrary. RSB timebase slaved to system bus RFSYNC. RMSYNC is aligned with the RX timebase and can follow a change of RX multiframe alignment without generating an alarm indication. RMSYNC is aligned with the RX timebase and can follow a change of RX multiframe alignment without generating an alarm indication. RFSYNC is aligned to RMSYNC.
Thru = 1 [RSIG_CR; addr 0D7]
IN
OUT
OUT
019--Programmable Output Enable (POE)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 TDL_OE 4 RDL_OE 3 INDY_OE 2 TCKO_OE 1 -- 0 --
TDL_OE
TDLCKO Output Buffer Control--When enabled, TDLCKO is output according to DL3_TS and DL3_BIT [addr 015, 016]. TDL_OE should be written to 1 on the CX28395 device. 0 = TDLCKO output enabled 1 = TDLCKO output three-stated RDLCKO and RDLO Output Buffer Control--When enabled, both bimodal signals are output by their respective internal circuits. Otherwise, both outputs are placed in high impedance state. RDL_OE should be written to 1 on the CX28395 device. 0 = RDLCKO and RDLO outputs enabled 1 = RDLCKO and RDLO outputs three-stated RINDO and TINDO Output Buffer Control--When enabled, both bimodal signals are output by their respective internal circuits. Otherwise, both outputs are forced into high impedance state. 0 = RINDO outputs enabled 1 = RINDO outputs three-stated TCKO Output Buffer Control--Allows the system to connect multiple devices to a common clock bus by providing programmable three-state control over the TCKO output buffer. 0 = TCKO output enabled 1 = TCKO output three-stated
RDL_OE
INDY_OE
TCKO_OE
100054E
Conexant
3-33
3.0 Registers
3.7 Primary Control and Status Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
01A--Clock Input Mux (CMUX)
Unused bits are reserved and should be written to 0.
7 -- 6 RSBCK 5 -- 4 TSBCK 3 -- 2 -- 1 TXCLK[1] 0 TXCLK[0]
RSBCK
RSBCK Source Select--Internal clock mux selects from one of two clock signals for application to the RSB timebase. The RSBCKI input pin is ignored if TSBCKI is selected.
RSBCK 0 1 RSBCK Source RSBCKI pin TSBCKI pin Notes Normal RSB timebase RSB slaved to TSB
TSBCK
TSBCK Source Select--Internal clock mux selects from one of three clock signals for application to the TSB timebase. If TSLIP is bypassed [TSB_CR; addr 0D4], TCKI is selected. The TSBCKI input pin is ignored if TCKI or RSBCKI is selected.
TSBCK 0 1 x TSBCK Source TSBCKI pin RSBCKI pin TCKI pin Notes Normal TSB timebase TSB slaved to RSB TSLIP is bypassed
TXCLK[1:0]
TXCLK Source Select--Internal transmit clock mux selects from one of three clock signals. The selected clock signal is applied to transmit clock monitor, acts as a timing reference for the transmitter block, and must operate at the T1/E1 line rate. The selected clock signal also appears on TCKO pin. The TCKI input pin is ignored whenever a clock source other than TCKI is selected.
TXCLK[1:0] 00 01 10 TXCLK Source TCKI RCKI RSBCKI Notes Normal transmit (With TSLIP) Transmit slaved to receiver (Loop Timed) Transmit slaved to RSB
020--Receive Alarm Configuration (RAC)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 RAL_CON 3 -- 2 -- 1 -- 0 --
RAL_CON
RALOS Alarm Configuration - Determines whether RALOS [ALM1; addr 047] reports loss of receive clock (RCKI) or loss of receive signal for 1 msec. 0 = RALOS reports that RLOS [ALM1; addr 047] has been active for 1 msec 1 = RALOS reports loss of clock on RCKI pin
3-34
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.7 Primary Control and Status Registers
021--Receive Line Code Status (RSTAT)
7 -- 6 -- 5 ZCSUB 4 EXZ 3 BPV 2 -- 1 -- 0 --
ZCSUB
Zero Code Substitution--Indicates one or more B8ZS/HDB3 substitution patterns have been detected on receiver input data, depending on T1/E1N line rate selection. ZCSUB is reported regardless of whether ZCS decoding is enabled [RAMI; addr 040]. ZCSUB is latched active high upon detection of the first ZCS pattern. The active high hold interval is defined by LATCH_ERR [addr 046].
ZCSUB 0 1 1 T1/E1N X 0 1 ZCSUB Status No ZCS patterns detected HDB3 pattern detected B8ZS pattern detected
EXZ
Excessive Zeros--Reports one or more long strings of zeros detected on the receiver data inputs. Depending on bits RZCS [addr 040] and T1/E1N [addr 001], occurrences of 8, 10, or 16 consecutive zeros are detected. EXZ is latched active high upon detection of the first error. The active high hold interval is defined by LATCH_ERR [addr 046]. If EXZ_LCV [addr 045] is enabled, EXZ errors are also accumulated in LCV count [addr 054, 055].
EXZ 0 1 1 1 T1/E1N. X 0 1 1 RZCS X X 0 1 EXZ Status No error 10 consecutive zeros 16 consecutive zeros 8 consecutive zeros
BPV
Bipolar Violation--Reports one or more bipolar violations detected on the receiver data inputs. Depending on RZCS [addr 040], BPV may or may not include bipolar violations received as part of a B8ZS or HDB3 zero code substitution. Detection of BPV or LCV errors can be selected regardless of whether receive ZCS decoding is enabled [RAMI; addr 040]. BPV is latched active high upon detection of the first error. The active high hold interval is defined by LATCH_ERR [addr 046]. BPV errors are also accumulated in LCV count [addr 054, 055].
BPV 0 1 1 1 1 T1/E1N X 0 0 1 1 RZCS X 0 1 0 1 No error All BPVs, including HDB3 coded BPV Code violation per ITU 0.162 (two consecutive BPVs of same polarity) All BPVs, including B8ZS coded BPV Only BPVs that are not part of B8ZS BPV Status
100054E
Conexant
3-35
3.0 Registers
3.8 Serial Interface Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.8 Serial Interface Registers
These registers are not used on the CX28395 device.
022--Serial Control (SER_CTL)
Writing to SER_CTL initiates a serial interface read or write operation. During a write operation, a 16-bit word, consisting of SER_CTL and SER_DAT, is transmitted to the LIU. During a read operation, SER_CTL is transmitted and 8-bit data from the LIU is received and placed in SER_DAT register. SER_RW is transmitted first and SER_DAT[0] is transmitted or received first.
7 SER_A[6] 6 SER_A[5] 5 SER_A[4] 4 SER_A[3] 3 SER_A[2] 2 SER_A[1] 1 SER_A[0] 0 SER_RW
SER_RW
Serial Read/Write - Selects the current serial interface operation type. 0 = Write 1 = Read Serial Interface Register Address - Identifies the LIU register address for the current read or write operation.
SER_A[6:0]
023--Serial Data (SER_DAT)
7 SER_DAT[7] 6 SER_DAT[6] 5 SER_DAT[5] 4 SER_DAT[4] 3 SER_DAT[3] 2 SER_DAT[2] 1 SER_DAT[1] 0 SER_DAT[0]
SER_DAT[7:0]
Serial Interface Data
024--Serial Status (SER_STAT)
7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 SER_DONE
SER_DONE
Serial Interface Done-During a read or write serial interface operation, SER_DONE is cleared indicating that an operation is in progress. After the operation is complete, this bit is set and an interrupt request is generated if enabled by SER_IER [addr 025]. SER_DONE is also cleared if read by the MPU. When the SER_DONE is cleared, the interrupt request is deactivated to allow the INTR* pin to also be deactivated if all other interrupt sources have been serviced.
3-36
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.8 Serial Interface Registers
025--Serial Configuration (SER_CONFIG)
Unused bits are reserved and should be written to 0.
7 SER_CS 6 SER_CLK 5 -- 4 -- 3 -- 2 -- 1 -- 0 SER_IER
SER_CS
Serial Interface Chip Select 1 0 = sets external SERCS1* signal low 1 = sets external SERCS2* signal low Serial Interface Clock 0 =1.024 MHz 1 = 8.192 MHz Serial Interface Interrupt Enable 0 = interrupt disabled 1 = interrupt enabled
SER_CLK
SER_IER
026--RAM Test
7 RT[7] 6 RT[6] 5 RT[5] 4 RT[4] 3 RT[3] 2 RT[2] 1 RT[1] 0 RT[0]
Reserved for Conexant Production test.
100054E
Conexant
3-37
3.0 Registers
3.9 Receiver Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.9 Receiver Registers
040--Receiver Configuration (RCR0)
7 RAMI 6 RABORT 5 RFORCE 4 RLOFD 3 RLOFC 2 RLOFB 1 RLOFA 0 RZCS
RAMI
Receive AMI Encoded Inputs--Disables B8ZS/HDB3 decoding for AMI formatted receive signals. Otherwise, ZCS decoder replaces 000VB0VB code (B8ZS) with 8 zeros in T1 mode or replaces X00V code (HDB3) with 4 zeros in E1 mode: where B is a normal AMI pulse, V is a bipolar violation, and X is a "don't- care." Regardless of RAMI setting, receipt of a ZCS signature is always detected and reported in ZCSUB status [RSTAT; addr 021]. 0 = receive B8ZS/HDB3 line format 1 = receive AMI line format Abort/Disable RX Offline Framer--When set, the offline framer ignores reframe requests from the online framer (RLOF) and aborts any in-progress RLOF reframe request. Loss of frame status [RLOF; addr 047] is not affected. While RABORT remains set, offline framer responds only to processor forced reframes (RFORCE). This allows the processor to manually control reframe criteria and prevent changes in the current receive frame alignment. RABORT is typically set only during unframed operation. 0 = normal framer operation 1 = framer disabled Force RX Reframe--Forces the offline framer to perform a single reframe according to selected receive framer mode. RFORCE is automatically cleared when offline framer acknowledges the request [FSTAT; addr 017]. The processor does not typically need to force reframe since the online framer reframe request (RLOF) is active whenever reframe criteria (RLOFD-A) is met. However, the processor may force reframe if frame or CRC error ratios indicate that the framer might have aligned to a duplicated frame alignment pattern. 0 = no effect 1 = force RX reframe RX Reframe Criteria--Determines the number of frame errors that the online framer must detect before declaring loss of frame alignment [ALM1; addr 047]. Refer to receive framer mode [RFRAME; addr 001] Table 2-1, Receive Framer Modes, to find which frame bits are monitored.
T1/E1N 0 0 1 1 1 RLOFD-A 0100 1100 0001 0010 0100 Reframe Criteria 3 consecutive FAS or 915 CRC errors 3 consecutive FAS errors 2 out of 4 F-bit errors 2 out of 5 F-bit errors 2 out of 6 F-bit errors
RABORT
RFORCE
RLOFD-RLOFA
NOTE(S): Other RLOFD-RLOFA combinations are invalid. RAIS and RLOF status is disabled if
RLOFD-RLOFA equals all zeros.
3-38
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
RZCS
3.0 Registers
3.9 Receiver Registers
Receive B8ZS/HDB3 Zero Code Substitution (affects only BPV/LCV/EXZ counting)--When set, the ZCS decoder does not include bipolar violations received as part of a B8ZS/HDB3 code in the LCV error count [addr 054, 055]. Otherwise, all bipolar violations are counted. EXZ detection criteria is either 8 or 16 consecutive zeros, depending on RZCS configuration. 0 = ZCS decoder reports all occurrences of BPV; also selects EXZ = 16 zeros 1 = ZCS decoder does not report BPVs received as part of ZCS; also selects EXZ = 8 zeros
041--Receive Test Pattern Configuration (RPATT)
7 -- 6 -- 5 RESEED 4 BSTART 3 FRAMED 2 ZLIMIT 1 RPATT[1] 0 RPATT[0]
RESEED
Reseed PRBS Sync Detector (auto clear)--If BSTART is active high, writing a one to RESEED forces the PRBS sync detector to reseed and search for test pattern sync [PSYNC; addr 00B]. The reseed and search algorithm remains active until test pattern sync is found. 0 = no effect 1 = reseed and search for test pattern sync Enable PRBS Detector and Start Counting PRBS Bit Errors--BERR [addr 058, 059] counting is enabled when BSTART is active high, and pattern sync is found [PSYNC=1; addr 00B]. Otherwise, BERR counter holds its present value until cleared by a processor read. 0 = PRBS detector disabled and BERR stops counting 1 = enable PRBS detector and BERR counter PRBS Framed--When set, PRBS test pattern bits are not checked during F-bit locations in T1 mode or TS0 locations in E1 mode. Otherwise, test patterns are checked in all T1/E1 bit locations. FRAMED, ZLIMIT, and RPATT establish the test pattern measurement type as listed in Table 3-12.
BSTART
FRAMED
Table 3-12. Receive PRBS Test Pattern Measurements (1 of 2) FRAMED
0 0 0 0 0 0 0 0 1 1
ZLIMIT
0 0 0 0 1 1 1 1 0 0
RPATT
00 01 10 11 00 01 10 11 00 01
Test Pattern Measurements
Unframed 211 Unframed 215 Unframed 220 Unframed 223 Unframed 211 with 7 zero limit Unframed 215 with 7 zero limit (non-std) Unframed 220 with 14 zero limit (QRSS/QRS/QRTS) Unframed 223 with 14 zero limit (non-std) Framed 211 Framed 215
Inversion
No Yes No Yes No No No No No Yes
100054E
Conexant
3-39
3.0 Registers
3.9 Receiver Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-12. Receive PRBS Test Pattern Measurements (2 of 2) FRAMED
1 1 1 1 1 1
ZLIMIT
0 0 1 1 1 1
RPATT
10 11 00 01 10 11 Framed 220 Framed 223
Test Pattern Measurements
Inversion
No Yes No No No No
Framed 211 with 7 zero limit Framed 215 with 7 zero limit (non-std) Framed 220 with 14 zero limit (QRSS/QRS/QRTS) Framed 223 with 14 zero limit (non-std)
ZLIMIT
PRBS Zero Limit--Determines the number of consecutive zeros allowed within the selected PRBS test pattern. Refer to Table 3-12 for test pattern measurement options. PRBS Test Pattern--Selects one of four PRBS test pattern lengths used to measure received bit error ratio during out of service testing. Refer to Table 3-12 for test pattern measurement options. PRBS test patterns used by RPATT [addr 041] and TPATT [addr 076] are defined in the ITU standards O.151 and O.152 to use either inverted or non-inverted data. Standard data inversion is used for selected PRBS test patterns unless ZLIMIT is enabled, in which case the test pattern always uses non-inverted data.
RPATT[1:0]
042--Receive Loopback Code Detector Configuration (RLB)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 DN_LEN[1] 2 DN_LEN[0] 1 UP_LEN[1] 0 UP_LEN[0]
DN_LEN[1:0]
Loopback Deactivate Code Length--Selects the number of loopback pattern bits from LBD [addr 044] that are compared to received data. This is done in order to determine whether a Loopback Deactivate Code [LOOPDN; addr 048] has been detected. LOOPDN is recovered if the received data pattern contains fewer than 63 bit errors in a 24 ms period, or lost if 64 or more bit errors are detected in a subsequent 24 ms period. F-bits that overwrite or are inserted into the loopback pattern are not counted as bit errors. Accurate code detection is provided on lines with up to 1E-3 BER.
DN_LEN 00 01 10 11 LBD Length 4 bits 5 bits 6 bits 7 bits
3-40
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
UP_LEN[1:0]
3.0 Registers
3.9 Receiver Registers
Loopback Activate Code Length--Selects the number of loopback pattern bits from LBA [addr 043] that are compared to received data. This is done in order to determine whether a Loopback Activate Code [LOOPUP; addr 048] has been detected. LOOPUP is recovered if the received data pattern contains fewer than 63 bit errors in a 24 ms period, or lost if 64 or more bit errors are detected in a subsequent 24 ms period. F-bits that overwrite or are inserted into the loopback pattern are not counted as bit errors. Accurate code detection is provided on lines with up to 1E-3 BER.
UP_LEN 00 01 10 11 LBA Length 4 bits 5 bits 6 bits 7 bits
043--Loopback Activate Code Pattern (LBA)
Unused bits are reserved and should be written to 0.
7 LBA[1] 6 LBA[2] 5 LBA[3] 4 LBA[4] 3 LBA[5] 2 LBA[6] 1 LBA[7] 0 --
LBA[1] LBA[2] LBA[3] LBA[4] LBA[5] LBA[6] LBA[7]
First bit expected of LOOPUP pattern Second bit expected of LOOPUP pattern Third bit expected of LOOPUP pattern Fourth bit expected--Last bit if UP_LEN selects a 4-bit pattern Fifth bit expected--Last bit if UP_LEN selects a 5-bit pattern Sixth bit expected--Last bit if UP_LEN selects a 6-bit pattern Seventh bit expected--Last bit if UP_LEN selects a 7-bit pattern
044--Loopback Deactivate Code Pattern (LBD)
Unused bits are reserved and should be written to 0.
7 LBD[1] 6 LBD[2] 5 LBD[3] 4 LBD[4] 3 LBD[5] 2 LBD[6] 1 LBD[7] 0 --
LBD[1] LBD[2] LBD[3] LBD[4] LBD[5] LBD[6] LBD[7]
First bit expected of LOOPDN pattern Second bit expected of LOOPDN pattern Third bit expected of LOOPDN pattern Fourth bit expected--Last bit if DN_LEN selects a 4-bit pattern Fifth bit expected--Last bit if DN_LEN selects a 5-bit pattern Sixth bit expected--Last bit if DN_LEN selects a 6-bit pattern Seventh bit expected--Last bit if DN_LEN selects a 7-bit pattern
100054E
Conexant
3-41
3.0 Registers
3.9 Receiver Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
045--Receive Alarm Signal Configuration (RALM)
Unused bits are reserved and should be written to 0.
7 -- 6 DIS_LCV 5 FS_NFAS 4 EXZ_LCV 3 YEL_INTEG 2 RLOF_INTEG 1 RPCM_YEL 0 RPCM_AIS
DIS_LCV
Disable LCV indication and counting. Primarily used in configurations where receive data is unipolar NRZ. If AUTO_PRM is enabled (PRM; addr 0AA) LV is transmitted with a default value of 0. 0 = LCV counting and indication enabled 1 = LCV counting and indication disabled Include FS/NFAS in FERR and FRED--Selects whether Fs bit errors (T1) or NFAS Bit2 errors (E1) are counted as frame errors [FERR; addr 050, 051]. Further selects whether loss of frame alignment [FRED; addr 049] includes Fs or NFAS bit errors as part of the detection criteria. Note that the number of Fs bit locations checked also depends on JYEL framer mode. 0 = FERR and FRED do not include FS/NFAS 1 = FERR and FRED include FS/NFAS Excess Zeros Included in LCV--Whether line code violation error count [LCV; addr 054, 055] includes EXZ errors depends on the EXZ_LCV control setting. Depending on RZCS bit setting [addr 040], each EXZ is equal to either 8 or 16 consecutive zeros. 0 = LCV does not include EXZ 1 = LCV includes EXZ Enable Yellow Alarm Integration--When set, both the receive frame and multiframe yellow alarms [RYEL and RMYEL; addr 047] are integrated, as described in Table 3-13 (per the selected framer mode). RYEL and RMYEL interrupt status [ISR7; addr 004] are similarly affected. 0 = normal RYEL and RMYEL status 1 = integrated RYEL and RMYEL status
FS_NFAS
EXZ_LCV
YEL_INTEG
Table 3-13. Receive Yellow Alarm Set/Clear Criteria (1 of 2) Mode
Y0 Y0_INT Y16 Y16_INT YB2 YB2_INT
Set/Clear Criteria
Set for 4 frames (500 s) if 2 consecutive NFAS frames each contain TS0 bit 3 = 1. Cleared for 4 frames if 2 consecutive NFAS frames each contain TS0 bit 3 = 0. Set for 16 multiframes (24 ms) if every NFAS frame contains TS0 bit 3 = 1. Cleared for 16 multiframes if 1 or more NFAS frames contain TS0 bit 3 = 0. Set for 2 multiframes (4 ms) if frame 0 in 2 consecutive multiframes contains TS16 bit 6 = 1. Cleared for 2 multiframes if frame 0 in 2 consecutive multiframes contains TS16 bit 6 = 0. Set for 16 multiframes (24 ms) if every frame 0 contains TS16 bit 6 = 1. Cleared for 16 multiframes if at least 1 frame 0 contains TS16 bit 6 = 0. Set for 1 frame (125 s) if all 24 time slots contain bit 2 = 0. Cleared for 1 frame if 1 or more time slots contain bit 2 = 1. Set for 192 frames (24 ms) if less than 15 time slots contain bit 2 = 0. Cleared for 192 frames if 15 or more time slots contain bit 2 = 1.
3-42
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-13. Receive Yellow Alarm Set/Clear Criteria (2 of 2) Mode
YJ YJ_INT Y24 Y24_INT YF YF_INT
3.0 Registers
3.9 Receiver Registers
Set/Clear Criteria
Set for 1 multiframe (1.5 ms) if frame 12 contains Fs bit = 1. Cleared for 1 multiframe if frame 12 contains Fs bit = 0. Set for 16 multiframes (24 ms) if every frame 12 contains Fs bit = 1. Cleared for 16 multiframes (24 ms) if at least 1 frame 12 contains Fs bit = 0. Set for 1 frame (125 s) if TS24 contains bit 6 = 0. Cleared for 1 frame if TS24 contains bit 6 = 1. Set for 192 frames (24 ms) if every TS24 bit 6 = 0. Cleared for 192 frames if at least 1 TS24 bit 6 = 1. Set for 32 frames (4 ms) if 16 FDL bits contain yellow alarm priority codeword pattern (00FFh). Cleared for 32 frames if 16 FDL bits do not contain a yellow alarm priority codeword pattern. Set upon reception of 16 FDL bits matching yellow alarm priority codeword and remains set as long as the codeword pattern is not interrupted for greater than 100 ms. Cleared when the yellow alarm priority codeword is not present for more than 100 ms (26 missing codewords = 104 ms).
RLOF_INTEG
Enable RLOF Integration--When set, the receive loss of frame status [RLOF; addr 047] is integrated for 2.0 to 2.5 seconds during T1 framer modes (not applicable to E1 modes). RLOF interrupt status [ISR7; addr 004] is also integrated. However, receive framer status in ALM3 [addr 049], loss of frame count [FRED[3:0]; addr 05A], and RLOF counter overflow [ISR4; addr 007] are unaffected. 0 = normal RLOF status 1 = integrated RLOF [addr 047] status Send Bit2 Yellow Alarm on RPCMO Output Pin--Similar to RPCM_AIS, except all RPCMO time slot Bit2 locations are replaced by all zeros. Bit2 yellow alarms are applicable only to T1 mode. E1 modes do not require yellow alarm forwarding. 0 = normal RPCMO data 1 = RPCMO includes Bit2 yellow alarm Send AIS on RPCMO Output Pin--Replaces RPCMO data with a continuous series of all ones. RPCM_AIS is useful in CSU or digital section applications, where the local interface must be able to forward an AIS to the opposing interface. RPCM_AIS has a higher priority than RPCM_YEL. 0 = normal RPCMO data 1 = RPCMO replaced with all ones
RPCM_YEL
RPCM_AIS
100054E
Conexant
3-43
3.0 Registers
3.9 Receiver Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
046--Alarm/Error/Counter Latch Configuration (LATCH)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 STOP_CNT 2 LATCH_CNT 1 LATCH_ERR 0 LATCH_ALM
STOP_CNT
Stop Error Count during RLOF/RLOS/RAIS--If enabled, error count registers [addr 050-057] are suspended at their present values during any receive loss of frame (RLOF), loss of signal (RLOS), or all ones (RAIS) alarm condition. STOP_CNT does not affect counting of test pattern errors [BERR; addr 058, 059] or alarm events [AERR; addr 05A]. The occurrence of a red or AIS CGA will inhibit further processing of all other performance parameters (i.e., BER, errored seconds, SLIPS, etc.). However, a CGA caused by a yellow alarm will not inhibit further alarm or performance monitoring 0 = continue error count during alarms 1 = stop error count during alarms Enable ONESEC Latching of Counters--Determines interval for which error counts remain held in all count registers [addr 050-057]. LATCH_CNT must be active in T1 mode whenever automatic one-second performance report messaging [AUTO_PRM; addr 0AA] is enabled. Note that LATCH_CNT active during E1 mode prevents the processor from using RLOF counter overflow [addr 007] as a 128 ms MFAS timeout. When LATCH_CNT is inactive, the processor read of the LSB register reports current LSB error count, it latches current MSB error count to MSB register, and clears LSB. Subsequently, reading MSB register reports current latched MSB error count and then clears MSB.
LATCH_CNT 0 1 Count Latched Never ONESEC interval Count Hold Time Until read clear ONESEC interval
LATCH_CNT
LATCH_ERR
Enable ONESEC Latching of Errors--Determines the interval for which latched active errors are held in error interrupt [ISR5; addr 006] and pattern interrupt [ISR0; addr 00B] status.
IER 0 0 1 LATCH_ERR 0 1 X ISR Latched Rising edge event Rising edge event Rising edge event ISR Hold Time Until read clear ONESEC interval Until read clear
LATCH_ALM
Enable ONESEC Latching of Alarms--Determines interval for which latched active alarms remain held in alarm interrupt status [ISR7, ISR6; addr 004, 005].
IER 0 0 1 LATCH_ALM 0 1 X ISR Latched Rising edge or transition Rising edge or transition Rising edge or transition ISR Hold Time Until read clear ONESEC interval Until read clear
NOTE(S): Interrupt type determines rising edge or transition event.
3-44
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.9 Receiver Registers
047--Alarm 1 Status (ALM1)
ALM1 reports current status of receive alarms. Any change in the current status activates the corresponding interrupt status bit [ISR7; addr 004].
7 RMYEL 6 RYEL 5 -- 4 RAIS 3 RALOS 2 RLOS 1 RLOF 0 SIGFRZ
RMYEL
Receive Multiframe Yellow Alarm--Real-time or integrated RMYEL status depends on the selected framer mode and the yellow alarm integration mode [YEL_INTEG; addr 045]. Refer to Table 2-1, Receive Framer Modes, for mode summary and Table 3-13 for set/clear criteria. 0 = no alarm 1 = receive multiframe yellow alarm
Table 3-14. Receive Yellow Alarm Receive Framer Mode
FT/SF/SLC JYEL T1DM ESF FAS CAS
YEL_INTEG = 0 RYEL
YB2 YJ Y24 YB2 Y0 Y0
YEL_INTEG = 1 RYEL
YB2_INT YJ_INT Y24_INT YB2_INT Y0_INT Y0_INT
RMYEL
-- -- -- YF -- Y16
RMYEL
-- -- -- YF_INT -- Y16_INT
NOTE(S): Last known frame alignment is used to locate and monitor yellow alarms.
Therefore, RYEL and RMYEL will not accurately report alarms during receive loss of frame alignment [RLOF; addr 047].
RYEL
Receive Yellow Alarm--Real-time or integrated RYEL status depends on selected receive framer mode and yellow alarm integration mode [YEL_INTEG; addr 045]. Refer to Table 3-14 for mode summary and Table 3-13 for set/clear criteria. 0 = no alarm 1 = receive Yellow Alarm
100054E
Conexant
3-45
3.0 Registers
3.9 Receiver Registers
RAIS
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Receive Alarm Indication Signal--Criteria for detection and clearance of RAIS per ITU G.775 and ANSI T1.231.
Mode E1 RAIS 0 Set/Clear Criteria Cleared if 2 consecutive double frames (500 s) each contain 3 or more zeros out of 512 bits or FAS alignment is recovered [FRED = 0; addr 049]. Set if 2 consecutive double frames each contain 2 or fewer zeros out of 512 bits and FAS alignment is lost [FRED = 1; addr 049]. Cleared if data received for a period of 3 ms contains 5 or more zeros out of 4632 bits or frame alignment is recovered [FRED = 0; addr 049]. Set if data received for a period of 3 ms contains 4 or fewer zeros out of 4632 bits and frame alignment is lost [FRED = 1; addr 049].
E1
1
T1
0
T1
1
RALOS
Receive Loss of Signal or Receive Clock--Reports loss of receive clock (RCKI) or loss of receive signal [RLOS; addr 047] for 1 msec depending on the RALOS configuration bit [RAL_CON; addr 020]. When set for loss of clock, RALOS becomes active (1) if the receive clock on the RCKI pin is not present, and inactive (0) if the clock is present. When set for loss of signal, RALOS indicates that all zeros have been received for at least 1 msec (RLOS is active for 1 msec). This status is provided for compatibility with ITU-I.431 loss of signal detection requirements; and works in conjunction with LIUs which detect loss of signal if the received signal level falls below a certain threshold and which have a signal `squelch' feature. Operation is as follows: * The LIU detects receive loss of signal if the receive level falls below: - 30 dB below nominal for T1. - 20 dB below nominal for E1 * The LIU squelches (turns off) the signal to the framer so all zeros are received. * RLOS is reported after 100 continuous zeros are detected. * RALOS is reported after RLOS is active for 1 msec.
RLOS
Receive Loss of Signal--Criteria for detection and clearance of RLOS per ITU G.775 and ANSI T1.231.
Mode T1 RLOS 0 Set/Clear Criteria Cleared if received data sustains an average pulse density of 12.5% over a period of 114 bits starting with the receipt of a pulse, and no occurrence of 100 consecutive zeros. Set if 100 consecutive zeros received. Cleared upon reception of 193 bits in which no interval of 32 consecutive zeros appear, where the 193-bit window begins with receipt of a pulse. Set upon reception of 32 consecutive zeros.
T1 E1
1 0
E1
1
3-46
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
RLOF
3.0 Registers
3.9 Receiver Registers
Receive Loss of Frame Alignment--Real-time or integrated RLOF status depends on selected receive framer mode, out of frame criteria [RLOFA-RLOFD; addr 040], and integration mode [RLOF_INTEG; addr 045]. Refer to Tables A-1 through A-6 in Appendix A to find which frame bits are monitored. Refer to Table 2-2, Criteria for Loss/Recovery of Receive Framer Alignment, for the loss/recovery criteria. During E1 mode, RLOF indicates logically OR'ed status of FAS/MFAS/CAS alignment machines from which individual alignment status is reported separately in FRED/MRED/SRED [addr 049]. 0 = no alarm 1 = receive loss of frame alignment Signaling Freeze--Real-time SIGFRZ status indicates when input ABCD signaling bit updates are no longer being written to the receive signaling buffer [RSIGn; addr IA0-IBF]. Consequently, ABCD signaling on RPCMO (if signaling insertion enabled) and RSIGO output pins are fixed to their existing buffered values. SIGFRZ remains active for 6 to 12 ms longer after COFA or RLOF clears. SIGFRZ status is also affected by manual SIGFRZ on/off controls [RSIG_CR; addr 0D7]. 0 = no alarm (or FRZ_OFF) 1 = signaling freeze (or FRZ_ON)
SIGFRZ
048--Alarm 2 Status (ALM2)
Reports real-time status of transmit alarms and inband loopback codeword detectors. Any change in the current status activates the corresponding interrupt status bit [ISR6; addr 005]. Unused bits are reserved and should be written to 0.
7 LOOPDN 6 LOOPUP 5 -- 4 -- 3 TLOC 2 -- 1 TLOF 0 --
LOOPDN
Inband Loopback Deactivate--Reports detection or loss of an inband loopback code which matches the programmed LOOPDN code [LBD; addr 044]. 0 = no inband code (or lost) 1 = LOOPDN code detected Inband Loopback Activate--Reports detection or loss of an inband loopback code which matches the programmed LOOPUP code [LBA; addr 043]. 0 = no inband code (or lost) 1 = LOOPUP code detected Transmit Loss of Clock--Clock monitor circuit reports TCKI lost if no signal transitions are detected on TCKI pin for eight clock cycles of T1ACKI(T1) or EIACKI(E1). TCKI is reported as present if four or more signal transitions are detected on TCKI pin during eight clock cycles of T1/E1ACKI. When used in conjunction with AISCLK [addr 068], TLOC also identifies which transmit line rate clock (TCKI or T1/E1ACKI) is presently in use and whether AIS data transmission is enforced. Note that TLOC status is indeterminate if the T1/E1ACKI input signal is not present. 0 = TCKI present 1 = TCKI lost Transmit Loss of Frame Alignment--Reports transmit framer status per selected mode [TFRAME; addr 070] and loss criteria [TLOFA-TLOFC; addr 071]. 0 = recovered 1 = lost
LOOPUP
TLOC
TLOF
100054E
Conexant
3-47
3.0 Registers
3.9 Receiver Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
049--Alarm 3 Status (ALM3)
Reports real-time status of the receive framer (not affected by ONESEC latch mode), and miscellaneous latched error status (SEF and RMAIS). Any change of the logical OR of (FRED or MRED or SRED) status activates RLOF interrupt [ISR7; addr 004]. Refer to Table 2-2, Criteria for Loss/Recovery of Receive Framer Alignment, [RFRAME; addr 001] to find the criteria for loss/recovery of frame alignment.
7 -- 6 RMAIS 5 SEF 4 SRED 3 MRED 2 FRED 1 LOF[1] 0 LOF[0]
RMAIS
Receive TS16 Alarm Indication Signal (CAS mode only)--RMAIS is latched active high and cleared by a processor read. Criteria for detection and clearance of RMAIS is per ITU G.775.
Mode CAS Other RMAIS Criteria Set if TS16 contains three or fewer zeros out of 128 bits in each mutiframe over two consecutive multiframes (4 ms). Not applicable (read zero).
SEF
Severely Errored Frame--SEF is latched active high and cleared by a processor read. Criteria for detection and clearance of SEF is per ANSI T1.231.
Mode E1 FT/SF/SLC ESF SEF Criteria Set if two or more (FAS or NFAS) errors detected out of six frames. (FAS + NFAS, or 2 FAS, or 2 NFAS errors, etc.). Set if two or more Ft errors are detected out of 3 Ft bits. Set if two or more FPS errors detected out of six FPS bits.
SRED
Loss of CAS Alignment--Real-time status of CAS alignment machine. SRED is applicable if CAS is enabled, otherwise SRED is zero. 0 = recovery of CAS alignment 1 = loss of CAS alignment Loss of MFAS Alignment--Real-time status of MFAS alignment machine. MRED is applicable if MFAS is enabled, otherwise MRED is zero. 0 = recovery of MFAS alignment 1 = loss of MFAS alignment Loss of T1/FAS Alignment--Real-time status of basic frame alignment machine. FRED alarm counter [AERR; addr 05A] increments for each low-to-high FRED transition. 0 = recovery of frame alignment 1 = loss of frame alignment Reason for Loss of Frame Alignment--LOF status is latched whenever FRED reports a loss of frame alignment and remains held at the latched value until the next loss of frame alignment.
LOF[1:0] 00 01 10 11 LOF Criteria Three consecutive FAS pattern errors Three consecutive NFAS pattern errors 915 or more CRC4 errors out of 1000 blocks checked Eight ms timeout while searching for MFAS
MRED
FRED
LOF[1:0]
3-48
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.10 Performance Monitoring Registers
3.10 Performance Monitoring Registers
If the counter overflow interrupt [IER4; addr 00F] is enabled for the respective Performance Monitoring counter, the counter is allowed to roll over after reaching its maximum count value. If the overflow interrupt is disabled, the counter will hold its maximum value upon saturation. Refer also to LATCH [addr 046] for a description of one-second latched counter operation. Processor must read LSB before reading MSB of each multi-byte counter.
050--Framing Bit Error Counter LSB (FERR)
7 FERR[7] 6 FERR[6] 5 FERR[5] 4 FERR[4] 3 FERR[3] 2 FERR[2] 1 FERR[1] 0 FERR[0]
FERR[7:0]
Ft/Fs/T1DM/FPS/FAS Error Count
051--Framing Bit Error Counter MSB (FERR)
If LATCH_CNT [addr 046] is inactive, reading FERR [addr 051] clears the entire FERR[11:0] count value.
15 0 14 0 13 0 12 0 11 FERR[11] 10 FERR[10] 9 FERR[9] 8 FERR[8]
FERR[11:8]
Ft/Fs/T1DM/FPS/FAS Error Count
052--CRC Error Counter LSB (CERR)
7 CERR[7] 6 CERR[6] 5 CERR[5] 4 CERR[4] 3 CERR[3] 2 CERR[2] 1 CERR[1] 0 CERR[0]
CERR[7:0]
CRC6/CRC4 Error Count
053--CRC Error Counter MSB (CERR)
If LATCH_CNT [addr 046] is inactive, reading CERR [addr 053] clears the entire CERR[9:0] count value.
15 0 14 0 13 0 12 0 11 0 10 0 9 CERR[9] 8 CERR[8]
CERR[9:8]
CRC6/CRC4 Error Count
100054E
Conexant
3-49
3.0 Registers
3.10 Performance Monitoring Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
054--Line Code Violation Counter LSB (LCV)
7 LCV[7] 6 LCV[6] 5 LCV[5] 4 LCV[4] 3 LCV[3] 2 LCV[2] 1 LCV[1] 0 LCV[0]
LCV[7:0]
BPV and EXZ (if EXZ_LCV enabled) Error Count
055--Line Code Violation Counter MSB (LCV)
If LATCH_CNT [addr 046] is inactive, reading LCV [addr 055] clears the entire LCV[15:0] count value.
15 LCV[15] 14 LCV[14] 13 LCV[13] 12 LCV[12] 11 LCV[11] 10 LCV[10] 9 LCV[9] 8 LCV[8]
LCV[15:8]
BPV and EXZ (if EXZ_LCV enabled) Error Count
056--Far End Block Error Counter LSB (FEBE)
7 FEBE[7] 6 FEBE[6] 5 FEBE[5] 4 FEBE[4] 3 FEBE[3] 2 FEBE[2] 1 FEBE[1] 0 FEBE[0]
FEBE[7:0]
FEBE Count (applicable only in E1 mode)
057--Far End Block Error Counter MSB (FEBE)
If LATCH_CNT [addr 046] is inactive, reading FEBE [addr 056, 057] clears the entire FEBE[9:0] count value.
15 0 14 0 13 0 12 0 11 0 10 0 9 FEBE[9] 8 FEBE[8]
FEBE[9:8]
FEBE Count (applicable only in E1 mode)
058--PRBS Bit Error Counter LSB (BERR)
Reading BERR transfers the most recent 12-bit count from the internal PRBS error counter to BERR[11:0], then clears the internal error counter without affecting the reported BERR[11:0] value. Subsequent reads of BERR MSB [addr 059] report the BERR [11:8] count value latched when BERR LSB was last read.
7 BERR[7] 6 BERR[6] 5 BERR[5] 4 BERR[4] 3 BERR[3] 2 BERR[2] 1 BERR[1] 0 BERR[0]
BERR[7:0]
BERR Count (applicable only for test pattern)
3-50
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.10 Performance Monitoring Registers
059--PRBS Bit Error Counter MSB (BERR)
15 0 14 0 13 0 12 0 11 BERR[11] 10 BERR[10] 9 BERR[9] 8 BERR[8]
BERR[11:8]
BERR Count (suspended if BSTART = 0)
05A--SEF/FRED/COFA Alarm Counter (AERR)
Reading AERR clears the SEF[1:0], COFA[1:0] and FRED[3:0] count values.
7 FRED[3] 6 FRED[2] 5 FRED[1] 4 FRED[0] 3 COFA[1] 2 COFA[0] 1 SEF[1] 0 SEF[0]
FRED[3:0]
Receive loss of basic frame alignment count--Increments for each occurrence of FRED [ALM3; addr 049]. The four bit count is large enough to count more than 100 ms worth of MFAS timeout intervals (8 ms each) during E1 modes. Processor may therefore use FRED counter overflow interrupt to indicate that a receive MFAS alignment search has timed out. Change of Frame Alignment Count--Increments each time the offline framer generates a reframe pulse that aligns the receiver timebase to a new bit position. Severely Errored Frame Count--Increments for each occurrence of SEF [ALM3; addr 049].
COFA[1:0]
SEF[1:0]
100054E
Conexant
3-51
3.0 Registers
3.11 Receive Sa-Byte Buffers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.11 Receive Sa-Byte Buffers
Five receive Sa-Byte buffers [RSA4-RSA8] are double-buffered. All five registers are updated with the Sa-bits received in TS0 of odd frames at each receive multiframe interrupt [RMF; addr 008]. Bit 0 of all RSA registers contains data from frame 1, Bit 1 contains data from frame 3, Bit 2 contains data from frame 5, etc. This gives the processor a full 2 ms after RMF interrupt to read any Sa-Byte buffer before the buffer content changes. Processor should ignore RSA buffer contents at all times during T1 mode and also when receiver reports loss of FAS alignment [FRED=1; addr 049] in E1 mode.
05B--Receive Sa4 Byte Buffer (RSA4)
7 RSA4[7] 6 RSA4[6] 5 RSA4[5] 4 RSA4[4] 3 RSA4[3] 2 RSA4[2] 1 RSA4[1] 0 RSA4[0]
RSA4[7] RSA4[6] RSA4[5] RSA4[4] RSA4[3] RSA4[2] RSA4[1] RSA4[0]
Sa4 bit received in frame 15 Sa4 bit received in frame 13 Sa4 bit received in frame 11 Sa4 bit received in frame 9 Sa4 bit received in frame 7 Sa4 bit received in frame 5 Sa4 bit received in frame 3 Sa4 bit received in frame 1
05C--Receive Sa5 Byte Buffer (RSA5)
7 RSA5[7] 6 RSA5[6] 5 RSA5[5] 4 RSA5[4] 3 RSA5[3] 2 RSA5[2] 1 RSA5[1] 0 RSA5[0]
RSA5[7] RSA5[6] RSA5[5] RSA5[4] RSA5[3] RSA5[2] RSA5[1] RSA5[0]
Sa5 bit received in frame 15 Sa5 bit received in frame 13 Sa5 bit received in frame 11 Sa5 bit received in frame 9 Sa5 bit received in frame 7 Sa5 bit received in frame 5 Sa5 bit received in frame 3 Sa5 bit received in frame 1
3-52
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.11 Receive Sa-Byte Buffers
05D--Receive Sa6 Byte Buffer (RSA6)
7 RSA6[7] 6 RSA6[6] 5 RSA6[5] 4 RSA6[4] 3 RSA6[3] 2 RSA6[2] 1 RSA6[1] 0 RSA6[0]
RSA6[7] RSA6[6] RSA6[5] RSA6[4] RSA6[3] RSA6[2] RSA6[1] RSA6[0]
Sa6 bit received in frame 15 Sa6 bit received in frame 13 Sa6 bit received in frame 11 Sa6 bit received in frame 9 Sa6 bit received in frame 7 Sa6 bit received in frame 5 Sa6 bit received in frame 3 Sa6 bit received in frame 1
05E--Receive Sa7 Byte Buffer (RSA7)
7 RSA7[7] 6 RSA7[6] 5 RSA7[5] 4 RSA7[4] 3 RSA7[3] 2 RSA7[2] 1 RSA7[1] 0 RSA7[0]
RSA7[7] RSA7[6] RSA7[5] RSA7[4] RSA7[3] RSA7[2] RSA7[1] RSA7[0]
Sa7 bit received in frame 15 Sa7 bit received in frame 13 Sa7 bit received in frame 11 Sa7 bit received in frame 9 Sa7 bit received in frame 7 Sa7 bit received in frame 5 Sa7 bit received in frame 3 Sa7 bit received in frame
100054E
Conexant
3-53
3.0 Registers
3.11 Receive Sa-Byte Buffers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
05F--Receive Sa8 Byte Buffer (RSA8)
7 RSA8[7] 6 RSA8[6] 5 RSA8[5] 4 RSA8[4] 3 RSA8[3] 2 RSA8[2] 1 RSA8[1] 0 RSA8[0]
RSA8[7] RSA8[6] RSA8[5] RSA8[4] RSA8[3] RSA8[2] RSA8[1] RSA8[0]
Sa8 bit received in frame 15 Sa8 bit received in frame 13 Sa8 bit received in frame 11 Sa8 bit received in frame 9 Sa8 bit received in frame 7 Sa8 bit received in frame 5 Sa8 bit received in frame 3 Sa8 bit received in frame 1
3-54
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.12 Transmitter Registers
3.12 Transmitter Registers
070--Transmit Framer Configuration (TCR0)
TCR0 selects the offline framer's criteria for recovery of transmit frame alignment and determines the output of transmit frame and alarm formatters overhead bits. In addition, TCR0 works in conjunction with TCR1 [addr 071] and TFRM [addr 072] to select the transmit online frame monitor's criteria for loss of frame alignment and to select which overhead bits are supplied by the transmit frame and alarm formatters. Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 TINCF 3 TFRAME[3] 2 TFRAME[2] 1 TFRAME[1] 0 TFRAME[0]
TINCF
Transmit CRC6 includes F-bit--Determines if the F-bit is included in the CR6 remainder calculation in T1 mode (T1/E1N = 1). This bit is ignored in E1 mode (T1/E1N = 0). 0 = T1 ESF CRC6 calculation is performed on the transmit data including a 1 in place of the F-bit. 1 = T1 ESF CRC6 calculation is performed on transmit data including the F-bit.
100054E
Conexant
3-55
3.0 Registers
3.12 Transmitter Registers
TFRAME[3:0]
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Frame formatter generates Ft, Fs, FPS, FAS, MFAS, and CRC bits. Alarm formatter generates YB2, YJ, Y0, and Y16 bits. Frame and alarm overhead formats are selected by TFRAME[3:0] and T1/E1N settings as given in Tables 3-15 through 3-18. Each yellow alarm is capable of being generated manually, automatically [TALM; addr 075], or bypassed [INS_MYEL; addr 072]. Frame formatter does not generate CAS or Sa-bit overhead. These bits are either supplied by TPCMI in bypass mode [TFRM; addr 072] or by programming TSIGn [addr 120-13F] or TSA4-TSA8 [addr 07B-07F] buffer contents. To insert CAS, the processor selects TLOCAL output signaling for time slot 0 and time slot 16 by programming transmit per-channel control registers TPC0 [addr 100] and TPC16 [addr 110]. The processor then fills ABCD local signaling value for TPC0 with MAS pattern (ABCD = 0000) and TPC16 with XYXX pattern (ABCD = 1011). Frame formatter does not generate SLC, T1DM, or FDL overhead. These bits are either supplied by TPCMI in bypass mode [TFRM; addr 072] or by programming TSLIP [addr 140-17F], TDL1 [addr 0AD], or TDL2 [addr 0B8] buffer contents. To insert SLC concentrator, maintenance, alarm, and switch field values, the processor selects any SLC framer format and programs either TDL1 or TDL2. This is done in order to operate in unformatted Pack6 mode over the F-bit channel during even frames, thus overwriting all Fs bits inserted by frame formatter. The data pattern to be sent in 36 Fs bit multiframe is then written as six 6-bit words to TDL1 or TDL2 circular buffer. For real-time overhead manipulation, the processor can rewrite the circular buffer with a new 36-bit pattern as desired. To insert T1DM, the processor enables TIDLE insertion on time slot 24 by programming the system bus per-channel control [SBC24; addr 0F8], then filling TSLIP buffer locations for TS24 [addr 138, 158] with the T1DM framing pattern (TS24 = 10111YR0). If specific T1DM elements need to be inserted and others bypassed, the processor configures TDL1 or TDL2 to selectively insert only the desired bits. T1DM sync pattern, R-bits, and/or Y-bits. The processor accomplishes this by programming data link bit enables [DL1_BIT; addr 0A5 or DL2_BIT; addr 0B0]. To insert FDL, the processor configures TDL1 to operate over the F-bit channel during odd frames [DL1_TS; addr 0A4] and Automatic Performance Report Messages [AUTO_PRM; addr 0AA] or manually programs TDL1 to send each message.
Table 3-15. E1 Transmit Framer Modes (T1/E1N = 0) TS0 Overhead Insertion TFRAME
00XX 01XX 10XX 11XX
Yellow Alarms FAS
Yes Yes Yes Yes
Framer Mode MFAS
FAS Only FAS + CRC FAS + CAS FAS + CRC + CAS Ones Yes Ones Yes
FEBE
Ones Yes Ones Yes
CRC4
Ones Yes Ones Yes
YEL
Y0 Y0 Y0 Y0
MYEL
- - Y16 Y16
3-56
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-16. T1 Transmit Framer Modes (T1/E1N = 1) F-bit Overhead Insertion TFRAME
0000 0100 0101 100X 0001 1100 1101
3.0 Registers
3.12 Transmitter Registers
Yellow Alarms Ft
Yes Yes Yes Yes - - -
Framer Mode Fs
FT Only SF SF + JYEL SLC ESF + No CRC ESF + Mimic CRC ESF + Force CRC Ones Yes Yes Yes - - -
FPS
- - - - Yes Yes Yes
CRC6
- - - - Ones Yes Yes
YEL
YB2 YB2 YJ YB2 YB2 YB2 YB2
MYEL
- - - - YF YF YF
Table 3-17. Criteria for E1 Loss/Recovery of Transmit Frame Alignment Mode
FAS
Description
Basic Frame Alignment (BFA) is recovered when the following search criteria are satisfied: * FAS pattern (0011011) is found in frame N. * Frame N+1 contains bit 2 equal to 1. * Frame N+2 also contains FAS pattern (0011011). During FAS only modes, BFA is recovered when the following search criteria are satisfied: * FAS pattern (0011011) is found in frame N. * No mimics of the FAS pattern present in frame N+1. * FAS pattern (0011011) is found in frame N+2.
NOTE(S): If FAS pattern is not found in frame N+2 or FAS mimic is found in frame N+1, then the search restarts in frame N+2.
Transmit Loss of Frame (TLOF) alignment is declared when: * Three consecutive FAS pattern errors are detected, where FAS pattern consists of a 7-bit (x0011011) pattern in FAS frames as well as bit 2 equalling one in NFAS frames. MFAS MFAS--CRC Multiframe Alignment is recovered when the following search criteria are satisfied: * BFA is recovered, identifying FAS and NFAS frames. * Within 6 ms after BFA, bit 1 of NFAS frames contains the first MFAS pattern (001011xx). * Within 8ms after BFA, bit 1 of NFAS frames contains the second MFAS pattern (001011xx), aligned to first MFAS. MFAS errors do not cause Transmit Loss of Frame (TLOF) alignment. CAS CAS Multiframe Alignment is recovered when the following search criteria are satisfied: * BFA is recovered, identifying TS0 through TS31. * MAS (0000xxxx) Multiframe Alignment Signal pattern is found in the first 4 bits of TS16, and 8 bits of TS16 in preceding frame contains nonzero value. CAS errors do not cause Transmit Loss of Frame (TLOF) alignment.
100054E
Conexant
3-57
3.0 Registers
3.12 Transmitter Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-18. Criteria for T1 Loss/Recovery of Transmit Frame Alignment Mode
FT Only
Description
Terminal Frame Alignment is recovered when: * One and only one valid Ft pattern (1010) is found in 12 alternate F-bit locations (3 ms), where F-bits are separated by 193 bits. Transmit Loss of Frame (TLOF) alignment is declared when: * Number of Ft bit errors detected meets selected loss of frame criteria [TLOFA-TLOFC; addr 071].
SF
Superframe alignment is recovered when: * Terminal frame alignment is recovered, identifying Ft bits. * Depends on SF submode: If JYEL: If SF pattern (00111x) found in Fs bits If no JYEL: SF pattern (001110) found in Fs bits. Fs errors do not cause Transmit Loss of Frame (TLOF) alignment. Transmit loss of frame alignment (TLOF) declared when: * Number of Ft bit errors detected meets selected reframe criteria [TLOFA-TLOFC; addr 071]. Notice that Fs bit multiframe errors are reported in TMERR [ISR0; addr 00B], but do not cause a loss of transmit frame alignment.
SLC
Superframe alignment is recovered when: * Terminal frame alignment is recovered, identifying Ft bits. * SLC pattern (refer to Table A-3, SLC-96 Fs Bit Contents) found in 16 of 32 Fs bits according to Bellcore TR-TSY-000008. Fs errors do not cause Transmit Loss of Frame (TLOF) alignment. Transmit loss of frame alignment (TLOF) declared when: * Number of Ft bit errors detected meets selected reframe criteria [TLOFA-TLOFC; addr 071]. Notice that Fs bit multiframe errors are reported in TMERR [ISR0; addr 00B], but do not cause a loss of transmit frame alignment.
ESF
Extended superframe alignment is recovered when: * Valid FPC candidate located (001011). Candidate bits are each separated by 772 digits and received without pattern errors: If only one valid FPS candidate and: No CRC mode: align to FPS regardless of CRC6 comparison. Mimic CRC mode: align to FPS regardless of CRC6 comparison. Force CRC mode: align to FPS only if CRC6 is correct. If two or more valid FPS candidates and: No CRC mode: do not align (INVALID status) Mimic CRC mode: align to first FPS with correct CRC6. Force CRC mode: align to first FPS with correct CRC6. Transmit loss of frame alignment (TLOF) declared when: * Number of FPS pattern errors detected meets selected loss of frame criteria [TLOFA-TLOFC; addr 071].
3-58
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.12 Transmitter Registers
071--Transmitter Configuration (TCR1)
7 TNRZ 6 TABORT 5 TFORCE 4 TLOFC 3 TLOFB 2 TLOFA 1 TZCS[1] 0 TZCS[0]
TNRZ
Transmit NRZ Data--Transmit dual-rail unipolar outputs TPOSO/TNEGO are replaced by non-return to zero unipolar data (TNRZO) and transmit multiframe sync (MSYNCO). Both outputs are clocked on the rising edge of transmitter clock (TCKI). TNRZ must be written to 1 on the CX28395 device. 0 = TPOSO/TNEGO encoded per TZCS[1:0] 1 = TPOSO/TNEGO replaced by TNRZO/MSYNCO
NOTE:
MSYNCO active (high) always marks the first bit of transmit multiframe according to the selected transmit framer mode.
TABORT
Abort/Disable TX Offline Framer--Offline framer ignores reframe requests from the online framer (TLOF) and aborts any in progress TLOF reframe requests. Loss of frame status [TLOF; addr 048] is not affected. While TABORT remains active, offline framer responds only to the processor force reframe request (TFORCE), which allows the processor to manually control reframe criteria or lock out changes in the current transmit frame alignment. 0 = normal framer operation 1 = framer disabled TABORT also interacts with EMBED [addr 0D0] to select which data stream is examined by online and offline transmit framer during embedded framing modes. If EMBED is active, TXDATA output from TSLIP is examined and used to align the TX timebase. Otherwise, TPCMI data stream is examined and used to align the TSB timebase as given in Table 3-19.
Table 3-19. Transmit Framer Position TABORT
0 0 1
NOTE(S):
EMBED
0 1 X
TSB Alignment
TPCMI TFSYNC/TMSYNC TFSYNC/TMSYNC
Tx Alignment
Flywheel TXDATA Flywheel
Tx Framing Mode
Transmit Framing Embedded Framing Normal
Notes
(1-5) (6-8) (5, 6)
1. 2. 3. 4. 5. 6. 7. 8.
TFSYNC and TMSYNC must be programmed as outputs. Offline framer examines TPCMI to supply TSB frame alignment. Online framer examines TPCMI to supply TSB multiframe alignment. SBI mode must match 2048k or 1544k line rate. TX timebase flywheels at initial alignment until TSB_CTR or TX_ALIGN [addr 0D4]. TSB timebase flywheels if TFSYNC/TMSYNC programmed as outputs. Offline framer examines TXDATA to supply TX frame alignment. Online framer examines TXDATA to supply TX multiframe alignment.
TFORCE
Force TX Reframe (auto clear)--Forces the offline framer to perform a single reframe according to the selected transmit framer mode. TFORCE is automatically cleared when the framer acknowledges a request [ACTIVE; addr 017]. The processor does not typically need to force reframe since online framer reframe request (TLOF) is active when reframe criteria TLOFC-A is met. However, the processor may wish to force reframe if frame or CRC bit error ratio indicates the framer has aligned to a mimic pattern. 0 = no effect 1 = force TX reframe
100054E
Conexant
3-59
3.0 Registers
3.12 Transmitter Registers
TLOFC-TLOFA
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Transmit Loss Of Frame Criteria--Determines the number of frame errors that the online framer must detect before declaring loss of frame alignment [TLOF; addr 048]. Refer to TFRAME [addr 070] to find which frame bits are monitored during the selected framer mode.
T1/E1N 0 1 1 1 TLOFC-A 100 001 010 100 Reframe Criteria Three consecutive FAS errors Two out of four frame bit errors Two out of five frame bit errors Two out of six frame bit errors
NOTE(S): All other TLOFC-A combinations are invalid.
TZCS[1:0]
Transmit Zero Code Suppression--Selects ZCS and Pulse Density Violation (PDV) enforcement options for TPOSO/TNEGO outputs. B8ZS and HDB3 replace transmitted sequences of 8 zeros or 4 zeros with a recoverable code and are standard T1 and E1 line code options, respectively (see Table 3-20).
Table 3-20. Transmit Zero Code Suppression TZCS
00 01 01 10 11 AMI
T1/E1N
X 0 1 1 1
T1DM
X X X 1 X
ZCS
AMI HDB3 B8ZS UMC AMI
PDV
None None None None Enforced None 000V or B00V 000VB0VB 10011000 on PDV errors
Zero Code Substitution (Sent left to right)
Alternate Mark Inversion. Bipolar line code forces successive ones to alternate their output pulse polarity. Analog and digital dual-rail outputs are always AMI encoded, although certain AMI codes are modified to include zero suppression. Prior to transmission, 4 consecutive zeros are substituted by 000V or B00V code, where B is an AMI pulse and V is a bipolar violation. ZCS encoder selects the code which will force the BPV output polarity opposite that of the prior BPV. Prior to transmission, 8 consecutive zeros are substituted by 000VB0VB code, where B is an AMI encoded pulse and V is a bipolar violation. Enforcer overwrites transmit zeros that would otherwise cause output data to fail to meet the minimum required pulse density per ANSI T1.403 sliding window. Note that the enforcer will never overwrite a framing bit and is not applicable during E1 mode. Note that each PDV enforced one causes a nonrecoverable transmitted bit error. Unassigned Mux Code. DS0 channels that contain 8 zeros are substituted with the 10011000 code, per Bellcore TA-TSY-000278. Note that the receiver's ZCS decoder cannot recover original data content from UMC encoded signal.
HDB3 B8ZS PDV
UMC
NOTE(S): PRBS, inband loopback, and YB2 alarm insertion occur after PDV enforcement. Therefore, output data might violate
minimum pulse density requirements while these functions are active.
3-60
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.12 Transmitter Registers
072--Transmit Frame Format (TFRM)
TFRM controls the insertion of overhead bits generated by transmit frame and alarm formatters. Bypassed overhead bits flow transparently from TPCMI system bus input through TSLIP buffer. Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 INS_MYEL 4 INS_YEL 3 INS_MF 2 INS_FE 1 INS_CRC 0 INS_FBIT
INS_MYEL
Insert Multiframe Yellow Alarm--Applicable to E1 modes only. Enables the alarm formatter to output Y16 Multiframe Yellow Alarm. Once enabled, TMYEL and AUTO_MYEL [addr 075] control the alarm output state. This bit must be set to 0 in T1 modes. 0 = bypass 1 = insert multiframe yellow alarm Insert Yellow Alarm--The alarm formatter outputs yellow alarms YB2 or YJ during T1 modes; or Y0 during E1 modes. In ESF framed T1 mode, the YF Yellow Alarm is transmitted by programming the DL1 data link controller and by transmitting the appropriate bit oriented code message (BOP message). Once enabled, TYEL and AUTO_YEL [addr 075] control the yellow alarm output state. If the system wants to bypass JYEL (Fs bit in frame 12), then it must bypass all Fs bits with INS_MF [addr 072]. 0 = bypass 1 = insert yellow alarm. Insert Multiframe Alignment--The frame formatter outputs 6-bit SF alignment pattern in T1 mode, or 6-bit MFAS alignment pattern in E1 mode. INS_MF should be set while TFRAME (addr 070) selects Fs (T1) or MFAS (E1) alignment. 0 = bypass 1 = insert multiframe alignment Insert FEBE-- During E1 mode, the alarm formatter automatically outputs TS0 bit 1 of frame 13 (FEBE13) and frame 15 (FEBE15) in response to received CRC4 errors. FEBE13 is active low for each received CRC4 error detected in SMF I. FEBE15 is active low for each received CRC4 error detected in SMF II. INS_FE should be set while TFRAME (addr 070) selects FEBE (E1) alignment. 0 = bypass 1 = insert FEBE Insert Cyclic Redundancy Check--The frame formatter outputs the calculated CRC6 bits in T1 mode or CRC4 bits in E1 mode. 0 = bypass 1 = insert cyclic redundancy check Insert Terminal Framing--The frame formatter outputs a 2-bit Ft alignment pattern in F-bits of odd frames (SF framing) or FPS framing pattern (ESF framing) during T1 modes--or 8-bit FAS/NFAS alignment pattern during E1 modes. INS_FBIT should be set while TFRAME (addr: 070) selects Ft (T1, SF), FPS (T1, ESF), or FAS (E1) alignment. 0 = bypass 1 = insert terminal framing If F-bits are bypassed while TSLIP is enabled, the system must either use embedded T1 framing or apply at least a double frame (250 s) multiframe sync pulse (TMSYNC) to provide odd/even frame alignment.
INS_YEL
INS_MF
INS_FE
INS_CRC
INS_FBIT
100054E
Conexant
3-61
3.0 Registers
3.12 Transmitter Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
073--Transmit Error Insert (TERROR)
Transmit error insertion capabilities are provided for system diagnostic, production test, and test equipment applications. Writing a one to any TERROR bit injects a single occurrence of the respective error on TPOSO/TNEGO or TNRZO outputs. Writing a zero has no effect. Multiple transmit errors can be generated simultaneously. Injected errors also affect data sent during a Framer Loopback [FLOOP; addr 014].
7 TSERR 6 TMERR 5 TBERR 4 BSLIP 3 TCOFA 2 TCERR 1 TFERR 0 TVERR
TSERR
Inject CAS Multiframe (MAS) Error--Injects a single MAS pattern error. TSERR performs a logical inversion of the first MAS bit transmitted. 0 = no effect 1 = inject MAS error Inject Multiframe Error--Injects a single Fs bit (T1) or MFAS (E1) bit error. TMERR performs a logical inversion of the next multiframe bit transmitted. Processor can pace writing to TMERR to control which MFAS bit is errored. 0 = no effect 1 = inject multiframe error Inject PRBS Test Pattern Error--Injects a single PRBS error by logically inverting the next PRBS generator output bit. Processor can pace writing to TBERR to create the desired bit error ratio (up to 5E-3 if TBERR asserted 1/192 bits at every frame interrupt). 0 = no effect 1 = inject PRBS error Inject Transmit COFA--Forces a 1-bit shift in the location of transmit frame alignment by deleting (or inserting) one bit position from the transmit frame. During E1 modes, BSLIP determines in which direction the bit slip will occur. In T1 modes, only one bit deletion is provided. TCOFA alters the extraction rate of data from the transmit slip buffer; thus, repeated TCOFAs eventually cause a controlled frame slip where one frame of data is repeated (T1/BSLIP = 0) or one frame of data is deleted (BSLIP = 1).
TCOFA 0 1 1 1 T1/E1N X 0 0 1 BSLIP X 0 1 X No effect Inhibit output of TS0 bit 1 for one frame Insert 1 prior to FAS pattern for one frame Inhibit output of F-bit for one frame Transmit COFA
TMERR
TBERR
BSLIP/TCOFA
TCERR
Inject CRC Error--Injects a single CRC6 (T1) or CRC4 (E1) bit error. TCERR performs a logical inversion of the next CRC bit transmitted. The processor can pace writing to TCERR to control which CRC bit is errored. 0 = no effect 1 = inject CRC error Inject Frame Bit Error--Injects a single Ft, FPS, or FAS bit error depending on the selected transmit framer mode. TFERR performs a logical inversion of the next frame bit transmitted. The processor can pace writing to TFERR, to control which frame bit is errored. 0 = no effect 1 = inject frame error
TFERR
3-62
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
TVERR
3.0 Registers
3.12 Transmitter Registers
Inject Line Code Violation--Injects a single LCV error, depending on line mode and ZCS selected. In T1 mode, the LCV injector waits for transmission of two consecutive pulses on the data output before performing BPV error insertion and clearing the TVERR bit. Therefore, a BPV error cannot be injected into a transmit data stream that does not contain two consecutive ones. TVERR is latched until an opportunity to inject a BPV error is presented. This prevents the receiving end from detecting: frame or multiframe bit errors, CRC errors, multiple BPV errors (due to ZCS pattern corruption), or PRBS test pattern bit errors as a consequence of error insertion. In E1 mode with HDB3 selected, the LCV injector sends two consecutive BPVs of the same polarity, which causes the receiving end to detect a single LCV error. 0 = no effect 1 = inject line code violation
074--Transmit Manual Sa-Byte/FEBE Configuration (TMAN)
7 INS_SA[8] 6 INS_SA[7] 5 INS_SA[6] 4 INS_SA[5] 3 INS_SA[4] 2 FEBE_II 1 FEBE_I 0 TFEBE
INS_SA[8] INS_SA[7] INS_SA[6] INS_SA[5] INS_SA[4] FEBE_II FEBE_I TFEBE
Manual Sa8-Byte Transmit (0-bypass) Manual Sa7-Byte Transmit (0-bypass) Manual Sa6-Byte Transmit (0-bypass) Manual Sa5-Byte Transmit (0-bypass) Manual Sa4-Byte Transmit (0-bypass) Transmit FEBE Frame 15. Transmit FEBE Frame 13. Manual Transmit FEBE (Overrides INS_FE; addr 072)--Provides a manual override for FEBE bits that are normally sent by the alarm formatter [INS_FE; addr 072]. When active, FEBE_I controls the data output in TS0 bit 1 of frame 13 (FEBE13) and, FEBE_II controls the data output in TS0 bit 1 of frame 15 (FEBE15).
INS_FE 0 1 1 TFEBE X 0 1 FEBE[13] TPCMI SMF I FEBE_I FEBE[15] TPCMI SMF II FEBE_II Description Bypass FEBE Automatic FEBE Manual FEBE
NOTE(S): Automatic FEBE insertion uses two separate CRC4 error signals from the receiver to
indicate SMF I and SMF II errors. Each error signal is latched and held for one full multiframe to compensate for phase differences between receive and transmit multiframe timing.
100054E
Conexant
3-63
3.0 Registers
3.12 Transmitter Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
075--Transmit Alarm Signal Configuration (TALM)
Unused bits are reserved and should be written to 0.
7 -- 6 AISCLK 5 AUTO_MYEL 4 AUTO_YEL 3 AUTO_AIS 2 TMYEL 1 TYEL 0 TAIS
AISCLK
Enable Automatic ACKI Switching--When AISCLK is active and the clock monitor reports a loss of transmit clock [TLOC; addr 048], the transmitter clock is automatically switched to reference TIACKI or EIACKI instead of TCKI. The transmitter is also forced to send AIS (all ones) data. If both AISCLK and TAIS [addr 075] are active, AIS is transmitted using TIACKI or EIACKI clock regardless of the clock monitor status. AISCLK should be set only if the system supplies an alternate line rate clock on TIACKI for TI or EIACKI for EI applications.
Inputs TAIS 0 0 0 0 0 0 1 1 0 0 AUTO_AIS 0 0 X 1 1 1 X X 0 1 AISCLK X 1 1 X 0 0 1 0 0 1 X X X 0 0 1 X X X 1 Status RLOS TLOC 0 0 1 0 1 X X X 1 0 TCKI TCKI TI/EIACKI TCKI TCKI TCKI TI/EIACKI TCKI TCKI TI/E1ACKI Transmit CLOCK DATA Normal Normal AIS Normal Normal AIS AIS AIS Normal AIS
AUTO_MYEL/TMYEL Manual/Automatic
Transmit Multiframe Yellow Alarm--Manual mode sends alarm for as long as TMYEL is active. Automatic mode sends alarm for the duration of a receive loss of multiframe alignment [SRED; addr 049].
INS_MYEL 0 1 1 1 TMYEL X 0 0 1 AUTO_MYEL X 0 1 X Transmit Multiframe Yellow Supplied by TPCMI Inactive Follows SRED status Active
NOTE(S): To transmit T1DM yellow alarm (Y24), the processor must program TDL1,
TDL2, or TSLIP buffer to transmit Y-bit output in time slot 24.
AUTO_YEL /TYEL
Manual/Automatic Transmit Yellow Alarm--Manual mode sends the alarm for as long as TYEL is active and yellow alarm insertion [INS_YEL; addr 072] is enabled. Automatic mode sends yellow alarm for the duration of a receive loss of frame alignment [FRED; addr 049].
INS_YEL 0 1 1 1 TYEL X 0 0 1 AUTO_YEL X 0 1 X Transmit Yellow Alarm Supplied by TPCMI Inactive Follows FRED status Active
NOTE(S): To transmit T1DM yellow alarm (Y24), processor must program TDL1,
TDL2 or TSLIP buffer to transmit Y-bit output in time slot 24.
3-64
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
AUTO_AIS /TAIS
3.0 Registers
3.12 Transmitter Registers
Manual/Automatic Transmit Alarm Indication Signal--When activated manually (TAIS) or automatically (AUTO_AIS), the alarm formatter replaces all data output on TPOSO/TNEGO/TNRZO with an unframed all ones signal (AIS). This includes replacing data from the receiver during line loopback [LLOOP; addr 014]. Automatic mode sends AIS for the duration of receive loss of signal [RLOS; addr 047]. If AISCLK [addr 075] is enabled, then TAIS also provides manual switch control over ACKI clock input. AUTO_AIS does not affect ACKI switching. AIS transmission [TAIS, AUTO_AIS; addr 075, or AISCLK; addr 075] does not affect transmit data that is looped back to the receiver during framer loopback [FLOOP; addr 014]. This allows both FLOOP and LLOOP to be active simultaneously, during a loss of signal, without disrupting data in the framer loopback path.
TAIS 0 0 0 0 1 1 AUTO_AIS 0 0 1 1 X X AISCLK 0 1 0 1 0 1 Transmit Data
Normal, No AIS AIS during TLOC AIS During RLOS AIS During TLOC or RLOS Manual AIS Manual AIS and ACKI
Transmit Clock (TCKO) TCKI TI/EIACKI while TLOC TCKI TI/EIACKI while TLOC TCKI ACKI
NOTE(S): Systems that transmit framed all ones can utilize inband loopback code generator
[TLB; addr 077] to send all ones in payload only.
076--Transmit Test Pattern Configuration (TPATT)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 TPSTART 3 FRAMED 2 ZLIMIT 1 TPATT[1] 0 TPATT[0]
TPSTART FRAMED
Enable Test Pattern Transmission. PRBS Framed--When set, the PRBS pattern does not overwrite framing bit positions and is stopped during these bit periods. In T1 mode, the frame bit (every 193rd bit) is not overwritten. In E1 mode, the PRBS test pattern is not written to time slot 0 (FAS and NFAS words) and time slot 16 (CAS signalling word) if CAS framing is also selected. CAS framing is selected by setting TFRAME[3] to 1 in the Transmit Configuration register [TCR0; addr 070]. If FRAMED is disabled, the test pattern is transmitted in all time slots. Enable Zero Limit; 7/14 depending on pattern. PRBS test patterns used by RPATT [addr 041] and TPATT [addr 076] are defined in the ITU standards O.151 and O.152 to use either inverted or non-inverted data. Standard data inversion is used for the selected PRBS test pattern unless ZLIMIT is enabled, in which case the test pattern uses non-inverted data (see Table 3-12).
ZLIMIT TPATT[1:0]
100054E
Conexant
3-65
3.0 Registers
3.12 Transmitter Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-21. Transmit PRBS Test Pattern Measurements FRAMED
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ZLIMIT
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
TPATT
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Test Pattern Measurements
Unframed 2^11 Unframed 2^15 Unframed 2^20 Unframed 2^23 Unframed 2^11 with 7 zero limit Unframed 2^15 with 7 zero limit Unframed 2^20 with 14 zero limit (QRSS/QRS/QRTS) Unframed 2^23 with 14 zero limit (non-std) Framed 2^11 Framed 2^15 Framed 2^20 Framed 2^23 Framed 2^11 with 7 zero limit Framed 2^15 with 7 zero limit (non std) Framed 2^20 with 14 zero limit (QRSS/QRS/QRTS)) Framed 2^23 with 14 zero limit (non-std)
Inversion
No Yes No Yes No No No No No Yes No Yes No No No No
077--Transmit Inband Loopback Code Configuration (TLB)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 LB_LEN[1] 2 LB_LEN[0] 1 UNFRAMED 0 LBSTART
LB_LEN[1:0]
Inband Loopback Code Length (from LBP): 00 = 4 bits 01 = 5 bits 10 = 6 bits 11 = 7 bits Loopback Code Overwrites Framing. Start Inband Loopback Code Transmission.
UNFRAMED LBSTART
3-66
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.12 Transmitter Registers
078--Transmit Inband Loopback Code Pattern (LBP)
Unused bits are reserved and should be written to 0.
7 LBP[1] 6 LBP[2] 5 LBP[3] 4 LBP[4] 3 LBP[5] 2 LBP[6] 1 LBP[7] 0 --
LBP[1] LBP[2] LBP[3] LBP[4] LBP[5] LBP[6] LBP[7]
First bit transmitted Second bit transmitted Third bit transmitted Fourth bit transmitted Fifth bit transmitted Sixth bit transmitted Seventh bit transmitted
100054E
Conexant
3-67
3.0 Registers
3.13 Transmit Sa-Byte Buffers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.13 Transmit Sa-Byte Buffers
Five transmit Sa-Byte buffers (TSA4-TSA8) are used to insert Sa-bits in TS0. The entire group of 40 bits is sampled every 16 frames, coincident with the TMF interrupt boundary [addr 008]. Bit 0 from each TSA register is then inserted during frame 1, Bit 1 during frame 3, Bit 2 during frame 5 and so on. This gives the processor up to 2 ms after TMF interrupt to write new Sa-Byte buffer values. Transmit Sa-bits maintain a fixed relationship to the transmit CRC multiframe.
07B--Transmit Sa4 Byte Buffer (TSA4)
7 TSA4[7] 6 TSA4[6] 5 TSA4[5] 4 TSA4[4] 3 TSA4[3] 2 TSA4[2] 1 TSA4[1] 0 TSA4[0]
TSA4[7] TSA4[6] TSA4[5] TSA4[4] TSA4[3] TSA4[2] TSA4[1] TSA4[0]
Sa4 bit transmitted in frame 15 Sa4 bit transmitted in frame 13 Sa4 bit transmitted in frame 11 Sa4 bit transmitted in frame 9 Sa4 bit transmitted in frame 7 Sa4 bit transmitted in frame 5 Sa4 bit transmitted in frame 3 Sa4 bit transmitted in frame 1
07C--Transmit Sa5 Byte Buffer (TSA5)
7 TSA5[7] 6 TSA5[6] 5 TSA5[5] 4 TSA5[4] 3 TSA5[3] 2 TSA5[2] 1 TSA5[1] 0 TSA5[0]
TSA5[7] TSA5[6] TSA5[5] TSA5[4] TSA5[3] TSA5[2] TSA5[1] TSA5[0]
Sa5 bit transmitted in frame 15 Sa5 bit transmitted in frame 13 Sa5 bit transmitted in frame 11 Sa5 bit transmitted in frame 9 Sa5 bit transmitted in frame 7 Sa5 bit transmitted in frame 5 Sa5 bit transmitted in frame 3 Sa5 bit transmitted in frame 1
3-68
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.13 Transmit Sa-Byte Buffers
07D--Transmit Sa6 Byte Buffer (TSA6)
7 TSA6[7] 6 TSA6[6] 5 TSA6[5] 4 TSA6[4] 3 TSA6[3] 2 TSA6[2] 1 TSA6[1] 0 TSA6[0]
TSA6[7] TSA6[6] TSA6[5] TSA6[4] TSA6[3] TSA6[2] TSA6[1] TSA6[0]
Sa6 bit transmitted in frame 15 Sa6 bit transmitted in frame 13 Sa6 bit transmitted in frame 11 Sa6 bit transmitted in frame 9 Sa6 bit transmitted in frame 7 Sa6 bit transmitted in frame 5 Sa6 bit transmitted in frame 3 Sa6 bit transmitted in frame 1
07E--Transmit Sa7 Byte Buffer (TSA7)
7 TSA7[7] 6 TSA7[6] 5 TSA7[5] 4 TSA7[4] 3 TSA7[3] 2 TSA7[2] 1 TSA7[1] 0 TSA7[0]
TSA7[7] TSA7[6] TSA7[5] TSA7[4] TSA7[3] TSA7[2] TSA7[1] TSA7[0]
Sa7 bit transmitted in frame 15 Sa7 bit transmitted in frame 13 Sa7 bit transmitted in frame 11 Sa7 bit transmitted in frame 9 Sa7 bit transmitted in frame 7 Sa7 bit transmitted in frame 5 Sa7 bit transmitted in frame 3 Sa7 bit transmitted in frame 1
100054E
Conexant
3-69
3.0 Registers
3.13 Transmit Sa-Byte Buffers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
07F--Transmit Sa8 Byte Buffer (TSA8)
7 TSA8[7] 6 TSA8[6] 5 TSA8[5] 4 TSA8[4] 3 TSA8[3] 2 TSA8[2] 1 TSA8[1] 0 TSA8[0]
TSA8[7] TSA8[6] TSA8[5] TSA8[4] TSA8[3] TSA8[2] TSA8[1] TSA8[0]
Sa8 bit transmitted in frame 15 Sa8 bit transmitted in frame 13 Sa8 bit transmitted in frame 11 Sa8 bit transmitted in frame 9 Sa8 bit transmitted in frame 7 Sa8 bit transmitted in frame 5 Sa8 bit transmitted in frame 3 Sa8 bit transmitted in frame 1
3-70
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.14 Bit-Oriented Protocol Registers
3.14 Bit-Oriented Protocol Registers
The Bit Oriented Protocol (BOP) transceiver sends and receives BOP messages, including ESF Yellow Alarm. These messages consist of repeated 16-bit patterns with an embedded 6-bit codeword. The BOP message channel is configured to operate over the same channel selected by the DL1 Time Slot Enable Register [DL1_TS; addr 0A4]. The channel must be configured to operate over the FDL channel in order for BOP messages to convey Priority, Command, and Response codeword messages according to ANSI T1.403, Section 9.4.1. Therefore, DL1 must be configured and enabled to allow BOP operation, as described in Table 3-22.
Table 3-22. DLI Configuration for T1-ESF, FDL Datalink Configuration Registers
DL1_TS [addr 0A4] DL1_BIT [addr 0A5] DL1-CTL [addr 0A6] RDL1_FFC [addr 0A7] TDL1_FEC [addr 0AB]
Value
0 x 40 0 x 00 0 x 03 00###### 00######
Description
Enabling odd frames, Fbit (T1) Select bits to use in time slot. Select normal FIFO mode, FCS, Tx enabled, Rx enabled. ###### is the threshold for receiver FIFO near full. ###### is the threshold FIFO near empty.
The precedence of transmitted BOP messages with respect to current DL1 transmit activity is configurable [TBOP_MODE; addr 0A0]. BOP messages can also be transmitted during E1 mode, although the 16-bit codeword pattern has not currently been adopted as an E1 standard. BOP message format:
0xxxxxx0 [543210] 11111111 (transmitted right to left) 6-bit codeword
0A0--Bit Oriented Protocol Transceiver (BOP)
7 RBOP_START 6 RBOP_INTEG 5 RBOP_LEN[1] 4 RBOP_LEN[0] 3 TBOP_LEN[1] 2 TBOP_LEN[0] 1 0
TBOP_MODE[1] TBOP_MODE[0]
RBOP_START
BOP Receiver Enable--When active, BOP receiver searches FDL channel for data that matches a 16-bit pattern in the form of 0xxxxxx011111111, where xxxxxx equals a 6-bit codeword. Otherwise, BOP receiver is disabled. 0 = disabled 1 = BOP receiver enable RBOP Integration--Requires receipt of two identical consecutive 16-bit patterns (without errors or gaps between patterns) to validate a single codeword. In this case, an errored codeword does not increment the pattern count. RBOP integration must be enabled to meet codeword detection criteria while receiving 1E-3 bit error ratio. RBOP_INTEG adds at least one to the number of successive 16-bit patterns needed to qualify receipt of BOP message (2 in a row counts as 1 pattern, 11 in a row counts as 10, and 26 in a row counts as 25). 0 = no integration 1 = RBOP integration
RBOP_INTEG
100054E
Conexant
3-71
3.0 Registers
3.14 Bit-Oriented Protocol Registers
RBOP_LEN[1:0]
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
RBOP Message Length--Selects the number of successive identical 16-bit patterns that are needed to qualify receipt of a single BOP message and to update RBOP [addr 0A2] with the received codeword. At this time RBOP interrupt [ISR1; addr 00A] is also activated. Successive patterns can be separated by any number of bits as long as they do not contain a different valid codeword.
RBOP_LEN 00 01 10 11 Successive Patterns 1 10 25 Change Notes Single 16-bit pattern updates RBOP Minimum command, response length Preferred command, response length RBOP updates on receipt of each new pattern
TBOP_LEN[1:0]
TBOP Message Length--Selects the number of repeated 16-bit patterns sent as a single message when a TBOP [addr 0A1] codeword is written. Another message, with the same or different codeword value, can be written to TBOP as soon as prior message start is acknowledged via activation of TBOP interrupt [ISR2; addr 009]. If no new message is written, the FDL channel returns to TDL1 output control upon completion of message transmission. Processor changes TBOP_LEN to end transmission of a continuously repeating message.
TBOP_LEN 00 01 10 11 Repeated Patterns 1 10 25 Continuous Message Length (ms) 4 40 100 Continuous Notes Single message sends 16 FDL bits Minimum command, response length Preferred command Required for ESF yellow alarm
TBOP_MODE[1:0]
Transmit BOP Mode--Enables BOP transmitter and establishes priority of TBOP [addr 0A1] output in relation to TDL1 [addr 0AD] output. When TBOP messages are given output priority, any write to TBOP aborts TDL1 output within the next eight FDL bit times and then suspends TDL1 data output until TBOP has completed transmission. The processor can check TMSG1 status [addr 0AE] before writing TBOP to determine if TDL1 output is idle. TDL1 buffer can be written while TBOP is granted priority. When TDL1 messages are given output priority, TBOP output is suspended when the TDL1 buffer becomes non-empty. Furthermore, TBOP is forced to wait until the TDL1 buffer is empty and the TDL1 output is in the idle state. If TBOP_LEN is continuous and TDL1/PRM message output is pending, then TBOP will be suspended at the next 16-bit pattern boundary. TDL1 priority is used to transmit PRM, DS1 Idle (ISID), or optional path maintenance (PID, TSID) messages separated by ESF Yellow Alarm codewords as defined in Annex D of ANSI T1.403.
TBOP_MODE 0X 10 11 TBOP output priority TDL1 output priority Mode Description Disabled: TBOP writes are ignored
3-72
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.14 Bit-Oriented Protocol Registers
0A1--Transmit BOP Codeword (TBOP)
7 -- 6 -- 5 TBOP[5] 4 TBOP[4] 3 TBOP[3] 2 TBOP[2] 1 TBOP[1] 0 TBOP[0]
TBOP[5] TBOP[4] TBOP[3] TBOP[2] TBOP[1] TBOP[0]
6th bit transmitted 5th bit transmitted 4th bit transmitted 3rd bit transmitted 2nd bit transmitted Transmit BOP codeword, 1st bit transmitted
0A2--Receive BOP Codeword (RBOP)
7 RBOP_LOST 6 RBOP_VALID 5 RBOP[5] 4 RBOP[4] 3 RBOP[3] 2 RBOP[2] 1 RBOP[1] 0 RBOP[0]
RBOP_LOST
Previous Message Overwritten--Activated when RBOP is updated and RBOP_VALID is already set, indicating that the previous codeword was never read by the processor. 0 = no error 1 = prior codeword lost RBOP Message Valid--Set each time RBOP[5:0] is updated with a codeword value. Reading from RBOP clears RBOP_VALID. 0 = no message or message read 1 = new RBOP message received 6th bit received 5th bit received 4th bit received 3rd bit received 2nd bit received Receive BOP codeword, 1st bit received
RBOP_VALID
RBOP[5] RBOP[4] RBOP[3] RBOP[2] RBOP[1] RBOP[0]
100054E
Conexant
3-73
3.0 Registers
3.14 Bit-Oriented Protocol Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0A3--BOP Status (BOP_STAT)
Real-time status of the BOP transmitter and receiver is reported primarily for diagnostic purposes.
7 TBOP_ACTIVE 6 RBOP_ACTIVE 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
TBOP_ACTIVE
TBOP Active--Remains set for the entire length of a message as defined by TBOP_LEN[1:0] [addr 0A0]. RBOP Active--Is set as soon as eight ones are detected and remains set if subsequent 1st and 8th bits are zero. For pattern length 1, RBOP_ACTIVE is a short pulse reported at the end of a received 16-bit pattern. For longer lengths, the signal goes high at the end of the first pattern and is held active until the desired number (or change) of patterns is detected. At this point RBOP interrupt is generated. Consequently, this signal is usually high.
RBOP_ACTIVE
3-74
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
3.15 Data Link Registers
Each framer contains two independent Data Link Controllers (DL1, DL2), which are programmed to send and receive HDLC formatted or unformatted serial data over any combination of bits within a selected time slot. The serial data channels operate at a multiple of 4 kbps up to the full 64 kbps time slot rate by selecting a combination of time slot bits from odd, even, or all frames. DL1 and DL2 each contain a 64-byte receive and 64-byte transmit buffer which, function either as programmable length circular buffers or full-length data FIFOs.
0A4--DL1 Time Slot Enable (DL1_TS)
7 DL1_TS[7] 6 DL1_TS[6] 5 DL1_TS[5] 4 DL1_TS[4] 3 DL1_TS[3] 2 DL1_TS[2] 1 DL1_TS[1] 0 DL1_TS[0]
DL1_TS[7] DL1_TS[6, 5]
Unchannelized--Test mode only; all time slots selected. Zero for normal operation. Frame Select--Transmit and receive data link 1 operates on data only during the specified T1/E1 frames. Frame select options give the processor access to different types of data link channels as well as overhead channels. Note that overhead bit insertion is performed after TDL1, so internal transmitter overhead insertion must be bypassed [TFRM; addr 072] before processor supplied overhead can be output from TDL1. 00 = all frames 01 = even frames only 10 = odd frames only 11 = not valid Time Slot Word Enable--Transmit and receive data link 1 operates on data only during the specified time slot. During T1 mode, selecting time slot zero enables data link operation on the F-bit positions.
DL1_TS[4:0] 00000 00001 | 11110 11111 Time Slot Enable F-bit (T1) or TS0 (E1) TS1 | TS30 TS31
DL1_TS[4:0]
100054E
Conexant
3-75
3.0 Registers
3.15 Data Link Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0A5--DL1 Bit Enable (DL1_BIT)
7 DL1_BIT[7] 6 DL1_BIT[6] 5 DL1_BIT[5] 4 DL1_BIT[4] 3 DL1_BIT[3] 2 DL1_BIT[2] 1 DL1_BIT[1] 0 DL1_BIT[0]
DL1_BIT[7:0]
DL1 Bit Select--Works in conjunction with DL1_TS [addr 0A4] to select one or more time slot bits for data link input and output. Any combination of bits may be enabled by writing the corresponding DL1_BIT active (high). The LSB enables first bit transmitted or received, and MSB enables eighth bit transmitted or received. DL1_BIT has no effect when DL1_TS selects T1 F-bits. 0 = disable data link bit 1 = enable data link bit
0A6--DL1 Control (DL1_CTL)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 TDL1_RPT 3 DL1[1] 2 DL1[0] 1 TDL1_EN 0 RDL1_EN
TDL1_RPT
Circular Transmit Buffer Enable--Processor can fill the transmit FIFO [TDL1; addr 0AD] with up to 64 bytes (Pack6 or Pack8 bits/byte) of unformatted data to be sent repeatedly. While TDL1_RPT is active high, data written to TDL1 is held until the processor writes an end of message [TDL1_EOM; addr 0AC]. After TDL1_EOM is written, the transmitter waits for the beginning of the next output multiframe (based on the selected transmit framing mode) before sending the first byte of the circular buffer. Subsequent bytes are output in the selected time slot/overhead bits and will continue to wrap around (recirculate) from the buffer until the processor writes new buffer data and another TDL1_EOM. This allows the processor to send multiframe aligned data patterns in ESF, SF, SLC, FAS, MFAS or CAS overhead bits. 0 = normal transmit FIFO 1 = enable circular transmit buffer Data Link 1 Mode--Selects either HDLC-formatted (FCS or Non-FCS) transmit and receive data link message mode or unformatted (Pack8 or Pack6) message mode. During HDLC modes, the transmit/receive circuits perform zero insertion/removal after each occurrence of 5 consecutive ones contained in the message bits, FLAG (0x7E) character insertion/removal during idle channel conditions, and ABORT (0xFF) code insertion/detection upon errored channel conditions. Refer to ITU-T Recommendation Q.921 for complete details of the HDLC link-layer protocol. FCS mode automatically generates, inserts, and checks the 16-bit Frame Check Sequence (FCS) without passing FCS bits through transmit and receive FIFOs.
DL1[1: 0]
3-76
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
Non-FCS mode passes all message bits that exist between the opening and closing FLAG characters through the FIFOs, without generating or checking FCS bits. Non-FCS mode allows the processor to generate and check the entire contents of each HDLC frame. Unformatted data link modes provide transparent channel access in which every data link bit transmitted is supplied by the processor through TDL1 and each bit received is passed to the processor through RDL1 [addr 0A8]. Pack8 and Pack6 unformatted mode options select the number of bits per byte that are stored in transmit/receive FIFOs, eight or six bits, respectively. The only data processing performed during unformatted mode is the alignment of transmitted and received data bits with respect to the transmit/receive multiframe. 00 = FCS 01 = No FCS 10 = Pack8 11 = Pack6
TDL1_EN
Transmit Data Link 1 Enable--When enabled, transmitter begins to empty and to format the contents of the transmit data link FIFO for output during the selected time slot bits according to the selected DL1[1:0] mode. Also enables generation of transmitter data link interrupt events. 0 = disabled 1 = enable transmit data link Receive Data Link 1 Enable--When enabled, receiver begins to format data from the selected time slot bits and to fill the receive data link FIFO according to the selected DL1[1:0] mode. Also enables generation of receiver data link interrupt events. 0 = disabled 1 = enable receive data link
RDL1_EN
0A7--RDL #1 FIFO Fill Control (RDL1_FFC)
7 MSG_FILL[1] 6 MSG_FILL[0] 5 FFC[5] 4 FFC[4] 3 FFC[3] 2 FFC[2] 1 FFC[1] 0 FFC[0]
MSG_FILL[1:0]
Unformatted Message Fill Limit--Applicable only for Pack8 and Pack6 modes, the message fill limit selects how many receive FIFO locations [RDL1; addr 0A8] are filled before the receive data link generates an RFULL interrupt [ISR2; addr 009] and generates a corresponding RDL1 Partial message status word entry. Fill limit thus determines how many bytes constitute an unformatted message. Fill limits give the processor an alternative to using RNEAR interrupts to signal the end of a received unformatted message. Note the number of bits per unformatted message must divide evenly by the number of bits monitored per multiframe.
100054E
Conexant
3-77
3.0 Registers
3.15 Data Link Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
For example, SLC applications monitor Fs bits during even frames for a total of 36 bits monitored out of 72 frames. Using Pack6 mode, that group of 36 Fs bits from each SLC multiframe can be chosen to constitute one unformatted message by selecting a message fill limit which equals 6 bytes (of 6 bits/byte). In the SLC example, an RFULL interrupt would then be generated every 9 ms on each SLC multiframe boundary. Fill limits provided for T1 cases are multiples of 6 bytes (i.e. 6, 12 or 18 FIFO locations) to hold 1 or more multiframes worth of monitored data. In E1 mode, fill limits are multiples of 8 bytes to correspond with the 16 frame multiframe lengths (i.e. monitoring CRC4 in MFAS framing mode or TS16 in CAS framing mode).
T1/E1N X 0 0 0 1 1 1
FFC[5:0]
MSG_FILL[1:0] 00 01 10 11 01 10 11
Message Fill Limit Disabled 8 bytes 16 bytes 24 bytes 6 bytes 12 bytes 18 bytes
Near Full FIFO Threshold--Selects FIFO depth of near full interrupt [RNEAR; addr 009] and near full level status [RNEAR1; addr 0A9]. The RNEAR interrupt and RNEAR1 indicator are both activated when the number of empty FIFO locations equals the selected threshold. The threshold controls how many data and/or status bytes (64 minus threshold value) that the processor must read from RDL1 after RNEAR interrupt. This is done to clear the RNEAR1 indicator as well as to determine how much time remains (in bytes) for the processor to read RDL1 before the receive FIFO is full. If a receive message is in progress when the near full threshold is reached, the receiver issues a message interrupt [RMSG; addr 009] and places a Partial message in the receive FIFO.
FFC[5:0] 00 0000 00 0001 00 0010 | 11 1110 11 1111 none 1 empty FIFO location 2 empty FIFO locations | 62 empty FIFO locations 63 empty FIFO locations Empty @ RNEAR Filled @ RNEAR 64 = RFULL 63 filled 62 filled | 1 filled 0 filled = empty
3-78
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
0A8--Receive Data Link FIFO #1 (RDL1)
Two different read byte values are supplied: WORD0 equals message status, and WORD1 equals message data. The processor determines which byte value is located in the FIFO by first reading the receiver data link status [RDL1_STAT; addr 0A9]. In some cases, multiple consecutive status bytes may be placed in the FIFO, so the processor must always read RDL1_STAT before reading RDL1 to distinguish between WORD0 and WORD1 byte values. However, each time a non-zero byte count [RDL1_CNT] status is read, the processor is guaranteed the next RDL1_CNT reads from RDL1 will equal message data [WORD1] and not message status. Note that a status byte occupies 1 byte of FIFO space, just the same as a message data byte occupies 1 byte of FIFO space. WORD0: Message Status
7 EOM[1] 6 EOM[0] 5 RDL1_CNT[5] 4 RDL1_CNT[4] 3 RDL1_CNT[3] 2 RDL1_CNT[2] 1 RDL1_CNT[1] 0 RDL1_CNT[0]
EOM[1, 0]
End of Message--Receive data link reports an End of Message status for each occurrence of a complete (Good), a continued (Partial), an errored (FCS/Non-integer), or an aborted (Abort) message. Note that properly received unformatted messages are reported with a Partial end of message status. The processor responds to Good or Partial status by reading the indicated number of data bytes [RDL1_CNT] from RDL1. For abort or error cases, RDL1_CNT equals zero to indicate that all received data from that message was discarded. Note that a Good status with RDL1_CNT=0 is reported if the processor reads RDL1 while the receiver is in progress of filling the FIFO (in which case RDL1_STAT contains RSTAT1=1 and RMSG1=1). If an abort or error status with zero byte count is reported after the processor has already buffered a prior HDLC Partial message, that partial buffered processor data should be discarded. Abort status is reported if the receiver detects a string of 7 or more consecutive ones during an HDLC message. FCS error status is reported if FCS mode is enabled, and the checksum calculated over the received HDLC message does not match the received 16-bit FCS. Non-integer error status is reported if the receiver detects a closing FLAG character that yields an HDLC message length which is not an integer number of 8-bit octets. 00 = Good 01 = FCS/Non-integer 10 = Abort 11 = Partial Byte Count [5:0]--Indicates the number of Message Data [WORD1] bytes that are stored in subsequent consecutive FIFO locations, constituting one received message. The reported byte count is the actual number of bytes, in the range of 0 to 63 bytes, where 0 indicates zero bytes for the processor to read. The processor can either read the specified number of message data bytes consecutively from RDL1 or can poll RDL1_STAT after reading each data byte until RDL1_STAT reports an end of message (i.e. RMPTY1=1 or RSTAT1=1).
RDL1_CNT[5:0]
100054E
Conexant
3-79
3.0 Registers
3.15 Data Link Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
WORD1: Message Data
7 RDL1[7] 6 RDL1[6] 5 RDL1[5] 4 RDL1[4] 3 RDL1[3] 2 RDL1[2] 1 RDL1[1] 0 RDL1[0]
RDL1[7:0]
Receive Message Data--Filled by the receiver data link, from LSB to MSB, with bits from the selected channel. Processor reads 8-bit FIFO data during HDLC and Pack8 modes. During Pack6 mode, only the six least significant bits RDL1[5:0] are filled.
0A9--RDL #1 Status (RDL1_STAT)
7 -- 6 -- 5 -- 4 RMSG1 3 RSTAT1 2 RMPTY1 1 RNEAR1 0 RFULL1
RMSG1
In Progress Receive Message--Real time status of receive message sequencer is provided mostly for processor polled applications. During HDLC modes, RMSG1 is high for the interval between opening and closing FLAG characters to indicate the receiver is actively filling FIFO locations (in which case RSTAT1 is also held high). RMSG1 is low while the channel receives FLAG or Abort characters. During unformatted modes, RMSG1 is high continuously. 0 = channel idle 1 = channel actively filling FIFO Next FIFO Read Equals Message Status--For non-empty FIFO conditions (RMPTY1=0), RSTAT1 indicates the next byte read from RDL1 returns WORD0 message status or WORD1 message data. Note that RSTAT1 equals zero if the FIFO is empty and there is no message in progress. The processor polls RSTAT1 before reading RDL1 to determine how to interpret RDL1 read byte value or the processor checks RSTAT1 in response to RMSG interrupt [ISR2; addr 009]. 0 = RDL1 byte equals Message Data (or empty FIFO, if RMTPY1=1) 1 = RDL1 byte equals Message Status (if RMPTY1=0) Receive FIFO Empty--Indicates no data or status bytes are present in the receive data link FIFO. 0 = FIFO contains data or status as indicated by RSTAT1 1 = FIFO empty Receive FIFO Near Full--Indicates data link has filled receive FIFO to the near full threshold level specified in FFC[5:0]. Upon reaching the near full level, the receiver updates the message status byte [WORD0] placed on top of the FIFO and reports the current in progress message with a Partial end of message status. The processor must read those filled FIFO locations to clear RNEAR1 status indicator and to enable the next RNEAR interrupt. 0 = FIFO depth is below the near full level 1 = FIFO has been filled to the near full level
RSTAT1
RMPTY1
RNEAR1
3-80
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
RFULL1
3.0 Registers
3.15 Data Link Registers
Receive FIFO Full--Indicates data link has completely filled 64 byte locations in the receive FIFO. In all cases, RFULL1 is an error, indicating the processor didn't keep pace with the receiver and indicates one or more received messages were discarded after the FIFO became full. The FIFO may still contain one or more Good received messages, and the processor may still process all receive FIFO contents as usual. However, any message that was in progress when FIFO reached full is discarded and is also reported with Partial end of message status and a zero byte count (which distinguishes a full end of message status from a normal abort or error message status). 0 = FIFO is less than full 1 = FIFO has been completely filled
0AA--Performance Report Message (PRM)
7 AUTO_PRM 6 PRM_CR 5 PRM_R 4 PRM_U1 3 PRM_U2 2 PRM_SL 1 AUTO_SL 0 SEND_PRM
AUTO_PRM
Automatic PRM Insertion--AUTO_PRM instructs the data link transmitter to format and send a Performance Report Message on the selected transmit channel after each occurrence of the ONESEC interrupt. To meet PRM requirements specified in ANSI T1.403-1995, FCS mode [DL1_CTL; addr 0A6] and one second error count latching [LATCH_CNT; addr 046] must both be enabled. In addition, the data link channel must be selected to output on Facility Data Link (FDL) framing bits [DL1_TS=0x40; addr 0A4]. Octets 1-14 of the transmit PRM message contents are automatically encoded as shown in Table A-5, Performance Report Message Structure. The encodings are based on the number of received CRC, FPS, LCV SEF , and FRED errors [addr 050-05A]. RFSLIP errors [SSTAT; addr 0D9] are also automatically encoded if AUTO_SL (described below) is enabled. The remaining PRM message contents typically remain fixed and are supplied by the processor from other bits that follow in the PRM register. Note that BOP priority codeword transmissions are interrupted by AUTO_PRM if TDL1 is granted output priority [TBOP_MODE=11; addr 0A0]. Note also that AUTO_PRM messages take up no space in the transmit data link FIFO, but are inserted on the transmit channel only after the FIFO is empty. Therefore, if the processor needs to transmit another type of FDL message between PRM messages, the processor must write that message after AUTO_PRM has begun sending (i.e. after ONESEC interrupt). 0 = no automatic PRM 1 = send PRM automatically every ONESEC Transmit CR Message Bit--The processor writes the selected C/R bit value to send in each PRM. Transmit R Message Bit--The processor writes the selected R bit value to send in each PRM. Transmit U1 Message Bit--The processor writes the selected U1 bit value to send in each PRM. Transmit U2 Message Bit--The processor writes the selected U2 bit value to send in each PRM. Transmit SL Message Bit--The processor writes the selected SL bit value to send in each PRM.
PRM_CR
PRM_R PRM_U1
PRM_U2
PRM_SL
100054E
Conexant
3-81
3.0 Registers
3.15 Data Link Registers
AUTO_SL
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Automatic SL Bit Insertion--RFSLIP error status is encoded into the transmit PRM contents. Or, the PRM_SL bit value supplied by the processor is sent. 0 = send PRM_SL value in SL bit 1 = send RFSLIP error status in SL bit Immediately Generate and Send PRM--Similar to AUTO_PRM mode, SEND_PRM instructs the data link transmitter to format and send a Performance Report Message according to ANSI T1.403-1995. But SEND_PRM executes immediately rather than waiting for ONESEC interrupt. Thus SEND_PRM gives processor control over PRM transmit timing. This is easier for the processor to manage if other FDL message types must also be transmitted.
SEND_PRM
0AB--TDL #1 FIFO Empty Control (TDL1_FEC)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 FEC[5] 4 FEC[4] 3 FEC[3] 2 FEC[2] 1 FEC[1] 0 FEC[0]
FEC[5:0]
Near Empty Transmit FIFO Threshold--Selects FIFO depth of near empty interrupt [TNEAR; addr 009] and near empty level status [TNEAR1; addr 0AE]. The TNEAR interrupt is activated when the number of data bytes remaining to be transmitted from the FIFO falls below the selected threshold. The TNEAR1 indicator is active as long as the number of processor filled FIFO locations is below the selected threshold. Thus TNEAR1 is active high when the transmit FIFO is completely empty and remains active until the processor writes the selected threshold number of bytes to TDL1 [addr 0AD]. Assuming the processor writes 64 bytes to completely fill an empty FIFO, then a TNEAR interrupt occurs after the transmitter has sent the number of bytes required to bring the FIFO level back down below the selected threshold. Hence, the processor can consecutively write 64 - FEC[5:0] number of bytes to the transmit FIFO in response to a TNEAR interrupt. The interrupt also signifies how much time remains (in bytes) for the processor to write TDL1 before transmit FIFO is emptied. Typically, FEC[5:0] is set to a small value (below 10 byte threshold) to minimize the number of TNEAR interrupts and maximize the time between TNEAR interrupts.
FEC[5:0] 00 0000 00 0001 00 0010 | 11 1110 11 1111 Byte threshold @ TNEAR Disabled 1 byte threshold 2 byte threshold | 62 byte threshold 63 byte threshold Empty @ TNEAR Disabled 63 empty 62 empty | 2 empty 1 empty
3-82
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
0AC--TDL #1 End Of Message Control (TDL1_EOM)
Unused bits are reserved and should be written to 0.
7 EOM[7] 6 EOM[6] 5 EOM[5] 4 EOM[4] 3 EOM[3] 2 EOM[2] 1 EOM[1] 0 EOM[0]
TDL1_EOM
End of Transmit Message. Writing any data value to TDL1_EOM marks the last byte of data written into the transmit FIFO as the end of an HDLC message (FCS or Non-FCS mode) or marks the end of a transmit circular buffer. Processor must write TDL1_EOM after writing a complete message or the last byte of a circular buffer into TDL1 [addr 0AD]. The written data value is ignored and cannot be read back. Multiple HDLC messages are allowed to be queued in the transmit FIFO simultaneously. In addition, the transition from one circular buffer to another occurs only after the end of message byte of the current circular buffer has been sent.
0AD--Transmit Data Link FIFO #1 (TDL1)
7 TDL1[7] 6 TDL1[6] 5 TDL1[5] 4 TDL1[4] 3 TDL1[3] 2 TDL1[2] 1 TDL1[1] 0 TDL1[0]
TDL1[7:0]
Transmit Message Data--Output by the transmitter data link, from LSB to MSB, and sent on the selected time slot bits. Processor writes 8-bit FIFO data during HDLC and Pack8 modes. During Pack6 mode, only the six least significant bits TDL1[5:0] are used.
0AE--TDL #1 Status (TDL1_STAT)
7 -- 6 -- 5 -- 4 -- 3 TMSG1 2 TMPTY1 1 TNEAR1 0 TFULL1
TMSG1
In Progress Transmit Message--The real time status of the transmit message sequencer is provided mostly for diagnostic purposes. During HDLC modes, TMSG1 is high for the interval between opening and closing FLAG characters. This indicates that transmitter is actively pulling data bytes from transmit FIFO locations. TMSG1 is low while the channel transmits FLAG or Abort characters. During unformatted and circular buffer modes, TMSG1 is high continuously. 0 = channel idle 1 = channel actively emptying FIFO
100054E
Conexant
3-83
3.0 Registers
3.15 Data Link Registers
TMPTY1
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Transmit FIFO Empty--Indicates no message data is present in transmit data link FIFO. This is typically checked by the processor in response to a TMSG or TNEAR interrupt. If this is a TMSG interrupt, the processor checks TMPTY1 to determine that all queued messages were sent (TMPTY1=1) or more queued messages remain to be sent (TMPTY1=0). If this is a TNEAR interrupt, the processor confirms TMPTY1=0 to verify the partial transmit message was not aborted by a FIFO underrun. 0 = FIFO contains data to be transmitted 1 = FIFO empty Transmit FIFO Near Empty--Indicates data link has emptied transmit FIFO to below the near empty threshold specified in FEC[5:0]. After sending the byte that occupied the near empty FIFO threshold level, TNEAR1 goes active high, which generates a TNEAR interrupt. The processor must write data to TDL1 to fill the transmit FIFO beyond the near empty threshold in order to clear TNEAR1 status and enable the next TNEAR interrupt event. 0 = FIFO depth is below the near empty level 1 = FIFO has been emptied past the near empty level Transmit FIFO Full--Indicates processor has completely filled 64 byte locations in transmit FIFO. While TFULL1 remains active, any subsequent processor writes to TDL1 are ignored. If the processor should inadvertently write to TDL1 while TFULL1 is active, the processor must allow FIFO to become completely empty without writing to TDL1_EOM in order to force the transmitter to send an Abort character. 0 = FIFO is less than full 1 = FIFO has been completely filled
TNEAR1
TFULL1
0AF--DL2 Time Slot Enable (DL2_TS)
7 DL2_TS[7] 6 DL2_TS[6] 5 DL2_TS[5] 4 DL2_TS[4] 3 DL2_TS[3] 2 DL2_TS[2] 1 DL2_TS[1] 0 DL2_TS[0]
DL2_TS[7] DL2_TS[6, 5]
Unchannelized--Test mode only; all time slots selected. Zero for normal operation. Frame Select--Transmit and receive data link 2 operates on data only during the specified T1/E1 frames. Frame select options give the processor access to different types of data link channels, as well as overhead channels. Overhead bit insertion is performed after TDL2, so internal transmitter overhead insertion must be bypassed [TFRM; addr 072] before the processor supplied overhead can be output from TDL2. 00 = all frames 01 = even frames only 10 = odd frames only 11 = Not valid
3-84
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
DL2_TS[4:0]
3.0 Registers
3.15 Data Link Registers
Time Slot Word Enable--Transmit and receive data link 2 operates on data only during the specified time slot. During T1 mode, selecting time slot zero enables data link operation on the F-bit positions.
DL2_TS[4:0] 00000 00001 | 11110 11111 Time Slot Enable F-bit (T1) or TS0 (E1) TS1 | TS30 TS31
0B0--DL2 Bit Enable (DL2_BIT)
7 DL2_BIT[7] 6 DL2_BIT[6] 5 DL2_BIT[5] 4 DL2_BIT[4] 3 DL2_BIT[3] 2 DL2_BIT[2] 1 DL2_BIT[1] 0 DL2_BIT[0]
DL2_BIT[7:0]
DL2 Bit Select--Works in conjunction with DL2_TS [addr 0AF] to select one or more time slot bits for data link input and output. Any combination of bits may be enabled by writing the corresponding DL2_BIT active (high). The LSB enables the first bit transmitted or received, and MSB enables eighth bit transmitted or received. DL2_BIT has no effect when DL2_TS selects T1 F-bits. 0 = disable data link bit 1 = enable data link bit
0B1--DL2 Control (DL2_CTL)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 TDL2_RPT 3 DL2[1] 2 DL2[0] 1 TDL2_EN 0 RDL2_EN
TDL2_RPT
Circular Transmit Buffer Enable--Processor can fill transmit FIFO [TDL2; addr 0B8] with up to 64 bytes (Pack6 or Pack8 bits/byte) of unformatted data to be sent repeatedly. While TDL2_RPT is active high, data written to TDL2 is held until the processor writes an end of message [TDL2_EOM; addr 0B7]. After TDL2_EOM is written, the transmitter waits for the beginning of the next output multiframe (based on the selected transmit framing mode) before sending the first byte of the circular buffer. Subsequent bytes are output in the selected time slot/overhead bits and will continue to wrap around (recirculate) from the buffer until the processor writes new buffer data and another TDL2_EOM. This allows the processor to send multiframe aligned data patterns in ESF, SF, SLC, FAS, MFAS, or CAS overhead bits. 0 = normal transmit FIFO 1 = enable circular transmit buffer
100054E
Conexant
3-85
3.0 Registers
3.15 Data Link Registers
DL2[1: 0]
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Data Link 2 Mode--Selects either HDLC formatted (FCS or Non-FCS) transmit and receive data link message mode or unformatted (Pack8 or Pack6) message mode. During HDLC modes, the transmit/receive circuits perform zero insertion/removal after each occurrence of 5 consecutive ones contained in the message bits. These include FLAG (0x7E) character insertion/removal during idle channel conditions and ABORT (0xFF) code insertion/detection upon errored channel conditions. Refer to ITU-T Recommendation Q.921 for complete details of the HDLC link-layer protocol. FCS mode automatically generates, inserts, and checks the 16-bit Frame Check Sequence (FCS) without passing FCS bits through transmit and receive FIFOs. While Non-FCS mode passes all message bits that exist between the opening and closing FLAG characters through the FIFOs, without generating or checking FCS bits. Non-FCS mode allows the processor to generate and check the entire contents of each HDLC frame. Unformatted data link modes provide transparent channel access in which every data link bit transmitted is supplied by the processor through TDL1, and each bit received is passed to the processor through RDL2 [addr 0B3]. Pack8 and Pack6 unformatted mode options select the number of bits per byte that are stored in transmit/receive FIFOs, eight or six bits, respectively. The only data processing performed during unformatted mode is the alignment of transmitted and received data bits with respect to the transmit/receive multiframe. 00 = FCS 01 = No FCS 10 = Pack8 11 = Pack6 Transmit Data Link 2 Enable--When enabled, the transmitter begins to empty and to format the contents of the transmit data link FIFO for output during the selected time slot bits according to the selected DL2[1:0] mode. Also enables generation of transmitter data link interrupt events. 0 = disabled 1 = enable transmit data link Receive Data Link 2 Enable--When enabled, the receiver begins to format data from the selected time slot bits and to fill the receive data link FIFO according to the selected DL2[1:0] mode. Also enables generation of receiver data link interrupt events. 0 = disabled 1 = enable receive data link
TDL2_EN
RDL2_EN
3-86
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
0B2--RDL #2 FIFO Fill Control (RDL2_FFC)
7 MSG_FILL[1] 6 MSG_FILL[0] 5 FFC[5] 4 FFC[4] 3 FFC[3] 2 FFC[2] 1 FFC[1] 0 FFC[0]
MSG_FILL[1:0]
Unformatted Message Fill Limit--This is applicable only for Pack8 and Pack6 modes. The message fill limit selects how many receive FIFO locations [RDL2; addr 0B3] are filled before the receive data link generates an RFULL interrupt [ISR1; addr 00A] and a corresponding RDL2 Partial message status word entry. Fill limit thus determines how many bytes constitute an unformatted message. The fill limits give the processor an alternative to using RNEAR interrupts to signal the end of a received unformatted message. The number of bits per unformatted message must divide evenly by the number of bits monitored per multiframe. For example, SLC applications monitor Fs bits during even frames for a total of 36 bits monitored out of 72 frames. Using Pack6 mode, the group of 36 Fs bits from each SLC multiframe can be chosen to constitute one unformatted message. This is accomplished by selecting a message fill limit which equals 6 bytes (of 6 bits/byte). In the SLC example, an RFULL interrupt would then be generated every 9 ms on each SLC multiframe boundary. Fill limits provided for T1 cases are multiples of 6 bytes (i.e. 6, 12 or 18 FIFO locations) to hold one or more multiframes worth of monitored data. In E1 mode, fill limits are multiples of 8 bytes to correspond with the 16-frame multiframe lengths (i.e. monitoring CRC4 in MFAS framing mode or TS16 in CAS framing mode).
T1/E1N X 0 0 0 1 1 1 MSG_FILL[1:0] 00 01 10 11 01 10 11 Message Fill Limit Disabled 8 bytes 16 bytes 24 bytes 6 bytes 12 bytes 18 bytes
FFC[5:0]
Near Full FIFO Threshold--Selects FIFO depth of near full interrupt [RNEAR; addr 00A] and near full level status [RNEAR2; addr 0B4]. The RNEAR interrupt and RNEAR2 indicator are both activated when the number of empty FIFO locations equals the selected threshold. The threshold controls how many data and/or status bytes (64 minus threshold value) the processor must read from RDL2 after RNEAR interrupt to clear the RNEAR2 indicator as well as how much time remains (in bytes) for the processor to read RDL2 before receive FIFO is full. If a receive message is in progress when the near full threshold is reached, the receiver issues a message interrupt [RMSG; addr 00A] and places a Partial message in the receive FIFO.
FFC[5:0] 00 0000 00 0001 00 0010 | 11 1110 11 1111 Empty @ RNEAR None 1 empty FIFO location 2 empty FIFO locations | 62 empty FIFO locations 63 empty FIFO locations Filled @ RNEAR 64 = RFULL 63 filled 62 filled | 1 filled 0 filled = empty
100054E
Conexant
3-87
3.0 Registers
3.15 Data Link Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0B3--Receive Data Link FIFO #2 (RDL2)
Two different read byte values are supplied: WORD0 equals message status, and WORD1 equals message data. The processor determines which byte value is located in the FIFO by first reading the receiver data link status [RDL2_STAT; addr 0B4]. In some cases, multiple consecutive status bytes may be placed in the FIFO. Thus, the processor must always read RDL2_STAT before reading RDL2 to distinguish between WORD0 and WORD1 byte values. However, each time a non-zero byte count [RDL2_CNT] status is read, the processor is guaranteed the next RDL2_CNT reads from RDL2 will equal message data [WORD1] and not message status. A status byte occupies 1 byte of FIFO space, just the same as a message data byte occupies 1 byte of FIFO space. WORD0: Message Status
7 EOM[1] 6 EOM[0] 5 RDL2_CNT[5] 4 RDL2_CNT[4] 3 RDL2_CNT[3] 2 RDL2_CNT[2] 1 RDL2_CNT[1] 0 RDL2_CNT[0]
EOM[1, 0]
End of Message--The receive data link reports an End of Message status for each occurrence of a complete (Good), a continued (Partial), an errored (FCS/Non-integer), or an aborted (Abort) message. Note that properly received unformatted messages are reported with a Partial end of message status. The processor responds to Good or Partial status by reading the indicated number of data bytes [RDL2_CNT] from RDL2. For abort or error cases, RDL2_CNT equals zero to indicate all received data from that message was discarded. Note that a Good status with RDL2_CNT=0 is reported if the processor reads RDL2 while the receiver is in progress of filling the FIFO (in which case RDL2_STAT contains RSTAT2=1 and RMSG2=1). If an abort or error status with zero byte count is reported after the processor has already buffered a prior HDLC Partial message, that partial buffered processor data should be discarded. Abort status is reported if the receiver detects a string of 7 or more consecutive ones during an HDLC message. FCS error status is reported if FCS mode is enabled, and the checksum calculated over the received HDLC message does not match the received 16-bit FCS. Non-integer error status is reported if the receiver detects a closing FLAG character yielding an HDLC message length which is not an integer number of 8-bit octets. 00 = Good 01 = FCS/Non-integer 10 = Abort 11 = Partial Byte Count [5:0]--Indicates the number of Message Data [WORD1] bytes that are stored in subsequent consecutive FIFO locations, constituting one received message. The reported byte count is the actual number of bytes in the range of 0 to 63 bytes, where 0 indicates for the processor to read. The processor can either read the specified number of message data bytes consecutively from RDL2 or can poll RDL2_STAT after reading each data byte until RDL2_STAT reports an end of message (i.e. RMPTY2=1 or RSTAT2=1).
RDL2_CNT[5:0]
WORD1: Message Data
7 RDL2[7] 6 RDL2[6] 5 RDL2[5] 4 RDL2[4] 3 RDL2[3] 2 RDL2[2] 1 RDL2[1] 0 RDL2[0]
RDL2[7:0]
Receive Message Data--Filled by the receiver data link, from LSB to MSB, with bits from the selected channel. The processor reads 8-bit FIFO data during HDLC and Pack8 modes. During Pack6 mode, only the six least significant bits RDL2[5:0] are filled.
3-88
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
0B4--RDL #2 Status (RDL2_STAT)
7 -- 6 -- 5 -- 4 RMSG2 3 RSTAT2 2 RMPTY2 1 RNEAR2 0 RFULL2
RMSG2
In Progress Receive Message--The real-time status of the receive message sequencer is provided mostly for processor polled applications. During HDLC modes, RMSG2 is high for the interval between opening and closing FLAG characters to indicate the receiver is actively filling FIFO locations (in which case RSTAT2 is also held high). RMSG2 is low while the channel receives FLAG or Abort characters. During unformatted modes, RMSG2 is high continuously. 0 = channel idle 1 = channel actively filling FIFO Next FIFO Read Equals Message Status--For non-empty FIFO conditions (RMPTY2=0), RSTAT2 indicates that the next byte read from RDL2 will be WORD0 message status or WORD1 message data. Notice that RSTAT2 equals zero if the FIFO is empty, and there is no message in progress. Processor polls RSTAT2 before reading RDL2 to determine how to interpret RDL2 read byte value, or checks RSTAT2 in response to RMSG interrupt [ISR1; addr 00A]. 0 = RDL2 byte equals Message Data (or empty FIFO, if RMTPY2=1) 1 = RDL2 byte equals Message Status (if RMPTY2=0) Receive FIFO Empty--Indicates no data or status bytes are present in receive data link FIFO. 0 = FIFO contains data or status as indicated by RSTAT2 1 = FIFO empty Receive FIFO Near Full--Indicates the data link has filled receive FIFO to the near full threshold level specified in FFC[5:0]. Upon reaching the near full level, the receiver updates the message status byte [WORD0] placed on top of the FIFO and reports the current in progress message with a Partial end of message status. The processor must read those filled FIFO locations to clear RNEAR2 status indicator, and to enable the next RNEAR interrupt. 0 = FIFO depth is below the near full level 1 = FIFO has been filled to the near full level Receive FIFO Full--Indicates data link has completely filled 64 byte locations in the receive FIFO. In all cases, RFULL2 is an error, indicating the processor didn't keep pace with the receiver and indicates one or more received messages were discarded after the FIFO became full. The FIFO may still contain one or more Good received messages, and the processor may still process all receive FIFO contents as usual. However, any message that was in progress when FIFO reached full is discarded and is also reported with Partial end of message status and a zero byte count (which distinguishes a full end of message status from a normal abort or error message status). 0 = FIFO is less than full 1 = FIFO has been completely filled
RSTAT2
RMPTY2
RNEAR2
RFULL2
100054E
Conexant
3-89
3.0 Registers
3.15 Data Link Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0B6--TDL #2 FIFO Empty Control (TDL2_FEC)
7 -- 6 -- 5 FEC[5] 4 FEC[4] 3 FEC[3] 2 FEC[2] 1 FEC[1] 0 FEC[0]
FEC[5:0]
Near Empty Transmit FIFO Threshold--Selects a FIFO depth of near empty interrupt [TNEAR; addr 00A] and near empty level status [TNEAR2; addr 0B9]. The TNEAR interrupt is activated when the number of data bytes remaining to be transmitted from the FIFO falls below the selected threshold. The TNEAR2 indicator is active as long as the number of processor filled FIFO locations is below the selected threshold. Thus, TNEAR2 is active high when the transmit FIFO is completely empty and remains active until the processor writes the selected threshold number of bytes to TDL2 [addr 0B8]. Assuming the processor writes 64 bytes to completely fill an empty FIFO, TNEAR interrupt occurs after the transmitter has sent the number of bytes required to bring the FIFO level back down below the selected threshold. Hence, the processor is guaranteed to be able to consecutively write 64 - FEC[5:0] number of bytes to the transmit FIFO in response to a TNEAR interrupt. The interrupt also signifies how much time remains (in bytes) for the processor to write TDL2 before transmit FIFO is emptied. Typically, FEC[5:0] is set to a small value (approximately 5-10 byte threshold) to minimize the number of TNEAR interrupts and maximize the time between TNEAR interrupts.
FEC[5:0] 00 0000 00 0001 00 0010 | 11 1110 11 1111 Byte Threshold @ TNEAR Disabled 1 byte threshold 2 byte threshold | 62 byte threshold 63 byte threshold Empty @ TNEAR Disabled 63 empty 62 empty | 2 empty 1 empty
0B7--TDL #2 End Of Message Control (TDL2_EOM)
7 EOM[7] 6 EOM[6] 5 EOM[5] 4 EOM[4] 3 EOM[3] 2 EOM[2] 1 EOM[1] 0 EOM[0]
TDL2_EOM
End of Transmit Message. Writing any data value to TDL2_EOM marks the last byte of data written into the transmit FIFO as the end of an HDLC message (FCS or Non-FCS mode) or the end of a transmit circular buffer. The processor must write TDL2_EOM after writing a complete message or the last byte of a circular buffer into TDL2 [addr 0B8]. The written data value is ignored and cannot be read back. Multiple HDLC messages are allowed to be queued in the transmit FIFO simultaneously. In addition, the transition from one circular buffer to another occurs only after the end of message byte of the current circular buffer has been sent.
3-90
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
0B8--Transmit Data Link FIFO #2 (TDL2)
7 TDL2[7] 6 TDL2[6] 5 TDL2[5] 4 TDL2[4] 3 TDL2[3] 2 TDL2[2] 1 TDL2[1] 0 TDL2[0]
TDL2[7:0]
Transmit Message Data--Output by the transmitter data link from LSB to MSB and sent on the selected time slot bits. Processor writes 8-bit FIFO data during HDLC and Pack8 modes. During Pack6 mode, only the six least significant bits, TDL2[5:0], are used.
0B9--TDL #2 Status (TDL2_STAT)
7 -- 6 -- 5 -- 4 -- 3 TMSG2 2 TMPTY2 1 TNEAR2 0 TFULL2
TMSG2
In Progress Transmit Message--The real time status of the transmit message sequencer is provided mostly for diagnostic purposes. During HDLC modes, TMSG2 is high for the interval between the opening and closing FLAG characters to indicate the transmitter is actively pulling data bytes from transmit FIFO locations. TMSG2 is low while the channel transmits FLAG or Abort characters. During unformatted and circular buffer modes, TMSG2 is continuously high. 0 = channel idle 1 = channel actively emptying FIFO Transmit FIFO Empty--Indicates that no message data is present in the transmit data link FIFO. This is typically checked by processor in response to a TMSG or TNEAR interrupt. If this is a TMSG interrupt, the processor checks TMPTY2 to determine that all queued messages were sent (TMPTY2=1) or more queued messages remain to be sent (TMPTY2=0). If this is a TNEAR interrupt, the processor confirms TMPTY2=0 to verify the partial transmit message was not aborted by a FIFO underrun. 0 = FIFO contains data to be transmitted 1 = FIFO empty Transmit FIFO Near Empty--Indicates data link has emptied transmit FIFO to below the near empty threshold specified in FEC[5:0]. After sending the byte that occupied the near empty FIFO threshold level, TNEAR2 goes active high, which generates a TNEAR interrupt. The processor must write data to TDL2 to fill the transmit FIFO beyond the near empty threshold. This is done in order to clear TNEAR2 status and enable the next TNEAR interrupt event. 0 = FIFO depth is below the near empty level 1 = FIFO has been emptied past the near empty level Transmit FIFO Full--Indicates processor has completely filled 64 byte locations in transmit FIFO. While TFULL2 remains active, any subsequent processor writes to TDL2 are ignored. If the processor should inadvertantly write to TDL2 while TFULL2 is active, the processor must allow FIFO to become completely empty without writing to TDL2_EOM, in order to force the transmitter to send an Abort character. 0 = FIFO is less than full 1 = FIFO has been completely filled
TMPTY2
TNEAR2
TFULL2
100054E
Conexant
3-91
3.0 Registers
3.15 Data Link Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0BA--DLINK Test Configuration (DL_TEST1)
Data link test registers [addr 0BA-0BE] are for Conexant production test. Set to zero for normal operation. Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 DL_TEST1[3] 2 DL_TEST1[2] 1 DL_TEST1[1] 0 DL_TEST1[0]
DL_TEST1[3]
Clock Test--Zero for normal operation, where clocks controlled by DL1_CTL and DL2_CTL [addr 0A6, 0B1]. When active high, clocks are always enabled. Shadow Select--Report shadow pointers instead of normal read/write pointers. FIFO Select: 00 = RDL1; 01 = RDL2; 10 = TDL1; 11 = TDL2
DL_TEST1[2] DL_TEST1[1, 0]
0BB--DLINK Test Status (DL_TEST2)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 DL_TEST2[5] 4 DL_TEST2[4] 3 DL_TEST2[3] 2 DL_TEST2[2] 1 DL_TEST2[1] 0 DL_TEST2[0]
DL_TEST2[5:0]
Read or Shadow Read Pointer--Reports selected FIFO read pointer current address.
0BC--DLINK Test Status (DL_TEST3)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 DL_TEST3[5] 4 DL_TEST3[4] 3 DL_TEST3[3] 2 DL_TEST3[2] 1 DL_TEST3[1] 0 DL_TEST3[0]
DL_TEST3[5:0]
Write or Shadow Write Pointer--Specifies selected FIFO write pointer address.
0BD--DLINK Test Control #1 or Configuration #2 (DL_TEST4)
7 -- 6 DL_TEST4[6] 5 DL_TEST4[5] 4 DL_TEST4[4] 3 DL_TEST4[3] 2 DL_TEST4[2] 1 DL_TEST4[1] 0 DL_TEST4[0]
DL_TEST4[6] DL_TEST4[5] DL_TEST4[4] DL_TEST4[3] DL_TEST4[2] DL_TEST4[1] DL_TEST4[0]
TFIFO1 Read Clear--Force transmit FIFO read pointer to empty. TFIFO1 Write Clear--Force transmit FIFO write pointer to empty. TFIFO1 Write--MPU data goes to specified write pointer address. RFIFO1 Read Clear--Force receive FIFO read pointer to empty state (flush). RFIFO1 Write Clear--Force receive FIFO write pointer to empty state (flush). RFIFO1 Write--MPU data goes to specified write pointer address. RFIFO1 Bypass--Pipe receive data.
3-92
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.15 Data Link Registers
0BE--DLINK Test Control #2 or Configuration #2 (DL_TEST5)
Unused bits are reserved and should be written to 0.
7 -- 6 DL_TEST5[6] 5 DL_TEST5[5] 4 DL_TEST5[4] 3 DL_TEST5[3] 2 DL_TEST5[2] 1 DL_TEST5[1] 0 DL_TEST5[0]
DL_TEST5[6] DL_TEST5[5] DL_TEST5[4] DL_TEST5[3] DL_TEST5[2] DL_TEST5[1] DL_TEST5[0]
TFIFO2 Read Clear--Force transmit FIFO read pointer to empty. TFIFO2 Write Clear--Force transmit FIFO write pointer to empty. TFIFO2 Write--MPU data goes to specified write pointer address. RFIFO2 Read Clear--Force receive FIFO read pointer to empty state (flush). RFIFO2 Write Clear--Force receive FIFO write pointer to empty state (flush). RFIFO2 Write--MPU data goes to specified write pointer address. RFIFO2 Bypass--Pipe receive data.
100054E
Conexant
3-93
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.16 System Bus Registers
0D0--System Bus Interface Configuration (SBI_CR)
7 X2CLK 6 SBI_OE 5 EMF 4 EMBED 3 SBI[3] 2 SBI[2] 1 SBI[1] 0 SBI[0]
X2CLK
Enable Times 2 Clocks--X2CLK modifies the number of RSB/TSB clock cycles used to clock a single data bit onto RSB and TSB. When X2CLK is active, two RSBCKI/TSBCKI clock cycles occur for each RPCMO, RSIGO, SIGFRZ, TPCMI, and TSIGI bit. But the FSYNC and MSYNC signals remain at the full 1x RSBCKI/TSBCKI clock rate. 0 = RSB/TSB signals at RSBCKI/TSBCKI 1 = Two SBCKI clock cycles per SBI bit (except FSYNC and MSYNC). Enable System Bus Outputs--Places RPCMO, RSIGO, RINDO, and SIGFRZ output buffers under the control of the RSB timebase. SBI_OE also places the TINDO output buffer under the control of TSB timebase. Inactive (low) forces SBI output buffers to a high-impedance state. Power on and RESET [addr 001] force SBI_OE to an inactive state to avoid bus contention on devices sharing system bus connections. 0 = SBI outputs forced to high-impedance state 1 = SBI outputs controlled by respective RSB or TSB timebase Embedded Framing--During T1 mode, EMF controls placement of T1 framing bits on RPCMO and sampling of T1 framing bits from TPCMI according to the selected embedded framing format. EMF supports system buses that carry T1 frames but operate above T1 line rate. EMF allows the system bus to transport and maintain 193-bit frame integrity as T1 data is passed through RSLIP and/or TSLIP buffers. 0 = G.802 embedded format 1 = Reserved embedded format EMBED instructs the transmit framer (refer to [TABORT; addr 071]) to align the TX timebase with respect to the frame and multiframe alignment embedded in the transmit line rate data output from TSLIP (TXDATA). EMBED is required during applications that bypass frame formatter [TFRM; addr 072] or Sa-bits [TMAN; addr 074]. If TSLIP is enabled, EMBED is inactive, and overhead is bypassed, TX timebase is not guaranteed to align to TXDATA, and bypassed overhead cannot reliably pass through TSLIP. EMBED is applicable to all system bus modes.
EMBED 0 1 1 T1/E1N X 0 1 Embedded Framing Mode Transmit framer searches TPCMI TS0 embedded; search TXDATA G.802 embedded; search TXDATA
SBI_OE
EMF
EMBED
NOTE(S): Embedded F-bits reach TX output only if frame formatter [TFRM; addr 072]
is in bypass or transparent mode.
3-94
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.16 System Bus Registers
SBI[3:0]
The offline framer examines TXDATA to align TX timebase to the embedded FAS pattern. If MFAS is also enabled [TFRAME; addr 070], transmit online framer examines TXDATA to align TX timebase to the embedded MFAS pattern. While EMBED is active, TXDATA output is monitored, and transmit frame errors are reported in ISR0 [addr 00B]. Embedded TS0 supports E1 overhead bypass options for applications where TSLIP buffer is enabled. G.802 Embedded Automatically supports ITU-T Recommendation G.802, which defines frame format conversion between T1 and E1 line rates. This is accomplished by locating T1 F-bits in Bit 1 of Time Slot 26 of each system bus frame. G.802 embedded mode is applicable for system buses that are 1x, 2x, or 4x multiples of E1 line rate. Full implementation of G.802 also requires the processor to program TS0, TS16, and TS26-TS31 as unassigned system bus time slots [SBCn; addr 0E0-0FF]. System Bus Interface Mode--Defines transmit and receive system bus data format. System buses operate in one of nine basic formats which differ in the number of total available data time slots and the associated system bus clock rate. If the total time slots are a multiple of 32, SBI also defines which bus group of 32 byte-interleaved time slots are assigned to the respective device.
SBI[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 Mode 128A 128B 128C 128D 64A 64B 32 24+F 24 Clock (Kbps) 8192 8192 8192 8192 4096 4096 2048 1544 1536 Total Time Slots 128 128 128 128 64 64 32 24 + F-bit 24 Bus Group Group 0 Group 1 Group 2 Group 3 Group 0 Group 1 -- -- --
TS0 Embedded
100054E
Conexant
3-95
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0D1--Receive System Bus Configuration (RSB_CR)
7 BUS_RSB 6 SIG_OFF 5 RPCM_NEG 4 RSYN_NEG 3 BUS_FRZ 2 RSB_CTR 1 RSBI[1] 0 RSBI[0]
BUS_RSB
Enable Bussed RSB Outputs--Applicable only if the system bus outputs are controlled by SBI timebases [SBI_OE = 1; addr 0D0]. When BUS_RSB is active, RPCMO, RSIGO, and RINDO outputs from multiple devices are allowed to share common receive system bus connections. Unused time slots are three-stated during those bus groups that are not selected by SBI mode [addr 0D0]. Otherwise, unused time slots repeat their output data value for all bus groups. 0 = RSB time slot value repeated for all bus groups 1 = three-state RSB outputs during unused bus groups Inhibit RPCMO Signaling Reinsertion--Disables insertion of ABCD signaling for all time slots on the receive system bus PCM output (RPCMO). Otherwise, ABCD signaling is reinserted on RPCMO as controlled by System Bus Per-Channel [SBCn; addr 0E0-0FF] and RX Per-Channel [RPCn; addr 180-19F] controls. 0 = enable insertion of signaling onto RPCMO 1 = inhibit RPCMO signaling Output Data on Falling Edge Clock--Selects RSBCKI rising or falling edge clock signal to output RPCMO, RSIGO, RINDO, and SIGFRZ. 0 = RSB rising edge outputs 1 = RSB falling edge outputs Output Sync on Falling Edge Clock--Selects RSBCKI rising or falling edge clock signal for RFSYNC or RMSYNC outputs. Opposite RSBCKI edge is used if RFSYNC or RMSYNC is programmed as an input. 0 = RFSYNC or RMSYNC rising edge output (falling edge input) 1 = RFSYNC or RMSYNC falling edge output (rising edge input) Enable Bused SIGFRZ Output--Enables SIGFRZ from multiple devices to share a common receive system bus connection. When active, SIGFRZ three-states during bus group time slots that are unused by the selected SBI mode [addr 0D0]. 0 = SIGFRZ repeats for all bus groups 1 = three-state SIGFRZ during unused bus groups Force RSLIP to Center--Writing a one to RSB_CTR forces RSLIP read buffer pointer to its initial delay condition. If RFSYNC or RMSYNC is programmed as an output, RSB_CTR consequently forces a change of system bus sync alignment. The processor must assert RSB_CTR after configuration of the receive slip buffer. Centering RSLIP does not effect RSLIP status reported in ISR.5 [addr 006]. 0 = no effect 1 = force RSLIP to center
SIG_OFF
RPCM_NEG
RSYN_NEG
BUS_FRZ
RSB_CTR
3-96
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
RSBI[1:0]
3.0 Registers
3.16 System Bus Registers
Receive Slip Buffer Interface Mode--Selects configuration of RSLIP buffer. RSBI determines the total buffer depth and initial delay conditions. While RSLIP is bypassed, RSB outputs and RSBCKI is ignored. RFSYNC and RMSYNC are also ignored in bypass mode if they are programmed as inputs.
RSBI 00 01 10 11 Mode Normal Short Elastic Bypass Total Depth 2 Frame 2 Frame 674 bits 0 bits Initial Delay 1 Frame 0.5 to 1.5 Frames 32 bits 32 bits 0 bits Conditions When RFSYNC is output When RFSYNC is input Reverts to normal upon slip Recenters automatically upon slip RSBCKI ignored
0D2--RSB Sync Bit Offset (RSYNC_BIT)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 -- 2 OFFSET[2] 1 OFFSET[1] 0 OFFSET[0]
OFFSET[2:0]
RSB Sync Bit Offset--Selects which RSB bit number coincides with RFSYNC and RMSYNC sync pulses. Sync pulses are programmed to align to one bit in relation to RPCMO, RSIGO, RINDO, and SIGFRZ time slots. If the sync pulses are desired to coincide with location of T1 F-bit or time slot zero Bit 1, then OFFSET is programmed to equal zero. Sync bit offset is added to time slot offset [RSYNC_TS; addr 0D3] to form a 10-bit OFFSET value. This value applies to RFSYNC location, which is then added to frame offset [RSYNC_FRM; addr 0D8] to form a 15-bit OFFSET value that applies to RMSYNC location. Both RFSYNC and RMSYNC offsets are expressed as RSB.OFFSET, allowing the system to generate or accept sync pulses at any bit location within the RSB multiframe.
OFFSET[2:0] 000 001 | 110 111 RSYNC Location Bit 1 or F-bit Bit 2 | Bit 7 Bit 8
100054E
Conexant
3-97
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0D3--RSB Sync Time Slot Offset (RSYNC_TS)
Unused bits are reserved and should be written to 0.
7 -- 6 OFFSET[9] 5 OFFSET[8] 4 OFFSET[7] 3 OFFSET[6] 2 OFFSET[5] 1 OFFSET[4] 0 OFFSET[3]
OFFSET[9:3]
RSB Sync Time Slot Offset--Selects which RSB time slot number coincides with RFSYNC and RMSYNC sync pulses, in the range of Time Slots 0-127. If the sync pulses coincide with location of T1 F-bit or TS0, then OFFSET is programmed to equal zero. Refer also to RSYNC_BIT and RSYNC_FRM [addr 0D2, 0D8].
2048, 1544, and 1536 Kbps/sec SBI Mode OFFSET[9:3] 0000000 0000001 | 0011110 0011111 4096 Kbps/sec SBI Mode OFFSET[9:4] 000000 000000 000001 000001 | 011110 011110 011111 011111 OFFSET[3] 0 1 0 1 | 0 1 0 1 RSYNC Time Slot 0 0 1 1 | 30 30 31 31 Group A B A B | A B A B RSYNC Time Slot 0 or F-bit 1 | 30 31
8192 Kbps/sec SBI Mode OFFSET[9:5] 00000 00000 00000 00000 00001 00001 00001 00001 | 11110 11110 11110 11110 OFFSET[4:3] 00 01 10 11 00 01 10 11 | 00 01 10 11 RSYNC Time Slot 0 0 0 0 1 1 1 1 | 30 30 30 30 Group A B C D A B C D | A B C D
3-98
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
8192 Kbps/sec SBI Mode OFFSET[9:5] 11111 11111 11111 11111 OFFSET[4:3] 00 01 10 11 RSYNC Time Slot 31 31 31 31 Group A B C D
3.0 Registers
3.16 System Bus Registers
NOTE(S): Offsets which are outside the RSB timebase range result in no pulses on
RFSYNC and RMSYNC outputs.
0D4--Transmit System Bus Configuration (TSB_CR)
7 BUS_TSB 6 TX_ALIGN 5 TPCM_NEG 4 TSYN_NEG 3 TSB_ALIGN 2 TSB_CTR 1 TSBI[1] 0 TSBI[0]
BUS_TSB
Enable Bused TSB Output--Applicable only if system bus outputs are controlled by SBI timebases [SBI_OE = 1; addr 0D0]. When BUS_TSB is active, TINDO outputs from multiple devices are allowed to share a common transmit system bus connection. Unused time slots are three-stated during those bus groups that are not selected by SBI mode [addr 0D0]. Otherwise, unused time slots repeat their TINDO value for all bus groups. 0 = TINDO repeated for all bus groups 1 = three-state TINDO during unused time slots Transmitter Output Multiframe Aligns to TSB Timebase--Allows multiframe alignment located at TSB (from TMSYNC or TFRAMER to pass across TSLIP buffer and force the corresponding multiframe alignment onto the transmitter timebase. Used primarily to pass TMSYNC from system bus. 0 = Transmitter multiframe does not follow TSB 1 = Transmitter multiframe follows TSB multiframe Output Data on Falling Edge Clock--Selects TSBCKI rising or falling edge clock signal to output TINDO and the opposite TSBCKI edge to sample TPCMI and TSIGI inputs. 0 = TINDO rising edge output (TPCMI and TSIGI falling edge inputs) 1 = TINDO falling edge outputs (TPCMI and TSIGI rising edge inputs) Output Sync on Falling Edge Clock--Selects TSBCKI rising or falling edge clock signal for TFSYNC or TMSYNC outputs. The opposite TSBCKI edge is used if TFSYNC or TMSYNC is programmed as input. 0 = TFSYNC or TMSYNC rising edge output (falling edge input) 1 = TFSYNC or TMSYNC falling edge output (rising edge input) Transmit System Bus Multiframe Aligns to Transmit Timebase--Allows multiframe alignment located at TX timebase to pass across TSLIP and force the corresponding multiframe alignment onto the TSB timebase. Used primarily to pass CAS or MFAS alignment located by the transmit online framer onto the TMSYNC output. 0 = TSB multiframe does not follow XMTR 1 = TSB multiframe aligned by XMTR
TX_ALIGN
TPCM_NEG
TSYN_NEG
TSB_ALIGN
100054E
Conexant
3-99
3.0 Registers
3.16 System Bus Registers
TSB_CTR
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Force TSLIP to Center--Writing a one to TSB_CTR forces TSLIP read buffer pointer to its initial delay condition. This can possibly force a change of transmit frame alignment if TSLIP is configured in Elastic or Bypass modes. Writing a zero has no effect. The processor must assert TSB_CTR after configuration of the transmit slip buffer. Afterwards, CX28398 automatically recenters TSLIP buffer according to the configured mode. Centering TSLIP does not effect TSLIP status reported in ISR5[addr 006]. 0 = no effect 1 = force TSLIP to center Transmit Slip Buffer Interface Mode--Selects the configuration of the TSLIP buffer. The TSBI determines the total buffer depth and initial delay conditions. While TSLIP is bypassed, TCKI clocks TSB input/output, and TSBCKI is ignored.
TSBI 00 01 10 11
NOTE(S):
TSBI[1:0]
Mode
Normal Short Elastic Bypass
Total Depth 2 Frame 2 Frame 64 Bits 0 Bits
Initial Delay 0.5 to 1.5 Frames 32 Bits 32 Bits 0 Bits
Conditions Dependent on present depth, no change of output frame. Reverts to normal upon slip Recenters automatically upon slip TSBCKI ignored
1. Bypass requires system bus equal to line rate. 2. Idle code and local signaling insertion apply to all modes.
0D5--TSB Sync Bit Offset (TSYNC_BIT)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 -- 2 OFFSET[2] 1 OFFSET[1] 0 OFFSET[0]
OFFSET[2:0]
TSB Sync Bit Offset--Selects which TSB bit number coincides with TFSYNC and TMSYNC sync pulses. Sync pulses are programmed to align to one bit in relation to TPCMI, TSIGI and TINDO time slots. If the sync pulses are desired to coincide with location of T1 F-bit or time slot zero Bit 1, then OFFSET is programmed to equal zero. Sync bit offset is added to time slot offset [TSYNC_TS; addr 0D6] to form a 10-bit OFFSET value. This value applies to TFSYNC and TMSYNC location. Both TFSYNC and TMSYNC offsets are expressed as TSB.OFFSET, allowing the system to generate or accept sync pulses at any bit location within the TSB frame.
OFFSET[2:0] 000 001 | 110 111 TSYNC Location Bit 1 or F-bit Bit 2 | Bit 7 Bit 8
3-100
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.16 System Bus Registers
0D6--TSB Sync Time Slot Offset (TSYNC_TS)
Unused bits are reserved and should be written to 0.
7 -- 6 OFFSET[9] 5 OFFSET[8] 4 OFFSET[7] 3 OFFSET[6] 2 OFFSET[5] 1 OFFSET[4] 0 OFFSET[3]
OFFSET[9:3]
TSB Sync Time Slot Offset--Selects which TSB time slot number coincides with TFSYNC and TMSYNC sync pulses, in the range of Time Slots 0 through 127. If the sync pulses coincide with location of T1 F-bit or TS0, then OFFSET is programmed to equal zero. Refer also to TSYNC_TS [addr 0D6].
2048, 1544, and 1536 Kbps/sec SBI Mode OFFSET[9:3] 0000000 0000001 | 0011110 0011111 TSYNC Time Slot 0 or F-bit 1 | 30 31 4096 Kbps/sec SBI Mode OFFSET[9:4] 000000 000000 000001 000001 | 011110 011110 011111 011111 OFFSET[3] 0 1 0 1 | 0 1 0 1 TSYNC Time Slot 0 0 1 1 | 30 30 31 31 Group A B A B | A B A B
8192 Kbps/sec SBI Mode OFFSET[9:5] 00000 00000 00000 00000 00001 00001 00001 00001 | 11110 OFFSET[4:3] 00 01 10 11 00 01 10 11 | 00 TSYNC Time Slot 0 0 0 0 1 1 1 1 | 30 Group A B C D A B C D | A
100054E
Conexant
3-101
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
8192 Kbps/sec SBI Mode OFFSET[9:5] 11110 11110 11110 11111 11111 11111 11111
TFSYNC and TMSYNC outputs.
OFFSET[4:3] 01 10 11 00 01 10 11
TSYNC Time Slot 30 30 30 31 31 31 31
Group B C D A B C D
NOTE(S): Offsets which are outside the TSB timebase range result in no pulses on
0D7--Receive Signaling Configuration (RSIG_CR)
7 -- 6 SET_RSIG 5 SET_SIG 4 UNICODE 3 DEBOUNCE 2 FRZ_OFF 1 FRZ_ON 0 THRU
SET_RSIG
Force 2 ms RSIG Interrupt--Allows the processor to receive an interrupt on RSIG [addr 008] at every CAS multiframe boundary. Applicable only to E1 mode with CAS enabled. Overrides STACK interrupt. 0 = RSIG interrupt on signaling STACK change 1 = RSIG interrupts every 2 ms at CAS multiframe Overwrite Robbed-Bit Signaling--Applicable only during T1 mode and function dependent on RIDLE. When RIDLE is inactive, SET_SIG forces received robbed-bit signaling to one before updating RSLIP time slot value. Therefore, bit 8 of each time slot received during signaling frames 6, 12, 18, and 24 is replaced with a one. This function is particularly useful in cross-connect and exchange systems that strip robbed-bit signaling or use different signaling frame alignment on inbound and outbound ports. 0 = no change to receive signaling 1 = replace robbed-bit signaling Inband Signaling Freeze (applicable to T1 modes only)--If UNICODE is enabled, received ABCD signaling on all channels is searched on a per-channel basis for the 4-bit UNICODE pattern. UNICODE pattern detection inhibits STACK. RSIG buffer updates for that channel as long as UNICODE is present, but does not affect SIGFRZ output and is not reported to the processor. This function is described in Bellcore TR-TSY-000303, Section 4.4.9, Revision 2, July 1989. 0 = no effect 1 = enable UNICODE detection and per-channel signaling freeze
SET_SIG
UNICODE
3-102
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
DEBOUNCE
3.0 Registers
3.16 System Bus Registers
Debounce Receive ABCD Signaling--Applicable only to those channels where signaling stack is enabled (SIG_STK; addr 180-19F). Output signaling buffer (RSIG) updates for these channels are evaluated after D-bit signaling is received. New signaling is placed into RSIG and STACK buffers only if the RSIG input and output values differ. DEBOUNCE filters single bit errors on ABCD signaling. This is accomplished by comparing incoming ABCD bits on a bit-by-bit basis with current buffered input and output ABCD bits and inverting the update signaling bit value when incoming and output bits are equal. However, these differ from the buffered input value below. At the end of each multiframe, the entire input ABCD value is copied to the output ABCD value. 0 = no effect 1 = debounce receive ABCD signaling
Sig Input 0 0 0 0 1 1 1 1 Current Bit I/O 00 01 10 11 00 01 10 11 Update Bit I/O 00 00 00 01 10 11 11 11 Debounce Change output -- Change output Debounce -- -- Notes --
NOTE(S): Normal (non-debounced) signaling always transfers ABCD input to ABCD output
buffer space coincident with the D-bit update.
FRZ_OFF/FRZ_ON
Manual Signaling Update and SIGFRZ Output--Allows the processor to manually control updates of the receive signaling buffer [RSIGn; addr 1A0-1BF], the signaling stack [addr 0DA], and the SIGFRZ output pin. FRZ_ON and FRZ_OFF control the SIGFRZ pin's output state, but do not affect normal operations of the SIGFRZ interrupt [ISR7; addr 004]. Receive ABCD input signaling is placed into STACK and RSIG buffers according to the modes shown below. Stack updates are individually enabled on a per-channel basis according to SIG_STK [addr 180-19F].
SIGFRZ FRZ_ON 0 0 0 X X 1 1 0 FRZ_OFF 0 0 0 SIG_STK 0 X 1 0 1 X Interrupt 0 1 0 X X X Pin 0 1 0 0 0 1 STACK No update No update ABCD Changes No Update ABCD Changes No update RSIGn All ABCD No update All ABCD All ABCD All ABCD No Update
100054E
Conexant
3-103
3.0 Registers
3.16 System Bus Registers
THRU
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Enable Transparent Robbed-Bit Signaling--RMSYNC is forced to align with respect to RX timebase and to follow each change of receiver's multiframe alignment, plus any frame offset caused by RSLIP buffer delay. In this manner, RMSYNC is able to retain its signaling multiframe alignment with respect to RPCMO output data frames. THRU mode is required when RSLIP is configured in bypass mode. It is also useful for ADPCM transcoder systems that utilize robbed-bit signaling during frames other than the normal (modulo 6) signaling frames and therefore cannot utilize RPCMO signaling reinsertion in ADPCM coded channels. During THRU mode, RMSYNC must be programmed as an output [PIO; addr 018]. RMSYNC can follow a change of RX multiframe alignment without generating an alarm indication (e.g., receiver change of SF alignment without accompanying loss of basic frame alignment). 0 = no effect 1 = transparent robbed-bit signaling
0D8--Signaling Reinsertion Frame Offset (RSYNC_FRM)
Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 OFFSET[14] 3 OFFSET[13] 2 OFFSET[12] 1 OFFSET[11] 0 OFFSET[10]
OFFSET[14:10]
RSB Sync Frame Offset--Selects which RSB frame number coincides with RMSYNC pulse in the range of frame 0-23. OFFSET specifies the frame in which RMSYNC is applied as an input or in which RMSYNC appears as an output, consequently locating RPCMO signaling frames used for T1 robbed-bit (frames 6,12,18, and 24) or E1 CAS signaling reinsertion. The only RPCMO channels affected are those with signaling insertion enabled [INSERT; addr 0E0-0FF].
T1/E1N 0 0 | 0 0 1 1 | 1 1 OFFSET[14:10] X0000 X0001 | X1110 X1111 00000 00001 | 10110 10111 RMSYNC Pulse RSB frame 0 RSB frame 1 | RSB frame 14 RSB frame 15 RSB frame 1 RSB frame 2 | RSB frame 23 RSB frame 24
3-104
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.16 System Bus Registers
0D9--Slip Buffer Status (SSTAT)
SSTAT[7:0] are updated at the start of each respective receive/transmit internal frame boundary (i.e. 125 s interval). Each bit in SSTAT is latched upon event detection and held until read cleared by the processor.
7 TSDIR 6 TFSLIP 5 TUSLIP 4 TDLY 3 RSDIR 2 RFSLIP 1 RUSLIP 0 RDLY
TSDIR
Transmit Slip Direction--TSDIR is updated each time a TSLIP error is latched in TFSLIP and TSDIR indicates which direction the slip occurred. 0 = TSLIP error deleted 1 frame on TX data output 1 = TSLIP error repeated 1 frame on TX data output Controlled TSLIP Event--TUSLIP and TFSLIP event status are latched active high when transmit slip error is detected. Either event reports a TSLIP error in ISR5 [addr 006]. Active high hold interval is defined by LATCH_ERR [addr 046]. Two types of errors are detected: FSLIP = Controlled frame slip on TX data output. FSLIP affects transmit time slot data, but does not change transmit timebase or frame alignment. 2. USLIP = Uncontrolled 1 to 256 bit slip on TX data. USLIP affects both time slot data and frame alignment. TUSLIP and TFSLIP status depends on transmit system bus configuration [TSB_CR; addr 0D4].
1.
TFSLIP
TSBI Mode Normal
TUSLIP 0 0 1 1
TFSLIP 0 1 0 1(1) 0 1 0 n/a n/a n/a
TSLIP Event None FSLIP USLIP Both FSLIP and USLIP None FSLIP USLIP None USLIP --
Short
0 0 1
Elastic Bypass
NOTE(S):
(1)
0 1 n/a
Most recent slip error direction is reported in TSDIR. 2. TFSLIP not applicable (read zero value) if TSLIP is bypassed or configured as elastic store. TUSLIP not applicable if TSLIP bypassed. In short delay mode, if the bus clock is faster than the receive clock, the system bus will resynchronize and USLIP is reported. If the receive clock is faster, RSLIP reverts to normal mode and subsequently reports FSLIP errors.
TUSLIP TDLY
Uncontrolled TSLIP Event--See TFSLIP description. Transmit Slip Buffer Delay > One Frame--Indicates that real-time phase difference between TSLIP read and write pointers is more than 192 bits (T1) or 256 bits (E1). TDLY provides a coarse phase indicator and toggles (low) if transmit system bus clock phase advances with respect to the transmit line rate clock. A finer granularity of TSLIP phase is reported in TPHASE [addr 0DC]. 0 = TSLIP delay less than or equal to 1 frame 1 = TSLIP delay greater than 1 frame
100054E
Conexant
3-105
3.0 Registers
3.16 System Bus Registers
RSDIR
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Receive Slip Direction--RSDIR is updated each time an RSLIP error is latched in RFSLIP or RUSLIP and indicates which direction the slip occurred. 0 = RSLIP error deleted one frame on RPCMO or SBI resync detected 1 = RSLIP error repeated one frame on RPCMO or SBI time slot reassigned Controlled RSLIP Event--RUSLIP and RFSLIP event status are latched active high when receive slip error is detected. Either event reports RSLIP error in ISR5 [addr 006]. Active high hold interval is defined by LATCH_ERR [addr 046]. Two types of errors are detected: FSLIP = Controlled 1 frame slip on RPCMO data output. FSLIP affects RPCMO, but does not change alignment of system bus RFSYNC or RMSYNC signals. 2. USLIP = Uncontrolled 1 to 256 bit slip on RPCMO. USLIP affects both system bus data and sync outputs. RUSLIP and RFSLIP status depends on receive system bus configuration [RSB_CR; addr 0D1].
1.
RFSLIP
RSBI Mode Normal
RUSLIP 0 0 1
RFSLIP 0 1 0
RSLIP Event None FSLIP USLIP
Notes
Most recent slip error direction is reported in RSDIR. An uncontrolled slip can occur in Normal mode due to a resync of the SBI, or in T1 rate converted applications, the active time slots are reassigned. The former sets RSDIR = 0, the latter RSDIR = 1.
Short
0 0 1
0 1 0
None FSLIP USLIP In short delay mode, if bus clock is faster than receive clock, system bus will resynchronize and USLIP is reported. If receive clock is faster, RSLIP reverts to Normal mode and subsequently reports FSLIP errors. RFSLIP is not applicable (read zero value) while RSLIP buffer is bypassed or configured as elastic store. FSLIP or USLIP errors reported upon bypass mode initialization should be ignored.
Elastic
0 1
0 0
None USLIP
Bypass
RUSLIP RDLY
-
-
-
Uncontrolled RSLIP Event--See RFSLIP description. Receive Slip Buffer Delay > 1 Frame--Indicates that real-time phase difference between RSLIP read and write pointers is more than 192 bits (T1) or 256 bits (E1). RDLY provides a coarse phase indicator and toggles (low) if receive clock phase advances with respect to receive system bus clock. A finer granularity of RSLIP phase is reported in RPHASE [addr 0DB]. 0 = RSLIP delay less than or equal to 1 frame 1 = RSLIP delay greater than 1 frame
3-106
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.16 System Bus Registers
0DA--Receive Signaling Stack (STACK)
STACK contains new signaling information from those channels with SIG_STK [addr 180-19F] enabled. STACK allows the processor to conveniently monitor only changed ABCD signaling values from the selected channels. RSIG interrupt [addr 008] is triggered at the end of any multiframe where one or more ABCD signaling values have changed. The processor reads the STACK address twice to retrieve the channel number (WORD = 0) and to retrieve the new ABCD value (WORD = 1). The processor continues to read from STACK until the last new value is retrieved (MORE = 0). Internal STACK read/write pointers are initialized by RESET [addr 001]. STACK contents are updated for each channel in which the stack is enabled [SIG_STK; addr 180-19F]. STACK contents are updated with new output signaling if the buffered RSIGn input and output ABCD signaling values differ. STACK is evaluated on a channel-by-channel basis after the D-bit is updated. The processor must poll the RSIG interrupt to determine when STACK has new information. Word 0: Channel Number (first read)
7 WORD 6 MORE 5 -- 4 CH[4] 3 CH[3] 2 CH[2] 1 CH[1] 0 CH[0]
WORD MORE CH[4:0]
Stack Word ID (always 0 in Word 0) More Stack Contents (always 1 in Word 0) Channel Number (E1 range 0-31; T1 range 1-24)
Word 1: New Signaling Value (second read)
7 WORD 6 MORE 5 -- 4 -- 3 SIG_BITA 2 SIG_BITB 1 SIG_BITC 0 SIG_BITD
WORD
Stack Word ID (always 1 in Word 1)
WORD 0 0 1 1 MORE 0 1 0 1 MPU Response First word, get channel Never used No change or last change, stop New signaling, keep reading
MORE SIG_BITA-D
More Stack Contents equal 1 if more available. Signaling Bit A-D-Processor reads the new ABCD signaling value from this location. The ABCD value is also preset in RSIGn (addr 1A0-1BF) output signaling buffer, so the processor does not need to store a local copy of each channel's signaling status.
100054E
Conexant
3-107
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
0DB--RSLIP Phase Status (RPHASE)
7 RDELAY[5] 6 RDELAY[4] 5 RDELAY[3] 4 RDELAY[2] 3 RDELAY[1] 2 RDELAY[0] 1 RSLIP_WR 0 RSLIP_RD
RDELAY[5:0]
RSLIP Buffer Delay--Difference between RX and RSB timebase in time slot intervals. Reported once per frame coincident with RFRAME interrupt [ISR3; addr 008]. Actual delay may vary significantly, depending on which time slots are assigned. 000000 = RX to RSB delay in the range of 0-7 bits | 111111 = RX to RSB delay in the range of 504-511 bits
RSLIP_WR
Active RSB Slip Buffer Half--This bit indicates which half of the receive slip buffer is currently supplying data to the Receive System Bus (0 = RLIP_LO, 1 = RSLIP_HI). The processor can write data to the opposite buffer half. Active Receiver Slip Buffer Half--This bit indicates which half of the receive slip buffer is currently receiving data from the receiver (0 = RSLIP_LO, 1 = RSLIP_HI). The processor can read data from the opposite buffer half.
RSLIP_RD
0DC--TSLIP Phase Status (TPHASE)
7 TDELAY[5] 6 TDELAY[4] 5 TDELAY[3] 4 TDELAY[2] 3 TDELAY[1] 2 TDELAY[0] 1 TSLIP_WR 0 TSLIP_RD
TDELAY[5:0]
TSLIP Buffer Delay--Difference between TSB and TX timebase in time slot intervals. Reported once per frame coincident with TFRAME interrupt [ISR3; addr 008]. The actual delay may vary significantly, depending on which time slots are assigned. 000000 = TSB to TX delay in the range of 0-7 bits | 111111 = TSB to TX delay in the range of 496-503 bits
TSLIP_WR
Active Transmitter Slip Buffer Half--This bit indicates which half of the transmit slip buffer is currently supplying data to the transmitter (0 = TSLIP_LO, 1 = TSLIP_HI). The processor can write data to the opposite buffer half. Active TSB Slip Buffer Half--This bit indicates which half of the transmit slip buffer is currently receiving data from the Transmit System Bus (0 = TSLIP_LO, 1 = TSLIP_HI). The processor can read data from the opposite buffer half.
TSLIP_RD
3-108
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.16 System Bus Registers
0DD--RAM Parity Status (PERR)
All system bus data, signaling, and controls are transferred through a set of internal RAMs that have parity error detection capabilities. Any parity error that is detected during a RAM access is reported in PERR. Each error event is latched active high and held until the processor read clears PERR. Parity errors are indicative of system clock glitches (REFCKI, TSBCKI, or RSBCKI), a failing or excessively noisy power supply, or general circuit failure.
7 -- 6 -- 5 -- 4 -- 3 -- 2 PERR_TPC 1 PERR_RPC 0 PERR_SBC
PERR_TPC PERR_RPC PERR_SBC
TPC (Transmit) RAM Parity Error RPC (Receive) RAM Parity Error SBC (Control) RAM Parity Error
0E0-0FF--System Bus Per-Channel Control (SBCn; n = 0 to 31)
7 -- 6 INSERT 5 SIG_LP 4 RLOOP 3 RINDO 2 TINDO 1 TSIG_AB 0 ASSIGN
INSERT
Insert RX Signaling on RPCMO--Enables per-channel signaling insertion on RPCMO output, where ABCD signaling is supplied by RLOCAL signaling (RPCn; addr 180-19F) or buffered signaling [RSIGn; addr 1A0-IBF]. INSERT is a lower priority than no signaling (SIG_OFF; addr 0D1). RSB signaling frame locations are specified by RMSYNC signal in conjunction with programmed frame offset [OFFSET; addr 0D8].
SIG_OFF 1 0 0 INSERT X 1 1 RLOCAL X 0 1 None ABCD from RSIGn output buffer ABCD from RPCn local buffer RPCMO Inserted Signal
SIG_LP
Local Signaling Loopback--RSIGO output signaling supplied from TSIGn buffer contents. 0 = normal 1 = local signaling loopback Local Loopback--RPCMO output data supplied from TSLIP buffer contents. 0 = normal 1 = local loopback Activate RINDO Time Slot Indicator--Receive system bus time slots are individually marked (active high for 8 bits) by RINDO. Note that SBI_OE (addr 0D0) overrides RINDO. 0 = RINDO signal inactive (low) 1 = RINDO signal active (high) Activate TINDO Time Slot Indicator--Transmit system bus time slots are individually marked (active high for 8 bits) by TINDO. 0 = TINDO inactive 1 = TINDO active
RLOOP
RINDO
TINDO
100054E
Conexant
3-109
3.0 Registers
3.16 System Bus Registers
TSIG_AB
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
TSIG_AB--AB Signaling. In T1 mode, only AB signaling bits are updated from TSIGI to the TSIGn buffer. If SIGFRZ active, output CD signaling bits are copied from the buffered output AB bits respectively. In E1 mode, setting TSIG_AB forces C = 0 and D = 1 when updating the TSIGn buffer. 0 = ABCD signaling 1 = AB signaling Assign System Bus Time Slot--During T1 line applications where the system bus group consists of 32 time slots, ASSIGN selects which 24 of 32 time slots are used to transport line time slots. The number of assigned system bus time slots must always equal the number of line time slots, therefore ASSIGN must be active in all 32 SBCn locations during E1 modes. Unassigned time slots are not updated by the receiver as it fills the RSLIP buffer. T1 time slots are filled sequentially from RSLIP 1 to 24. Time slots 0 and 25 to 31 are reserved for unassigned values. Values are read from either the assigned or unassigned locations in a sequential fashion based upon the ASSIGN bit. System bus output data for unassigned time slots is taken from RSLIP buffer, which the processor can fill with any desired 16-bit fixed value (8 bits in RSLIP_LO, plus 8 bits in RSLIP_HI). 0 = unassigned system bus time slot 1 = assigned system bus time slot
ASSIGN
100-11F--Transmit Per-Channel Control (TPCn; n = 0 to 31)
7 TB7ZS/EMF-BIT 6 TLOOP 5 TIDLE 4 TLOCAL 3 TSIGA/TSIGO 2 TSIGB/RSIGO 1 TSIGC 0 TSIGD
TB7ZS/EMF-BIT
Bit7 Zero Code Substitution/Embedded F-bit Value (Applicable in T1 mode only)--For assigned system bus time slots [ASSIGN; addr 0E0-0FF], TB7ZS replaces Bit 7 of the time slot with a 1, if examination of 8-bit output detects all zeros. For an unassigned time slot where TIDLE is active, EMF-BIT replaces all embedded F-bit outputs with the programmed EMF-BIT value. 0 = no effect or force embedded F-bit (low) 1 = enable B7ZS or force embedded F-bit (high)
3-110
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
TLOOP
3.0 Registers
3.16 System Bus Registers
Remote DS0 Channel Loopback--Transmit data supplied from RSLIP buffer contents. TLOOP works in conjunction with other TPCn control bits to select the source of transmitted data and signaling (see Table 3-23).
Table 3-23. Remote DS0 Channel Loopback TLOOP
0 0 1 1
TIDLE
0 1 0 1
Data Source
TPCMI TSLIP_LO RXDATA TSLIP_LO Normal
Channel Mode
Transmit Idle Remote Loop Transmit Idle
NOTE(S): If RX Signaling, then RSIGn output buffer supplies transmit signaling.
Table 3-24. Signaling Loopback TLOCAL
0 0 0 1
TSIGO
0 0 1 X
RSIGO
0 1 0 X
Sig Source
None RSIGn TSIGn TSIGA-D
Signaling Mode
No Transmit Signaling Remote Signaling Loopback TX Signaling Loopback Local Signaling
NOTE(S): If RX Signaling, then RSIGn output buffer supplies transmit signaling.
TIDLE
Transmit Idle--Transmit data supplied from TSLIP_LO buffer contents. The processor writes an 8-bit idle pattern to TSLIP_LO for output on the selected time slot or optionally writes real-time data output to TSLIP_LO after each TFRAME interrupt [ISR3; addr 008]. Only the TSLIP_HI buffer is updated from TPCMI to allow continued local DS0 channel loopback. 0 = normal data output 1 = transmit idle data output Transmit Local Signaling--When active, TLOCAL transmits TSIGA-TSIGD values in output ABCD signaling bits. 0 = TSIGO or RSIGO control output signaling 1 = transmit signaling from TSIGA-TSIGD Transmit Local Signaling--Holds the 4-bit ABCD signaling value, which is output when TLOCAL is active. In AB only applications, such as T1/SF framing, TSIGC and TSIGD must also be written with the same data as TSIGA and TSIGB. In E1 modes, TS0 and TS16 local signaling value determines CAS multiframe alignment signal (MAS) and XYXX output. Transmit Signaling Output--Applicable only if TLOCAL is inactive. ABCD signaling from TSIGn buffer is transmitted. 0 = no effect 1 = transmit signaling from TSIGn buffer Receive Signaling Output--Applicable only if TLOCAL is inactive. Forces transmit ABCD signaling to be supplied from RSIGn buffer, affecting a remote signaling loopback. 0 = no effect 1 = transmit signaling from RSIGn buffer
TLOCAL
TSIGA-TSIGD
TSIGO
RSIGO
100054E
Conexant
3-111
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
120-13F--Transmit Signaling Buffer (TSIGn; n = 0 to 31)
Transmit signaling from the TSIGI pin is automatically placed into the TSIGn buffer. Processor controls TSIGn insertion into the transmitter output by selecting TSIGO[inTPCn]. The processor can read monitor TSIGn from system supplied signaling or can use TSIGn for inter-processor communication. During E1 modes, TSIG0 and TSIG16 buffer locations hold the CAS multiframe alignment signal (MAS.1 through MAS.4), Extra bits (X.1 through X.4), and multiframe yellow alarm (MYEL) bits supplied from TSIGI. Unused bits are reserved and should be written to 0.
7 -- 6 -- 5 -- 4 -- 3 TSIGn[3] 2 TSIGn[2] 1 TSIGn[1] 0 TSIGn[0]
TSIG0 (E1)
TSIGn.3. TSIGn.2. TSIGn.1. TSIGn.0.
TSIG16 (E1) X.1 MYEL X.3 X.4
Input Signaling A Bit Input Signaling B Bit Input Signaling C Bit Input Signaling D Bit
MAS.1 MAS.2 MAS.3 MAS.4
140-15F--Transmit PCM Slip Buffer (TSLIP_LOn; n = 0 to 31)
7 TPCM[1] 6 TPCM[2] 5 TPCM[3] 4 TPCM[4] 3 TPCM[5] 2 TPCM[6] 1 TPCM[7] 0 TPCM[8]
TPCM[1] TPCM[2] TPCM[3] TPCM[4] TPCM[5] TPCM[6] TPCM[7] TPCM[8]
First bit Second bit Third bit Fourth bit Fifth bit Sixth bit Seventh bit Eighth bit received on TPCMI
3-112
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.16 System Bus Registers
160-17F--Transmit PCM Slip Buffer (TSLIP_HIn; n = 0 to 31)
7 TPCM[1] 6 TPCM[2] 5 TPCM[3] 4 TPCM[4] 3 TPCM[5] 2 TPCM[6] 1 TPCM[7] 0 TPCM[8]
TPCM[1] TPCM[2] TPCM[3] TPCM[4] TPCM[5] TPCM[6] TPCM[7] TPCM[8]
First bit Second bit Third bit Fourth bit Fifth bit Sixth bit Seventh bit Eighth bit received on TPCMI
180-19F--Receive Per-Channel Control (RPCn; n = 0 to 31)
7 RSIG_AB/ EMF-BIT 6 RIDLE 5 SIG_STK 4 RLOCAL 3 RSIGA 2 RSIGB 1 RSIGC 0 RSIGD
RSIG_AB/EMF-BIT
AB Signaling (Per-Channel RSIG_AB [without DEBOUNCE])--In E1 mode, received signaling is placed into RSIGn as usual. However, RSIGO output duplicates the buffered AB bit value in the CD output bits, thus sending ABAB on RSIGO instead of ABCD. In T1 mode, RSIG_AB instructs the receiver to use available RSIGn buffer space to meet PUB43801 and TR-170. PUB43801 and TR-170 require three SF multiframes of receive signaling buffer storage before output. Every 24 frames, the received ABCD signaling value is transferred from the RSIGn input buffer space to RSIGn output buffer space, regardless of whether the receiver operates in SF, SLC, or ESF mode. Therefore, in SF mode, the ABCD value contains AB = AB(N-1) and CD = AB(N) from two multiframes. Since multiframe N-1 is the older sample, AB(N-1) replaces AB(N) in the event of signaling freeze. RSIGO and RPCMO signaling bit output values are always taken from the RSIGn output buffer, according to the RSB frame number.
100054E
Conexant
3-113
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
AB Signaling (Per-Channel RSIG_AB [with DEBOUNCE])--Debounce is applicable only for T1 modes and affects the RSIGn input buffer update mechanism. This is accomplished by comparing, on a bit-by-bit basis, the present received input signaling bit value with the current buffered signaling bit values from two prior multiframes. If signaling from prior multiframe (N) differs from input, and input equals buffered value from 2 multiframes prior (N-1), signaling bit value from multiframe N is inverted when the input buffer is updated.
Sig Input 0 0 0 0 1 1 1 1 Buffer N, N-1 00 01 10 11 00 01 10 11 Update N, N-1 00 00 00 01 10 11 11 11 Notes -- Change update Debounce -- -- Debounce Change update --
When RIDLE is active in an unassigned time slot defined to carry embedded F-bits, EMFBIT replaces all embedded F-bit outputs on RPCMO with the programmed value. 0 = normal ABCD and embedded F-bit throughput 1 = AB signaling and embedded F-bit replacement
RIDLE
Time Slot Idle--When RIDLE is active, the incoming RX time slot data is only updated in the RSLIP_HIn buffer, and the RSB time slot data output is only extracted from RSLIP_LOn buffer. Thus, the processor can write an 8-bit idle code pattern in RSLIP_LOn buffer for output during the RSB time slot. 0 = no effect 1 = RSB time slot replaced by contents of RSLIP_LOn Receive Signaling Stack--Selects whether changes detected in the ABCD signaling value are reported in signaling stack [addr 0DA]. Note that signaling for all time slots is continuously updated in RSIGn buffer, regardless of the SIG_STK setting. 0 = no effect 1 = signaling stack Enable Local Signaling Output--Determines whether the RSIGO output signaling and RPCMO inserted signaling [INSERT; addr 0E0-0FF] are supplied from RSIGn output buffer or processor supplied local signaling from RSIGA-RSIGD. 0 = RSIGn buffer signaling 1 = RSIGA-RSIGD local signaling Local Receive Signaling--When RLOCAL is active, these 4 bits are inserted into RSIGO instead of the buffered signaling from RSIGn. If both RLOCAL and INSERT are active, these 4 bits are also inserted into RPCMO during system bus signaling frames. 0 = output signaling bit equals zero 1 = output signaling bit equals one
SIG_STK
RLOCAL
RSIGA-RSIGD
3-114
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.0 Registers
3.16 System Bus Registers
1A0-1BF--Receive Signaling Buffer (RSIGn; n = 0 to 31)
The Receive Signaling Buffer (RSIGn) contains all ABCD signaling inputs from all channels, regardless of whether signaling is active [SIG_STK; addr 180-19F]. RSIGn is not updated during signaling freeze conditions, or when the receive framer is configured in a non-signaling mode. Normal signaling buffer operation transfers ABCD input to ABCD output coincident with the D-bit update (in T1 mode) or coincident with receipt of respective channel's ABCD signaling during TS16 (in E1 mode). When DEBOUNCE is active, output signaling for active channels is updated coincident with the sampling of each input signaling bit and may cause the buffered output value to transition in the middle of the received multiframe.
7 RSIGn[7] 6 RSIGn[6] 5 RSIGn[5] 4 RSIGn[4] 3 RSIGn[3] 2 RSIGn[2] 1 RSIGn[1] 0 RSIGn[0]
RSIGn[7] RSIGn[6] RSIGn[5] RSIGn[4]
Output Signaling A Bit Output Signaling B Bit Output Signaling C Bit Output Signaling D Bit RSIG0 (E1) RSIG16 (E1) X.1 MYEL X.3 X.4
RSIGn[3]. RSIGn[2]. RSIGn[1]. RSIGn[0].
Input Signaling A Bit Input Signaling B Bit Input Signaling C Bit Input Signaling D Bit
MAS.1 MAS.2 MAS.3 MAS.4
1C0-1DF--Receive PCM Slip Buffer (RSLIP_LOn; n = 0 to 31)
7 RPCM[1] 6 RPCM[2] 5 RPCM[3] 4 RPCM[4] 3 RPCM[5] 2 RPCM[6] 1 RPCM[7] 0 RPCM[8]
RPCM[1] RPCM[2] RPCM[3] RPCM[4] RPCM[5] RPCM[6] RPCM[7] RPCM[8]
First bit Second bit Third bit Fourth bit Fifth bit Sixth bit Seventh bit Eighth bit received from receiver
100054E
Conexant
3-115
3.0 Registers
3.16 System Bus Registers
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
1E0-1FF--Receive PCM Slip Buffer (RSLIP_HIn; n = 0 to 31)
7 RPCM[1] 6 RPCM[2] 5 RPCM[3] 4 RPCM[4] 3 RPCM[5] 2 RPCM[6] 1 RPCM[7] 0 RPCM[8]
RPCM[1] RPCM[2] RPCM[3] RPCM[4] RPCM[5] RPCM[6] RPCM[7] RPCM[8]
First bit Second bit Third bit Fourth bit Fifth bit Sixth bit Seventh bit Eighth bit received from receiver
3-116
Conexant
100054E
3
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3.17 Register Summary
Table 3-25. Global Control and Status Registers ADDR (hex)
000 080 081
Register Label
DID FCR MIR MIE TEST
Read Write
R R/W R R/W R/W
Bit Number 7
DID[7] GRESET MIR[7] MIE[7] --
6
DID[6] -- MIR[6] MIE[6] --
5
DID[5] -- MIR[5] MIE[5] --
4
DID[4] -- MIR[4] MIE[4] --
3
DID[3] -- MIR[3] MIE[3] --
2
DID[2] ONESEC_IO MIR[2] MIE[2] --
1
DID[1] SBIMODE[1] MIR[1] MIE[1] TEST
0
DID[0] SBIMODE[0] MIR[0] MIE[0] --
Conexant
3-117
082 083
Table 3-26. Primary Control Register ADDR (hex)
001
Register Label
CR0
Read Write
R/W
Bit Number 7
RESET
6
--
5
--
4
RFRAME[3]
3
RFRAME[2]
2
RFRAME[1]
1
RFRAME[0]
0
TI/EIN
Table 3-27. Interrupt Control Register ADDR (hex)
003
3.17 Register Summary
Register Label
IRR
Read Write
R
Bit Number 7
ALARM1
6
ALARM2
5
ERROR
4
COUNT
3
TIMER
2
DL1
1
DL2
0
PATT
3.0 Register
3-118
3.17 Register Summary
2.0 Register
Table 3-28. Interrupt Status Registers ADDR (hex)
004 005 006 007 008 009 00A 00B
Register Label
ISR7 ISR6 ISR5 ISR4 ISR3 ISR2 ISR1 ISR0
Read Write
R R R R R R R R
Bit Number 7
RMYEL LOOPDN TSLIP RLOF[4] TSIG TBOP RBOP --
6
RYEL LOOPUP RSLIP COFA[2] TMSYNC RFULL1 RFULL2 --
5
RPDV TPDV -- SEF[2] TMF RNEAR1 RNEAR2 BSLIP
4
RAIS -- -- BERR[12] TFRAME RMSG1 RMSG2 PSYNC
3
RALOS TLOC CERR FEBE[10] RSIG TDLERR1 TDLERR2 TCERR
2
RLOS -- SERR LCV[16] RMSYNC TEMPTY1 TEMPTY2 TSERR
1
RLOF TLOF MERR CRC[10] RMF TNEAR1 TNEAR2 TMERR
0
SIGFRZ ONESEC FERR FERR[12] RFRAME TMSG1 TMSG2 TFERR
Conexant
100054E
Table 3-29. Interrupt Enable Registers ADDR (hex)
00C 00D 00E 00F 010 011 012 013
Register Label
IER7 IER6 IER5 IER4 IER3 IER2 IER1 IER0
Read Write
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Number 7
RMYEL LOOPDN TSLIP LOF TSIG TBOP RBOP --
6
RYEL LOOPUP RSLIP COFA TMSYNC RFULL1 RFULL2 --
5
RPDV TPDV -- SEF TMF RNEAR1 RNEAR2 BSLIP
4
RAIS -- -- BERR TFRAME RMSG1 RMSG2 PSYNC
3
RALOS TLOC CERR FEBE RSIG TDLERR1 RDLERR2 TCERR
2
RLOS -- SERR LCV RMSYNC TEMPTY1 TEMPTY2 TSERR
1
RLOF TLOF MERR CRC RMF TNEAR1 TNEAR2 TMERR
0
SIGFRZ ONESEC FERR FERR RFRAME TMSG1 TMSG2 TFERR
Quad/x16/Octal--T1/E1/J1 Framers
CX28394/28395/28398
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-30. Primary Control and Status Registers ADDR (hex)
014 015 016 017 018 019 01A 020 021
Register Label
LOOP DL3_TS DL3_BIT FSTAT PIO POE CMUX RAC RSTAT
Read Write
R/W R/W R/W R R/W R/W R/W R/W R
Bit Number 7
-- DL3EN DL3_BIT[7] -- RMSYNC_EN -- -- -- --
6
-- ODD DL3_BIT[6] -- RDL_IO -- RSBCK -- --
5
-- EVEN DL3_BIT[5] -- TMSYNC_EN TDL_OE -- -- ZCSUB
4
-- TS[4] DL3_BIT[4] INVALID TDL_IO RDL_OE TSBCK RAL_CON EXZ
3
PLOOP TS[3] DL3_BIT[3] FOUND RFSYNC_IO INDY_OE -- -- BPV
2
LLOOP TS[2] DL3_BIT[2] TIMEOUT RMSYNC_IO TCKO_OE -- -- --
1
FLOOP TS[1] DL3_BIT[1] ACTIVE TFSYNC_IO -- TXCLKI[1] -- --
0
-- TS[0] DL3_BIT[0] RX/TXN TMSYNC_IO -- TXCLKI[0] -- --
Conexant
3-119
Table 3-31. Serial Interface Registers ADDR (hex)
022 023 024 025 026
Register Label
SER_CTL SER_DAT SER_STAT SER_CONFIG RAM Test
Read Write
R/W R/W R/W R/W R/W
Bit Number 7
SER_A[6] SER_DAT[7] -- SER_CS RT[7]
6
SER_A[5] SER_DAT[6] -- SER_CLK RT[6]
5
SER_A[4] SER_DAT[5] -- -- RT[5]
4
SER_A[3] SER_DAT[4] -- -- RT[4]
3
SER_A[2] SER_DAT[3] -- -- RT[3]
2
SER_A[1] SER_DAT[2] -- -- RT[2]
1
SER_A[0] SER_DAT[1] -- -- RT[1]
0
SER_RW SER_DAT[0] SER_DONE SER_IER RT[0]
3.17 Register Summary
3.0 Register
3-120
3.17 Register Summary
2.0 Register
Table 3-32. Receiver Registers ADDR (hex)
040 041 042 043 044 045 046 047 048
Register Label
RCR0 RPATT RLB LBA LBD RALM LATCH ALM1 ALM2 ALM3
Read Write
R/W R/W R/W R/W R/W R/W R/W R R R
Bit Number 7
RAMI -- -- LBA[1] LBD[1] -- -- RMYEL LOOPDN --
6
RABORT -- -- LBA[2] LBD[2] -- -- RYEL LOOPUP RMAIS
5
RFORCE RESEED -- LBA[3] LBD[3] FS_NFAS -- -- -- SEF
4
RLOFD BSTART -- LBA[4] LBD[4] EXZ_LCV -- RAIS -- SRED
3
RLOFC FRAMED DN_LEN[1] LBA[5] LBD[5] YEL_INTEG STOP_CNT RALOS TLOC MRED
2
RLOFB ZLIMIT DN_LEN[0] LBA[6] LBD[6] RLOF_INTEG LATCH_CNT RLOS -- FRED
1
RLOFA RPATT[1] UP_LEN[1] LBA[7] LBD[7] RPCM_YEL LATCH_ERR RLOF TLOF LOF[1]
0
RZCS RPATT[0] UP_LEN[0] -- -- RPCM_AIS LATCH_ALM SIGFRZ -- LOF[0]
Conexant
100054E
049
Quad/x16/Octal--T1/E1/J1 Framers
CX28394/28395/28398
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-33. Performance Monitoring Registers ADDR (hex)
050 051 052 053 054 055 056 057 058
Register Label
FERR FERR CERR CERR LCV LCV FEBE FEBE BERR BERR AERR
Read Write
R R R R R R R R R R R
Bit Number 7
FERR[7] 0 CERR[7] 0 LCV[7] LCV[15] FEBE[7] 0 BERR[7] 0 FRED[3]
6
FERR[6] 0 CERR[6] 0 LCV[6] LCV[14] FEBE[6] 0 BERR[6] 0 FRED[2]
5
FERR[5] 0 CERR[5] 0 LCV[5] LCV[13] FEBE[5] 0 BERR[5] 0 FRED[1]
4
FERR[4] 0 CERR[4] 0 LCV[4] LCV[12] FEBE[4] 0 BERR[4] 0 FRED[0]
3
FERR[3] FERR[11] CERR[3] 0 LCV[3] LCV[11] FEBE[3] 0 BERR[3] BERR[11] COFA[1]
2
FERR[2] FERR[10] CERR[2] 0 LCV[2] LCV[10] FEBE[2] 0 BERR[2] BERR[10] COFA[0]
1
FERR[1] FERR[9] CERR[1] CERR[9] LCV[1] LCV[9] FEBE[1] FEBE[9] BERR[1] BERR[9] SEF[1]
0
FERR[0] FERR[8] CERR[0] CERR[8] LCV[0] LCV[8] FEBE[0] FEBE[8] BERR[0] BERR[8] SEF[0]
Conexant
3-121
059 05A
Table 3-34. Receive Sa-Byte Buffers ADDR (hex)
05B 05C 05D 05E 05F
Register Label
RSA4 RSA5 RSA6 RSA7 RSA8
Read Write
R R R R R
Bit Number 7
RSA4[7] RSA5[7] RSA6[7] RSA7[7] RSA8[7]
6
RSA4[6] RSA5[6] RSA6[6] RSA7[6] RSA8[6]
5
RSA4[5] RSA5[5] RSA6[5] RSA7[5] RSA8[5]
4
RSA4[4] RSA5[4] RSA6[4] RSA7[4] RSA8[4]
3
RSA4[3] RSA5[3] RSA6[3] RSA7[3] RSA8[3]
2
RSA4[2] RSA5[2] RSA6[2] RSA7[2] RSA8[2]
1
RSA4[1] RSA5[1] RSA6[1] RSA7[1] RSA8[1]
0
RSA4[0] RSA5[0] RSA6[0] RSA7[0] RSA8[0]
3.17 Register Summary
3.0 Register
3-122
3.17 Register Summary
2.0 Register
Table 3-35. Transmitter Registers ADDR (hex)
070 071 072 073 074 075 076 077 078
Register Label
TCR0 TCR1 TFRM TERROR TMAN TALM TPATT TLB LBP
Read Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Number 7
-- TNRZ -- TSERR INS_SA[8] -- -- -- LBP[1]
6
-- TABORT -- TMERR INS_SA[7] AISCLK -- -- LBP[2]
5
-- TFORCE INS_MYEL TBERR INS_SA[6] AUTO_MYEL -- -- LBP[3]
4
-- TLOFC INS_YEL BSLIP INS_SA[5] AUTO_YEL TPSTART -- LBP[4]
3
TFRAME[3] TLOFB INS_MF TCOFA INS_SA[4] AUTO_AIS FRAMED LB_LEN[1] LBP[5]
2
TFRAME[2] TLOFA INS_FE TCERR FEBE_II TMYEL ZLIMIT LB_LEN[0] LBP[6]
1
TFRAME[1] TZCS[1] INS_CRC TFERR FEBE_I TYEL TPATT[1] UNFRAMED LBP[7]
0
TFRAME[0] TZCS[0] INS_FBIT TVERR TFEBE TAIS TPATT[0] LBSTART --
Conexant
100054E
Table 3-36. Transmit Sa-Byte Buffers ADDR (hex)
07B 07C 07D 07E 07F
Register Label
TSA4 TSA5 TSA6 TSA7 TSA8
Read Write
R/W R/W R/W R/W R/W
Bit Number 7
TSA4[7] TSA5[7] TSA6[7] TSA7[7] TSA8[7]
6
TSA4[6] TSA5[6] TSA6[6] TSA7[6] TSA8[6]
5
TSA4[5] TSA5[5] TSA6[5] TSA7[5] TSA8[5]
4
TSA4[4] TSA5[4] TSA6[4] TSA7[4] TSA8[4]
3
TSA4[3] TSA5[3] TSA6[3] TSA7[3] TSA8[3]
2
TSA4[2] TSA5[2] TSA6[2] TSA7[2] TSA8[2]
1
TSA4[1] TSA5[1] TSA6[1] TSA7[1] TSA8[1]
0
TSA4[0] TSA5[0]
Quad/x16/Octal--T1/E1/J1 Framers
TSA6[0] TSA7[0] TSA8[0]
CX28394/28395/28398
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 3-37. Bit-Oriented Protocol Registers ADDR (hex)
0A0 0A1 0A2 0A3
Register Label
BOP TBOP RBOP BOP_STAT
Read Write
R/W R/W R R
Bit Number 7
RBOP_START -- RBOP_LOST TBOP_ACTIVE
6
RBOP_INTEG -- RBOP_VALID RBOP_ACTIVE
5
RBOP_LEN[1] TBOP[5] RBOP[5] --
4
RBOP_LEN[0] TBOP[4] RBOP[4] --
3
TBOP_LEN[1] TBOP[3] RBOP[3] --
2
TBOP_LEN[0] TBOP[2] RBOP[2] --
1
TBOP_MODE[1] TBOP[1] RBOP[1] --
0
TBOP_MODE[0] TBOP[0] RBOP[0] --
Table 3-38. Data Link Registers (1 of 2) ADDR (hex)
0A4
Register Label
DL1_TS DL1_BIT DL1_CTL RDL1_FFC RDL1 RDL1_STAT PRM TDL1_FEC TDL1_EOM TDL1 TDL1_STAT DL2_TS DL2_BIT DL2_CTL RDL2_FFC
Read Write
R/W R/W R/W R/W R
Bit Number 7
DL1_TS[7] DL1_BIT[7] -- MSG_FILL[1] EOM[1]
6
DL1_TS[6] DL1_BIT[6] -- MSG_FILL[0] EOM[0] RDL1[6] -- PRM_CR -- -- TDL1[6] -- DL2_TS[6] DL2_BIT[6] -- MSG_FILL[0]
5
DL1_TS[5] DL1_BIT[5] -- FFC[5] RDL1_CNT[5] RDL1[5] -- PRM_R FEC[5] -- TDL1[5] -- DL2_TS[5] DL2_BIT[5] -- FFC[5]
4
DL1_TS[4] DL1_BIT[4] TDL1_RPT FFC[4] RDL1_CNT[4] RDL1[4] RMSG1 PRM_U1 FEC[4] -- TDL1[4] -- DL2_TS[4] DL2_BIT[4] TDL2_RPT FFC[4]
3
DL1_TS[3] DL1_BIT[3] DL1[1] FFC[3] RDL1_CNT[3] RDL1[3] RSTAT1 PRM_U2 FEC[3] -- TDL1[3] TMSG1 DL2_TS[3] DL2_BIT[3] DL2[1] FFC[3]
2
DL1_TS[2] DL1_BIT[2] DL1[0] FFC[2] RDL1_CNT[2] RDL1[2] RMPTY1 PRM_SL FEC[2] -- TDL1[2] TMPTY1 DL2_TS[2] DL2_BIT[2] DL2[0] FFC[2]
1
DL1_TS[1] DL1_BIT[1] TDL1_EN FFC[1] RDL1_CNT[1] RDL1[1] RNEAR1 AUTO_SL FEC[1] -- TDL1[1] TNEAR1 DL2_TS[1] DL2_BIT[1] TDL2_EN FFC[1]
0
DL1_TS[0] DL1_BIT[0] RDL1_EN FFC[0] RDL1_CNT[0] RDL1[0] RFULL1 SEND_PRM FEC[0] -- TDL1[0]
Conexant
3-123
0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2
RDL1[7] R R/W R/W W W R R/W R/W R/W R/W -- AUTO_PRM -- -- TDL1[7] -- DL2_TS[7] DL2_BIT[7] -- MSG_FILL[1]
3.17 Register Summary
TFULL1 DL2_TS[0] DL2_BIT[0] RDL2_EN FFC[0]
3.0 Register
Table 3-38. Data Link Registers (2 of 2) ADDR (hex)
0B3 0B4 0B6 0B7 0B8 0B9 0BA 0BB
3-124
3.17 Register Summary
2.0 Register
Register Label
RDL2 RDL2_STAT TDL2_FEC TDL2_EOM TDL2 TDL2_STAT DL_TEST1 DL_TEST2 DL_TEST3 DL_TEST4 DL_TEST5
Read Write
R
Bit Number 7
EOM[1] RDL2[7]
6
EOM[0] RDL2[6] -- -- -- TDL2[6] -- -- -- -- DL_TEST4[6] DL_TEST5[6]
5
RDL2_CNT[5] RDL2[5] -- FEC[5] -- TDL2[5] -- -- DL_TEST2[5] DL_TEST3[5] DL_TEST4[5] DL_TEST5[5]
4
RDL2_CNT[4] RDL2[4] RMSG2 FEC[4] -- TDL2[4] -- -- DL_TEST2[4] DL_TEST3[4] DL_TEST4[4] DL_TEST5[4]
3
RDL2_CNT[3] RDL2[3] RSTAT2 FEC[3] -- TDL2[3] TMSG2 DL_TEST1[3] DL_TEST2[3] DL_TEST3[3] DL_TEST4[3] DL_TEST5[3]
2
RDL2_CNT[2] RDL2[2] RMPTY2 FEC[2] -- TDL2[2] TMPTY2 DL_TEST1[2] DL_TEST2[2] DL_TEST3[2] DL_TEST4[2] DL_TEST5[2]
1
RDL2_CNT[1] RDL2[1] RNEAR2 FEC[1] -- TDL2[1] TNEAR2 DL_TEST1[1] DL_TEST2[1] DL_TEST3[1] DL_TEST4[1] DL_TEST5[1]
0
RDL2_CNT[0] RDL2[0] RFULL2 FEC[0] -- TDL2[0] TFULL2 DL_TEST1[0] DL_TEST2[0] DL_TEST3[0] DL_TEST4[0] DL_TEST5[0]
R R/W W R/W R R/W R/W R/W R/W R/W
-- -- -- TDL2[7] -- -- -- -- -- --
Conexant
100054E
0BC 0BD 0BE
Table 3-39. System Bus Registers (1 of 2) ADDR (hex)
0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7
Register Label
SBI_CR RSB_CR RSYNC_BIT RSYNC_TS TSB_CR TSYNC_BIT TSYNC_TS RSIG_CR
Read Write
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Number 7
X2CLK BUS_RSB -- -- BUS_TSB -- -- --
6
SBI_OE SIG_OFF -- OFFSET[9] TX_ALIGN -- OFFSET[9] SET_RSIG
5
EMF RPCM_NEG -- OFFSET[8] TPCM_NEG -- OFFSET[8] SET_SIG
4
EMBED RSYN_NEG -- OFFSET[7] TSYN_NEG -- OFFSET[7] UNICODE
3
SBI[3] BUS_FRZ -- OFFSET[6] TSB_ALIGN -- OFFSET[6] DEBOUNCE
2
SBI[2] RSB_CTR OFFSET[2] OFFSET[5] TSB_CTR OFFSET[2] OFFSET[5] FRZ_OFF
1
SBI[1] RSBI[1] OFFSET[1] OFFSET[4] TSBI[1] OFFSET[1] OFFSET[4] FRZ_ON
0
Quad/x16/Octal--T1/E1/J1 Framers
SBI[0] RSBI[0] OFFSET[0] OFFSET[3] TSBI[0] OFFSET[0] OFFSET[3] THRU
CX28394/28395/28398
Table 3-39. System Bus Registers (2 of 2) ADDR (hex)
0D8 0D9 0DA 0DB 0DC 0DD 0E0-0FF 100-11F
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Register Label
RSYNC_FRM SSTAT STACK RPHASE TPHASE PERR SBCn; n = 0 to 31 TPCn; n = 0 to 31 TSIGn; n = 00 to 31 TSLIP_LOn; n = 0 to 31 TSLIP-HIn; n = 0 to 31 RPCn; n = 0 to 31 RSIGn; n = 0 to 31 RSLIP_LOn; n = 0 to 31 RSLIP_HIn; n = 0 to 31
Read Write
R/W R R
Bit Number 7
-- TSDIR WORD WORD
6
-- TFSLIP MORE MORE RDELAY[4] TDELAY[4] -- INSERT TLOOP -- TPCM[2] TPCM[2] RIDLE RSIGn[6] RPCM[2] RPCM[2]
5
-- TUSLIP -- -- RDELAY[3] TDELAY[3] -- SIG_LP TIDLE -- TPCM[3] TPCM[3] SIG_STK RSIGn[5] RPCM[3] RPCM[3]
4
OFFSET[14] TDLY CH[4] -- RDELAY[2] TDELAY[2] -- RLOOP TLOCAL -- TPCM[4] TPCM[4] RLOCAL RSIGn[4] RPCM[4] RPCM[4]
3
OFFSET[13] RSDIR CH[3] SIG_BITA RDELAY[1] TDELAY[1] -- RINDO TSIGA/TSIGO TSIGn[3] TPCM[5] TPCM[5] RSIGA RSIGn[3] RPCM[5] RPCM[5]
2
OFFSET[12] RFSLIP CH[2] SIG_BITB RDELAY[0] TDELAY[0] PERR_TPC TINDO TSIGB/RSIGO TSIGn[2] TPCM[6] TPCM[6] RSIGB RSIGn[2] RPCM[6] RPCM[6]
1
OFFSET[11] RUSLIP CH[1] SIG_BITC RSLIP_WR TSLIP_WR PERR_RPC TSIG_AB TSIGC TSIGn[1] TPCM[7] TPCM[7] RSIGC RSIGn[1] RPCM[7] RPCM[7]
0
OFFSET[10] RDLY CH[0] SIG_BITD RSLIP_RD TSLIP_RD PERR_SBC ASSIGN TSIGD TSIGn[0] TPCM[8] TPCM[8] RSIGD RSIGn[0] RPCM[8] RPCM[8]
R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
RDELAY[5] TDELAY[5] -- -- TB7ZS/EMFBIT -- TPCM[1] TPCM[1] RSIG_AB/ EMFBIT RSIGn[7] RPCM[1] RPCM[1]
Conexant
3-125
120-13F 140-15F 160-17F 180-19F 1A0-1BF 1C0-1DF 1E0-1FF
3.17 Register Summary
3.0 Register
2.0 Register
3.17 Register Summary
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
3-126
Conexant
100054E
4
4.0 Electrical/Mechanical Specifications
4.1 Absolute Maximum Ratings
Table 4-1. Absolute Maximum Ratings Symbol
VDD VGG
VDD
Parameter
Power Supply (measured to GND) High Voltage Reference Voltage Differential (between any 2 VDD pins) Constant Voltage on any Signal Pin Transient Voltage on any Signal Pin HBM rating CDM rating MMM rating Constant Current on any Signal Pin Transient Current on any Signal Pin Storage Temperature Junction Temperature: (jA x VDD x IDD) + Tamb Vapor Phase Soldering Temperature (1 minute) Thermal Resistance (208 PQFP), Still Air Thermal Resistance (128 TQFP), Still Air Thermal Resistance (272 BGA), Still Air Thermal Resistance (318 BGA), Still Air Thermal Resistance (208 CABGA), Still Air
Minimum
-0.5 -0.5 -- -1.0 -- -- -- -10 -200 -65 -40 -- -- -- -- -- --
Maximum
5.75 5.75 0.5 VGG + 0.5 1.5 200 100 +10 +200 150 125 220 20 36 29 29 44.6
Units
V V V V kV V V mA mA C C C C/W C/W C/W C/W C/W
Vi ESD
Ii LATCHUP Ts Tj Tvsol jA jA jA jA jA
NOTE(S): Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions beyond those indicated in the other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
100054E
Conexant
4-1
4.0 Electrical/Mechanical Specifications
4.2 Recommended Operating Conditions
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
4.2 Recommended Operating Conditions
Table 4-2. Recommended Operating Conditions Symbol
VDD VGG VGG Tamb Supply Voltage High Voltage Reference (5 V Tolerant Inputs) High Voltage Reference (Non-5 V Tolerant Inputs) Ambient Operating Temperature KPF Suffix EPF Suffix Input High Voltage Input Low Voltage SYSCLK Frequency
Parameter
Minimum
3.135 4.75 3.135 0 -40 2.0 -0.5 32.765
Typical
3.3 5.0 3.3 25 25 -- -- 32.768
Maximum
3.465 5.25 3.465 70 85 VGG + 0.5 0.8 32.771
Units
V V V C C V V MHz
Vih Vil SYSCLK
4-2
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
4.0 Electrical/Mechanical Specifications
4.3 Electrical Characteristics
4.3 Electrical Characteristics
Table 4-3. DC Characteristics Symbol
IDD
Parameter
Supply Current (All signals and clocks operating at maximum frequency. All outputs loaded: 85 pF + 1 mA) CX28394 CX28398 CX28395
Minimum
Typical
Maximum
Units
-- -- -- -- 2.0 -- 2.4 -- -- 40 -10 -10 -- -- -- -- 37
80 140 280 -- -- -- -- -- -- 100 1 1 2 5 2 70 50
90 155 310 1 VGG + 0.5 0.8 -- 0.4 4 500 10 10 5 10 5 85 160
mA mA mA mA V V V V mA A A A pF pF pF pF mA
IGG Vih Vil Voh Vol Iod Ipr Il Ioz Cin Cio Cout Cld Iosc
NOTE(S):
High Voltage Reference Current Input High Voltage Input Low Voltage Output High Voltage (Ioh = -2 mA) Output Low Voltage (Iol = 2 mA) Open Drain Output Current Sink Resistive Pullup Current Input Leakage Current Three-state Leakage Current Input Capacitance (f = 1MHz, Vin = 2.4V) I/O Capacitance (PIO, AD[7:0] pins) Output Capacitance Capacitive Loading (Test Condition) Short Circuit Output Current
1. All typical values are at VDD = 3.3 V and Tamb = 25 C. 2. Maximum and minimum values are over VDD = 3.3 V + 5% and Tamb = appropriate temperature range: KPF suffix (0 to 70 C) or EPF suffix (-40 to 85 C).
100054E
Conexant
4-3
4.0 Electrical/Mechanical Specifications
4.4 AC Characteristics
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
4.4 AC Characteristics
Table 4-4. Input Clock Timing Symbol
1 MCLK Frequency SYSCLK Frequency RCKI, TCKI, ACKI Frequency RSBCKI, TSBCKI Frequency TCK Frequency 2 3 4 5 Clock Width High Clock Width Low Clock Rise Time Clock Fall Time
Parameter
Minimum
8.0 32.765 1.5 1.5 0 0.4 x t(1) 0.4 x t(1) -- --
Maximum
35.7 32.771 2.1 8.2 5.0 0.6 x t(1) 0.6 x t(1) 20 20
Units
MHz MHz MHz MHz MHz ns ns ns ns
Figure 4-1. Minimum Clock Pulse Widths
1 2 90% 50% 10% 3
4
5
4-4
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 4-5. Input Data Setup and Hold Timing Symbol
1 (tsetup)
4.0 Electrical/Mechanical Specifications
4.4 AC Characteristics
Clock
MCLK
Edge
Rising
Input Data
ONESEC RST*
Minimum
5 5 2 2 6 5 5 5 5 5 5 5 5 3 3 2 5 5 2 5 2 2
Maximum
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RCKI
Rising
RPOSI RNEGI
TDLCKO RSBCKI
Falling RSYN_NEG (addr 0D1) TPCM_NEG (addr 0D4) TSYN_NEG (addr 0D4)
TDLI RMSYNC RFSYNC
TSBCKI TCKI(1)
TPCMI TSIGI TFSYNC TMSYNC
2 (thold)
MCLK
Rising
ONESEC RST*
RCKI
Rising
RPOSI RNEGI
TDLCKO RSBCKI
Falling RSYN_NEG (addr 0D1) TPCM_NEG (addr 0D4) TSYN_NEG (addr 0D4)
TDLI RMSYNC RFSYNC
TSBCKI TCKI(1)
TPCMI TSIGI TFSYNC(2) TMSYNC
NOTE(S):
(1)
If the TSLIP buffer is bypassed (TSB_CR; addr OD4), TCKI is used; otherwise, TSBCKI is used.
100054E
Conexant
4-5
4.0 Electrical/Mechanical Specifications
4.4 AC Characteristics
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table 4-6. Output Data Delay Timing Symbol
1 (tdelay)
Clock
MCLK
Edge
Rising
Output Data
ONESEC INTR
Minimum
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maximum
10 10 15 20 28 28 10 10 20 20 10 20 20 10 10 10 10 10
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TCKI or ACKI
-- -- Rising
TCKO TDLCKO TNRZO MSYNCO
TCKO
Rising
TPOSO TNEGO
RDLCKO RSBCKI
Rising RPCM_NEG (addr 0D1)
RDLO RPCMO RSIGO RINDO SIGFRZ
RSYN_NEG (addr 0D1) TSBCKI TCKI(1) TPCM_NEG (addr 0D4) TSYN_NEG (addr 0D4)
NOTE(S):
(1)
RFSYNC RMSYNC TINDO TFSYNC TMSYNC
If the TSLIP buffer is bypassed (TSB_CR; addr OD4), TCKI is used; otherwise, TSBCKI is used.
Table 4-7. One-Second Input/Output Timing Symbol
1 2 Input Pulse Width Output Pulse Width
Parameter
Minimum
1/MCLK 125
Maximum
1 second - 125 s 250
Units
As shown s
4-6
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-2. Input Data Setup/Hold Timing
4.0 Electrical/Mechanical Specifications
4.4 AC Characteristics
Clock 1 Rising Edge Input Data 2
1 Falling Edge Input Data
2
Figure 4-3. Output Data Delay Timing
Clock 1 1
Rising Edge Output Data
Falling Edge Output Data
Figure 4-4. One-Second Input/Output Timing
1 ONESECI
2 ONESECO
NOTE(S): ONESEC pin can be either an input (ONESECI) or an output (ONESECO).
100054E
Conexant
4-7
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
4.5 MPU Interface Timing
Figure 4-5. Motorola Asynchronous Read Cycle
MOTO* = 0, SYNCMD = 0 1 AS* 2 A[8:0] Address 3 CS*
R/W*
DS* 4 AD[7:0] 5 Read Data
Table 4-8. Motorola Asynchronous Read Cycle Symbol
1 2 3 4 5
Parameter
AS* high pulse width A[8:0] Address setup to AS* low A[8:0] Address hold after AS* low CS* low and R/W* high, and DS* low to AD[7:0] valid CS* high and DS* high, and R/W* low to AD[7:0] invalid/three-state
Minimum
15 5 10 -- 5
Maximum
-- -- -- 80 20
Units
ns ns ns ns ns
4-8
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-6. Motorola Asynchronous Write Cycle
MOTO* = 0, SYNCMD = 0 1 AS* 2 A[8:0] Address 3 CS* 4 R/W* 8 9
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
7 DS* 5 AD[7:0] Write Data 6
Table 4-9. Motorola Asynchronous Write Cycle Symbol
1 2 3 4 5 6 7 8 9
Parameter
AS* high pulse width A[8:0] Address setup to AS* low A[8:0] Address hold after AS* low CS* low and R/W* low to DS* low AD[7:0] setup to DS* low AD[7:0] hold after DS* low DS* low pulse width CS*, R/W* hold after DS* low DS* low to AS* high
Minimum
15 5 2 5 0 15 38 38 70
Maximum
-- -- -- -- -- -- -- -- --
Units
ns ns ns ns ns ns ns ns ns
100054E
Conexant
4-9
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-7. Intel Asynchronous Read Cycle
MOTO* = 1, SYNCMD = 0 1 ALE 2 A[8] Address 3 AD[7:0] Address 4 RD* 6 Read Data 7 9
WR* 5 CS* 8
Table 4-10. Intel Asynchronous Read Cycle Symbol
1 2 3 4 5 6 7 8 9
Parameter
ALE high pulse width A[8], AD[7:0] Address setup to ALE low A[8], AD[7:0] Address hold after ALE low ALE low to RD* and CS* both low WR* high setup to RD* and CS* both low RD* and CS* both low to AD[7:0] valid RD* or CS* high to AD[7:0] invalid/three-state WR* high hold after RD* or CS* high RD* or CS* high to next ALE
Minimum
15 2 5 0 0 -- 0 0 0
Maximum
-- -- -- -- -- 80 25 -- --
Units
ns ns ns ns ns ns ns ns ns
4-10
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-8. Intel Asynchronous Write Cycle
MOTO* = 1, SYNCMD = 0 1 ALE 2 A[8] Address 3 AD[7:0] Address 6
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
9
Write Data 7
WR* 5 RD* 4 8
CS*
Table 4-11. Intel Asynchronous Write Cycle Symbol
1 2 3 4 5 6 7 8 9
Parameter
ALE high pulse width A[8], AD[7:0] Address setup to ALE low A[8], AD[7:0] Address hold after ALE low CS*, RD* setup to WR* low WR* pulse width low AD[7:0] input data setup to WR* or CS* high AD[7:0] input data hold after WR* or CS* high RD* hold after WR* or CS* high End write cycle to next ALE high
Minimum
15 2 5 0 20 2 10 0 55
Maximum
-- -- -- -- -- -- -- -- --
Units
ns ns ns ns ns ns ns ns ns
100054E
Conexant
4-11
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-9. Motorola Synchronous Read Cycle
MOTO* = 0, SYNCMD = 1 MCLK 1 AS* 2 A[8:0] Address 3 CS* 4 DTACK* 6 R/W* 5 9
DS* 7 AD[7:0] 8 Read Data
Table 4-12. Motorola Synchronous Read Cycle Symbol
1 2 3 4 5 6 7 8 9
Parameter
AS* high pulse width A[8:0] Address setup to AS* low A[8:0] Address hold after AS* low AS* and CS* low to DTACK* low AS* or CS* high to DTACK* high AS*, DS*, CS*, R/W* setup to MCLK high DS* sampled low to AD[7:0] valid CS* or DS* high to AD[7:0] invalid/three-state MCLK high to AS* high
Minimum
15 2 2 0 0 15 -- 0 1/MCLK + 12
Maximum
-- -- -- 10 10 -- 0.5/MCLK +20 30 --
Units
ns ns ns ns ns ns ns ns ns
4-12
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-10. Motorola Synchronous Write Cycle
MOTO* = 0, SYNCMD = 1 MCLK 1 AS* 2 A[8:0] Address 3 DTACK* 4 CS* 6 R/W* 9 DS* 7 AD[7:0] Write Data 8 10 12 11
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
5
Table 4-13. Motorola Synchronous Write Cycle Symbol
1 2 3 4 5 6 7 8 9 10 11 12
Parameter
AS* high pulse width A[8:0] Address setup to AS* low A[8:0] Address hold after AS* low AS* and CS* low to DTACK* low AS* or CS* high to DTACK* high CS* and R/W* low to DS* low AD[7:0] setup to DS* low AD[7:0] hold after DS* low DS* setup to MCLK high DS* hold after MCLK high DS* sampled low to data latch (internal) DS* sampled low to AS* high
Minimum
15 5 2 0 0 2 2 5 2 5 -- 1/2 MCLK + 15
Maximum
-- -- -- 10 10 -- -- -- -- -- 1/MCLK+15 --
Units
ns ns ns ns ns ns ns ns ns ns ns ns
100054E
Conexant
4-13
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-11. Intel Synchronous Read Cycle
MOTO* = 1, SYNCMD = 1 MCLK 1 ALE 2 A[8] Address 3 AD[7:0] Address 4 RD* 5 6 7 Read Data 8 9
WR*
CS*
Table 4-14. Intel Synchronous Read Cycle Symbol
1 2 3 4 5 6 7 8 9
NOTE(S):
(1)
Parameter
ALE high pulse width A[8], AD[7:0] Address setup to ALE low A[8], AD[7:0] Address hold after ALE low ALE low to RD* and CS* both low RD*, CS*, WR* setup to MCLK high (Start RD cycle) RD*, CS*, WR* hold after MCLK high Start RD* cycle to AD[7:0] valid RD* or CS* high to AD[7:0] invalid/three-state End RD cycle to next ALE high
Minimum
15 2 5 5 3 5 -- 0 0
Maximum
-- -- -- -- -- -- (1) 25 --
Units
ns ns ns ns ns ns ns ns ns
Parameter 7 equals 40 ns or 1/2* MCLK + 17 ns, whichever is greater.
4-14
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-12. Intel Synchronous Write Cycle
MOTO* = 1, SYNCMD = 1 MCLK 1 ALE 2 A[8] Address 3 AD[7:0] Address 6 8
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
Write Data 7
WR*
RD* 4 CS* 5
Table 4-15. Intel Synchronous Write Cycle Symbol
1 2 3 4 5 6 7 8
Parameter
ALE high pulse width A[8], AD[7:0] Address setup to ALE low A[8], AD[7:0] Address hold after ALE low WR*,RD*,CS* setup to MCLK high (start WR cycle) WR*,RD*,CS* hold after MCLK high Start WR* cycle to AD[7:0] input data valid AD[7:0] input data hold after Start WR cycle Start WR cycle to next ALE high
Minimum
15 2 5 2 5 -- 1/MCLK+9 1/MCLK+10
Maximum
-- -- -- -- -- 1/MCLK-10 -- --
Units
ns ns ns ns ns ns ns ns
100054E
Conexant
4-15
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-13. Serial Control Port Timing
Read Timing
CS\
SCLK
SDI
R/W A0 1
A1
A2
A3
A4
A5
A6
Address/Control Byte D0 D1 D2 D3 D4 D5 D6 D7
SDO
Register Data Byte
Write Timing
CS\
SCLK
SDI
R/W A0 0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
Address/Control Byte
Register Data Byte
8394-8-5_071
SDO
Figure 4-14. Serial Control Port Write Timing
SERCS*
1
2
3
SERCKO
Address/Command Byte
Write Data Byte
4-16
Conexant
100054E
8394-8-5_072
SERDO
A0
A1
D5
D6
D7
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-15. Serial Control Port Read Timing
4.0 Electrical/Mechanical Specifications
4.5 MPU Interface Timing
SERCS*
1 2 3
SERCKO
4
5
SERDO
1
A0
Address/Command Byte
A1
SERDI
D5
D6
D7
8394-8-5_073
Read Data Byte
Table 4-16. Host Serial Port Timing Symbol
1 2, 3 2, 3 4 5 --
Parameter
SERCKO Falling Edge to SERCS* and SERDO SERCKO Duty Cycle SERCKO Frequency (Programmable) SERDI to SERCKO Rising Edge Setup Time SERCKO Rising Edge to SERDI Hold Time Rise/Fall Time (10% to 90%) SERCKO, SERDI, SERDO
Minimum
10 40 1.024 10 5 --
Maximum
-- 60 8.192 -- -- 20
Units
ns % MHz ns ns ns
100054E
Conexant
4-17
4.0 Electrical/Mechanical Specifications
4.6 System Bus Interface (SBI) Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
4.6 System Bus Interface (SBI) Timing
Figure 4-16. SBI Timing--1536K Mode(1)
Transmit TSBCKI TSYNCO TSYNCI TSYNCO
(3)
Receive RSBCKI RSYNCO RSYNCI RSYNCO
(3) (4) (4)
Offset = 008 (TS1, Bit1) X2CLK = 0
Offset = 018
(5)
TSYNCI TSYNCO TSYNCI
RSYNCI RSYNCO Offset = 0C7 RSYNCI TS24 TS1 TS2 TS3
TPCMI SBI Signal Group
RPCMO
567812345678123456781234 SIG24 SIG1 ABCD SIG2 ABCD
TSIGI
(2)
RSIGO
(2)
ABCD
TINDO
RINDO
SIGFRZ
TSBCKI X2CLK = 1 TSYNCO TSYNCI TSYNCO TSYNCI
RSBCKI RSYNCO Offset = 008 RSYNCI RSYNCO Offset = 018 RSYNCI
(5)
NOTE(S):
(1) (2) (3) (4) (5)
Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for other edge combinations. RINDO/TINDO programmed high or low on a per-time slot basis (SBCn; addr 0E0-0FF). TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offset. Multiple offset values shown for illustration, refer to OFFSET controls (addr 0D2-0D3, 0D5-0D6). X2CLK control bit located in SBI_CR (addr 0D0).
4-18
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-17. SBI Timing--1544K Mode(1)
Transmit TSBCKI TSYNCO TSYNCI TSYNCO
(3)
4.0 Electrical/Mechanical Specifications
4.6 System Bus Interface (SBI) Timing
Receive RSBCKI
(4)
RSYNCO Offset = 000 (F-bit) RSYNCI RSYNCO
(3) (4)
X2CLK = 0
Offset = 00F
(5)
TSYNCI TSYNCO TSYNCI
RSYNCI RSYNCO Offset = 0C7 RSYNCI TS24 TS1 TS2 TS3
TPCMI SBI Signal Group
RPCMO
5678F12345678123456781234 SIG24 SIG1 ABCD SIG2 ABCD
TSIGI
(2)
RSIGO
(2)
F ABCD
TINDO
RINDO
SIGFRZ
TSBCKI X2CLK = 1 TSYNCO TSYNCI TSYNCO TSYNCI
RSBCKI RSYNCO Offset = 000 RSYNCI RSYNCO Offset = 00F RSYNCI
(5)
NOTE(S):
(1) (2) (3) (4) (5)
Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for other edge combinations. RINDO/TINDO programmed high or low during F-bit (SBC0; addr 0E0). TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offset. Multiple offset values shown for illustration, refer to OFFSET controls (addr 0D2-0D3, 0D5-0D6). X2CLK control bit located in SBI_CR (addr 0D0).
100054E
Conexant
4-19
4.0 Electrical/Mechanical Specifications
4.6 System Bus Interface (SBI) Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-18. SBI Timing--2048K Mode(1)
Transmit TSBCKI TSYNCO TSYNCI TSYNCO
(3)
Receive RSBCKI RSYNCO RSYNCI RSYNCO
(3) (4) (4)
Offset = 000 (TS0, Bit1) X2CLK = 0
Offset = 00B
(5)
TSYNCI TSYNCO TSYNCI
RSYNCI RSYNCO Offset = 0FF RSYNCI TS31 TS0 TS1 TS2
TPCMI SBI Signal Group
RPCMO
567812345678123456781234 SIG31 SIG0 ABCD SIG1 ABCD
TSIGI
(2)
RSIGO
(2)
ABCD
TINDO
RINDO
SIGFRZ
TSBCKI X2CLK = 1 TSYNCO TSYNCI TSYNCO TSYNCI
RSBCKI RSYNCO Offset = 000 RSYNCI RSYNCO Offset = 00B RSYNCI
(5)
NOTE(S):
(1) (2) (3) (4) (5)
Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for other edge combinations. RINDO/TINDO programmed high or low on a per-time slot basis (SBCn; addr 0E0-0FF). TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offset. Multiple offset values shown for illustration, refer to OFFSET controls (addr 0D2-0D3, 0D5-0D6). X2CLK control bit located in SBI_CR (addr 0D0).
4-20
Conexant
100054E
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-19. SBI Timing--4096K Mode(1),(5)
4.0 Electrical/Mechanical Specifications
4.6 System Bus Interface (SBI) Timing
SBCKI SYNCO Offset = 000 X2CLK = 0 SYNCI SYNCO Offset = 008 SYNCI SYNCO Offset = 1FF SYNCI TS0A BUSSED GroupA TS31B GroupB 4 5 6 7 8 12345678 TS0B 12345678 TS1A 12345678 TS1B 1234
NON-BUSSED
TS31A
TS0A
TS0A
TS1A
TS1A
GroupA 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 TS31B TS0B TS0B TS1B TS1B
GroupB 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4
SBCKI SYNCO X2CLK = 1 Offset = 000 SYNCI SYNCO Offset = 008 SYNCI
NOTE(S):
1. Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for other edge combinations. 5. BUSSED or NON-BUSSED signal group controls located in BUS_RSB, BUS_FRZ (addr 0D1) and BUS_TSB (addr 0D4).
100054E
Conexant
4-21
4.0 Electrical/Mechanical Specifications
4.6 System Bus Interface (SBI) Timing
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-20. SBI Timing--8192K Mode
SBCKI SYNCO Offset = 000 X2CLK = 0 SYNCI SYNCO Offset = 010 SYNCI SYNCO Offset = 3FF SYNCI
TS0A GroupA BUSSED 12345678 TS0B GroupB 12345678 TS0C GroupC TS31D GroupD 4 5 6 7 8 12345678 TS0D 1234
TS31A NON-BUSSED
TS0A
TS0A
TS0A
TS0A
GroupA 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 TS31B TS0B TS0B TS0B TS0B
GroupB 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 TS31C TS0C TS0C TS0C TS0C
GroupC 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 TS31D TS0D TS0D TS0D TS0D
GroupD 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4
SBCKI SYNCO X2CLK = 1 Offset = 000 SYNCI SYNCO Offset = 010 SYNCI
4-22
Conexant
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Quad/x16/Octal--T1/E1/J1 Framers
4.0 Electrical/Mechanical Specifications
4.6 System Bus Interface (SBI) Timing
Figure 4-21. SBI Timing--Eight Clock Edge Combinations (Applicable to Any SBI Mode)
SBCKI
PCM SYNC
X2CLK PCM_NEG SYN_NEG 0 0 0
PCM SYNC
X2CLK PCM_NEG SYN_NEG 0 0 1
PCM SYNC
X2CLK PCM_NEG SYN_NEG 0 1 0
PCM SYNC
X2CLK PCM_NEG SYN_NEG 0 1 1
SBCKI
PCM SYNC
X2CLK PCM_NEG SYN_NEG 1 0 0
PCM SYNC
X2CLK PCM_NEG SYN_NEG 1 0 1
PCM SYNC
X2CLK PCM_NEG SYN_NEG 1 1 0
PCM SYNC
X2CLK PCM_NEG SYN_NEG 1 1 1
LEGEND:
Rising Edge Sample Falling Edge Sample
Rising Edge Output Falling Edge Output
NOTE(S): PCM output/sample points are shown only for the corresponding SYNC output/sample point.
100054_004
100054E
Conexant
4-23
4.0 Electrical/Mechanical Specifications
4.7 JTAG Interface Timing
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Quad/x16/Octal--T1/E1/J1 Framers
4.7 JTAG Interface Timing
Table 4-17. Test and Diagnostic Interface Timing Requirements
Symbol 1 2 3 4 TCK pulse width high TCK pulse width low TMS, TDI setup to TCK rising edge TMS, TDI hold after TCK high Parameter Minimum 80 80 5 20 Maximum -- -- -- -- Units ns ns ns ns
Table 4-18. Test and Diagnostic Interface Switching Characteristics
Symbol 5 6 7 8 Parameter TDO hold after TCK falling edge TDO delay after TCK low TDO enable (Low Z) after TCK falling edge TDO disable (High Z) after TCK low Minimum 0 -- 10 -- Maximum -- 20 -- 10 Units ns ns ns ns
Figure 4-22. JTAG Interface Timing
TDO 7 1 5 6 8
TCK 3 4 2
TDI TMS
4-24
Conexant
100054E
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Quad/x16/Octal--T1/E1/J1 Framers
4.0 Electrical/Mechanical Specifications
4.8 Mechanical Specifications
4.8 Mechanical Specifications
Figure 4-23. 318-Pin Ball Grid Array (BGA)
27.000 24.000 Triangle Pin #1 Indicator 18.000 R .500 TYP 3 PL SEATING PLANE .600 .100
2.000 Dia. TYP 4 PL (Ejector Pin) 18.000 24.000 27.000
15
.520 .070 R 1.7 MM TYP 4 PL 1.414 Chamfer Optional
TOP VIEW
Engraving Cavity ID
1.100 .050 2.220 .220
24.130 12.065 1.270 Pin #1 Triangle
SIDE VIEW
20 10 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y
24.130
1.270
NOTES: - ALL DIMENSIONS ARE IN MILLIMETERS (MM). - REFLOW APPLIES TO SOLDERING TO HOST PC BOARD. - THERMAL BALLS IN CENTER CONNECTED TO GROUND.
8394-8-5_010
12.065
BOTTOM VIEW
5 Perimeter Rows + 18 Balls (1.27 MM Pitch)
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4-25
4.0 Electrical/Mechanical Specifications
4.8 Mechanical Specifications
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-24. 272-Pin Ball Grid Array (BGA)
27.000 24.000 Triangle Pin #1 Indicator 18.000 R .500 TYP 3 PL SEATING PLANE .600 .100
2.000 Dia. TYP 4 PL (Ejector Pin) 18.000 24.000 27.000
15
.520 .070 R 1.7 MM TYP 4 PL 1.414 Chamfer Optional
TOP VIEW
Engraving Cavity ID
1.100 .050 2.220 .220
24.130 12.065 1.270 Pin #1 Triangle
SIDE VIEW
20 10 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y
24.130
1.270
NOTES: - ALL DIMENSIONS ARE IN MILLIMETERS (MM). - REFLOW APPLIES TO SOLDERING TO HOST PC BOARD. - THERMAL BALLS IN CENTER CONNECTED TO GROUND.
8394-8-5_009
12.065
BOTTOM VIEW
4 Perimeter Rows + 16 Balls (1.27 MM Pitch)
4-26
Conexant
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Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-25. 208-Pin Ball Grid Array (CABGA)
4.0 Electrical/Mechanical Specifications
4.8 Mechanical Specifications
D
D1
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 A B C D E F G H J K L M N P R T U
e E
E1
e
b
TOP VIEW BOTTOM VIEW
(208 Solder Balls)
A1 A2
Dim.
Millimeters Min. Max. Min.
Inches Max.
c A
A 1.50 1.059 A1 0.31 0.41 0.12 0.016 A2 0.65 0.76 0.026 0.030 D 15.00 REF. 0.591 REF. D1 12.80 REF. 0.504 REF. E 15.00 REF. 0.591 REF. E1 12.80 REF. 0.504 REF. M 17 N 208 e 0.80 REF. 0.031 REF. b 0.48 REF. 0.018 REF. c 0.29 0.39 0.011 0.015 Coplanarity 0.12 MAX. 0.005 MAX. Warpage 0.10 MAX. 0.004 MAX. Ref: 208-Pin CABGA (GP00-D576-001)
SIDE VIEW
100054_002
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Conexant
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4.0 Electrical/Mechanical Specifications
4.8 Mechanical Specifications
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-26. 208-Pin Plastic Quad Flat Pack (PQFP)
E E1 E2
PIN 1 REF
D2 D1 D
D1
e
b DETAIL A S Y M B O L A A1 A2 D D1 D2 E E1 E2 L L1 e b c ALL DIMENSIONS IN MILLIMETERS MIN. 3.64 0.25 3.39 30.40 27.90 30.40 27.29 0.50 NOM. MAX 4.09 0.50 3.50 30.80 28.10 30.80 27.99
E1
A
A2
c
DETAIL A
L1
4-28
Conexant
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8394-8-5_008
A1
L
0.75 1.00 REF. 0.500 0.215 0.225
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Quad/x16/Octal--T1/E1/J1 Framers
Figure 4-27. 128-Pin (TQFP) Mechanical Drawing
E E1 E2
4.0 Electrical/Mechanical Specifications
4.8 Mechanical Specifications
2.00
PIN 1 REF
2.00
D2 D1 D
D1
PIN 1 REF MARK
e
b S Y M B O L A A1 A2 D D1 D2 E E1 E2 L L1 e b c ALL DIMENSIONS IN MILLIMETERS MIN. 1.6 MAX. 0.10 1.4 REF 21.85 20.0 REF 18.5 REF 15.8 14.0 REF 12.5 REF 0.4 1.0 REF 0.50 BSC
8394-8-5_002
DETAIL A
MAX 0.15 22.15
E1
16.15
A
A2
c
0.65
A1
L
DETAIL A
L1
0.17 0.11
0.27 0.17
Ref. 128-PIN TQFP (GP00-D268)
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4.0 Electrical/Mechanical Specifications
4.8 Mechanical Specifications
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Quad/x16/Octal--T1/E1/J1 Framers
4-30
Conexant
100054E
A
Appendix A
A.1 Superframe Format (SF)
The Superframe Format (SF), is also referred to as the D4 format. The requirement for associated signaling in frames 6 and 12 dictates that the frames be distinguishable. This leads to a multiframe structure consisting of 12 frames per superframe (SF). See Figure A-1 and Tables A-1 and A-2. The SF structure consists of a multiframe of 12 frames. Each frame has 24 channels, plus an F-bit, and 8 bits per channel. A channel is equivalent to one voice circuit or one 64 kbps data circuit. This structure of frames and multiframes is defined by the F-bit pattern. The F-bit is designated alternately as an Ft bit (terminal framing bit) or Fs bit (signalling framing bit). The Ft bit carries a pattern of alternating zeros and ones (101010) in odd frames that defines the frame boundaries so that one channel may be distinguished from another. The Fs bit carries a pattern of (001110) in even frames and defines the multiframe boundaries so that one frame may be distinguished from another.
Figure A-1. T1 Superframe PCM Format
Signaling Information 8 Bits per Channel 1 2 3 4 5 6 7 8 B A Bit 8 During: Frame 12 Frame 6
Ft or Fs
CH 1
CH 2
CH 13
CH 24
24 Channels per Frame Frame = 193 Bits
FR 1
FR 2
FR 7
FR 11
FR 12
Multiframe SF = 12 Frames
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A-1
Appendix A
A.1 Superframe Format (SF)
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Quad/x16/Octal--T1/E1/J1 Framers
Table A-1. Superframe Format F-Bits Frame # Bit # Terminal Framing Ft
1 -- 0 -- 1 -- 0 -- 1 -- 0 --
Bit Use in Each Time Slot Signaling Framing Fs
-- 0 -- 0 -- 1 -- 1 -- 1 -- 0
Traffic
1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7
Sig
-- -- -- -- -- 8 -- -- -- -- -- 8
Signaling Channel
-- -- -- -- -- A -- -- -- -- -- B
1 2 3 4 5 6 7 8 9 10 11 12
0 193 386 579 772 965 1158 1351 1544 1737 1930 2123
A-2
Conexant
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Appendix A
A.2 T1DM Format
A.2 T1DM Format
Table A-2. T1DM Frame Format F-Bits Frame # Bit # Terminal Framing Ft
1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 0 185-192 193 378-385 386 571-578 579 764-771 772 957-964 965 1150-1157 1158 1343-1350 1351 1536-1543 1544 1729-1736 1737 1922-1929 1930 2115-2122 2123 1 -- -- -- 0 -- -- -- 1 -- -- -- 0 -- -- -- 1 -- -- -- 0 -- --
Bit Use in Each Time Slot Sync Byte
-- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 -- 10111YR0 --
Signaling Framing Fs
-- -- 0 -- -- -- 0 -- -- -- 1 -- -- -- 1 -- -- -- 1 -- -- -- 0
Info
1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7 -- 1-7
Ctrl
8 -- 8 -- 8 -- 8 -- 8 -- 8 -- 8 -- 8 -- 8 -- 8 -- 8 -- 8
Note(s): 1. Y bit is used to indicate a Yellow Alarm (active low). 2. R bit is used solely by AT&T as an 8Kpbs communications channel to collect performance data on long haul DDS facilities.
100054E
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A-3
Appendix A
A.3 SLC 96 Format (SLC)
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Quad/x16/Octal--T1/E1/J1 Framers
A.3 SLC 96 Format (SLC)
SLC framing mode allows synchronization to the SLC 96 data link pattern. This pattern, described in the Bellcore TR-TSY-000008, contains both signaling information and a framing pattern that overwrites the Fs bit of the SF framer pattern. (See Table A-3).
Table A-3. SLC-96 Fs Bit Contents Frame #
2 4 6 8 10 12 14 16 18 20 22 24
Fs Bit
0 0 1 1 1 0 0 0 1 1 1 C1
Frame #
26 28 30 32 34 36 38 40 42 44 46 48
Fs Bit
C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 0 1
Frame #
50 52 54 56 58 60 62 64 66 68 70 72
Fs Bit
0 M1 M2 M3 A1 A2 S1 S2 S3 S4 1 0
Note(s): 1. The SLC-96 frame format is similar to that of SF as shown in Table A-1 with the exceptions shown in this table. 2. C1 to C11 are concentrator field bits. 3. M1 to M3 are maintenance field bits. 4. A1 and A2 are alarm field bits. 5. S1 to S4 are line switch field bits. 6. The Fs bits in frames 46, 48, and 70 are spoiler bits which are used to protect against false multiframing.
A-4
Conexant
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Appendix A
A.4 Extended Superframe Format (ESF)
A.4 Extended Superframe Format (ESF)
In Extended Superframe Format (ESF), as illustrated in Figure A-2 and Table A-4, the multiframe structure is extended to 24 frames. The channel structure is identical to D4 (SF) format. Robbed-bit signaling is accommodated in frame 6 (A-bit), frame 12 (B-bit), frame 18 (C-bit), and frame 24 (D-bit). The F-bit pattern of ESF contains three functions: 1. Framing Pattern Sequence (FPS), which defines the frame and multiframe boundaries. 2. Facility Data Link (FDL), which allows data such as error performance to be passed within the T1 link. 3. Cyclic Redundancy Check (CRC), which allows error performance to be monitored and enhances the reliability of the receiver's framing algorithm.
Figure A-2. T1 Extended Superframe Format
Signaling Information D C 8 Bits per Channel 1 2 3 4 5 6 7 8 B A Bit 8 During: Frame 24 Frame 18 Frame 12 Frame 6
CRC FDL FPS CH or 1 Fs
CH 2
CH 13
CH 24
24 Channels per Frame Frame = 193 Bits
FR 1
FR 2
FR 13
FR 23
FR 24
Multiframe ESF = 24 Frames
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A-5
Appendix A
A.4 Extended Superframe Format (ESF)
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Quad/x16/Octal--T1/E1/J1 Framers
Table A-4. Extended Superframe Format F-Bits Frame # Bit # FPS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 193 386 579 772 965 1158 1351 1544 1737 1930 2123 2316 2509 2702 2895 3088 3281 3474 3667 3860 4053 4246 4439 -- -- -- 0 -- -- -- 0 -- -- -- 1 -- -- -- 0 -- -- -- 1 -- -- -- 1
Bit Use in Each Time Slot CRC
-- C1 -- -- -- C2 -- -- -- C3 -- -- -- C4 -- -- -- C5 -- -- -- C6 -- --
Signaling Channel 16
-- -- -- -- -- A -- -- -- -- -- B -- -- -- -- -- C -- -- -- -- -- D
DL
m -- m -- m -- m -- m -- m -- m -- m -- m -- m -- m -- m --
Traffic
1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7
Sig
-- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- 8
4
-- -- -- -- -- A -- -- -- -- -- B -- -- -- -- -- A -- -- -- -- -- B
2
-- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- A
Note(s): 1. FPS indicates the Framing Pattern Sequence (...001011...). 2. DL indicates the 4Kbps Data Link with message bits m. 3. CRC indicates the cyclic redundancy check with bits C1 to C6. 4. Signaling options include 16 state, 4 state, and 2 state.
A-6
Conexant
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Table A-5. Performance Report Message Structure Octet No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 G3 FE G3 FE G3 FE G3 FE LV SE LV SE LV SE LV SE G4 LB G4 LB G4 LB G4 LB U1 G1 U1 G1 U1 G1 U1 G1 SAPI TEI CONTROL U2 R U2 R U2 R U2 R G5 G2 G5 G2 G5 G2 G5 G2 SL Nm SL Nm SL Nm SL Nm
Appendix A
A.4 Extended Superframe Format (ESF)
LSB
FLAG C/R
MSB
EA EA
G6 NI G6 NI G6 NI G6 NI
FCS (Most Significant Byte) FCS (Least Significant Byte)
Note(s): 1. The 1-second report consists of octets 5-12. 2. R, U1, and U2 are reserved for future standardization and should be set to 0.
100054E
Conexant
A-7
Appendix A
A.5 E1 Frame Format
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Quad/x16/Octal--T1/E1/J1 Framers
A.5 E1 Frame Format
Figure A-3. E1 Format
Time Slot 0 a. Even Frames (0, 2, 4-14) I 0011011 FAS b. Odd Frames (1, 3, 5-15) 8 Bits/ Time Slot I 1ANNNNN Time Slot 16 a. Frame 0 0000XYXX MAS Channel Data b. Frames 1-15 ABCDABCD 123 45 67 8 Time Slots 1-15, 17-31
32 Time Slots/Frame
TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16 Frames/Multiframe
FR 0
FR 1
FR 2
FR 3
FR 4
FR 5
FR 6
FR 7
FR 8
FR 9
FR 10
FR 11
FR 12
FR 13
FR 14
FR 15
A-8
Conexant
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Table A-6. ITU-T CEPT Frame Format Time Slot 0 Bit Allocations SMF Frame # 1
0 1 I 2 3 4 5 6 7 8 9 II 10 11 12 13 14 15 C1/Si 0/Si C2/Si 0/Si C3/Si 1/Si C4/Si 0/Si C1/Si 1/Si C2/Si 1/Si C3/Si E/Si C4/Si E/Si
Appendix A
A.5 E1 Frame Format
Time Slot 0 Bits 1 to 8 of each frame 2
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
3
0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A
4
1 SA4 1 SA4 1 SA4 1 SA4 1 SA4 1 SA4 1 SA4 1 SA4
5
1 SA5 1 SA5 1 SA5 1 SA5 1 SA5 1 SA5 1 SA5 1 SA5
6
0 SA6 0 SA6 0 SA6 0 SA6 0 SA6 0 SA6 0 SA6 0 SA6
7
1 SA7 1 SA7 1 SA7 1 SA7 1 SA7 1 SA7 1 SA7 1 SA7
8
1 SA8 1 SA8 1 SA8 1 SA8 1 SA8 1 SA8 1 SA8 1 SA8
Note(s): 1. SMF indicates the sub-multiframe. This partitioning is used in the CRC-4 calculation. 2. Si bits are International Spare Bits. 3. A bit is used to indicate a remote alarm condition (active high). 4. SA4 to SA8 are spare bits that may be recommended by ITU-T for use in specific point-to-point applications (e.g., transcoder equipment conforming to Recommendation G.761). 5. SA4 to SA8 where these are not used should be set to 1 on links crossing an international border. 6. E bit is used to indicate a CRC-4 error. The normal state is both bits set to 1; when a CRC-4 error is detected, one of the E bits is set to 0. 7. C1 to C4 bits are used to carry the CRC-4 code. 8. Time slot 0 that contains the 0011011 sequence is defined as the FAS word. Time slot 0 that does not contain the FAS is the Not-Word.
100054E
Conexant
A-9
Appendix A
A.6 IRSM CEPT Frame Format
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Quad/x16/Octal--T1/E1/J1 Framers
A.6 IRSM CEPT Frame Format
Table A-7. IRSM CEPT Frame Format Time Slot 0 Bit Allocations SMF Frame # 1
0 1 I 2 3 4 5 6 7 8 9 II 10 11 12 13 14 15 C1/Si 0/Si C2/Si 0/Si C3/Si 1/Si C4/Si 0/Si C1/Si 1/Si C2/Si 1/Si C3/Si E/Si C4/Si E/Si
Time Slot 0 Bits 1 to 8 of each frame 2
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
3
0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A
4
1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D
5
1 E0 1 E2 1 E4 1 E6 1 E8 1 E10 1 E12 1 E14
6
0 E1 0 E3 0 E5 0 E7 0 E9 0 E11 0 E13 0 E15
7
1 E16 1 E18 1 E20 1 E22 1 E24 1 E26 1 E28 1 E30
8
1 E17 1 E19 1 E21 1 E23 1 E25 1 E27 1 E29 1 E31
Note(s): 1. SMF indicates the sub-multiframe. This partitioning is used in the CRC-4 calculation. 2. Si bits are International Spare Bits. 3. NA bit is used to indicate a remote alarm condition (active high). 4. Ei are per channel control bits. 5. E bit is used to indicate a CRC-4 error. The normal state is both bits set to 1; when a CRC-4 error is detected, one of the E bits is set to 0. 6. C1 to C4 bits are used to carry the CRC-4 code. 7. Time slot 0 that contains the 0011011 sequence is defined as the FAS word. Time slot 0 that does not contain the FAS is the Not-Word. 8. D bits are a 4 kbps data link. 9. Bit 2 of the Not-Word is defined as the alternate framing bit.
A-10
Conexant
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Table A-8. CEPT (ITU-T and IRSM) Frame Format Time Slot 16 Bit Allocations SMF Frame # 1
0 1 I 2 3 4 5 6 7 8 9 II 10 11 12 13 14 15 0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
Appendix A
A.6 IRSM CEPT Frame Format
Time Slot 16 Bits 1 to 8 of each frame 2
0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
3
0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
4
0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
5
X0 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
6
Y B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31
7
X1 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31
8
X2 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Note(s): 1. SMF indicates the sub-multiframe. 2. Ai-Di are the per channel signaling bits. 3. X0-X2 are the X spare bits normally set to 1. 4. Y is the Remote Multiframe Yellow Alarm Indication bit. When Y is set to a 1, this indicates that the alarm is active. 5. The Multiframe Alignment Sequence (MAS) is defined as the Time Slot 16 word that contains the 0000XYXX sequence.
100054E
Conexant
A-11
Appendix A
A.6 IRSM CEPT Frame Format
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A-12
Conexant
100054E
B
Appendix B
B.1 Applicable Standards
Table B-1. Applicable Standards (1 of 3) Standard
ANSI T1.101-1987 T1.102-1993 T1.107-1991 (Newer Draft Standard T1X1.4/93-002R3) T1.403-1995 T1.408-1990 T1.231-1993 Digital Hierarchy--Timing Synchronization Digital Hierarchy--Electrical Interfaces Digital Hierarchy--Formats Specification
Title
Network to Customer Installation--DS1 Metallic Interface ISDN Primary Rate--Customer Installation Metallic Interfaces Layer 1 In-Service Digital Transmission Performance Monitoring AT&T
TR 41449-1986 TR 43801(A)-1985 TR 54016-1989 TR 62411-1990
ISDN Primary Rate Interface Specification Digital Channel Bank--Requirements and Objectives Rqts. for Interfacing DTE to Services Employing Extended Superframe Format Accunet T1.5 Service Description and Interface Specification Bellcore
TR-TSY-000008 Issue 2, 1987 TR-TSY-000009 Issue 1, 1986 TR-NPL-000054 Issue 1, 1989 TR-NWT-000057 Issue 2, 1993 TA-TSY-000147 Issue 1, 1987 TR-TSY-000170 Issue 2, 1993 TR-TSY-000191 Issue 1, 1986
Digital Interface Between the SLC 96 Digital Loop Carrier System and a Local Digital Switch Asynchronous Digital Multiplexer Requirements and Objectives High-Capacity Digital Service (HCDS) Interface Generic Requirements Functional Criteria for Digital Loop Carrier Systems DS1 Rate Digital Service Monitoring Unit Digital Cross-Connect System (DCS) Requirements and Objectives Alarm Indication Signal (AIS) Requirements and Objectives
100054E
Conexant
B-1
Appendix B
B.1 Applicable Standards
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Table B-1. Applicable Standards (2 of 3) Standard
TR-TSY-000194 Issue 1, 1987 TA-TSY-000278 Issue 1, 1985 TR-TSY-000303 Issue 2, 1992 TR-TSY-000312 Issue 1, 1988 TR-NPL-000320 Issue 1, 1988 TA-TSY-000435 Issue 1, 1987 TR-NWT-000499 Issue 5, 1993 TR-TSY-000510 Issue 2, 1987 TR-NWT-000773 Issue 1, 1991 TR-TSY-000776 Issue 2, 1993 GR-820-CORE Issue 1, 1994 (replaced TR-NWT-000820) TA-NWT-000821 Issue 1, 1991 (replaced TR-TSY-000821) SR-TSY-000977 Issue 1, 1988 TR-NWT-001219 Issue 1, 1992 (Rev 1, 1993) SR-NWT-002343 Issue 1, 1993
Title
The Extended Superframe Format Interface Digital Data System (DDS)--T1 Digital Multiplexer (T1DM) Requirements Integrated Digital Loop Carrier (IDLC) System Generic Requirements Functional Criteria for the DS1 Interface Connector Fundamental Generic Requirements for Metallic Digital Signal Cross-connect Systems DS1 Automatic Facility Protection Switching (AFPS) Rqts. and Objectives Transport Systems Generic Requirements LSSGR: System Interfaces, Section 10 Local Access System Requirements, Objectives and Interfaces for SMDS Network Interface Description for ISDN Customer Access Generic Digital Transmission Surveillance Additional Transport and Transport-Based Surveillance Generic Rqts. ISDN Primary Rate Access Maintenance ISDN Primary Rate Access Testing Requirements ISDN Primary Rate Interface Guidelines for Customer Premises Equipment ETSI
ETS 300 011 (4/92) ETS 300 233
ISDN Primary Rate User-Network Interface Specification and Test Principles Access Digital Section for ISDN Primary Rate ITU-T
Recommendation G.703 (1991) Recommendation G.704 (1991) Recommendation G.706 (1991) Recommendation G.732 Recommendation G.733 Recommendation G.734 Recommendation G.735 Recommendation G.736 Recommendation G.737 Recommendation G.738 Recommendation G.739 Recommendation G.761
Physical/Electrical Characteristics of Hierarchical Digital Interfaces Synchronous Frame Structures used at Primary Hierarchical Levels Frame Alignment and CRC Procedures Relating to G.704 Frame Structures Characteristics of Primary PCM Multiplex Equipment at 2048 kbps Characteristics of Primary PCM Multiplex Equipment at 1544 kbps Characteristics of Synchronous Digital Multiplex Equipment at 1544 kbps Characteristics of Primary PCM Multiplex Equipment at 2048 kbps; offering Synchronous Digital Access at 384 kbps and/or 64 kbps Characteristics of Synchronous Digital Multiplex Equipment at 2048 kbps Characteristics of External Access Equipment at 2048 kbps; offering Synchronous Digital Access at 384 kbps and/or 64 kbps Characteristics of Primary PCM Multiplex Equipment at 2048 kbps; offering Synchronous Digital Access at 320 kbps and/or 64 kbps Characteristics of External Access Equipment at 2048 kbps; Offering Synchronous Digital Access at 320 kbps and/or 64 kbps
B-2
Conexant
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CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Table B-1. Applicable Standards (3 of 3) Standard
Draft Recommendation G.775 Recommendation G.796 Recommendation G.802 (1988) Recommendation G.821 Recommendation G.823 (3/93) Recommendation G.824 (3/93) Recommendation G.921 Recommendation G.962 (3/93) Recommendation G.963 (3/93) Recommendation I.411 Recommendation I.412 Recommendation I.421 Recommendation I.431 Recommendation K.10 Recommendation K.20 Recommendation M.3604 Recommendation O.150 Recommendation O.151 Recommendation O.152 Recommendation O.162 (10/92) Recommendation Q.921 IEEE Std 1149.1a-1993 Natural Microsystems Corporation, Release 1.0, March 1993 FCC Part 68.302 (d) FCC Part 68.308
Appendix B
B.1 Applicable Standards
Title
Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection Characteristics of 64 kbps Cross-Connect Equipment with 2048 kbps Access Ports Interworking between Networks based on Different Digital Hierarchies Error Performance Monitoring on International Connections Control of Jitter and Wander in Digital Networks based on 2048 kbps Control of Jitter and Wander in Digital Networks based on 1544 kbps Digital Sections based on 2048 kbps Hierarchy Access Digital Section for ISDN Primary Rate at 2048 kbps Access Digital Section for ISDN Primary Rate at 1544 kbps ISDN User-Network Interfaces--References Configurations ISDN User-Network Interfaces--Structures and Access Capabilities Primary Rate User-Network Interface Primary Rate User-Network Interface--Layer 1 Specification Unbalance about Earth of Telecommunication Installations Resistibility of Switching Equipment to Overvoltages and Overcurrents Application of Maintenance Principles to ISDN Primary Rate Access Digital Test Patterns for Performance Measurements Error Performance Measuring Equipment Operating at Primary Rate and Above Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and NX 64 kbit/s Equipment to Perform In-Service Monitoring on 2048 kbps Signals ISDN User-Network Interface - Data Link Layer Specification IEEE Standard Test Access Port and Boundary Scan Architecture (JTAG) Multi-Vendor Integration Protocol (MVIP) Reference Manual Environment Simulation metallic voltage surge Signal Power Limitations
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Appendix B
B.1 Applicable Standards
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
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C
Appendix C
C.1 System Bus Compatibility
C.1.1 AT&T Concentration Highway Interface (CHI):
DX = RPCMO + output on rising or falling edge of clock + output on every CLKXR or CLKXR/2 + Tri-stated during inactive time slots DR = TPCMI + sampled on rising or falling edge of clock + sampled on every CLKXR or CLKXR/2 (see X2CLK mode) FS = TFSYNC + sampled on rising or falling edge of clock (FE select) + rising edge determines frame start + 8 kHz rate TSC* = RINDO + Optional CHI pin is driven low during active DX time slots CLKXR = TSBCLKI = RSBCLKI + N x 64 kHz rates, where N = 4, 8, 16, 32, 48 or 64
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C-1
Appendix C
C.1 System Bus Compatibility
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
C.1.2 CHI Programming Options:
CMS = clock mode select 0 = line rate 1 = 2X line rate XEN = transmitter enable 0 = disable (DX tri-stated) 1 = enable (DX driven during active time slots) FE = frame edge select 0 = falling edge 1 = rising edge XCE = CLKXR output edge select for DX 0 = falling edge 1 = rising edge RCE = CLKXR input edge select for DR 0 = falling edge 1 = rising edge XBOFF = 3-bit transmit output bit offset 000-1111 = CLKXR (or 2xCLKXR) delay from FS to DX bit0 RBOFF = 3-bit receive input bit offset 000-111 = CLKXR (or 2xCLKXR) delay from FS to DR bit0 XTS = 6-bit transmit output TS offset 00-3F = CLKXR (or 2xCLKXR) TS delay from FS to DX bit0 RTS = 6-bit receive input TS offset 00-3F = CLKXR (or 2xCLKXR) TS delay from FS to DR bit0 The device only supports CHI and GCI buses if N = 24, 32, or 48, although either bus is defined to operate at N x 64 from N = 4 to N = 48. The device does not support AT&T's Dual CHI (separate A/B buses) or K2 buses, nor does it support INTEL's SLD (ping/pong) 3-pin bus.
C-2
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D
Appendix D
D.1 Notation and Acronyms
D.1.1 Arithmetic Notation
Time Slot Bit Numbering associated with time slots in the primary rate channel, are numbered 1 to 8, where bit number 1 is transmitted first and is specified as the MSB. Configuration and Status Word Bit Numbering, associated with configuration or status words, 7 to 0, where bit number 7 is specified as the MSB, and bit number 0 is specified as the LSB.
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Appendix D
D.2 Acronyms and Abbreviations
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
D.2 Acronyms and Abbreviations
ADC AFPS AGC AIS ALBO ALOS AMI ANSI B8ZS BER BERR BFA BOP BPV BSDL CAS ITU-T CCS CERR CGA CI CLAD CMOS COFA CRC CSU DAC DCS DDS DMI DPLL DPM DS1 DSU ESF EXZ Analog to Digital Converter Automatic Facility Protection Switching Automatic Gain Control Alarm Indication Signal Automatic Line Build Out Analog Loss of Signal Alternate Mark Inversion American National Standards Institute Binary with 8 Zero Substitution Bit Error Rate Bit Error Counter Basic Frame Alignment Bit-Oriented Protocol Bipolar Violation Boundary Scan Description Language Channel Associated Signaling International Telegraph and Telephone Consultative Committee Common Channel Signaling CRC Errors Carrier Group Alarm Customer Installation Clock Rate Adapter Complementary Metal Oxide Semiconductor Change of Frame Alignment Cyclic Redundancy Check Channel Service Unit Digital to Analog Converter Digital Cross-Connect System Digital Data System Digital Multiplexed Interface Digital Phase Locked Loop Driver Performance Monitor Digital Signal Level 1 Data Service Unit Extended Superframe Excessive Zeros
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Quad/x16/Octal--T1/E1/J1 Framers
Appendix D
D.2 Acronyms and Abbreviations
FAS FCC FCS FDL FEBE FERR FPS HCDS HDB3 ICOT IDLC ISDN JAT JCLK JTAG LBO LCV LEC LIU LOAS LOF LOS LSB MAIS MART MAS MAT MERR MFAS MOP MOS MPU MQFP MSB MUX MVIP MYEL NCO NI NRZ OOF
Frame Alignment Sequence (E1 Format) Federal Communications Committee Frame Check Sequence Facility Data Link Far End Block Error Framing Bit Error Frame Pattern Sequence (EFS Format) High-Capacity Digital Service High-Density Bipolar of Order 3 Intercity and Outstate Trunk Integrated Digital Loop Carrier Integrated Service Digital Network Jitter Attenuator Jitter Attenuated Clock Joint Test Action Group Line Build Out Line Code Violation Local Exchange Carrier Line Interface Unit Loss of Analog Signal Loss of Frame Loss of Signal -DS1 Least Significant Bit Multiframe AIS Maximum Average Reframe Time Multiframe Alignment Sequence (CAS Format) Metropolitan Area Trunk MFAS Error Multiframe Alignment Sequence (CRC4 format) Message Oriented Protocol Message Oriented Signaling Microprocessor Interface Metric Quad Flat Pack Most Significant Bit Multiplexer Multi-Vendor Integration Protocol Multiframe Yellow Alarm Numerical Controlled Oscillator Network Interface Non-Return to Zero Out of Frame
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Appendix D
D.2 Acronyms and Abbreviations
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
PCM PDV PIC PLCC PLL PM PQFP PRBS PRI PRM RAI RBOP RBS RCVR RDL1 RDL2 RDL3 RFRAME RJAT RLIU RMAIS RPDV RPLL RSB RSBI RSIG RSLIP RXCLK RZCS QRSS SEF SERR SF SLC TAP TBOP TDL1 TDL2 TDL3 TDM TSB TSBI TJAT TLIU
Pulse Code Modulation Pulse Density Violation Polyethylene-Insulated Cable Plastic Leaded Chip Carrier Phase Locked Loop Performance Monitoring Plastic Quad Flat Pack Pseudo-Random Bit Sequence Primary Rate Interface Performance Report Message Remote Alarm Indication Bit-Oriented Protocol Detector Robbed Bit Signaling Receiver Receive Data Link 1 Receive Data Link 2 External Receive Data Link Receive Framer Receive Jitter Attenuator Receive Line Interface Unit Receive Multiframe AIS Receive Pulse Density Violation Receive Phase Locked Loop Receive System Bus Receive System Bus Interface Receive Signaling Buffer Receive Slip Buffer Receive Clock AMI/HDB3/B8ZS Line Decoder Quasi-Random Signal Source Severely Errored Framing Event CAS Error Super Frame Subscriber Loop Carrier Test Access Port Bit Oriented Protocol Formatter Transmit Data Link 1 Transmit Data Link 2 External Transmit Data Link Time Division Multiplexed Transmit System Bus Transmit System Bus Interface Transmit Jitter Attenuator Transmit Line Interface Unit
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CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
Appendix D
D.2 Acronyms and Abbreviations
TLOS TSB TSIC TSIG TSLIP TZCS UI UMC UNICODE UTP VCO VCXO VGA XMTR YEL ZCS
Transmit Loss of Signal Transmit System Bus Time Slot Interchange Transmit Signaling Buffer Transmit Slip Buffer AMI/HDB3/B8ZS Line Encoder Unit Interval Unassigned Mux Code Universal Trunk Out of Service Code Unshielded Twisted Pair Voltage Controlled Oscillator Voltage Controlled Crystal Oscillator Variable Gain Amplifier Digital Transmitter Yellow Alarm Zero Code Suppression
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Appendix D
D.2 Acronyms and Abbreviations
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
D-6
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E
Appendix E
E.1 Revision History
Table E-1. Document Revision History Revision
A B
Level
Advanced Preliminary
Date
July 1998 April 1999 Created
Description
1. Added two new products to the data sheet: CX28394 (quad framer) and CX28395 (x16 framer). 2. Re-named data sheet. 3. Changed the device part number from RS8398 to CX28398. 4. Transmitter, Overhead Pattern Generator, Alarm Generator section rewritten for clarity. Removed RLOC from automatic AIS generation description. Removed reference to RDIGI bit. Added description of RLOF integration to automatic Yellow Alarm/RAI generation description. 5. Removed 2Kbps datalink mode and ZBTSI support. 6. Added chapter: System Bus, to describe multiplexed and non-multiplexed modes. 7. Changed RLOS clearing criteria for T1 to "at least 12.5% density over a period of 114 bits." 8. Changed default register settings for registers 040, 041, 042, and 043. These registers are not reset. 9. Removed 8398 Embedded mode from the System Bus description and SBI_CR register description. 1. Incorporated edits from Errata #N8398ER1A dated May 13, 1999. 1. Incorporated edits from Errata #100354C, formerly N8398ER1C. 2. Updated timing parameters. 1. Updated marking numbers.
C D
Preliminary Final
May 1999 November 1999
E
Preliminary
May 2000
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E-1
Appendix E
E.1 Revision History
CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
E-2
Conexant
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0.0 Sales Offices
Further Information literature@conexant.com (800) 854-8099 (North America) (949) 483-6996 (International) Printed in USA World Headquarters Conexant Systems, Inc. 4311 Jamboree Road Newport Beach, CA 92660-3007 Phone: (949) 483-4600 Fax 1: (949) 483-4078 Fax 2: (949) 483-4391 Americas U.S. Northwest/ Pacific Northwest - Santa Clara Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. Southwest - Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Southwest - Orange County Phone: (949) 483-9119 Fax: (949) 483-9090 U.S. Southwest - San Diego Phone: (858) 713-3374 Fax: (858) 713-4001 U.S. North Central - Illinois Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. South Central - Texas Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Northeast - Massachusetts Phone: (978) 367-3200 Fax: (978) 256-6868 U.S. Southeast - North Carolina Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southeast - Florida/ South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Mid-Atlantic - Pennsylvania Phone: (215) 244-6784 Fax: (215) 244-9292 Canada - Ontario Phone: (613) 271-2358 Fax: (613) 271-2359 Europe Europe Central - Germany Phone: +49 89 829-1320 Fax: +49 89 834-2734
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