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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91FY22 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (NMI , INT0 to 4, INTRTC) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91FY22 CMOS 16-Bit Microcontrollers TMP91FY22F 1. Outline and Features TMP91FY22F is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91FY22F comes in a 100-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4-channels (1.0 s/2 bytes at 16 MHz) (2) Minimum instruction execution time: 148 ns (at 27 MHz) (3) Built-in RAM: 16 Kbytes Built-in ROM: 256 Kbytes Flash memory 2 Kbytes mask ROM (used for booting) (4) External memory expansion Expandable up to 16 Mbytes (shared program/data area) * * * Dynamic Can simultaneously support 8-/16-bit width external data bus data bus sizing (5) 8-bit timers: 8 channels (6) 16-bit timer/event counter: 2 channels (7) General-purpose serial interface: 2 channels UART/ Synchronous mode: 2 channels IrDA ver1.0 (115.2 kbps) supported 030519EBP1 The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 91FY22-1 2003-05-21 TMP91FY22 (8) Serial bus interface: 1 channel I2C bus mode/clock synchronous Select mode (9) 10-bit AD converter: 8 channels (10) Watchdog timer (11) Timer for real-time clock (RTC) (12) Chip Select/Wait controller: 4 channels (13) Interrupts: 45 interrupts 9 CPU interrupts: Software interrupt instruction and illegal instruction 26 internal interrupts: 10 external interrupts: (14) Input/Output ports: 81 pins (15) Standby function Three HALT modes: IDLE2 (programmable), IDLE1, STOP (16) Triple-clock controller Clock Doubler (DFM) Clock Gear (fc to fc/16) SLOW mode (fs (17) Operating voltage VCC (18) Package 100-pin QFP: P-QFP100-1414-0.50E 2.7 V to 3.6 V (fc max 27 MHz) 32.768 kHz) Seven selectable priority levels 91FY22-2 2003-05-21 TMP91FY22 DVCC [3] DVSS [3] X1 X2 EMU0 EMU1 XT1 (P96) XT2 (P97) RESET ADTRG (P53) AN0 to AN7 (P50 to P57) CPU (TLCS-900/L1) AVCC, AVSS VREFH, VREFL TXD0 (P90) RXD0 (P91) SCLK0/ CTS0 (P92) TXD1 (P93) RXD1 (P94) SCLK1/ CTS1 (P95) SCK (P60) SO/SDA (P61) SI / SCL (P62) 10-Bit 8CH AD Converter SIO/UART/IrDA XWA XBC XDE XHL XIX XIY XIZ XSP (SIO0) SIO/UART (SIO1) Serial Bus Interface (SBI) 8-Bit Timer (TMRA0) 8-Bit Timer (TMRA1) WA BC DE HL IX IY IZ SP 32 bits SR F PC H-OSC Clock Gear Clock doubler L-OSC AM0 AM1 ALE Port 0 Port 1 (P00 to P07) AD0 to AD7 (P10 to P17) AD8/A8 to AD15/A15 (P20 to P27) A0/A16 to A7/A23 RD (P30) WR (P31) HWR (P32) BUSRQ (P34) BUSAK (P35) R/ W (P36) P37(BOOT) (P64) SCOUT, P65, P66 PA4 to PA7 (P40 to P43) CS0 to CS3 WAIT (P33) Watchdog Timer (WDT) Port 2 TA0IN (P70) TA1OUT (P71) REAL-CLOCK TIMER (RTC) Port 3 16-KB RAM 8-Bit Timer (TMRA2) TA3OUT (P72) 8-Bit Timer (TMRA3) 8-Bit Timer (TMRA4) 8-Bit Timer (TMRA5) 8-Bit Timer (TMRA6) TA7OUT (P75) 8-Bit Timer (TMRA7) 2-KB BOOT ROM 256-KB FLASH E2PROM Port 6 Port A CS/WAIT Controller (4-BLOCK) Interrupt Controller TA4IN (P73) TA5OUT (P74) 16-Bit Timer (TMRB0) 16-Bit Timer (TMRB1) NMI INT0 (P64) INT1 to 4 (PA0 to 3) TB0IN0/INT5 (P80) TB0IN1/INT6 (P81) TB0OUT0 (P82) TB0OUT1 (P83) TB1IN0/INT7 (P84) TB1IN1/INT8 (P85) TB1OUT0 (P86) TB1OUT1 (P87) ( ): Initial function after reset Figure 1.1 TMP91FY22F Block Diagram 91FY22-3 2003-05-21 TMP91FY22 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91FY22F, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91FY22F. 88 P65 DVCC P66 DVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3/ADTRG P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/TA7OUT P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RX1 P95/SCLK1/CTS1 AM0 DVCC X2 DVSS X1 AM1 RESET P96/XT1 P97/XT2 EMU0 EMU1 PA0/INT1 PA1/INT2 PA2/INT3 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 87 P64/SCOUT 86 P63/INT0 85 P62/SI/SCL 84 P61/SO/SDA 83 P60/SCK 82 P43/CS3 81 P42/CS2 80 P41/CS1 79 P40/CS0 78 P37/BOOT 77 P36/R/W 76 P35/BUSAK 75 P34/BUSRQ 74 P33/WAIT 73 P32/HWR 72 P31/WR 71 P30/RD 70 P27/A7/A23 69 P26/A6/A22 68 P25/A5/A21 67 P24/A4/A20 66 P23/A3/A19 65 P22/A2/A18 QFP100 Top View 64 DVCC 63 NMI 62 DVSS 61 P21/A1/A17 60 P20/A0/A16 59 P17/AD15/A15 58 P16/AD14/A14 57 P15/AD13/A13 56 P14/AD12/A12 55 P13/AD11/A11 54 P12/AD10/A10 53 P11/AD9/A9 52 P10/AD8/A8 51 P07/AD7 50 P06/AD6 49 P05/AD5 48 P04/AD4 47 P03/AD3 46 P02/AD2 45 P01/AD1 44 P00/AD0 43 ALE 42 PA7 41 PA6 40 PA5 39 PA4 38 PA3/INT4 Figure 2.1.1 Pin assignment diagram (100-pin QFP) 91FY22-4 2003-05-21 TMP91FY22 2.2 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions. Table 2.2.1 Pin names and functions (1/3) Pin Name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O I/O Tri-state I/O Tri-state Output I/O Output Output Functions Port 0: I/O port that allows I/O to be selected at the bit level Address and data (lower): Bits 0 to 7 of address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level (with pull-down resistor) Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data to pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port 34: I/O port (with pull-up resistor) Bus Request: Signal used to request Bus Release Port 35: I/O port (with pull-up resistor) Bus Acknowledge: Signal used to acknowledge Bus Release Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. Port 37: I/O port (with pull-up resistor) This pin sets single boot mode. Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 if address is within specified address area Port 42: I/O port (with pull-up resistor) Chip Select 2: Outputs 0 if address is within specified address area Port 43: I/O port (with pull-up resistor) Chip Select 3: Outputs 0 if address is within specified address area Port 5: Pin used to input port Analog input: Pin used to input to AD converter AD Trigger: Signal used to request start of AD converter Port 60: I/O port Serial bus interface clock in SIO Mode Port 61: I/O port Serial bus interface output data in SIO Mode Serial bus interface data in I2C bus Mode Port 62: I/O port Serial bus interface input data in SIO Mode Serial bus interface clock in I2C bus Mode Port 63: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level/rising edge/falling edge Port 64: I/O port System Clock Output: Outputs fFPH or fs clock. 8 1 1 1 1 1 1 1 1 1 Output Output Output Output I/O Output I/O Input I/O Input I/O Output I/O Output I/O Input I/O Output I/O Output I/O Output I/O Output Input Input Input I/O I/O I/O Output I/O I/O Input I/O I/O Input I/O Output P31 WR P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK P36 R/W P37 BOOT P40 CS0 P41 CS1 1 1 1 8 P42 CS2 P43 CS3 P50 to P57 AN0 to AN7 ADTRG P60 SCK P61 SO SDA P62 SI SCL P63 INT0 P64 SCOUT 1 1 1 1 1 91FY22-5 2003-05-21 TMP91FY22 Table 2.2.1 Pin names and functions (2/3) Pin Name P65 P66 P70 TA0IN P71 TA1OUT P72 TA3OUT P73 TA4IN P74 TA5OUT P75 TA7OUT P80 TB0IN0 INT5 P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 P90 TXD0 P91 RXD0 P92 SCLK0 CTS0 Number of Pins 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O Input I/O Output I/O Output I/O Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O Input I/O Input Port 65: I/O port Port 66: I/O port Port 70: I/O port Timer A0 Input Port 71: I/O port Timer A1 Output Port 72: I/O port Timer A3 Output Port 73: I/O port Timer A4 Input Port 74: I/O port Timer A5 Output Port 75: I/O port Timer A7 Output Functions Port 80: I/O port Timer B0 Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge/falling edge. Port 81: I/O port Timer B0 Input 1 Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port Timer B0 Output 0 Port 83: I/O port Timer B0 Output 1 Port 84: I/O port Timer B1 Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge/falling edge. Port 85: I/O port Timer B1 Input 1 Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port Timer B1 Output 0 Port 87: I/O port Timer B1 Output 1 Port 90: I/O port Serial Send Data 0 (programmable open-drain) Port 91: I/O port Serial Receive Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 (programmable open-drain) Port 94: I/O port (with pull-up resistor) Serial Receive Data 1 Port 95: I/O port (with pull-up resistor) Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port (open-drain output) Low-frequency oscillator connection pin 1 1 1 1 1 1 1 1 1 1 P93 TXD1 P94 RXD1 P95 SCLK1 CTS1 1 1 1 P96 XT1 1 91FY22-6 2003-05-21 TMP91FY22 Table 2.2.1 Pin names and functions (3/3) Pin Name P97 XT2 PA0 to PA3 INT1 to INT4 PA4 to PA7 ALE Number of Pins 1 4 I/O I/O Output I/O Input I/O Output Input Input Output Input Input Input I/O Functions Port 97: I/O port (open-drain output) Low-frequency oscillator connection pin Ports A0 to A3: I/O ports Interrupt Request Pins 1 to 4: Interrupt request pins with programmable rising edge / falling edge. Ports A4 to A7: I/O ports Address Latch Enable Can be disabled to reduce noise. Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling edge or both edge. Address Mode: The Vcc pin should be connected. Test Pins: Open pins Reset: initializes TMP91FY22. (With pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) High-frequency oscillator connection pins Power supply pin for AD converter GND pin for AD converter (0 V) Power supply pins (All Vcc pins should be connected with the power supply pin.) GND pins (0 V) (All Vss pins should be connected with the power supply pin.) 4 1 1 2 1 1 1 1 1 1 2 3 3 NMI AM0 to 1 EMU0/EMU1 RESET VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS Note: An external DMA controller cannot access the device's built-in memory or built-in I/O devices using the BUSRQ and BUSAK signal. 91FY22-7 2003-05-21 TMP91FY12A 3. Functional Description This section shows the hardware configuration of the TMP91FY12A and explains how it operates. This device is a version of the created by replacing the predecessor's internal mask ROM with a 256-Kbyte internal flash memory. The configuration and the functionality of this device are the same as those of the TMP91CW12A. For the functions of this device that are not described here, refer to the TMP91CW12A data sheet. 3.1 Outline of operation modes There are single-chip and single-boot modes. Which mode is selected depends on the device's pin state after a reset (including when the watchdog timer output is connected to reset (inside the chip)). Single Chip Mode: The device normally operates in this mode. After a reset, the device starts executing the internal flash memory program. Single Boot Mode: This mode is used to rewrite the internal flash memory by serial transfer (UART). After a reset, the internal boot ROM starts up, executing a on-board rewrite program. Table 3.1.1 Operation Mode Setup table Operation Mode RESET Single-chip mode Single-boot mode Mode Setup Input Pin BOOT (P37) H L AM0 H AM1 H 91FY12A-8 2003-05-21 TMP91FY12A 3.2 Memory Map The memory map of this device differs from that of the TMP91CW12A. Figure 3.2.1 shows a memory map of the device in single-chip mode and its memory areas that can be accessed in each addressing mode of the CPU. 000000H Internal I/O (4 Kbytes) Direct area (n) 000100H 001000H Internal RAM (4 Kbytes) 002000H 64-Kbyte area (nn) 010000H External memory FC0000H Internal ROM (256 Kbytes) 16-Mbyte area (R) ( R) (R ) (R R8/16) (R d8/16) (nnn) FFFF00H FFFFFFH Vector Table (256 Bytes) ( Internal area) Figure 3.2.1 Memory Map (Single-chip Mode) 91FY12A-9 2003-05-21 TMP91FY12A 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Output Current Output Current Output Current (total) Output Current (total) Power Dissipation (Ta 85C) Symbol Vcc VIN IOL IOH IOL IOH PD TSOLDER TSTG TOPR NEW Rating 0.5 to 4.0 0.5 to Vcc 2 2 80 80 600 260 65 to 150 20 to 70 10000 0.5 Unit V V mA mA mA mA mW C C C Cycle Soldering Temperature (10 s) Storage Temperature Operating Temperature Number of Times Program Erase Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 91FY12A-45 2003-05-21 TMP91FY12A 4.2 DC Characteristics (1/2) Typ. (Note 1) Parameter Power Supply Voltage (Avcc DVcc) (Avss DVss 0 V) P00 to P17 (AD0 to 15) Input Low Voltage P20 to PA7 (except P63) RESET , NMI , P63 (INT0) Symbol Condition Min Max Unit VCC VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH fc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc IOL IOH 4 to 27 MHz 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V 1.6 mA 400 A fs 30 to 34 kHz 2.7 3.6 0.6 0.3 Vcc V 0.3 0.25 Vcc 0.3 0.2 Vcc AM0, 1 X1 P00 to P17 (AD0 to 15) P20 to PA7 (except P63) RESET , NMI , P63 (INT0) 2.0 0.7 Vcc 0.75 Vcc Vcc 0.3 0.8 Vcc Vcc Vcc 2.7 to 3.6 V 2.7 to 3.6 V 2.4 0.45 Vcc 0.3 V Input High Voltage AM0, 1 X1 Output Low Voltage Output High Voltage V Note 1: Typical values are for when Ta 25C and Vcc 3.0 V unless otherwise noted. 91FY12A-46 2003-05-21 TMP91FY12A 4.2 DC Characteristics (2/2) Typ. (Note 1) 0.02 0.2 2.7 100 0.05 Parameter Input Leakage Current) Output Leakage Current Power Down Voltage (at STOP, RAM back-up) RESET Pull-up Resistor Pin Capacitance Schmitt Width RESET , NMI , INT0 Programmable Pull-up Resistor Normal (Note 2) Idle2 Idle1 Slow (Note 2) Idle2 Idle1 Stop Symbol ILI ILO VSTOP RRST CIO VTH RKH Icc 0.0 0.2 VIN VIN Condition Vcc Vcc Min Max 5 10 3.6 400 10 Unit A V K PF V V IL2 0.2 Vcc, V IH2 0.8 Vcc Vcc fc Vcc Vcc 3V 1 MHz 2.7 to 3.6 V 3V 10% 10% 0.4 100 1.0 400 30.0 4.5 2.0 30.0 9.0 6.0 1.0 45.0 7.0 4.0 40 25 15 15 K Vcc 3 V 10% fc 27 MHz Vcc 3 V 10% fs 32.768 kHz Vcc 3V 10% mA A A Note 1: Typical values are for when Ta 25C and Vcc 3.0 V unless otherwise noted. Note 2: Icc measurement conditions (Normal, Slow): All functions are operating; output pins are open and input pins are fixed. 91FY12A-47 2003-05-21 TMP91FY12A 4.3 AC Characteristics (1) Vcc No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 3.0 V 10% Symbol tFPH Parameter fFPH Period ( x) A0 to A15 Vaild ALE Fall ALE Fall RD Rise WR Rise Variable Min 37.0 0.5x 0.5x x 0.5x 0.5x x x 1.5x 0.5x x 6 16 20 14 10 10 23 26 13 13 3.0x 3.5x 2.0x 2.0x 0 x 1.5x 1.5x x 15 15 35 25 3.5x 3.0x 2.0x 0 3.5x 3.5x 3.5x 80 89 60 50 15 38 41 30 fFPH Min 37.0 12 2 17 4 8 27 14 29 5 24 27 MHz Max Unit ns ns ns ns ns ns ns ns ns ns ns 73 88 44 ns ns ns ns ns ns ns ns ns 69 61 ns ns ns 40 ns ns 209 ns Max 31250 ALE Fall tAL tLA tLL tLC tCLR tCLW tACL tACH tCAR tCAW tADL tADH tRD tRR tHR tRAE tWW tDW tWD 1 WAIT n Mode 1 WAIT n Mode 1 WAIT n Mode A0 to A15 Hold RD / WR Fall ALE High Width ALE Rise ALE Rise RD / WR Fall RD / WR Fall A0 to A15 Valid A0 to A23 Valid RD Rise WR Rise A0 to A23 Hold A0 to A23 Hold D0 to D15 Input D0 to D15 Input A0 to A15 Valid A0 to A23 Valid RD Fall RD Low Width RD Rise RD Rise D0 to D15 Input D0 to A15 Hold A0 to A15 Output WR Rise 59 0 22 40 20 12 WR Low Width D0 to D15 Valid WR Rise D0 to D15 Hold WAIT Input WAIT Input WAIT Hold A0 to A23 Valid A0 to A15 Valid RD / WR Fall tAWH tAWL tCW tAPH tAPH2 tAP 74 A0 to A23 Valid A0 to A23 Valid A0 to A23 Valid Port Input Port Hold Port Valid 129 AC Measuring Conditions Output Level: High = 0.7 Vcc, Low 0.3 Vcc, CL Input Level: High = 0.9 Vcc, Low 0.1 Vcc 50 pF Note: x used in an expression shows a frequency for the clock fFPH selected by SYSCR1 91FY12A-48 2003-05-21 TMP91FY12A (2) Raed Cycle tFPH fFPH A0 to A23 CS0 to CS3 R/ W tAWH tAWL tCW WAIT tAPH Port input tAPH2 tADH RD tCAR tRR tRAE tHR D0 to D15 tACH tACL tLC tRD tADL AD0 to AD15 A0 to A15 tAL tLA tCLR ALE tLL 91FY12A-49 2003-05-21 TMP91FY12A (3) Write Cycle fFPH A0 to 23 CS0 to CS3 R/ W WAIT tAP Port Output tCAW WR , HWR tWW tDW tWD AD0 to 15 A0 to 15 D0 to 15 tCLW ALE 91FY12A-50 2003-05-21 TMP91FY12A 4.4 AD Conversion Characteristics AVcc Parameter Analog Reference Voltage ( ) Analog Reference Voltage ( ) Analog Input Voltage Range Analog Current for Analog Reference Voltage Vcc, AVss Max VCC VSS 0.2 V Vss Unit Symbol VREFH VREFL Condition VCC VCC 3V 3V 10% 10% Min VCC 0.2 V Typ. VCC VSS VSS VREFL V VAIN IREF (VREFL 0 V) VCC VCC VCC 3V 3V 3V 10% 10% 10% VREFH 0.94 0.02 1.0 1.20 5.0 4.0 mA A LSB Error (not including quantizing errors) Note 1: 1 LSB (VREFH VREFL)/1024 [V] 4 MHz. Note 2: The operation above is guaranteed for fFPH Note 3: The value for ICC includes the current which flows through the AVCC pin. 91FY12A-51 2003-05-21 TMP91FY12A 4.5 Serial Channel Timing (I/O Internal Mode) (1) SCLK Input Mode Parameter SCLK Period Output Data SCLK Rising /Falling Edge (Note) SCLK Rising/Falling Edge (Note) Output Data Hold SCLK Rising/Falling Edge (Note) Input Data Hold SCLK Rising/Falling Edge (Note) Valid Data Input Valid Data InputSCLK Rising/Falling Edge (Note) Symbol tSCY tOSS tOHS tHSR tSRD tRDS Variable Min 16X tSCY/2 tSCY/2 3x 4X-110 2x 10 tSCY 0 0 0 10 MHz Max Min 1.6 290 1000 310 1600 0 27 MHz Min 0.59 38 370 121 592 0 Max Max Unit s ns ns ns ns ns Note: SCLK Rinsing/Falling Edge: The rising edge is used in SCLK Rising Mode. The falling edge is used in SCLK Falling Mode. (2) SCLK Output Mode Parameter SCLK Period (programable) Output Data SCLK Rising Edge Output Data Hold Input Data Hold Valid Data Input SCLK Rising Edge SCLK Rising Edge SCLK Rising Edge SCLK Rising Edge Valid Data Input Symbol tSCY tOSS tOHS tHSR tSRD tRDS Variable Min 16X tSCY/2 tSCY/2 0 tSCY 1x 180 1x 180 40 40 10 MHz 27 MHz Max 8192X Min 1.6 760 760 0 Max 819 Min 0.59 256 256 0 Max 303 Unit s ns ns ns 1320 280 217 375 ns ns tSCY SCLK Output Mode/ Input Mode SCLK (Input Mode) OUTPUT DATA TxD INPUT DATA RxD tOSS 0 tOHS 1 tSRD 0 Valid tRDS 1 Valid tHSR 2 Valid 3 Valid 2 3 91FY12A-52 2003-05-21 TMP91FY12A 4.6 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1) Parameter Clock Perild Clock Low Level Width Clock High Level Width Symbol tVCK tVCKL tVCKH Variable Min 8X 4X 4X 100 40 40 10 MHz Min 900 440 440 27 MHz Min 396 188 188 Max Max Max Unit ns ns ns 4.7 Interrupt and Capture (1) NMI , INT0 to INT4 Interrupts Parameter NMI , INT0 to INT4 Low level width NMI , INT0 to INT4 High level width Symbol tINTAL tINTAH 4X 4X Variable Min 40 40 10 MHz Min 440 440 27 MHz Min 188 188 Unit ns ns Max Max Max (2) INT5 to INT8 Interrupts, Capture The INT5 to INT8 input width depends on the system clock and prescaler clock settings. System Clock Selected 0 (fc) 1 (fs) tINTBL tINTBH Prescaler Clock (INT5 to INT8 Low level Width) (INT5 to INT8 High Level Width) Unit Selected 00 (fFPH) 10 (fc/16) 00 (fFPH) 8X 128Xc 8X 100 0.1 0.1 396 4.8 244.3 8X 128Xc 8X 100 0.1 0.1 396 4.8 244.3 ns s Note: Xc Period of Clock fc 4.8 SCOUT Pin AC Characteristics Parameter Low level Width High level Width Symbol tSCH tSCL Variable Min Max 0.5T 0.5T 13 13 10 MHz Min Max 37 37 27 MHz Min Max 5 5 Condition Vcc Vcc 2.7 to 3.6 V 2.7 to 3.6 V Unit ns ns Note: T Period of SCOUT Measrement Condition Output Level: High 0.7 Vcc/Low 0.3 Vcc, CL tSCH tSCL SCOUT 10pF 91FY12A-53 2003-05-21 TMP91FY12A 4.9 Bus Request/Bus Acknowledge BUSRQ BUSAK (Note 1) tCBAL tBA AD0 to AD15 A0 to A23, RD , WR tABA (Note 2) (Note 2) CS0 to CS3 , R/ W , HWR ALE Paramter Output Buffer Off to BUSAK Low Symbol Variable Min Max 80 fFPH Min 0 10 MHz fFPH Max 80 27 MHz Max 80 Condition Unit Min 0 tABA BUSAK High to Output Buffer On 0 Vcc 2.7 to 3.6 V ns tBAA 0 80 0 80 0 80 Vcc 2.7 to 3.6 V ns Note 1:Even if the BUSRQ Signal goes Low, the bus will not be released while the WAIT signal is Low. The bus will only be released when BUSRQ goes Low while WAIT is High. Note 2: This line shows only that the output buffer is in the Off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the Active and Non-Active states by the internal signal. 91FY12A-54 2003-05-21 TMP91FY12A 4.10 Recommended Oscillation Circuit The TMP91FY12AF has been evaluated by the following resonator manufacturer. The evaluation results are shown below for your information. Note: The load capacitance of the oscillation terminal is the sum of the load capacitances of C1 and C2 to be connected and the stray capacitance on the board. Even if the ratings of C1 and C2 are used, the load capacitance varies with each board and the oscillator may malfunction. Therefore, when designing a board, make the pattern around the oscillation circuit shortest. It is recommended that final evaluation of the resonator be performed on the board. (1) Examples of resonator connection X1 X2 XT1 XT2 Rd Rd C1 C2 C1 C2 Figure 4.10.1 High-frequency Oscillator Connection Figure 4.10.2 Low-frequency Oscillator Connection (2) Recommended ceramic resonators for the TMP91FY12AF: Murata Manufacturing Co., Ltd. Ta 40 to 85 C Item Oscillation frequency [MHz] 4.0 6.75 Recommended resonator CSTS0400MG06 CSTS0675MG06 CSA12.5MTZ CST12.5MTW CSA20.00MXZ040 CSA27.00MXZ040 CST27.00MXW040 Recommended rating C1 [pF] C2 [pF] Rd [k ] (47) (47) 30 (30) 7 5 (5) (47) (47) 30 (30) 7 5 (5) VCC [V] Remarks High-freq uency oscillator 12.5 20.0 27.0 0 2.7 to 3.3 The values enclosed in brackets in the C1 and C2 columns apply to the condenser built-in type. The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL; http://www.murata.co.jp/search/index.html 91FY12A-55 2003-05-21 |
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