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E2B0011-27-Y3 Semiconductor
Semiconductor MSM6660-01,02,03
GENERAL DESCRIPTION
This version: Nov. 1997 MSM6660-01,02,03 Previous version: Mar. 1996
1/2, 1/3 DUTY LCD DRIVER WITH 3-DOT COMMON DRIVER AND 62-DOT SEGMENT DRIVER
The MSM6660 is a dynamic display LCD driver, equipped with a function that can switch between 1/2 and 1/3 duty. The MSM6660 can directly drive LCDs with up to 124 or 186 segments, depending on whether 1/2 or 1/3 duty is selected. The MSM6660's on-board display synchronization circuit allows display in a multi-chip configuration.
FEATURES
* * * * * * * * * * * Power supply voltage : 4 to 6 V (for both logic and LCD driver) Operating temperature : -40C to +85C Applicable LCD duty : 1/2 (1/2 bias), 1/3 (1/3 bias) Common output : 2 (1/2 duty), 3 (1/3 duty) Segment output : 62 Serial transfer clock rate : 2 MHz Maximum On-board display synchronization circuit which enables display in a multi-chip configuration. CE, DATA, and CK are provided for microcomputer interface. Handling of display data segments in three blocks enables efficient data transfer. Equipped with display-blanking input and display segment test input functions. A built-in voltage dividing resistor for bias voltage generation. - 01: No internal resistance - 02: 1 k internal resistance - 03: 30 k internal resistance * A built-in RC oscillation circuit which uses an external RC. * Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-K) (Product name: MSM6660-01GS-K) (Product name: MSM6660-02GS-K) (Product name: MSM6660-03GS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM6660-01GS-BK) (Product name: MSM6660-02GS-BK) (Product name: MSM6660-03GS-BK)
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Semiconductor
MSM6660-01,02,03
BLOCK DIAGRAM
SEG0 SEG61
BL
62-BIT OUTPUT DRIVER
LT
VDD 62-SEGMENT DATA SELECTOR GND
CE
186-BIT DATA LATCH
DATA
72-BIT SHIFT REGISTER
CK COM1
Oscillation
OSC
circuit
1/4
1/2 or 1/3
COM2 Timing generation circuit COM3 COMOUT
SEL
Synchronization circuit
SYNC
2/3
VLC1 VLC2 VLC3
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PIN CONFIGURATION (TOP VIEW)
80
77
76
75
74
73
72
71
70
69
68
67
66
79
78
65
COM3 COM2 COM1 GND VLC3 VLC2 VLC1 VDD BL LT 2/3 SEL OSC CK DATA CE
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SYNC COMOUT SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
SEG24
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 80-Pin Plastic QFP
40
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG Condition Ta=25C Ta=25C Ta=85C -- Rating -0.3 to +7 -0.3 to VDD+0.3 300 -55 to +150 Unit V V mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage "H" Input Voltage "L" Input Voltage Shift Frequency Operating Temperature Symbol VDD VIH VIL fCK Top Condition -- -- -- -- -- Range 4 to 6 VDD 0.7 to VDD 0 to VDD 0.3 0.1 to 2 -40 to +85 Unit V V V MHz C
Oscillation Circuit
Parameter Oscillation Resistance Oscillation Capacitance Oscillation Frequency COMOUT Frequency Symbol RO CO fOSC fCOM Condition -- -- -- -- Min. 20 0.0047 -- -- Typ. 100 0.01 1.4 350 Max. 120 0.047 -- -- Unit kW mF kHz Hz
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 5V20%, Ta = -40 to +85C) Parameter "H" Input Voltage1 "L" Input Voltage1 "H" Input Voltage2 "L" Input Voltage2 Hysteresis Width "H" Input Current "L" Input Current 1 "L" Input Current 2 Leakage Current "H" Output Voltage "L" Output Voltage Segment Output ON Resistance Symbol VIH1 VIL1 VIH2 VIL2 VHS IIH IIL1 IIL2 IZ VOH VOL VIH = VDD VIL = GND VDD = 5V, VIL = GND VI = VDD or GND VDD = 4V, IOH = -0.4mA VDD = 4V, IOH = 0.4mA Condition
*1 *1 *12 *12 *2 *3 *4 *5 *6 *7 *7 *8,*11 *8,*11 *8,*11 *8,*11 *9,*11 *9,*11 *9,*11 *9,*11 *10
Min. VDD 0.7 -- VDD 0.85 -- -- -1 -1 -15 -1 3.5 -- -- -- -- -- -- -- -- -- --
Typ. -- -- -- -- 0.8 -- -- -50 -- -- -- -- -- -- -- -- -- -- -- 0.3
Max. -- VDD 0.3 -- 0.4 -- 1 1 -100 1 -- 0.4 1 3 3 3 1 3 3 3 1.0
Unit V V V V V mA mA mA mA V V kW kW kW kW kW kW kW kW mA
RONDP VDD = 5V, IO = -0.5mA RONV1 VLC1 = 3.33V, IO = 0.5mA RONV2 VLC2 = 1.67V, IO = 0.5mA RONV3 VLC3 = 0.0V, IO = 0.5mA RONDP VDD = 5V, IO = -0.5mA Common Output ON Resistance Supply Current RONV1 VLC1 = 3.33V, IO = 0.5m RONV2 VLC2 = 1.67V, IO = 0.5mA RONV3 VLC3 = 0.0V, IO = 0.5mA IDD fOSC = 1.4kHz, no load, CK=DC
*1 *2 *3 *4 *5 *6 *7 *8 *9 *10
Applicable to all input pins except OSC pin on the master side. Applicable to CE, CK, and DATA input. Applicable to CE, CK, DATA, SEL, 2/3, BL, and LT. Applicable to CE, CK, DATA, SEL, and 2/3. Applicable to BL and LT input. Applicable to SYNC. Applicable to SYNC and COMOUT. Applicable to SEG0 - SEG61. Applicable to COM1 - COM3. If a voltage-dividing resistor for bias voltage generation is included (- 02 and - 03), the value does not include the current that flows through the resistor. *11 If a voltage-dividing resistor for bias voltage generation is included (- 02 and - 03), the output ON resistance value depends on the built-in dividing resistor. *12 Applicable to the OSC pin on the master side.
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Voltage-dividing resistor for bias voltage generation
Code Name -02 -03 Symbol RLCD RLCD Condition Ta = -40 to +85C Ta = -40 to +85C Min. 0.6 10 Typ. 1 30 Max. 1.4 100 Unit kW kW
VDD RLCD RLCD RLCD
VLC1 VLC2 VLC3
AC Characteristics
(VDD = 5V 20%, Ta = -40 to +85C) Parameter Maximum Clock Frequency Clock Pulse Width Data Set-up Time Data Hold Time CE Pulse Width COMOUT-SYNC Delay Time Oscillation Frequency Symbol fCK tCKW tS tH tCEW tDS fOSC Condition -- -- -- -- -- CL=50pF
OSC Pin Operating Frequency
Min. 2 200 200 200 200 -- --
Typ. -- -- -- -- -- -- 1.4
Max. -- -- -- -- -- 40 50
Unit MHz ns ns ns ns ns kHz
CE
DATA
CK tS tS tCKW tH 1/fCK tH tH tCEW
COMOUT
SYNC tDS tDS
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FUNCTIONAL DESCRIPTION
Pin Functional Description * OSC (pin 68) When the master mode is selected, connect an external resistor and capacitor for the RC oscillation circuit to this pin. When the slave mode is selected, this pin becomes the input pin for an external clock signal. The relationship of oscillation frequency to external CO and RO, when the master mode is selected, is shown below. fOSC =
1 0.69ROCO
(Ta = 25C)
Example: When CO = 0.01F and RO = 100 k, the oscillation frequency, fOSC, is approximately 1.4 kHz.
VDD
SEL
OSC CO RO
* CE (pin 65) This is a chip select input pin. Input data is valid only when this pin is set to "H". Data that is input into the 72-stage shift register synchronously with the rising edge of CK will be latched with the falling edge of this pin, and the display will be updated. A Schmitt trigger is built into the input area. * DATA (pin 66) This is a data input pin. Data input is valid only when the CE pin is set to "H". The 72-stage shift register contents are latched with the falling edge of this pin, and the display will be updated. A Schmitt trigger is built into the input area. * CK (pin 67) This is a serial data shift lock input pin. Data is input synchronously with the rising edge of the shift clock. A Schmitt trigger is built into the input area. Data can be latched even if the shift clock is stopped, since a static shift register is used. * SEL (pin 69) This is an input pin used to switch between the master and the slave modes when a multi-chip configuration is used. Set this pin to "H" to select the master mode, and to "L" to select the slave mode. * SYNC (pin 64) When the master mode is selected, this pin becomes an output pin for synchronous signals. When the slave mode is selected, this pin becomes an input pin for synchronous signals. 7/18
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MSM6660-01,02,03
* 2/3 (pin 70) This pin is used to switch between 1/2 and 1/3 duty. Set this pin to "H" to select 1/2 duty, and to "L" to select 1/3 duty. * COMOUT (pin 63) This is an output pin for clock synchronization. A frequency equal to fOSC/4 is output from this pin. * VLC1 (pin 74), VLC2 (pin 75) and VLC3 (pin 76) When the code is -01, these pins are used as input pins for LCD bias voltage. The VLC3 pin should be connected with GND. The settings for these pins should be as follows: VDD VLC1 VLC2 VLC3 = GND When the code is -02 or -03, VLC1 and VLC2 pins should be left open, and VLC3 pin connected with GND since a voltage-dividing resistor for bias voltage generation has been built in. (However, when the code setting is -02 or -03, and if 1/2 duty is selected, VLC1 and VLC2 should be externally shorted.) * COM1-COM3 (pins 78 to 80) These are common signal output pins for driving the LCD. In the 1/2 duty mode, leave the COM3 pin open. * SEG0-SEG61 (pins 1 to 62) These are segment signal output pins for driving the LCD. 1/2 or 1/3 duty can be selected using the 2/3 pin, and 1/2 or 1/3 bias can be selected using pins VLC1 through VLC3. * LT (pin 71) This is an input pin for controlling the display on the LCD. If this pin is set to "L", all segments will be turned on. A pull-up resistor is included. * BL (pin 72) This is an input pin for controlling the display on the LCD. If this pin is set to "L", all segments will be turned off. A pull-up resistor is included.
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MSM6660-01,02,03
Data Input Display data should be input according to the timing diagram below.
CE
CK
LSB DATA D0 D1 D2 D3 Dn-2 Dn-1
MSB Dn
Display
Old
New
* Display Data
Duty Mode 1/2 Duty 2/3 Pin H Data Length 48-Bit (D0 - D47) 3 COM Data COM1: D0, D2.....D0+2n COM2: D1, D3.....D1+2n n = 0 - 61 COM1: D0, D3.....D0+3n COM2: D1, D4.....D1+3n COM2: D2, D5.....D2+3n n = 0 - 61
1/3 Duty
L
72-Bit (D0 - D71) 3
* Address Data The most significant 3 bits (the last 3 bits) contain the address data. Address data: "100" -- SEG0 - SEG20 "010" -- SEG21 - SEG41 "001" -- SEG42 - SEG61 Since the last 3 bits correspond to each group of segments, if the address is "110", SEG0 - SEG20 and SEG21 - SEG41 are all updated at a time in accordance with the data.
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MSM6660-01,02,03
1) Data format when 1/2 duty (124 segments) is selected.
D0
S0 C1
D1
S0 C2
D2
S1 C1
D3
S1 C2
D4
S2 C1
D5
S2 C2
D39
S19 C2
D40
S20 C1
D41 D42S20 C2
D44 D45
1
D46
0
D47
0
D42 - D44 are Dummy Data D0
S21 C1
D1
S21 C2
D2
S22 C1
D3
S22 C2
D4
S23 C1
D5
S23 C2
D39
S40 C2
D40
S41 C1
D41 D42S41 C2
D44 D45
0
D46
1
D47
0
D42 - D44 are Dummy Data
D0
S42 C1
D1
S42 C2
D2
S43 C1
D3
S43 C2
D4
D37
S60 C2
D38
S61 C1
D39 D40S61 C2
D44
D45
0
D46
0
D47
1
D40 - D44 are Dummy Data
2) Data format when 1/3 duty (186 segments) is selected.
D0
S0 C1
D1
S0 C2
D2
S0 C3
D3
S1 C1
D4
S1 C2
D5
S1 C3
D60
S20 C1
D61
S20 C2
D62 D63S20 C3
D68 D69
1
D70
0
D71
0
D63 - D68 are Dummy Data
D0
S21 C1
D1
S21 C2
D2
S21 C3
D3
S22 C1
D4
S22 C2
D5
S22 C3
D60
S41 C1
D61
S41 C2
D62 D63S41 C3
D68 D69
0
D70
1
D71
0
D63 - D68 are Dummy Data
D0
S42 C1
D1
S42 C2
D2
S42 C3
D3
S43 C1
D4
D57
S61 C1
D58
S61 C2
D59 D60S61 C3
D68
D69
0
D70
0
D71
1
D60 - D68 are Dummy Data
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Semiconductor
MSM6660-01,02,03
LCD Display Timing 1) 1/2 duty mode (2/3 = "H")
VDD COMOUT SYNC GND VDD GND VDD COM1 VLC1,2 VLC3 VDD COM2 VLC1,2 VLC3 VDD SEGn VLC1,2 VLC3 On Off On Off On Off On Off On Off On Off On
Note:
When 1/2 duty is selected and 1/2 bias is used, perform the following: - When the code is -01, short VLC1 and VLC2, and supply the bias voltage. - When the code is -02 or -03, externally short VLC1 and VLC2.
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MSM6660-01,02,03
2) 1/3 duty mode (2/3 = "L")
VDD COMOUT GND VDD GND VDD COM VLC1 VLC2 VLC3 VDD COM2 VLC1 VLC2 VLC3 VDD COM3 VLC1 VLC2 VLC3 VDD SEGn VLC1 VLC2 VLC3 Off On Off Off On Off Off On Off Off On Off
SYNC
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MSM6660-01,02,03
Pin Functions in a Multi-chip Configuration When MSM6660 ICs are used in a multi-chip configuration, one of them is used in the master mode to generate the common frequency and the synchronization signal. These signals are then received by the slave mode ICs to enable synchronous operation.
Symbol COMOUT SYNC OSC SEL Pin 63 64 68 69 Master Mode LSI Connect to Slave IC OSC Connect to Slave IC SYNC
Connect an external resistor and capacitor
Slave Mode LSI Open (Unused) Connect to Master IC SYNC Connect to Master IC COMOUT "L" (GND) level
"H" (VDD) level
LCD Bias Voltage Application Method 1) For 1/2 bias (when 1/2 duty is selected)
VDD VLC1 VLC2 VLC3
RLCD
RLCD
Note:
The above case is for code -01. When the code is -02 or -03, an external voltage-dividing resistor is not needed, because it is already built into the type signified by these settings. However, pins VLC1 and VLC2 must be shorted externally.
2) For 1/3 bias (when 1/3 duty is selected)
VDD VLC1 VLC2 VLC3
RLCD
RLCD
RLCD
Note:
The above case is for the code -01. When the code is -02 or -03, an external voltagedividing resistor is not needed, because it is already built into the type signified by these settings. Leave VLC1 through VLC3 open.
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Method of Reducing the Transfer Time When Unused Segments Exist When unused segments exist, it is not required to transfer the data of unused segments. This allows the data transfer time to be reduced. However, the last 3 bits are address data.
D0
S2 C1
D1
S2 C2
D35
S19 C2
D36
S20 C1
D37 D38S20 C2
D40 D41
1
D42
0
D43
0
Unused segment data reduced
D38 - D40 are dummy data
When SEG0 and 1 are not used, the data can be reduced from the original 48 bits to 44 bits.
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MSM6660-01,02,03
APPLICATION CIRCUIT
For 1/3 duty, 1/3 bias (when the code setting is -01)
LCD PANEL
BL CK DATA CE
SEG0 - SEG61
COM1 COM2 MSM6660 COM3 (Master Mode) COMOUT SYNC SEL VLC1 VLC2 VLC3 OSC
BL CK DATA CE SEL VLC1
SEG0 - SEG61 MSM6660 (Slave Mode) VLC2 VLC3 COM1 COM2 COM3 COMOUT SYNC
OSC
Ro RLCD RLCD RLCD
Co
BL CK DATA CE1 CE2
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REFERENCE DATA
fCOM vs. RO, CO
4
VDD = 5V, Ta = Room Temp. Capacitance CO (mF) 0.0022 0.0047 0.01 0.022
3
fCOM (kHz)
2
1
0
40
60
80
100
120
140
160
Resistance RO (kW)
fOSC vs. VDD
1.6
1.5
fOSC (kHz)
1.4
1.3
Ta = Room Temp. RO = 100kW, CO = 0.01mF
1.2
2
3
4
5 VDD (V)
6
7
8
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PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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MSM6660-01,02,03
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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