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May 1998 FDC636P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features -2.8 A, -20 V. RDS(ON) = 0.130 @ VGS = -4.5 V RDS(ON) = 0.180 @ VGS = -2.5 V. SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 S D D 1 6 .63 6 2 5 G SuperSOT TM pin 1 D D 3 4 -6 Absolute Maximum RatingsT A = 25C unless otherwise noted Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1a) FDC636P -20 8 -2.8 -11 1.6 0.8 -55 to 150 Units V V A W TJ,TSTG RJA RJC Operating and Storage Temperature Range C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 78 30 C/W C/W (c) 1998 Fairchild Semiconductor Corporation FDC636P Rev.B ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 A ID = -250 A, Referenced to 25 oC VDS = -16 V, VGS = 0 V TJ = 55 C IGSSF IGSSR VGS(th) Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 8 V, VDS = 0 V VGS = -8 V, VDS = 0 V VDS = VGS, ID = -250 A ID = -250 A, Referenced to 25 oC VGS = -4.5 V, ID = -2.8 A TJ = 125 C VGS = -2.5 V, ID = -2.2 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd IS VSD Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. a. 78oC/W when mounted on a 1 in2 pad of 2oz Cu on FR-4 board. b. 156oC/W when mounted on a minimum pad of 2oz Cu on FR-4 board. 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%. o o -20 -22 -1 -10 100 -100 V mV/oC A A nA nA BVDSS/TJ IDSS ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Gate Threshold VoltageTemp.Coefficient Static Drain-Source On-Resistance -0.4 -0.6 2 0.11 0.17 0.146 -11 4 0.13 0.21 0.18 A S -1 V mV/oC VGS(th)/TJ RDS(ON) On-State Drain Current Forward Transconductance VGS = -4.5 V, VDS = -5 V VDS = -5 V, ID = -2.8 A VDS = -10 V, VGS = 0 V, f = 1.0 MHz DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 390 170 45 pF pF pF SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = -5 V, ID = -2.8 A, VGS = -4.5 V VDD = -10 V, ID = -1 A, VGS = -4.5 V, RGEN = 6 30 26 8 15 6 0.9 1 48 42 16 27 8.5 ns ns ns ns nC nC nC DRAIN-SOURCE DIODE CHARACTERISTICS Continuous Source Diode Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A (Note 2) -1.3 -0.77 -1.2 A V FDC636P Rev.B Typical Electrical Characteristics DRAIN-SOURCE ON-RESISTANCE 15 -I D , DRAIN-SOURCE CURRENT (A) 2 VGS = -4.5V RDS(ON) , NORMALIZED 12 -3.5V -3.0V - 2.5V 1.8 1.6 1.4 1.2 1 0.8 9 V GS= -2.5V -3.0V -3.5V -4.0V -4.5V 6 - 2.0V 3 -5.0V 0 0 1 2 3 4 5 0 3 6 9 12 15 -VDS , DRAIN-SOURCE VOLTAGE (V) -I D , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE 0.5 R DS(ON) ,ON-RESISTANCE(OHM) 1.4 I D = - 2.8A VGS = - 4.5V I D = -1.4A 0.4 1.2 0.3 1 0.2 TA = 125C 0.8 0.1 25C 0.6 -50 -25 0 25 50 75 100 125 150 0 1 -V 2 GS 3 4 5 TJ , JUNCTION TEMPERATURE (C) ,GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-To-Source Voltage. -I S , REVERSE DRAIN CURRENT (A) 10 10 VDS = -5V -I D , DRAIN CURRENT (A) 8 TA = -55C VGS = 0V 1 25C 125C 6 0.1 TJ = 125C 25C -55C 4 0.01 2 0.001 0 0 1 2 3 4 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -VGS , GATE TO SOURCE VOLTAGE (V) -V SD , BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDC636P Rev.B Typical Electrical Characteristics (continued) 5 -VGS , GATE-SOURCE VOLTAGE (V) 1000 I D = -2.8A 4 3 CAPACITANCE (pF) VDS = -5V -10V -15V 600 400 200 100 50 C iss Coss 2 1 f = 1 MHz V GS = 0 V 0.2 0.5 1 2 5 C rss 0 0 1 2 3 4 5 6 7 8 Q g , GATE CHARGE (nC) 20 0.1 10 20 -VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 20 10 -I D , DRAIN CURRENT (A) 5 T IMI )L (ON DS R 100 1m s 10m s 5 us 4 POWER (W) SINGLE PULSE RJA =156C/W TA = 25C 1 0.5 10 0m s 1s DC 3 2 0.1 0.05 VGS = -4.5V SINGLE PULSE RJA =156 C/W TA = 25C A 0.2 0.5 1 2 1 0.01 0.1 5 10 30 0 0.01 0.1 1 10 100 300 - VDS , DRAIN-SOURCE VOLTAGE (V) SINGLE PULSE TIME (SEC) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. 1 TRANSIENT THERMAL RESISTANCE r(t), NORMALIZED EFFECTIVE 0.5 0.2 0.1 0.05 0.02 0.01 0.005 D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk) R JA(t) = r(t) * R JA R JA = 156C/W t1 t2 TJ - TA = P * R JA (t) Duty Cycle, D = t 1/ t 2 0.00001 0.0001 0.001 0.01 0.1 t 1, TIME (sec) 1 10 100 300 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. FDC636P Rev.B |
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