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CD54HC4514, CD74HC4514, CD74HC4515
Data sheet acquired from Harris Semiconductor SCHS280C November 1997 - Revised July 2003
High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer with Input Latches
Description
The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4- to 16-line decoder. The selected output is enabled by a low on the enable input (E). A high on E inhibits selection of any output. Demultiplexing is accomplished by using the E input as the data input and the select inputs (A0A3) as addresses. This E input also serves as a chip select when these devices are cascaded. When Latch Enable (LE) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads.
Features [ /Title (CD74 HC451 4, CD74 HC451 5) /Subject (High Speed CMOS
* Multifunction Capability - Binary to 1-of-16 Decoder - 1-to-16 Line Demultiplexer * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
Ordering Information
PART NUMBER CD54HC4514F3A TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 24 Ld CERDIP 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC 24 Ld SOIC 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC 24 Ld SOIC
Pinout
CD54HC4514 (CERDIP) CD74HC4514, CD74HC4515 (PDIP, SOIC) TOP VIEW
CD74HC4514E CD74HC4514EN CD74HC4514M CD74HC4514M96
LE 1 A0 2 A1 3 Y7 4 Y6 5 Y5 6 Y4 7 Y3 8 Y1 9 Y2 10 Y0 11 GND 12
24 VCC 23 E 22 A3 21 A2 20 Y10 19 Y11 18 Y8 17 Y9 16 Y14 15 Y15 14 Y12 13 Y13
CD74HC4515E CD74HC4515EN CD74HC4515M CD74HC4515M96
NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) 2003, Texas Instruments Incorporated
1
CD54HC4514, CD74HC4514, CD74HC4515 Functional Diagram
HC 4514 11 Y0 9 Y1 10 Y2 8 Y3 7 Y4 6 Y5 5 Y6 4 Y7 18 Y8 17 Y9 20 Y10 19 Y11 14 Y12 13 Y13 16 Y14 15 Y15 GND = 12 VCC = 24 HC 4515 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
A0 A1 A2 A3 LE
2 3 21 LATCH 22 1 4-TO-16 DECODER
23 E
DECODE TRUTH TABLE (LE = 1) DECODER INPUTS ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X ADDRESSED OUTPUT 4514 = LOGIC 1 (HIGH) 4515 = LOGIC 0 (HIGH) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 All Outputs = 0, 4514 All Outputs = 1, 4515
X = Don't Care; Logic 1 = High; Logic 0 = Low
2
CD54HC4514, CD74HC4514, CD74HC4515
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) E (PDIP) Package (Note 1) . . . . . . . . . . . . . . . . . . . 67 EN (PDIP) Package (Note 1) . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package (Note 2). . . . . . . . . . . . . . . . . . . 46 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 -0.02 -0.02 High Level Output Voltage TTL Loads -4 -5.2 2 4.5 6 4.5 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 V V V V V V V V V V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
VCC (V)
3
CD54HC4514, CD74HC4514, CD74HC4515
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads SYMBOL VOL VI (V) VIH or VIL IO (mA) 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND 0 25oC MIN TYP MAX 0.1 0.1 0.1 0.26 0.26 0.1 8 -40oC TO 85oC -55oC TO 125oC MIN MAX 0.1 0.1 0.1 0.33 0.33 1 80 MIN MAX 0.1 0.1 0.1 0.4 0.4 1 160 UNITS V V V V V V A A
VCC (V) 2 4.5 6 4.5 6 6 6
Prerequisite For Switching Specifications
PARAMETER HC TYPES LE Pulse Width tW 2 4.5 6 Select to LE Set-Up Time tSU 2 4.5 6 Select to LE Hold Time tH 2 4.5 6 75 30 35 100 20 17 0 0 0 95 19 16 125 25 21 0 0 0 110 22 19 150 30 26 0 0 0 ns ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
Switching Specifications
CL = 50pF, Input tr, tf = 6ns 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay Select to Outputs
SYMBOL
TEST CONDITIONS
tPHL, tPLH
CL = 50pF 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 23 19 275 55 47 225 45 38 345 69 59 280 56 48 415 83 71 340 68 58 ns ns ns ns ns ns ns ns
LE to Outputs
tPHL, tPLH
CL = 50pF
4
CD54HC4514, CD74HC4514, CD74HC4515
Switching Specifications
CL = 50pF, Input tr, tf = 6ns (Continued) 25oC VCC (V) 2 4.5 CL = 15pF CL = 50pF Output Transition Time tTHL, tTLH CL = 50pF 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. CIN CPD CL = 50pF 5 MIN 10 TYP 14 70 MAX 175 35 30 75 15 13 10 -40oC TO 85oC MIN MAX 220 44 37 95 19 16 10 -55oC TO 125oC MIN MAX 265 53 45 110 22 19 10 UNITS ns ns ns ns ns ns ns pF pF
PARAMETER E to Outputs
SYMBOL tPHL, tPLH
TEST CONDITIONS CL = 50pF
Test Circuits and Waveforms
tr = 6ns trCL CLOCK 90% 10% tfCL I tWL + tWH = fCL VCC 50% 10% tWL 50% 50% GND tWH INVERTING OUTPUT tTHL tTLH 90% 50% 10% tPHL tPLH INPUT 90% 50% 10% tf = 6ns VCC
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tr = 6ns INPUT 90% 50% 10%
tf = 6ns VCC
GND tTLH 90% 50% 10%
tTHL
INVERTING OUTPUT tPHL tPLH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
5
CD54HC4514, CD74HC4514, CD74HC4515 Test Circuits and Waveforms
(Continued)
trCL CLOCK INPUT 90% 10% tH(H)
tfCL VCC 50% GND tH(L) VCC DATA INPUT tSU(H) CLOCK INPUT
trCL 90% 10% tH(H)
tfCL VCC 50% GND tH(L) VCC 50% GND tSU(L) tTLH 90% tTHL 90% 50% 10% tPHL
DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL
50% GND
OUTPUT tPLH tREM VCC SET, RESET OR PRESET
50% GND
50% GND
IC
CL 50pF
IC
CL 50pF
FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
PACKAGING INFORMATION
Orderable Device 5962-9865501QJA CD54HC4514F3A CD74HC4514E CD74HC4514EE4 CD74HC4514EN CD74HC4514ENE4 CD74HC4514M CD74HC4514M96 CD74HC4514M96E4 CD74HC4514ME4 CD74HC4515E CD74HC4515EE4 CD74HC4515EN CD74HC4515ENE4 CD74HC4515M CD74HC4515M96 CD74HC4515M96E4 CD74HC4515ME4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CDIP CDIP PDIP PDIP PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP PDIP PDIP SOIC SOIC SOIC SOIC
Package Drawing J J N N NT NT DW DW DW DW N N NT NT DW DW DW DW
Pins Package Eco Plan (2) Qty 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 1 1 15 15 15 15 25 TBD TBD Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br)
Lead/Ball Finish Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 15 15 15 15 25 Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCDI004A - JANUARY 1995 - REVISED NOVEMBER 1997
J (R-GDIP-T**)
24 PINS SHOWN B 24 13
CERAMIC DUAL-IN-LINE PACKAGE
C
1
0.065 (1,65) 0.045 (1,14) 0.090 (2,29) 0.060 (1,53)
12 Lens Protrusion (Lens Optional) 0.010 (0.25) MAX 0.175 (4,45) 0.140 (3,56) A
Seating Plane 0.018 (0,46) MIN 0.022 (0,56) 0.014 (0,36) 0.125 (3,18) MIN 0.012 (0,30) 0.008 (0,20) 28 WIDE NARR WIDE NARR 32 WIDE NARR 40 WIDE
0.100 (2,54)
PINS ** DIM "A" MAX MIN "B" "C" MAX MIN MAX MIN NARR
24
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53) 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 4040084/C 10/97
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin). This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 - OCTOBER 1994
NT (R-PDIP-T**)
24 PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
A DIM 24 13
PINS **
24 1.260 (32,04) 1.230 (31,24) 0.310 (7,87) 0.290 (7,37)
28 1.425 (36,20) 1.385 (35,18) 0.315 (8,00) 0.295 (7,49)
A MAX
0.280 (7,11) 0.250 (6,35)
A MIN
B MAX 1 0.070 (1,78) MAX 12 B MIN
0.020 (0,51) MIN
B
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0- 15
4040050 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI006B - SEPTEMBER 2001 - REVISED APRIL 2002
N (R-PDIP-T24)
1.222 (31,04) MAX 24 13
PLASTIC DUAL-IN-LINE
0.360 (9,14) MAX
1 0.070 (1,78) MAX
12
0.200 (5,08) MAX 0.020 (0,51) MIN 0.425 (10,80) MAX
Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0'-15' 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25) NOM 4040051-3/D 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-010
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI008 - OCTOBER 1994
N (R-PDIP-T**)
24 PIN SHOWN A 24 13
PLASTIC DUAL-IN-LINE PACKAGE
0.560 (14,22) 0.520 (13,21)
1 0.060 (1,52) TYP
12 0.200 (5,08) MAX 0.020 (0,51) MIN
0.610 (15,49) 0.590 (14,99)
Seating Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.125 (3,18) MIN 0.010 (0,25) NOM
0- 15
PINS ** DIM A MAX
24 1.270 (32,26) 1.230 (31,24)
28 1.450 (36,83) 1.410 (35,81)
32 1.650 (41,91) 1.610 (40,89)
40 2.090 (53,09) 2.040 (51,82)
48 2.450 (62,23) 2.390 (60,71)
52 2.650 (67,31) 2.590 (65,79) 4040053 / B 04/95
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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