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Preliminary
SPCA701A
DIGITAL VIDEO ENCODER FOR VIDEOCD
GENERAL DESCRIPTION The SPCA701A is designed specifically for VideoCD, video games and other digital video systems, which require the conversion of digital YCrCb (MPEG) data to analog NTSC/PAL video. The device supports a glue-less interface to most popular MPEG decoders. The SPCA701A supports worldwide video standards, including NTSC (N America, Japan) PAL-B, D, G, H, I (Europe, Asia). Furthermore, the SPCA701A operates with a single 2x clock and can be powered with a single 3.3V supply. The composite analog video signal is output simultaneously onto two outputs. Therefore, it allows one output to provide base-band composite video while the other drives a RF modulator. Alternatively, analog luminance (Y) and chrominance (C) information is available for interfacing to S-video equipment. As a slave, the SPCA701A automatically detects the input data formats (PAL/NTSC, CCIR601) and switches internally to provide the proper format on the outputs. This feature, along with the on-board voltage reference and single clock interface, makes the SPCA701A extremely simple to use. In addition, use of 2x over-sampling on-chip simplifies external filter design resulting in reduced overall system cost.
FEATURES 8-bit 4:2:2 YCrCb inputs for glue-less interface to
BLOCK DIAGRAM
VBIAS VREFOUT FSADJUST
MPEG decoders NTSC/PAL composite video outputs (North
CLK Internal VREF COMP
American NTSC and Western European PAL) CVBS or S-video outputs
P[7:0]
VRDAC
9 DAC 2x Upsample Latch 1.3MHz LPF VSYNC* Mod. and Mixer 9 DAC CVBS/C CVBS/Y
3.3 V supply voltage 5 V tolerant for all digital I/O data pins CCIR 601 operation 2x over sampling simplifies external filtering 9-bit DACs
MODE[3:0] MASTER HSYNC*
CBSWAP
SVIDEO
SLEEP
Master or slave video timing Interlaced operation Automatic mode detection/switching in slave mode On-board voltage reference 32-pin PLCC package APPLICATIONS VideoCD Karaoke/video games Digital Video Disk (DVD) Digital VCR Digital set top box
Sunplus Technology Co., Ltd.
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Rev.: 0.2
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Preliminary
SPCA701A
PIN DESCRIPTION (Table 1.) Mnemonic DATA[7:0] PIN No. 21-28 Type I Description YCrCb pixel inputs. They are latched on the rising edge of CLK. YCrCb input data conform to CCIR 601. CLK VSYNC 29 32 I I/O Pixel clock input. Vertical sync input/output. VSYNC is latched/output following the rising edge of CLK. HSYNC 1 I/O Horizontal sync input/output. HSYNC is latched/output following the rising edge of CLK. MASTER 16 I Master/slave mode selection. A logical high for master mode operation. A logical 0 for slave mode operation CBSWAP 15 I Cr and Cb pixel sequence configuration pin. A logic high swap the Cr and Cb sequence. SVIDEO 14 I SVIDEO select input pin. A logic high selects Y/C output. A logic low selects composite video output. SLEEP 13 I Power save mode. A logic high on this pin puts the chip into powerdown mode. Mode[3:2] Mode[1:0] TEST VREFIN 17-18 19-20 2 9 I I I I Mode configuration pin. Useless pins. It will be better to connect them to VDD or DGND. Test pin. These pins must be connected to DGND. Voltage reference input. An external voltage reference must supply typical 1.235V to this pin. A 0.1 F ceramic capacitor must be used to de-couple this input to GND. The decoupling capacitor must be as closed as possible to minimize the length of the load. This pin may be connected directly to VREFOUT. VREFOUT 8 O Voltage reference output. It generates typical 1.2V voltage reference and may be used to drive VREFIN pin directly. FSADJ 5 Full-Scale adjust control pin. The Full-Scale current of D/A converters can be adjusted by connecting a resistor (RSET) between this pin and ground. COMP 6 Compensation pin. A 0.1 F ceramic capacitor must be used to bypass this pin to VAA. The lead length must be kept as short as possible to avoid noise. CVBSY 4 O Composite/Luminance output. This is a high-impedance current source output. The output format can be selected by the PAL pin. The CVBSY can drive a 37.5 Sunplus Technology Co., Ltd. 2 load. If unused, this pin must be connected Rev.: 0.2 1999.12.07
Preliminary
SPCA701A
Mnemonic PIN No. Type directly to GND. CVBSC 11 O Composite/Chroma output. This is a high impedance current source Output. The output format can be selected by the PAL pin. The pin can drive a 37.5 to GND. VBIAS VDD DGND VAA AGND 10 31 30 7 3,12 DAC bias voltage. Potential normally 0.7V less than COMP. Digital power pin Digital ground pin Analog power pin Analog ground pin load. If unused, this pin must be connected directly Description
MODE SELECTION Master mode is selected when MASTER = 1; slave mode is selected when MASTER = 0. Two pins, MODE [3:2], drive three different configuration registers. The most common operating modes can be selected with these pins while in master mode. In slave mode, the common operating modes are automatically determined from the timing of the incoming HSYNC* and VSYNC* signals.
NOTE: The term "common operating mode" refers to North American NTSC and Western European PAL Table 2 illustrates the multi-functionality of the mode pins during master and slave mode. To access the more exotic video formats, slave mode is preferred since the necessary registers are always accessible. If
master mode is needed, the less common modes can still be programmed by first registering the modes as a slave, and then switching to a master. During power-up, the MODE [3:2] pins configure the master registers; i.e., EFIELD, PAL625, are written. Also, during power-up, the slave registers are reset to zero, i.e., YCSWAP.
Table 2. Mode Selection PIN Description The MASTER pin 0 1 MODE[3] YCSWAP EFIELD MODE[2] --PAL625 MODE[1] ----MODE[0] -----
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Preliminary
SPCA701A
Table 3. Configuration Register Settings Mode Register Name EFIELD set to 0 The VSYNC pin will output normal vertical synchronization signal. PAL625 525-line operation will be select YCSWAP Do not swap Y and Cr/Cb Set to 1 The VSYNC pin will output field signal. Low at VSYNC pin for even field, high for odd field The 625-line operation will be select Swap Y and Cr/Cb sequence This is only used at master mode ---Comments This is only used at master mode.
CLOCK TIMING A clock signal with a frequency twice the luminance sampling rate must be present at the CLK pin. All setup and hold timing specifications are measured with respect to the rising edge of this signal.
PIXEL INPUT TIMING PIXEL SEQUENCE Multiplexed Y, Cb, and Cr data is input through the DATA[7:0] inputs. By default, the input sequence for active video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc., in accordance with CCIR-656. This pattern begins during the first CLK period after the falling edge of HSYNC* (regardless of the setting of SLAVE/MASTER mode). The order of Cb and Cr can be reversed by setting the CBSWAP pin. Figure 1 illustrates the timing. If the pixel stream input to the SPCA701A is off by one CLK period, the SPCA701A can lock to the pixel stream by setting the YCSWAP register. This would solve the problem of having the Y and Cr/Cb pixels swapped.
Figure 1. Pix Sequence
CBSWAP(1)
CLK(2) HSYNC*(3)
0
P[7:0]
Cbn
Yn
Crn
Yn + 1
Cbn+2
1
P[7:0]
Crn
Yn
Cbn
Yn + 1
Crn+2
Notes: (1). CBSWAP is pin 11. (2). Pixel transitions must occur observing setup and hold timing about the rising edge of CLK. (3). Pixel sequence will beging with Cbn at 4 x m clock periods following the falling edge of HSYNC*, when m is an integer.
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Preliminary
SPCA701A
VIDEO TIMING The width of the analog horizontal sync pulses and the start and end of color burst is automatically calculated and inserted for each mode according to CCIR-624-4. Color burst is disabled on appropriate scan lines.
Serration and equalization pulses are generated on appropriate scan lines. In addition, rise and fall times of sync, and the burst envelope are internally controlled. Video timing figures follow the text in this section.
SYNC AND BURST TIMING Table 4 lists the resolutions and clock rates for the various modes of operation. Table 5 lists the horizontal counter values for the end of horizontal sync, start of color burst, end of color burst, front porch, back porch, and the first active pixel for the various modes of operation. The front porch is the interval before the next expected falling HSYNC* when outputs are automatically blanked. The horizontal sync width is measured between the 50% points of the falling and rising edges of horizontal sync. The start of color burst is measured between the 50% point of the falling edge of horizontal sync and the first 50% point of the color burst amplitude (nominally +20 IRE for NTSC and 150 mV for PAL-B, D, G, H, I above the blanking level). The end of color burst is measured between the 50% point of the falling edge of horizontal sync and the last 50% point of the color burst envelope (nominally +20 IRE for NTSC and 150 mV for PAL-B, D, G, H, I above the blanking level).
Table 4. Field Resolutions and Clock Rates for Various Modes of Operation Operating Mode NTSC CCIR601 PAL-B,D,G,H,I Active pixels 720 x 240 720 x 288 Total Pixels 858 x 262 864 x 313 CLK Frequency (MHz) 27 27
Table 5. Horizontal Counter Values for Various Video Timings Operation Mode NTSC CCIR601 PAL-B CCIR601 Front porch (a) 20 20 Horizontal Sync Width (b) 63 63 Start of Burst (c) 72 76 Duration of Burst (d) 34 30 Back porch (e) 127 142
Notes: (1) The unit is the number of luminance pixel.
Sunplus Technology Co., Ltd.
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Rev.: 0.2
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Preliminary
SPCA701A
MASTER MODE Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from internal timing and optional software bits. HSYNC*, and VSYNC* are output following the rising edge of CLK. The horizontal counter is
incremented on every other rising edge of CLK. After reaching the appropriate value (determined by the mode of operation), it is reset to one, indicating the start of a new line. The vertical counter is incremented at the start of each new line. After reaching the appropriate value, determined by the mode of operation, it is reset to one, indicating the start of a new field. VSYNC* is asserted for 3 or 2.5 scan lines for 262/525 line and 312/625 line, respectively.
SLAVE MODE Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are inputs that are registered on the rising edge of CLOCK. The horizontal counter is incremented on the rising edge of CLOCK. Two clock cycles after falling edge of HSYNC*, the counter is reset to one, indicating the start of a new line. The vertical counter is
incremented on the falling edge of HSYNC*. A falling edge of VSYNC* resets it to one, indicating the start of a new field. A falling edge of VSYNC* occurring within 1/4 of a scan line from the falling edge of HSYNC* cycle time (line time) indicates the beginning of Field 1. A falling edge of VSYNC* occurring within 1/4 scan line from the mid-point of the line indicates the beginning of Field 2.
The operating mode (NTSC/PAL) can be programmed with the MODE[3:2] bits when the SETMODE (MASTER pin) bit is set high. Alternatively, when SETMODE is low, the mode is automatically detected in slave mode. For example, 525-line operation is assumed, 625-line operation is detected by the number of HSYNC* edges between VSYNC* edges. The frequency of operation (CCIR-601) for both PAL and NTSC is detected by counting the number of clocks per line. The pixel rate is assumed to be 13.5 MHz, 1 count which is detected in between two successive falling edges of HSYNC*.
BURST BLANKING For NTSC, color burst information is automatically disabled on scan lines 1-9 and 264-272, inclusive. (SMPTE line numbering convention.) For PAL-B, D, G, H, I color burst information is automatically disabled on scan lines 1-6, 310-318, and 623-625, inclusive, for fields 1, 2, 5, and 6. During fields 3, 4, 7, and 8, color burst information is disabled on scan lines 1-5, 311-319, and 622-625, inclusive.
Sunplus Technology Co., Ltd.
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Rev.: 0.2
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Preliminary
SPCA701A
VERTICAL BLANKING INTERVALS For NTSC, scan lines 1-9 and 263-272, inclusive, are always blanked. There is no setup on scan lines 10-21 and 273-284 inclusive. All displayed lines in the vertical blanking interval (10-21 and 273-284 for interlaced NTSC; 7-13 and 320-335 for interlaced PAL-B, D, G, H, I) are forced to blank. For PAL-B, D, G, H, I, scan lines 1-6, 311-318, and 624-625, inclusive, during fields 1, 2, 5, and 6, are always blanked. During fields 3, 4, 7, and 8, scan lines 1-5, 311-319, and 624-625, inclusive, are always blanked.
DIGITAL PROCESSING Once the input data is converted into internal YUV format, the UV components are low-pass filtered with a filter. The Y and filtered UV components are up-sampled to CLK frequency by a digital filter.
SUBCARRIER GENERATION To maintain a synchronous sub-carrier relative to HSYNC*, the sub-carrier phase is reset every frame for NTSC and every 8 fields for PAL. The SCA phase is non-zero and depends upon the clock frequency and the video format. For a perfect clock input, the burst frequency is 4.43361875 MHz for PAL-B, D, G, H, I, 3.579545 MHz for NTSC interlaced.
POWER-DOWN MODE In power-down mode (SLEEP pin set to 1), the internal clock is stopped and also an internal reset is forced and the DACs are powered down. When returned high, the device starts from a reset state (horizontal and vertical counters = 0, which is the start of VSYNC in Field 1). This mode should be set when the SPCA701A may be subjected to clock frequencies outside its functional range. If Master = 1, the HSYNC* and VSYNC* pins remain driven to the value previously output before SLEEP was activated and power down current is dependent on loading on the HSYNC* and VSYNC* pins.
Sunplus Technology Co., Ltd.
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Rev.: 0.2
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Preliminary
SPCA701A
Figure 2. Interlaced 525-Line (NTSC) Video Timing
Analog Field 1
Start of YSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
22
Burst Phase Analog Field 2
261
262
263
264
265
266
267
268
269
270
271
272
285
Analog Field 3
523
524
525
1
2 Analog Field 4
3
4
5
6
7
8
9
10
22
Burst Phase
261
262
263
264
265
266
267
268
269
270
271
272
285
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 0 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 0 Relative to B-Y Note: SMPTE line numbering convention rather than CCIR-624 is used.
Sunplus Technology Co., Ltd.
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Rev.: 0.2
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Preliminary
SPCA701A
Figure 3a. Interlaced 625-Line (PAL) Video Timing
Start of VSYNC
Analog Field 1
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
-U Phase Analog Field 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 3
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
Analog Field 4
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Field One Burst Blanking Intervals Field Two Field Three Field Four
Burst Phase = Reference Phase = 135 0 Relative to U PAL Switch = 0, + V Component Burst Phase = Reference Phase + 90 0 = 2250 Relative to U PAL Switch = 1, -V Component
Sunplus Technology Co., Ltd.
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Rev.: 0.2
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Preliminary
SPCA701A
Figure 3b. Interlaced 625-Line (PA L) Video Timing
Start of VSYNC
Analog Field 5
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
-U Phase Analog Field 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 7
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
Analog Field 8
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Field Five Burst Blanking Intervals Field Six Field Seven Field Eight
Burst Phase = Reference Phase = 135 0 Relative to U PAL Switch = 0, + V Component Burst Phase = Reference Phase + 90 0 = 2250 Relative to U PAL Switch = 1, -V Component
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Rev.: 0.2
1999.12.07
Preliminary
SPCA701A
PIXEL INPUT RANGES AND COLORSPACE CONVERSION YC INPUTS (4:2:2 YCRCB) Y has a nominal range of 16-235; Cb and Cr have a nominal range of 16-240, with 128 equal to zero. Values of 0 and 255 are interpreted as 1 and 254 respectively. Y values of 1-15 and 236-254, and CrCb values of 1-15 and 241-254, are interpreted as valid linear values. NTSC mode with setup disabled has 2% less black-to-white range than NTSC mode with setup enabled.
DAC CODING White is represented by a DAC code of 400. For PAL-B, D, G, H, I, the standard blanking level is represented by a DAC code of 120. For NTSC, the standard blanking level is represented by a DAC code of 114, 1 IRE is equivalent to a DAC code of 2.857.
OUTPUTS All digital-to-analog converters are designed to drive standard video levels into an equivalent 37.5 load.
Unused outputs should be connected directly to ground to minimize supply switching currents. Either two composite video outputs or Y/C S-Video outputs are available (selectable by the SVIDEO pin). If the SLEEP pin is high, the DACs are essentially turned off and only the leakage current is present.
COMPOSITE AND LUMINANCE (CVBS/Y)ANALOG OUTPUT When SVIDEO is a logical zero, digital composite video information drives the 9-bit D/A converter that generates the CVBS output. When SVIDEO is a logical one, digital luminance information drives the DAC that generates the analog Y video output.
COMPOSITE AND CHROMINANCE (CVBS/C) ANALOG OUTPUT When SVIDEO is a logical zero, digital composite video information drives the 9-bit D/A converter that generates the CVBS output. When SVIDEO is a logical one, digital chrominance information drives the 9-bit D/A converter that generates the analog C video output.
PC BOARD CONSIDERATIONS The layout should be optimized for lowest noise on the power and ground planes by providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. A well-designed power distribution network is critical to eliminate digital switching noise. The ground plane must provide a low-impedance return path for the digital circuits. A PC board with a minimum of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for ground and power, respectively.
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Preliminary
SPCA701A
COMPONENT PLACEMENT Components should be placed as close as possible to the associated pin. The optimum layout enables the SPCA701A to be located as close as possible to the power supply connector and the video output connector.
POWER AND GROUND PLANES For optimum performance, a common digital and analog ground plane is recommended. Separate digital and analog power planes are recommended. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all SPCA701A power pins, VREF circuitry, and COMP decoupling. At least a 1/8-inch gap is required in between the digital power plane and the analog power plane. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 4, Table 6. This bead should be located within 3 inches of the SPCA701A. The bead provides resistance to switching-currents, acting as a resistance at high frequencies. A low-
resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001.
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Preliminary
SPCA701A
Figure 4. Typical Connection Diagram (Internal Voltage Reference)
Analog Power Plane SPCA701A VAA C4 L1 +3.3V (VCC) VCC
C2,C3
COMP VREFIN VREFOUT C5
GND
Ground (Power Supply Connector) Y/C 2.0K 0.1A 75K Buffer RF Audio
FSADJUST L2 (2) CVBS/Y L3 (2) CVBS/C VAA P + 4.7A Buffer P LPF + Buffer P RF Mod To Video Connector
Schottky Diodes To Filter Schottky Diodes GND 22pF 75 1k Regulated +5V
DAC Output
LPF 22pF
75
10 A H
1.8 AH 330pF
1.8 AH 330pF 82
RF Modulator (1) ZIN = 1K
270pF
270pF
TRAP
Notes: (1). Some modulators may require AC coupling capacitors (10 F). (2). Optional for chroma boost. (3). VREF must be connected to either VREF_OUT or VBIAS.
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3.3K
C6
C1
RESET
Rev.: 0.2
1999.12.07
Preliminary
SPCA701A
Table 6. Typical Parts List (Internal Voltage Reference) Locations C5 - 1, C7 C6 L1 L2, L3 RESET TRAP Description 0.1 F Ceramic Capacitor 47 F Capacitor Ferrite Bead - Surface Mount Ferrite Bead(z < 300 @ 5MHz) Vendor Part Number Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743021447 ATC LCB0805, Taiyo Yuden BK2125LM182 Dale CMF-55C Murata TPSx.xMJ or MB2 (where x.x = sound carrier frequency in MHz) Schottky Diodes BAT85 (BAT54F Dual) HP 5082-2305 (1N6263) Siemens BAT 64-04 (Dual) Note: Vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect SPCA701A performance.
1% Metal Film Resistor Ceramic Resonator
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Rev.: 0.2
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Preliminary
SPCA701A
PACKAGE INFORMATION
Model Number SPCA701A
Package 32-pin PLCC
Ambient Temperature Range 0 - 70
NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product
Sunplus Technology Co., Ltd.
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Rev.: 0.2
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Preliminary
SPCA701A
inches Symbol Min. A A1 B B1 D D1 D2 E E1 E2 e N Nd Ne 0.1 0.06 0.013 0.026 0.485 0.447 0.39 0.585 0.547 0.49 Typ. 0.05 Max. 0.14 0.09 0.02 0.03 0.49 0.45 0.43 0.59 0.55 0.53 Min. 2.54 1.52 0.33 0.66 12.3 11.3 9.91 14.8 13.8 12.5 -
mm Typ. 1.27 32 7 9 Max. 3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.1 13.46 -
DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. reference purposes only. Please note that application circuits illustrated in this document are for
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