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TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633
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SLVS351B - SEPTEMBER 2002 - REVISED NOVEMBER 2003
ULTRALOW-NOISE, HIGH PSRR, FAST RF 1-A LOW-DROPOUT LINEAR REGULATORS
FEATURES
* * * * * * * * * 1-A Low-Dropout Regulator With EN Available in 1.8-V, 2.5-V, 2.8-V, 3-V, 3.3-V, and Adjustable High PSRR (53 dB at 10 kHz) Ultralow Noise (40 V) Fast Start-Up Time (50 s) Stable With a 1-F Ceramic Capacitor Excellent Load/Line Transient Very Low Dropout Voltage (250 mV at Full Load, TPS79630) 5-Pin SOT223-5 and 5-Pin DDPAKPackage
DESCRIPTION
The TPS796xx family of low-dropout (LDO) low-power linear voltage regulators features high power supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in small outline, SOT223-5 and 5-pin DDPAK packages. Each device in the family is stable with a small 1-F ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (e.g., 250 mV at 1 A). Each device achieves fast start-up times (approximately 50 s with a 0.001 F bypass capacitor) while consuming very low quiescent current (265 A typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 A. The TPS79630 exhibits approximately 40 VRMS of output voltage noise with a 0.1 F bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time.
APPLICATIONS
* Powering Noise-Sensitive Circuitry - - RF - - Audio - - VCOs DSP/FPGA/Microprocessor Supplies Post Regulator for Switching Supplies
DCQ PACKAGE SOT223-5 (TOP VIEW) EN IN GND OUT BYPASS/FB
1 2 3 4 5
80 70 Ripple Rejection - dB 60 50 40 30 20 10 0 1 10 100 1k IO = 1 mA
* *
TPS79630
TPS79630
RIPPLE REJECTION vs FREQUENCY
VI = 4 V CO = 10 F C(byp) = 0.01 F Output Spectral Noise Density - V/ Hz
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
0.7 0.6 0.5 0.4 0.3 IO = 1 mA 0.2 0.1 IO = 1.5 A 0.0 100 1k 10k 100k VI = 5.5 V CO = 2.2 F C(byp) = 0.1 F
Tab is GND
IO = 1 A
KTT (DDPAK) PACKAGE (TOP VIEW) EN IN GND OUT BYPASS/FB 1 2 3 4 5
10k 100k
1M
10M
f - Frequency - Hz
f - Frequency - Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002-2003, Texas Instruments Incorporated
TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633
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AVAILABLE OPTIONS
TJ voltage 1.2 to 5.5 V 1.8 V 2.5 V -40C to 125C 2.8 V 3V 3.3 V package SOT223-5 DDPAK SOT223-5 DDPAK SOT223-5 DDPAK SOT223-5 DDPAK SOT223-5 DDPAK SOT223-5 DDPAK part number TPS79601DCQ (1) TPS79601KTT (1) TPS79618DCQ (1) TPS79618KTT (1) TPS79625DCQ (1) TPS79625KTT (1) TPS79628DCQ (1) TPS79628KTT (1) TPS79630DCQ (1) TPS79630KTT (1) TPS79633DCQ (1) TPS79633KTT (1) SYMBOL PS79601 TPS79601 PS79618 TPS79618 PS79625 TPS79625 PS79628 TPS79628 PS79630 TPS79630 PS79633 TPS79633
(1)
Add R for DCQ devices in tape and reel (quantity =2500). Add T for KTT devices in tube (quantity = 50). Add R for KTT devices in tape and reel (quantity = 500).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)(2)
UNIT Input voltage range Voltage range at EN Voltage on OUT Peak output current ESD rating, HBM ESD rating, CDM Continuous total power dissipation Operating junction temperature range, TJ Storage temperature range, Tstg (1) (2) -0.3 V to 6 V -0.3 V to VI + 0.3 V 6V Internally limited 2 kV 500 V See Dissipation Rating Table -40C to 150C -65C to 150C
Stresses beyond those listed under,, absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE DDPAK SOT223 (1) (2) BOARD High K (see Note Low K (see Note
(1)) (2))
RJC 2 C/W 15 C/W
RJA 23 C/W 53 C/W
The JEDEC high K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce copper traces on top of the board.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range EN = VI, TJ = -40 to 125 C, VI = VO(typ) + 1 V, IO= 1 mA, Co = 10 F, C(byp) = 0.01 F (unless otherwise noted)
PARAMETER VI Input voltage (see Note 4) IO Continuous output current (see Note 5) TJ Operating junction temperature 2 TEST CONDITIONS MIN 2.7 0 40 TYP MAX 5.5 1 125 UNIT V A C
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range EN = VI, TJ = -40 to 125 C, VI = VO(typ) + 1 V, IO= 1 mA, Co = 10 F, C(byp) = 0.01 F (unless otherwise noted)
PARAMETER TJ = 25C TPS79601 0 A< IO < 1 A,(see Note 6) TJ = 25C 0 A< IO < 1 A, TJ = 25C 0 A< IO < 1 A, TJ = 25C 0 A< IO < 1 A, TJ = 25C 0 A< IO < 1 A, TJ = 25C 0 A< IO < 1 A, 0 A< IO < 1 A, 0 A< IO < 1 A 0 A< IO < 1 A, VO + 1 V < VI 5.5 V, VO + 1 V < VI 5.5 V, C(byp) = 0.001 F Output noise voltage (TPS79630) BW = 100 Hz to 100 kHz,IO = 1 A, TJ = 25C C(byp) = 0.0047 F C(byp) = 0.01 F C(byp) = 0.1 F Time, start-up (TPS79630) Output current limit Standby current High level enable input voltage Low level enable input voltage Input current (EN) Input current (FB) RL = 3 , Co=1 F, TJ = 25C VO =0 V, 2.7 V < VI < 5.5 V 2.7 V < VI < 5.5 V EN = 0 FB = 1.8 V f = 100 Hz, TJ = 25C, Power supply ripple rejection TPS79630 f = 100 Hz, TJ = 25C, f = 10 kHz, TJ = 25C, f = 100 kHz, TJ = 25C, TPS79628 Dropout voltage (see Note
(1))
TEST CONDITIONS
MIN
TYP VO
MAX
UNIT V
1.22 V VO 5.5 V,
0.98 VO 1.8
1.02 VO
TPS79618 TPS79625 Output voltage TPS79628 TPS79630 TPS79633 Quiescent current (GND current) Load regulation Output voltage line regulation (VO/VO) (see Note 7)
2.8 V < VI < 5.5 V 3.5 V < VI < 5.5 V 3.8 V < VI < 5.5 V 4 V < VI < 5.5 V 4.3 V < VI < 5.5 V TJ = 25C TJ = 25C TJ = 25C
1.764 2.5 2.45 2.8 2.744 3 2.94 3.3 3.234 265
1.831 2.55 2.856 3.06 3.366 385 5 0.05 0.12 54 46 41 40 50 75 110
V
V
A mV %/V
VRMS
C(byp) = 0.001 F C(byp) = 0.0047 F C(byp) = 0.01 F See Note 6 2.4
s 3.5 A A V 0.7 V A A 1 1
EN = 0 V, 2.7 V < VI < 5.5 V 2 1 IO = 10 mA IO = 1 A IO = 1 A IO = 1 A TJ = 25C TJ = 25C TJ = 25C
0.07
1
59 54 53 42 270 365 250 345 220 325 mV dB
IO = 1 A, IO = 1 A IO = 1 A, IO = 1 A IO = 1 A, IO = 1 A
TPS79630 TPS79633
(1)
VIN voltage equals VO(typ) - 100 mV; The TPS79625 and TPS79618 dropout voltage is limited by the input voltage range limitations.
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FUNCTIONAL BLOCK DIAGRAM--ADJUSTABLE VERSION
VIN UVLO Current Sense ILIM GND EN UVLO Thermal Shutdown 250 k Vref R2 _ SHUTDOWN R1 + FB VOUT
External to the Device
VIN
Bandgap Reference
FUNCTIONAL BLOCK DIAGRAM--FIXED VERSION
VIN UVLO GND EN UVLO R2 Thermal Shutdown Current Sense ILIM _ SHUTDOWN R1 + VOUT
VIN
Bandgap Reference
250 k
Vref
Bypass
Terminal Functions
TERMINAL NAME BYPASS EN FB GND VIN VOUT ADJ NA 1 5 3 2 4 FIXED 5 1 N/A 3 2 4 I O I I I/O DESCRIPTION An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise. The EN terminal is an input which enables or shuts down the device. When EN goes to a logic high, the device will be enabled. When the device goes to a logic low, the device is in shutdown mode. This terminal is the feedback input voltage for the adjustable device. Regulator ground The VIN terminal is the input to the device. The VOUT terminal is the regulated output of the device.
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TYPICAL CHARACTERISTICS
TPS79630 OUTPUT VOLTAGE vs OUTPUT CURRENT
3.05 3.04 3.03 VO - Output Voltage - V 3.02 3.01 3.00 2.99 2.98 2.97 2.96 2.95 0.0 0.2 0.4 0.6 0.8 1.0 IO - Output Current - A 0 2.775 -40 -25 -10 5 20 35 50 65 80 95 110 125 290 -40 -25 -10 5 20 35 50 65 80 95 110 125 VI = 4 V CO = 10 F TJ = 25C 2.795 4 VI = 3.8 V CO = 10 F VO - Output Voltage - V Ground Current - A 3 2.790 IO = 1 mA 330 320 IO = 1 A 310 IO = 1 mA 300
TPS79628 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE
350 340
TPS79628 GROUND CURRENT vs JUNCTION TEMPERATURE
VI = 3.8 V CO = 10 F
2 2.785 IO = 1 A
1 2.780
TJ - Junction Temperature - C
TJ - Junction Temperature - C
Figure 1. TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
0.7 Output Spectral Noise Density - V/ Hz 0.6 0.5 0.4 0.3 IO = 1 mA 0.2 0.1 IO = 1.5 A 0.0 100 1k 10k 100k VI = 5.5 V CO = 2.2 F C(byp) = 0.1 F Output Spectral Noise Density - V/ Hz
Figure 2. TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
Output Spectral Noise Density - V/ Hz 0.6 0.5 0.4 0.3 0.2 0.1 0.0 100 IO = 1 A IO = 1 mA VI = 5.5 V CO = 10 F C(byp) = 0.1 F
Figure 3. TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
2.5 VI = 5.5 V CO = 10 F IO = 1 A
2.0
C(byp) = 0.01 F C(byp) = 0.1 F
1.5
1.0
C(byp) = 0.0047 F C(byp) = 0.001 F
0.5
1k
10k
100k
0.0 100
1k
10k
100k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 4. TPS79630 ROOT MEAN SQUARED OUTPUT NOISE vs BYPASS CAPACITANCE
RMS - Root Mean Squared Output Noise - V(RMS) 60 50 40 30 20 10 IO = 250 mA CO = 10 F BW = 100 Hz to 100 kHz 0 0.001 F 0.0047 F 0.01 F 0.1 F V(DO) - Dropout Voltage - mV 350 300 250 200 150 100 50 0 -40 -25 -10 5 VI = 2.7 V CO = 10 F IO = 1 A
Figure 5. TPS79628 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
80 70 60 Ripple Rejection - dB 50 40 30 20 10 0 20 35 50 65 80 95 110 125 1 10 100
Figure 6. TPS79630 RIPPLE REJECTION vs FREQUENCY
VI = 4 V CO = 10 F C(byp) = 0.01 F
IO = 1 mA
IO = 1 A
1k
10k 100k
1M
10M
C(byp) - Bypass Capacitance - F
TJ - Junction Temperature - C
f - Frequency - Hz
Figure 7.
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
TPS79630 RIPPLE REJECTION vs FREQUENCY
80 70 Ripple Rejection - dB 60 50 40 30 20 10 0 1 10 100 1k 10k 100k 1M 10M f - Frequency - Hz IO = 1 mA VI = 4 V CO = 10 F C(byp) = 0.1 F Ripple Rejection - dB 80 70 60 50 40 30 20 10 0 1 10 100 1k 10k 100k 1M 10M f - Frequency - Hz IO = 1 mA VI = 4 V CO = 2.2 F C(byp) = 0.01 F
TPS79630 RIPPLE REJECTION vs FREQUENCY
3 2.75 2.50 2.25 2 IO = 1 A Voltage - V 1.75 1.50 1.25 1 0.75 0.50 0.25 0 0 100
START-UP TIME
VI = 4 V, CO = 10 F, II = 1.0 A C(byp) = 0.001 F C(byp) = 0.0047 F Enable
IO = 1 A
C(byp) = 0.01 F
200
300
400
500
600
t - Time - ns
Figure 10. TPS79618 LINE TRANSIENT RESPONSE
VI - Input Voltage - V VI - Input Voltage - V 5 4 3 2 40 VO - Change in Output Voltage - mV 20 0 -20 -40 0 20 40 60 80 100 120 140 160 180 200 t - Time - s IO = 1 A CO = 10 F C(byp) = 0.01 F dv 1V + ms dt 6 5 4 3 40 VO - Change in Output Voltage - mV 20 0 -20 -40 0
Figure 11. TPS79630 LINE TRANSIENT RESPONSE
IO - Output Current - A 2 1 0 -1 150 75 0 -75
Figure 12. TPS79628 LOAD TRANSIENT RESPONSE
IO = 1 A CO = 10 F C(byp) = 0.01 F
dv 1V + ms dt
VI = 3.8 V CO = 10 F C(byp) = 0.01 F
di 1A + ms dt
VO - Change in Output Voltage - mV
20 40 60 80 100 120 140 160 180 200 t - Time - s
-150 0
100 200 300 400 500 600 700 800 900 1000 t - Time - s
Figure 13.
Figure 14. TPS79630 DC DROPOUT VOLTAGE vs OUTPUT CURRENT
350 300 250 Dropout Voltage - mV TJ = 125C 250 200 150 100 50 0 TJ = -40C TJ = 25C 300 DC Dropout Voltage - mV
Figure 15. TPS79601 DROPOUT VOLTAGE vs INPUT VOLTAGE
TPS79625 POWER UP/POWER DOWN
4.0 3.5 3.0 500 mV/Div 2.5 2.0 1.5
VI VO = 2.5 V RL = 10 C(byp) = 0.01 F
TJ = 125 C 200 TJ = 25 C 150 TJ = -40 C 100 50 0 IO = 1 A CO = 10 F C(byp) = 0.01 F 2.5 3.0 3.5 4.0 4.5 5.0
1.0 0.5 0 0 1 2 3 4 5 6 7 8 9 10 200 s/Div
VO
0 100 200 300 400 500 600 700 800 9001000 IO - Output Current - mA
VI - Input Voltage - V
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
MINIMUM REQUIRED INPUT VOLTAGE vs OUTPUT VOLTAGE
4.5 ESR - Equivalent Series Resistance - Minimum Required Input Voltage - V IO = 1 A 4.0 TJ = 125 C
TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT
100 ESR - Equivalent Series Resistance - CO = 1 F Region of Instabilty
TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT
100 CO = 2.2 F Region of Instabilty
10
10
3.5
1 Region of Stabilty 0.1
1 Region of Stabilty 0.1
3.0 TJ = -40 C 2.5 TJ = 25 C
2.0 1.5 2.0 2.5 3.0 3.5 4.0 VO - Output Voltage - V
0.01 1 10 30 60 125 250 500 750 1000 IO - Output Current - mA
0.01 1 10 30 60 125 250 500 750 1000 IO - Output Current - mA
Figure 19.
Figure 20. TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT
100 ESR - Equivalent Series Resistance - CO = 10.0 F Region of Instabilty
Figure 21.
10
1 Region of Stabilty 0.1
0.01 1 10 30 60 125 250 500 750 1000 IO - Output Current - mA
Figure 22.
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APPLICATION INFORMATION
The TPS796xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265 A typically), and enable input to reduce supply currents to less than 1 A when the regulator is turned off. A typical application circuit is shown in Figure 23.
TPS796xx VI IN
BYPASS
OUT 2.2 F EN + GND
VO 0.01 F 1 F
Figure 23. Typical Application Circuit
External Capacitor Requirements
A 2.2-F or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS796xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. Like all low dropout regulators, the TPS796xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 1 F. Any 1 F or larger ceramic capacitor is suitable. The internal voltage reference is a key source of noise in an LDO regulator. The TPS796xx has a BYPASS pin which is connected to the voltage reference through a 250-k internal resistor. The 250-k internal resistor, in conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the BYPASS pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. For example, the TPS79630 exhibits 40 VRMS of output voltage noise using a 0.1-F ceramic bypass capacitor and a 10-F ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250-k resistor and external capacitor.
Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device.
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APPLICATION INFORMATION (continued) Regulator Mounting
The tab of the SOT223-5 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation. Although the tab of the SOT223-5 is electrically grounded, it is not intended to carry any current. The copper pad that acts as a heat sink should be isolated from the rest of the circuit to prevent current flow through the device from the tab to the ground pin. Solder pad footprint recommendations for the devices are presented in an application bulletin Solder Pad Recommendations for Surface-Mount Devices, literature number AB-132, available from the TI web site (www.ti.com).
Programming the TPS79601 Adjustable LDO Regulator
The output voltage of the TPS79601 adjustable regulator is programmed using an external resistor divider as shown in Figure 29. The output voltage is calculated using:
V O +V ref 1 ) R1 R2
where Vref = 1.2246 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 40-A divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error. The recommended design procedure is to choose R2 = 30.1 k to set the divider current at 40 A, C1 = 15 pF for stability, and then calculate R1 using:
V R1 + V O *1 ref R2
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. The approximate value of this capacitor can be calculated as:
C1 + (3 x 10 -7) x (R1 ) R2) (R1 x R2)
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration) then the minimum recommended output capacitor is 2.2 F instead of 1 F.
TPS79601 VI 2.2 F 2V 0.7 V FB GND R2 EN OUT C1 R1 VO 1 F IN OUTPUT VOLTAGE PROGRAMMING GUIDE OUTPUT VOLTAGE 1.8 V 3.6 V R1 R2 C1 33 pF 15 pF
14.0 k 30.1 k 57.9 k 30.1 k
Figure 24. TPS79601 Adjustable LDO Regulator Programming
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APPLICATION INFORMATION (continued) Regulator Protection
The TPS796xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. The TPS796xx features internal current limiting and thermal protection. During normal operation, the TPS796xx limits output current to approximately 2.8 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately 165C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately 140C, regulator operation resumes.
THERMAL INFORMATION
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax) above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:
P max + V *V D I(avg) O(avg) I O(avg) )V I(avg) xI (Q) (3)
where: * VI(avg) is the average input voltage. * VO(avg) is the average output voltage. * IO(avg) is the average output current. * I(Q) is the quiescent current. For most TI LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RJC), the case to heatsink (RCS), and the heatsink to ambient (RSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object's thermal resistance. Figure 25 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and (b) a DDPAK package mounted on a JEDEC high-K board.
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THERMAL INFORMATION (continued)
A CIRCUIT BOARD COPPER AREA C B B RCS A C RSA DDPAK Package (b) C TC RJC TJ A B
SOT223 Package (a)
TA
Figure 25. Thermal Resistances Equation 4 summarizes the computation:
T J + T ) PDmax x R )R )R A JC CS SA (4)
The RJC is specific to each regulator as determined by its package, lead frame, and die size provided in the regulator's data sheet. The RSA is a function of the type and size of heatsink. For example, black body radiator type heatsinks can have RCS values ranging from 5C/W for very large heatsinks to 50C/W for very small heatsinks. The RCS is a function of how the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a SOT223 package, RCSof 1C/W is reasonable. Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground plane for additional heatsinking to improve their thermal performance. Computer aided thermal modeling can be used to compute very accurate approximations of an integrated circuit's thermal performance in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks, and different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (RJA). This RJAis valid only for the specific operating environment used in the computer model. Equation 4 simplifies into equation 5:
T J + T ) PDmax x R A JA (5)
Rearranging equation 5 gives equation 6:
R JA + T J-T A PDmax (6)
Using equation 5 and the computer model generated curves shown in Figure 26 and Figure 29, a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment.
DDPAK Power Dissipation
The DDPAK package provides an effective means of managing power dissipation in surface mount applications. The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the package.
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THERMAL INFORMATION (continued)
To illustrate, the TPS72525 in a DDPAK package was chosen. For this example, the average input voltage is 5 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is:
P Dmax + (5 * 2.5) V x 1 A + 2.5 W (7)
Substituting TJmax for TJ into equation 6 gives equation 8:
R JA max + (125 * 55) C 2.5 W + 28 C W (8)
From Figure 26, DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm2 for the part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 26 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 27 shows the side view of the operating environment used in the computer model.
THERMAL RESISTANCE vs COPPER HEATSINK AREA 40 No Air Flow
C/W
R JA - Thermal Resistance -
35 150 LFM 30
250 LFM 25
20
15 0.1
1 10 Copper Heatsink Area - cm2
100
Figure 26. DDPAK Thermal Resistance vs Copper Heatsink Area
12
TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633
www.ti.com SLVS351B - SEPTEMBER 2002 - REVISED NOVEMBER 2003
THERMAL INFORMATION (continued)
2 oz. Copper Solder Pad with 25 Thermal Vias
1 oz. Copper Power Plane
1 oz. Copper Ground Plane
Thermal Vias, 0.3 mm Diameter, 1,5 mm Pitch
Figure 27. DDPAK Thermal Resistance From the data in Figure 28 and rearranging equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed.
MAXIMUM POWER DISSIPATION vs COPPER HEATSINK AREA 5 TA = 55 C PD - Maximum Power Dissipation - W
4
250 LFM
150 LFM 3
No Air Flow 2
1 0.1
1 10 Copper Heatsink Area - cm2
100
Figure 28. Maximum Power Dissipation vs Copper Heatsink Area
SOT223 Power Dissipation
The SOT223 package provides an effective means of managing power dissipation in surface mount applications. The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the package.
13
TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633
SLVS351B - SEPTEMBER 2002 - REVISED NOVEMBER 2003 www.ti.com
THERMAL INFORMATION (continued)
To illustrate, the TPS72525 in a SOT223 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55C, no air flow is present, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is:
P Dmax + (3.3 * 2.5) V x 1 A + 800 mW (9)
Substituting TJmax for TJ into equation 6 gives equation 10:
R JA max + (125 * 55) C 800 mW + 87.5 C W (10)
From Figure 29, RJA vs PCB Copper Area, the ground plane needs to be 0.55 in2 for the part to dissipate 800 mW. The operating environment used to construct Figure 29 consisted of a board with 1 oz. copper planes. The package is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1 oz. ground plane.
THERMAL RESISTANCE vs PCB COPPER AREA 180 No Air Flow
C/W
R JA - Thermal Resistance -
160 140 120 100 80 60 40 20 0 0.1
1 PCB Copper Area - in2
10
Figure 29. SOT223 Thermal Resistance vs PCB AREA From the data in Figure 29 and rearranging equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed (see Figure 30).
14
TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633
www.ti.com SLVS351B - SEPTEMBER 2002 - REVISED NOVEMBER 2003
THERMAL INFORMATION (continued)
MAXIMUM POWER DISSIPATION vs COPPER HEATSINK AREA 6 TA = 25 C PD - Maximum Power Dissipation - W 5
4 4 in2 PCB Area 3 0.5 in2 PCB Area
2
1
0 0 25 50 75 100 125 150 TA - Ambient Temperature - C
Figure 30. SOT223 Power Dissipation
15
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