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STV9427 STV9428-STV9429
HIGH SPEED MULTISYNCH ON-SCREEN DISPLAY FOR MONITOR
. . . . . . . . . . . . . . . . .
CMOS SINGLE CHIP OSD FOR MONITOR BUILT IN 1 KBYTE RAM HOLDING : - CHARACTER CODES - USER DEFINABLE CHARACTERS 207 ALPHANUMERIC CHARACTERS OR GRAPHIC SYMBOLS IN INTERNAL ROM 12 x 18 CHARACTER DOT MATRIX PROGRAMMABLE ACCENTUATED CHARACTER SET CHARACTER BLINKING RAM DEFINABLE COLOR LOOK UP TABLE UP TO 16 USER DEFINABLE CHARACTERS UP TO 80MHz PIXEL CLOCK INTERNAL HORIZONTAL PLL (15 TO 120kHz) PROGRAMMABLE VERTICAL HEIGHT OF CHARACTER WITH A SLICE INTERPOLATOR TO MEET MULTI-SYNCH REQUIREMENTS PROGRAMMABLE VERTICAL AND HORIZONTAL POSITIONING FLEXIBLE SCREEN DESCRIPTION 22 CONTROL CODES FOR POWERFULL SERIAL ATTRIBUTES 2-WIRES ASYNCHRONOUS SERIAL MCU INTERFACE (I2C PROTOCOL) 8 x 8 BITS PWM DAC OUTPUTS SINGLE POSITIVE 5V SUPPLY
8 x 8 bits PWM DAC are available to provide DC voltage control to other peripherals. The STV9427/28/29 provides the user an easy to use and cost effective solution to display alphanumeric or graphic information on monitor screen.
DIP16 (Plastic Package) ORDER CODE : STV9427
DIP20 (Plastic Package) ORDER CODE : STV9428
DESCRIPTION The STV9427/28/29 is an ON SCREEN DISPLAY for monitor. It is built as a slave peripheral connected to a host MCU via a serial I2C bus. It includes a display memory, controls all the display attributes and generates pixels from the data read in its on chip memory. The line PLL and a special slice interpolator allow to have a display aspect which does not depend on the line and frame frequencies. I2C interface allows MCU to make transparent internal access to prepare the next pages during the display of the current page. Toggle from one page to another by programming only one register.
June 1998
DIP24 (Plastic Package) ORDER CODE : STV9429
1/20
STV9427 - STV9428 - STV9429
PIN CONNECTIONS
DIP16 (STV9427)
VDD1 TST XTO XTI RESET VSYNC HSYNC GND
DIP20 (STV9428)
VDD2 B G R FBLK GND SDA SCL
PWM1 VDD1 TST XTO XTI RESET VSYNC HSYNC GND PWM2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PWM0 VDD2 B G R FBLK GND SDA SCL PWM3
PWM6 PWM1 VDD1 TST XTO XTI RESET VSYNC HSYNC GND PWM2 PWM5
DIP24 (STV9429)
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PWM7 PWM0 VDD2 B G
9427-01.EPS / 9428-01.EPS / 9429-01.EPS 9427-01.TBL
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
R FBLK GND SDA SCL PWM3 PWM4
PIN DESCRIPTION
Symbol PWM6 PWM1 VDD1 TST XTO XTI RESET VSYNC HSYNC GND PWM2 PWM5 PWM4 PWM3 SCL SDA GND FBLK R G B VDD2 PWM0 PWM7 Pin Number DIP24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DIP20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DIP16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O O O S I O I I I I S O O O O I I/O S O O O O S O O DAC0 Output DAC1 Output +5V Logic Supply Reserved (not to be connected) Crystal Output Crystal or Clock Input Reset Input (Active Low) Vertical Sync Input Horizontal Sync Input Logic Ground DAC2 Output DAC3 Output DAC4 Output DAC5 Output Serial Clock Serial Input/output Data Ground Fast Blanking Output Red Output Green Output Blue Output +5V Outputs Supply DAC6 Output DAC7 Output Description
2/20
STV9427 - STV9428 - STV9429
BLOCK DIAGRAMS STV9427
XTI 4 XTO 3 TST 2 VDD1 1 VDD2 16
HSYNC 7
HORIZONTAL DIGITAL PLL
4K ROM
1K RAM
Address/Data
VSYNC 6 RESET 5
DISPLAY CONTROLLER
I C BUS INTERFACE
2
13 R
14 G
15 B
12 FBLK
8
11
9 SCL
10 SDA
GND GND
STV9428
XTI 5 XTO 4 TST 3 VDD1 2 VDD2 19
HSYNC 8
HORIZONTAL DIGITAL PLL
4K ROM
1K RAM 20 PWM0
Address/Data
PWM
11 PWM3 10 PWM2
VSYNC 7 RESET 6
DISPLAY CONTROLLER
I2C BUS INTERFACE
1 PWM1
16 R
17 G
18 B
15 FBLK
9
14
12 SCL
13 SDA
GND GND
STV9429
XTI XTO TST VDD1 VDD2
6
5
4
3
22 24 PWM7 23 PWM0
HSYNC 9
HORIZONTAL DIGITAL PLL
4K ROM
1K RAM
14 PWM3
PWM
Address/Data
13 PWM4 12 PWM5 11 PWM2
VSYNC 8 RESET 7
DISPLAY CONTROLLER
I2C BUS INTERFACE
2 PWM1 1 PWM6
19 20 21
R G B
18
FBLK
10
17
15
SCL
16
SDA
GND GND
3/20
9429-02.EPS
STV9429
9428-02.EPS
STV9428
9427-02.EPS
STV9427
STV9427 - STV9428 - STV9429
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VIN TOPER TSTG Supply Voltage Input Voltage Operating Temperature Storage Temperature Parameter Value -0.3, +7.0 -0.3, +7.0 0, +70 -40, +125 Unit V V C C
9427-02.TBL 9427-03.TBL
ELECTRICAL CHARACTERISTICS (VDD1 = VDD2 = 5V, VSS = 0V, TA = 0 to 70C, fXTAL = 8 to 15MHz, TEST = 0 V, unless otherwise specified)
Symbol SUPPLY VDD IDD INPUTS SCL, SDA, RESET, VSYNC and HSYNC VIL VIH IIL OUTPUTS SDA open drain and PWMi (i = 0 to 7) VOL VOH VOL VOH Output Low Voltage (IOL = 1.6mA) Output High Voltage (IOH = -0.1mA) Output Low Voltage (IOL = 1.6mA) Output High Voltage (IOH = -0.1mA) 0 0.9VDD 0 0.9VDD 0.4 VDD 0.4 VDD V V V V Input Low Voltage Input High Voltage Input Leakage Current 2.4 -10 +10 0.8 V V A Supply Voltage Supply Current 4.75 5 65 5.25 90 V mA Parameter Min. Typ. Max. Unit
R, G, B, FBLK
Figure 1 :
R, G, B, FBLK Typical Outputs Static Characteristics
5
VOL , VOH (V)
VOH 2.5
VOL 0 10 -5 10 -4 10 -3 10 -2 10 -1
9427-17.EPS
I (A)
4/20
STV9427 - STV9428 - STV9429
TIMINGS
Symbol Parameter Min. Typ. Max. Unit OSCILATOR INPUT : XTI (see Figure 2) tWH tWL fXTAL fPXL RESET tRES RESET Low Level Pulse 4 s 5 5 5 ns ns ns Clock High Level Clock Low Level Clock Frequency Pixel Frequency 20 20 6 30 15 80 ns ns MHz MHz
R, G, B, FBLK (CLOAD = 30pF) tR tF tSKEW
2
Rise Time (see Note 1) Fall Time (see Note 1) Skew between R, G, B, FBLK
I C INTERFACE : SDA AND SCL (see Figure 3) fSCL tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tF tR SCL Clock Frequency (Horizontal frequency = 32kHz) Time the bus must be free between 2 access Hold Time for Start Condition Set up Time for Stop Condition Clock Low Level Clock High Level Hold Time Data Set up Time Data SDA Fall Time SCL and SDA Rise Time 500 500 500 400 400 0 500 20 Depend on the pull-up resistor and on the load capacitance 288 kHz ns ns ns ns ns ns ns
9427-04.TBL
ns
Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization.
Figure 2
Figure 3
Stop Start tBUF Data tHDAT Stop
tWL XTI
9427-03.EPS
SDA
9427-04.EPS
tWH
tHDS SCL tHIGH
tSUDAT
tSUP tLOW
5/20
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION The STV9427/28/29 display processor operation is controlled by a host MCU via the I2C interface. It is fully programmable through internal read/write registers and performs all the display functions by generating pixels from data stored in its internal memory. After the page downloading from the MCU, the STV9427/28/29 refreshes screen by its built in processor, without any MCU control (access). In addition, the host MCU has a direct access to the on chip 1Kbytes RAM during the display of the current page to make any update of its contents. With the STV9427/28/29, a page displayed on the screen is made of several strips which can be of 2 types : spacing or character and which are described by a table of descriptors and character codes in RAM. Several pages can be downloaded at the same time in the RAM and the choice of the current display page is made by programming the DISPLAY CONTROL register. I - Serial Interface The 2-wires serial interface is an I2C interface. To be connected to the I2C bus, a device must own its slave address ; the slave address of the STV9427/28/29 is BA (in hexadecimal).
A6 1 A5 0 A4 1 A3 1 A2 1 A1 0 A0 1 R/W
I.1 - Data Transfer in Write Mode T h e h os t MC U ca n w ri t e d at a in t o t he STV9427/28/29 registers or RAM. To write data into the STV9427/28/29, after a start, the MCU must send (Figure 4) : - First, the I2C address slave byte with a low level for the R/W bit, - The two bytes of the internal address where the MCU wants to write data(s), - The successive bytes of data(s). All bytes are sent MSB bit first and the write data transfer is closed by a stop. Each byte is synchronously transfered at each HSYNC period. I.2 - Data Transfer in Read Mode T h e h ost MC U ca n read d at a f ro m t he STV9427/28/29 registers, RAM or ROM. To read data from the STV9427/28/29 (Figure 5), the MCU must send 2 different I2C sequences. The first one is made of I2C slave address byte with R/W bit at low level and the 2 internal address bytes. The second one is made of I2C slave address byte with R/W bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence. Each byte is synchronously transfered at each HSYNC period. The first data byte, in read mode, is available one Hsync period after the acknowledge of the address byte.
Figure 4 : MCU I2C Write Operation
SCL R/W SDA Start I2 C Slave Address ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK A13 A12 A11 A10 A9 A8 ACK
LSB Address
MSB Address
SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop
Data Byte 1
Data Byte 2
Data Byte n
Figure 5 : MCU I2C Read Operation
SCL SDA
Start R/W A7 A6 A5 A4 A3 A2 A1 A0 ACK A13 A12 A10 A10 MSB Address A9 A8 ACK Stop
I2C Slave Address
ACK
LSB Address
SCL SDA
Start R/W
D7
ACK *
D6
D5
D4
D3
D2
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK Stop
I2C Slave Address
Data Byte 1
Data Byte n
Note : The first data bit out (D7) is valid after one scanline period.
6/20
9427-06.EPS
9427-05.EPS
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) I.3 - Addressing Space I.3.1 - General Mapping STV9427/28/29 registers, RAM and ROM are mapped in a 16Kbytes addressing space. The mapping is the following :
0000 1024 bytes RAM 03FF 0400 Empty Space 07FF 0800 Character Generator ROM 3FBF 3FC0 Empty Space 3FD0 3FCF Internal Registers 3FD0
2
I.4 - Register Set I.4.1 - PWM Registers The eight registers described below are only available with the STV9429 : PULSE WIDTH MODULATOR 0 (STV9429)
3FD0 V07 V06 V05 V04 V03 V02 V01 V00 V0[7:0] : Digital value of the 1st PWM D to A converter.
Descriptors character codes and user definable characters
PULSE WIDTH MODULATOR 1 (STV9429)
3FD1 V17 V16 V15 V14 V13 V12 V11 V10
V1[7:0] : Digital value of the 2nd PWM DAC.
I.3.2 - I C Registers Mapping
3FCF 3FD0
PULSE WIDTH MODULATOR 2 (STV9429)
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 Reserved 3FD2 V27 PWM registers V26 V25 V24 V23 V22 V21 V20
V2[7:0] : Digital value of the 3rd PWM DAC.
PULSE WIDTH MODULATOR 3 (STV9429)
3FD3 V37 V36 V35 V34 V33 V32 V31 V30
3FD7 3FD8 3FDF 3FE0
V3[7:0] : Digital value of the 4th PWM DAC.
3FE7 3FE8
3FEF 3FF0
3FF8 3FF9 3FFF
Color 0 Color 1 Color 2 Color 3 Color 4 Color 5 Color 6 Color 7 Color look-up table (CLUT) Color 8 Color 9 Color 10 Color 11 Color 12 Color 13 Color 14 Color 15 Line Duration Top Margin Horizontal Delay Character Height Display Control Control registers Locking Time Constant Capture Time Constant Initial Pixel period Frequency Multiplier Reserved
PULSE WIDTH MODULATOR 4 (STV9429)
3FD4 V47 V46 V45 V44
th
V43
V42
V41
V40
V4[7:0] : Digital value of the 5 PWM DAC.
PULSE WIDTH MODULATOR 5 (STV9429)
3FD5 V57 V56 V55 V54 V53 V52 V51 V50
V5[7:0] : Digital value of the 6th PWM DAC.
PULSE WIDTH MODULATOR 6 (STV9429)
3FD6 V67 V66 V65 V64
th
V63
V62
V61
V60
V6[7:0] : Digital value of the 7 PWM DAC.
PULSE WIDTH MODULATOR 7 (STV9429)
3FD7 V77 V76 V75 V74 V73 V72 V71 V70
V7[7:0] : Digital value of the 8th PWM DAC.
Note : Power on reset default value of PMW register is 00H
7/20
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) I.4.2 - Look-up Table Registers Color look-up table [CLUT] is read/write RAM table. Mapping address is described in Chapter I.3.2. The CLUT is splitted in 2 blocks of 8 bytes. Each byte contains foreground and background informations as described below :
SHA BR BG BB FL FR FG FB
Table 2 : CLUT Color Selection
Code Name COL1 COL2 COL6 COL7 COL0 COL1 COL6 COL7 Code Nbr (h) 10 11 16 17 10 11 16 17 Color Look-up Table in RAM @ 3FE0 : Color 0 @ 3FE1 : Color 1 @ 3FE6 : Color 6 @ 3FE7 : Color 7 @ 3FE8 : Color 8 @ 3FE9 : Color 9 @ 3FEE : Color 14 @ 3FEF : Color 15
SHA : Shadowing FL : Flashing foreground BR, BG, BB : Background color FR, FG, FB : Foreground color If SHA = 1 and BR = BG = BB = 0, the background of the character is transparent. Each block may store a different set of colors. One block of colors may be used for the normal items of the menu while the second block, with brighter colors, may be used for selected items of the menu. The block selection is done by programming bit CLU3 of CLU[3:0] of the character descriptor (see Table 1). It remains selected all the row long. Bit CLU2, CLU1 and CLU0 of CLU[3:0] of the character descriptor select the active color at the beginning of the row. The active color can be changed along the row, using 8 control codes COL0 to COL7. Each control code (COL0 to COL7) active a dedicated color byte in the CLUT as described in Table 2. Table 1 : CLUT Block Selection
CLU3 CLU[2:0] 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Code Name Col 0 Col 1 Col 2 Col 3 Col 4 Col 5 Col 6 Col 7 Col 0 Col 1 Col 2 Col 3 Col 4 Col 5 Col 6 Col 7 Ram @(hex) @3FE0 @3FE1 @3FE2 @3FE3 @3FE4 @3FE5 @3FE6 @3FE7 @3FE8 @3FE9 @3FEA @3FEB @3FEC @3FED @3FEE @3FEF Reset Value (hex) 07 16 25 34 43 52 61 70 70 61 52 43 34 25 16 07
I.4.3 - Control Registers LINE DURATION (Reset Value : 20h)
3FF0 VSP HSP LD6 LD5 LD4 LD3 LD2 LD1 VSP : V-SYNC active edge selection = 0, falling egde, = 1, rising edge. : H-SYNC active edge selection = 0, falling egde, = 1, rising edge.
HSP
LD[6:1] : LINE DURATION LD0 = 0 LD1 = 2 periods of character One character period is 12 pixels long.
TOP MARGIN (Reset Value : 60h)
3FF1 M8 M7 M6 M5 M4 M3 M2 M1
0
M[8:1] : TOP MARGIN height from the VSYNC reference edge. M0 = 0 M1 = 2 scan lines
Note : The top margin is displayed before the first strip of descriptor list. It can be black if FBK of DISPLAY CONTROL register is set or transparent if FBK is clear.
HORIZONTAL DELAY (Reset Value : 20h)
3FF2 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 DD[7:0] : HORIZONTAL DISPLAY DELAY from the HSYNC reference edge to the 1st pixel position of the character strips. Unit = 6 pixel periods. Minimum value is 08h. First pixel position = [DD[7:0] - 6] x 6 + 54. with DD[7:0] = 1,3,5 then the delay is 60 pixel.
1
8/20
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) CHARACTERS HEIGHT (Reset Value : 24h)
3FF3 CH5 CH4 CH3 CH2 CH1 CH0 : Lock enable 0 = R,G,B, FBLK are always enabled, 1 = R,G,B, FBLK are enabled only when PLL is locked. AF[2:0] : Phase constant during the capture process. BF[2:0] : Frequency constant during the capture process. LEN
CH[5:0] : HEIGHT of the character strips in scan lines. For each scan line, the number of the slice which is displayed is given by : SLICE-NUMBER = SCAN-LINE-NUMBER x 18 round . CH[5:0] SCAN-LINE-NUMBER = Number of the current scan line of the strip.
INITIAL PIXEL PERIOD (Reset Value : 28h)
3FF7 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PP[7:0] : Value to initialize the pixel period of the PLL.
DISPLAY CONTROL (Reset Value : 00h)
3FF4 OSD FBK FL1 OSD FBK FL0 P9 P8 P7 P6
FREQUENCY MULTIPLIER (Reset Value : 0Ah)
3FF8 FM3 FM2 FM1 FM0
: ON/OFF (if 0, R, G, B and FBLK outputs are 0). : Fast blanking control : = 1, forces FBLK pin at "1" outside and inside the OSD area. This leads to blank video RGB and to only display OSD RGB. = 0, FBLK pin is driven according character code for normal display of OSD data. FL[1:0] : Flashing mode : - 00 : No flashing. The character attribute is ignored, - 01 : Flashing at fF (50% duty cycle), - 10 : Flashing at 2 fF, - 11 : Flashing at 4 fF. Note : fF is 128 time vertical frequency. P[9:6] : Address of the 1st descriptor of the current displayed pages. P[13:10] and P[5:0] = 0 ; up to 16 different pages can be stored in the RAM.
FM[3:0] : Frequency multiplier of the crystal frequency to reach the high frequency used by the PLL to derive the pixel frequency.
Note : For high pixel frequency (over 70MHz), write at address 3FFF, Data F0h.
II - Descriptors SPACING
MSB LSB L/C 0 SL7 L/C SL6 SL5 SL4 SL0
SL3 SL2 SL1
: LINE or CHARACTER spacing : = 0, spacing descriptor defined as character height (SL[7:0] = 1 to 255 character). = 1, spacing descriptor defined as scan line height (SL[7:0] = 1 to 255 scan lines). SL[7:0] : Number of selected height (character or scan lines according L/C).
LOCKING CONDITION TIME CONSTANT (Reset Value : 01h)
3FF5 FR FR AS2 AS1 AS0 LUK BS2 BS1 BS0
CHARACTER
MSB LSB DE 1 DE CLU3 CLU2 CLU1 CLU0 C9 C5 C4 C3 C2 C8
C7 C6
C1 UEN
: Free Running ; if = 1 PLL is disabled and the pixel frequency keeps its last value. AS[2:0] : Phase constant during locking conditions. BS[2:0] : Frequency constant during locking conditions. LUK : Lock unlock status bit 0 = unlocked PLL 1 = Locked PLL
CAPTURE PROCESS TIME CONSTANT (Reset Value : 24h)
3FF6 LEN AF2 AF1 AF0 BF2 BF1 BF0
: Display enable : = 0, R = G = B = 0 and FBLK = FBK bit of display control register on the whole strip, = 1, display of the characters. CLU[3:0] : Active color selection at the begining of the strip. C[9:1] : Address of the first character code of the strip. UEN : UDC enable 0 : codes 240 to 254 (FOh to FEh) are read in ROM, 1 : codes 240 to 255 (FOh to FFh) are read in RAM (UDC).
9/20
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) III - Code Format The codes of STV9427/28/29 are all single byte codes. There are basically 3 kinds of code : - The control codes from 0 to 27 (00h to 1Bh) and from 224 to 239 (E0h to EFh). - The ROM character codes from 32 to 223 (20h to DFh) and from 240 to 255 (F0h to FFh). - The user definables characters codes from 240 to 254 (F0h to FFh). Each row must begin with a displayable character code followed by a NOP or any control code. For code definition see Table 4. III.1 - Control Codes Control codes must be followed by a displayable code (from 32 to 223), except for RTN & EOL. They must not be used twice consecutively without a displayable code between them. The control code CALL is preceded by an address byte. The control codes are not displayed except if mentioned.
Code 0 (00h) : NOP : no operation and no display is performed, can be used to spare a location in RAM for an active control code. : SYMETRIES : TSHS(01) Top S i d e H o r iz on t al Symetry code displays the top half side of the following displayable code symetricaly to the bottom side. BSHS(02) Bottom Side Horizontal Symetry code displays the bottom half side of the following displayable code symetricaly to the top side. HFLIP(03) Horizontal Flip code flips horizontaly the following displayable code. LSVS(04) Left Side Vertical Symetry code displays the left half side of the f o ll o w i n g d i sp l ay a bl e c o de symetricaly to the right side. RSVS(05) Right Side Vertical symetry code displays the right half side of the f o ll o w i n g d i sp l ay a bl e c o de symetricaly to the left side. VFLIP(06) Vertical Flip code flips verticaly the following displayable code. HVFLIP(07) Horizontal & Vertical Flip code flips horizontaly and verticaly the following displayable code. Codes 8 (08h) (at odd @) Code 09 to 14 (09h to 0Eh) Code 15 (0Fh) Codes 16 to 23 (10h to 17h) : RTN : return to the CALL + 1 code location (see Note). : Reserved : EOL, end of line terminates the display of the current row. : COL0 to COL7 codes select 1 byte among 8 within the CLUT in RAM. The block selection is fixed by CLU3 bit of the active character descriptor (see Table 1 and Table 2). : CALL, these control codes switch the display of the next character to the code address given by the next byte as following :
0 0 0 1 1 0 0 A9
Codes 24 to 27 (18h to 19h)
CALL CODE (odd @) MSB ADDRESS BYTE (even @) LSB A[9:1]
A8
A7
A6
A5
A4
A3
A2
A1
: Address of the next code to be used (A0 = 0 only even addresses).
Notes : CALL and RTN code must be used twin. They cannot be nested. CALL and RTN codes are displayed as a SPACE character. CALL and RTN codes must be placed at odd addresses. They may be preceed by a NOP in order to place them at the right position.
Codes 28 to 31 (1Ch to 1Fh)
: Reserved
Codes 1 to 7 (01h to 07h)
Code 224 to 239 : Accent shapes from 224 to 239 (E0h (E0h to EFh) to EFh) are used combined with all other character codes 32 to 223 (10h to DFh) and placed before the target character. The first set of accents, 224 to 231 (E0h to E7h) must be used with lower case letters. The 5 upper slices of the target character are replaced by the accent shape. The second set of accents, 232 to 239 (E8h to EFh) must be used with the upper case letters (capital letters). The 3 upper slices of the target character are replaced by the accent shape. Accent code must always be followed by a displayable character or a space.
III.2 - ROM Character Codes
Codes 32 to 223 : R O M c h ar ac t e r s h ap e s ar e described as 12x18 pixel matrix as (20h to DFh) and Codes 240 to 254 shown in Table 5. It comprises 60 logos dedicated for (F0h to FEh) monitor application (Horizontal position, keystone, ...), 25 characters f o r h o r i z o n t a l b a r -g ra p h an d additional shapes.
10/20
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) Table 4
Code N MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 NOP TSHS BSHS HFLIP LSVS RSVS VFLIP RTN EOL 1 1 COL0 COL1 COL2 COL3 COL4 COL5 COL6 CALL CALL 2 2 Space ! " # $ % & ' ( * + , . / 3 3 0 1 2 3 4 5 6 7 8 9 : ; < = / ? 4 4 @ A B C D E F G H I J K L M N O 5 5 P Q R S T U V W X Y Z [ (R) (c) _ 6 6 a b c d e f g h i j k l m n o 7 7 p q r s t u v w x y z { | << Arr If Arr up 8 8 C c AE ae O o 1/2 1/4 3/4 fh fv hz 9 9 Cont1 Cont2 Bright Color Spkr Mute Dgaus Balance Vfcus Hfcus Vsz Vpos Vlin Hsz Hpos1 Hpos2 10 A Hlin1 Hlin2 Kystn Kybal1 Kybal2 Pincus Pinbal Tilt1 Tilt2 Cornr0 Cornr2 Cornr3 Cornr4 kh hz 11 B Box0 Box1 Box2 Box3 Box4 Box5 Box6 Box7 Box8 Box9 Bar0 Bar1 Bar2 Bar3 Bar4 12 C Bar5 Bar6 Bar7 Bar8 Bar9 Bar11 Bar12 Bar13 Bar14 Bar16 Bar17 Bar18 13 D Bar21 Bar22 10o 1o0 Indxrgt rtn hbar0 hbar1 vbar0 vbar1 treble bass mic 14 E ' dn ' up ^ dn x dn dn up dot dn
..
15 F R G B 1 2 clock0 clock1 clock2 A E T S Z D
9427-09.TBL
Bar10 Indxup
HVFLIP COL7
dn
' up ` up ^ up x up up up
..
Cornr1 Box10 Bar15
L
Bar19 upidx0 dot up Bar20 upidx1 up
11/20
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) III.3 - User Definable Character Codes (UDC) Codes 240 to 254 (F0h to FEh) refer to character shape loaded in RAM. The STV9427/28/29 allows the user to dynamically define character(s) for his own needs (for a special LOGO for example). Like the ROM characters, a UDC is made of a 12 pixels x 18 slices dot matrix. In a UDC, each pixel is defined with a bit, 1 refers to foreground, and 0 to background color. Each slice of a UDC uses 2 bytes :
add + 1 add (even) PX7 PX6 PX5 PX4 PX11 PX3 PX10 PX2 PX9 PX1 PX8 PX0
PX11 is the left most pixel. Character slice address : SLICE ADDRESS = 64 (CHARACTER NUMBER - 240) + (SLICE NUMBER + 7) x 2. Where : - CHARACTER NUMBER is the number given by the character code. - SLICE NUMBER is the number given by the slice interpolator (n of the current slice of the strip : 1 <<18). Figure 6 : User Definable Character Codes
Code Number Ram Location hex dec 00 00 Code 240/F0h 3F 63 40 64 Code 241/F1h 7F 127 80 128 Code 242/F2h BF 191 C0 192 Code 243/F3h FF 255 100 256 Code 244/F4h 319 140 320 Code 245/F5h 383 180 384 Code 246/F6h 447 1C0 448 Code 247/F7h 511 200 512 Code 248/F8h 575 240 576 Code 249/F9h 639 280 640 Code 250/FAh 703 2C0 704 Code 251/FBh 767 300 768 Code 252/FCh 831 340 832 Code 253/FDh 895 380 896 Code 254/FEh 959 3C0 960 Code 255/FFh 1023
UDC LOCATION
hex
0B 0D 0F 11
21
31
3F
CHARACTER ORGANIZATION
12/20
9427-18.EPS
Slice Offset dec hex 01 03 05 07 09 11 0A 13 0C 15 0E 17 10 19 21 23 25 27 29 31 33 20 35 37 39 41 43 45 47 49 30 51 53 55 57 59 61 63 3E
dec 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
Unused Unused Unused Unused Unused Unused Unused Slice 0 Slice 1 Slice 2 Slice 3 Slice 4 Slice 5 Slice 6 Slice 7 Slice 8 Slice 9 Slice 10 Slice 11 Slice 12 Slice 13 Slice 14 Slice 15 Slice 16 Slice 17 Unused Unused Unused Unused Unused Unused Unused
SLICER ORGANIZATION x x x x 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) Figure 7 : Hozizontal Timing
HSYNC R, G, B 1 LD[6:1] = 40 DD[7:0] = 10 Nber of characters of the row 6.5 Active OSD Video
9427-07.EPS
67
80 81
IV - Clock and Timing The whole timing is derived from the XTI and the horizontal SYNCHRO input frequencies. The XTI input frequency can be an external clock, crystal or a ceramic resonator signal thanks to XTI/XTO pins. The value of this frequency can be chosen between 6 and 15MHz is used by the PLL to generate a pixel clock locked on the horizontal synchro input signal. IV.1 - Horizontal Timing (see Figure 7) The number of pixel periods is given by the LINE DURATION register and is equal to : [LD[6:1] x 2 + 1 ] x 12. (LD[6:1] : value of the LINE DURATION register). This value allows to define the horizontal size of the characters. The horizontal left margin is given by the HORIZONTAL DELAY register and is equal to : (DD[7:0] -6 ) x 6 + 54 (DD[7:0] : value of the DISPLAY DELAY register). This value allows to define the horizontal position of the characters on the screen. Due to internal logic, minimum horizontal delay is fixed at 4.5 characters (54 pixel) when DD is even and lower or equal to 6, and it is fixed at 5 characters (60 pixel) when DD is odd and lower or equal to 7. IV.2 - D to A Timing (STV9427) The D/A converters of the STV9427 are pulse width modulator converter. The frequency of the output signal is : the duty cycle is :
Vi[7:0] 256 x 6 fXTAL 256 x 6
ered in several strips. Each strip is defined by a descriptor stored in memory. A table of descriptors allows screen composition and different tables can be stored in memory at the page addresses (16 possible addresses). Two types of strips are available : - Spacing strip : its descriptor (see II) gives the number of black (FBK = 1 in DISPLAY CONTROL register) or transparent (FBK = 0) lines. - Character strip : its descriptor gives the memory address of the character codes corresponding to the 1st displayed character. The characters and attributes (see code format III) are defined by a succession of codes stored in the RAM at addresses starting from the 1st one given by the descriptor. A character strip can be displayed or not by using the DE bit of its descriptor. After the VSYNC edge, the first strip descriptor is read at the top of the current table of descriptors at the address given by P[9:0] (see DISPLAY CONTROL register) ; if it is a spacing strip, SL[7:0] black or transparent scan lines are displayed ; if it is a character strip, during CH[5:0] scan lines (CH[5:0] given by the CHARACTER HEIGHT register), the character codes are read at the addresses starting from the 1st one given by the descriptor until a end of line character or the end of the scan line ; the next descriptor is then read and the same process is repeated until the next edge of VSYNC. Figure 8 : PWM Timing
V1[7:0] 0 TXTAL 1 128 255
9427-08.EPS
and
PWM1 Signal
256 . TXTAL
per cent.
After a low pass filter, the average value of the Vi [7:0] V DD output is :
256 x 6
V - Display Control A screen is composed of successive scanlines gath-
13/20
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) Figure 9 : Relation between Screen/Address Page/Character Code in RAM
DISPLAY CONTROL Register OSD FBK FL1 FL0 P9 P8 P7 P6 V-SYNC
2nd CHARACTER STRIP CODES OTHER TABLE OF DESCRIPTORS OTHER (UDC for example) 1st CHARACTER STRIP CODES 3rd CHARACTER SRTIP CODES OTHER (CODES OR DESCRIPTORS) RAM CODE AND DESCRIPTORS
SPACING ROW1 ROW2 SPACING ROW3
TOP MARGIN (see note) TOP SPACING STRIP 1st CHARACTER STRIP 2nd CHARACTER STRIP SPACING STRIP 3 CHARACTER STRIP
rd
SPACING TABLE OF THE DESCRIPTORS
| BOTTOM SPACING STRIP SCREEN
Note : Height of Top Margin is given by TOP MARGIN Register
Figure 10 : User Definable Character
ON THE SCREEN 36 Pixels (= 3 Characters) 1 2 3 Character Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
IN THE RAM (example for Character n5)
Slice 1 Slice 2 Slice 3 Slice 4 Slice 5 Slice 6 Slice 7 Slice 8 Slice 9 Slice 10 Slice 1 1 Slice 12 Slice 13 Slice 14 Slice 15 Slice 16 Slice 17 Slice 18
: 0x00 : 0x08 : 0x0c : 0x0e : 0x0f : 0x0f : 0x0f : 0x0f : 0x0e : 0x0c : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 Odd Address
0xff 0x7f 0x3f 0x1f 0x1f 0x1f 0x1e 0x1e 0x3c 0x3c 0x78 0x78 0xf1 0x00 0x00 0x00 0x00 0x00 Even Address
36 Slices (= 2 Characters)
MSB
LSB
9427-10.EPS
4
5
6
Character Number
14/20
9427-09.EPS
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) Table 5 : ROM Character Generator
2 3 4 5 6 7 8 9 A B C D E F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
15/20
9427-11A.EPS / 9427-11B.EPS
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) VI - PLL The PLL function of the STV9427/28/29 provides the internal pixel clock locked on the horizontal synchro signal and used by the display processor to generate the R, G, B and fast blancking signals. It is made of 2 PLLs. The first one analogic (see Figure 11), provides a high frequency signal locked on the crystal frequency. The frequency multiplier is given by : N = 2 (FM[3:0] + 3) Where FM[3:0] is the value of the FREQUENCY MULTIPLIER register. Figure 11 : Analogic PLL
N . FXTAL VCO %N FXTAL
VI.1 - Programming of the PLL Registers Frequency Multiplier (@3FF8) This register gives the ratio between the crystal frequency and the high frequency of the signal used by the 2nd PLL to provide, by division, the pixel clock. The value of this high frequency must be near to 200MHz (for example if the crystal is a 8MHz, the value of FM must be equal to 10) and greater than 2.5 x (pixel frequency). The frequency of VCO must stand within limits given below : Fpxlmin x 16 FVCO Fpxlmax x 2.5 Initial Pixel Period (@3FF7) This register allows to increase the speed of the convergence of the PLL when the horizontal frequency changes (new graphic standart). The relationship between FM[3:0], PP[7:0], LD[6:1], fHSYNC and fXTAL is :
2 (FM[3:0] + 3) FXTAL PP[7:0] = round 8 - 24 6 (LD[6:1] 2 + 1) FHSYNC
9427-12.AI
FILTRE
The second PLL, full digital (see Figure 12), provides a pixel frequency locked on the horizontal synchro signal. The ratio between the frequencies of these 2 signals is : M = 12 x (LD[6:1] x 2 + 1) Where LD[6:1] is the value of the LINE DURATION register. Figure 12 : Digital PLL
M . FH-SYNC N . FXTAL %D %M FH-SYNC
D(n)
ALGO
err(n)
Locking Condition Time Constant (@ 3FF5) This register gives the constants AS[2:0] and BS[2:0] used by the algo part of the PLL (see Figure 11) to calculate, from the phase error, err(n), the new value, D(n), of the division of the high frequency signal to provide the pixel clock. These two constants are used only in locking condition, which is true, if the phase error is less than a fixed value during at least, 4 scan lines. If the phase error becomes greater than the fixed value, the PLL is not in locking condition but in capture process. In this case, the algo part of the PLL used the other constants, AF[2:0] and BF[2:0], given by the next register. Capture Process Time Constant (@ 3FF6) The choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the PLL.
16/20
9427-13.AI
STV9427 - STV9428 - STV9429
FUNCTIONAL DESCRIPTION (continued) VI.2 - How to choose the value of the time constant ? The time response of the PLL is given by its characteristic equation which is : (x - 1)2 + ( + ) (x - 1) + = 0. Where : = 3 LD[6:1] 2A - 11 and = 3 LD[6:1] 2B - 19. (LD[6:1] = value of the LINE DURATION register, A = value of the 1st time constant, AF or AS and B = value of the 2d time constant, BF or BS). As you can see, the solution depend only on the LINE DURATION and the TIME CONSTANTS given by the I2C registers. If ( + )2 - 4 0 and 2 - < 4, the PLL is stable and its response is like this presented on Figure 13. Figure 13 : Time Response of the PLL/Characteristic Equation Solutions (with real solutions)
PLL Frequency f1 f0 Input Frequency
9427-14.AI
In this case the PLL is stable if > 0.7 damping coefficient). Figure 14 : Time Response of the PLL/Characteristic Equation Solutions (with Complex Solutions)
PLL Frequency f1 f0 Input Frequency f1 f0 t t
The Table 6 gives some good values for A and B constants for different values of the LINE DURATION. Summary For a good working of the PLL : - A and B time constants must be chosen among values for which the PLL is stable, - B must be equal or greater than A and the difference between them must be less than 3, - The greater (A, B) are, the faster the capture is. An optimal choice for the most of applications might be : - For locking condition : AS = 0 and BS = 1, - For capture process : AF = 2 and BF = 4. But for each application the time constants can be calculated by solving the characteristic equation and choosing the best response.
t
f1 f0 t
If ( + )2 - 4 0, the response of the PLL is like this presented on Figure 14. Table 6 : Valid Time Constants Examples
B\A 0 1 2 3 4 5 6 7 0 YYYY YYYY NYYY NNNY NNNN NNNN NNNN NNNN
16 N
Note 1 : Case of A[2:0] = 1 (001) and B[2:0] = 4 (100) : LD Valid Time Constants 32 Y 48 Y 64 Y
Value of LINE DURATION Register (@ 3FF0) : LD = 16 :LD[6:0] = 0010000, LD[6:1] = 001000 LD = 32 :LD[6:0] = 0100000 LD = 48 :LD[6:0] = 0110000 LD = 64 :LD[6:0] = 1000000, LD[6:1] = 100000. Table meaning : N = No possible capture - No stability Y = PLL can lock
17/20
9427-05.TBL
1 YYYY YYYY YYYY YYYY NYYY(1) NNNY NNNN NNNN
2 YYYY YYYY YYYY YYYY YYYY YYYY NYYY NNNY
3 YYYN YYYN YYYN YYYN YYYN YYYN YYYN YYYN
4 YNNN YNNN YNNN YNNN YNNN YNNN YNNN YNNN
5 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN
6 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN
9427-15.AI
STV9427 - STV9428 - STV9429
PACKAGE MECHANICAL DATA (STV9427) 16 PINS - PLASTIC DIP
Dimensions a1 B b b1 D E e e3 F I L Z
Min. 0.51 0.77
Millimeters Typ.
Max. 1.65
Min. 0.020 0.030
Inches Typ.
Max. 0.065
0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27
0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050
DIP16.TBL
18/20
PM-DIP16.EPS
STV9427 - STV9428 - STV9429
PACKAGE MECHANICAL DATA (STV9428) 20 PINS - PLASTIC DIP
Dimensions a1 B b b1 D E e e3 F I L Z
Min. 0.254 1.39
Millimeters Typ.
Max. 1.65
Min. 0.010 0.055
Inches Typ.
Max. 0.065
0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34
0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 0.053
DIP20.TBL
19/20
PM-DIP20.EPS
STV9427 - STV9428 - STV9429
PACKAGE MECHANICAL DATA (STV9429) 24 PINS - PLASTIC DIP
Dimensions a1 b b1 b2 D E e e3 F I L
Min.
Millimeters Typ. 0.63 0.45 1.27
Max.
Min.
Inches Typ. 0.025 0.018 0.050
Max.
0.23
0.31 32.2 16.68 2.54 27.94 14.1 4.445 3.3
0.009
0.012 1.268 0.657 0.100 1.100 0.555
DIP24.TBL
15.2
0.598
0.175 0.130
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
20/20
PM-DIP24.EPS

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