View AD5318_239802.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

=
PRELIMINARY TECHNICAL DATA
2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP AD5308/AD5318/AD5328*
GENERAL DESCRIPTION
FEATURES AD5308: Eight Buffered 8-Bit DACs in 16-Lead TSSOP AD5318: Eight Buffered 10-Bit DACs in 16-Lead TSSOP AD5328: Eight Buffered 12-Bit DACs in 16-Lead TSSOP Low Power Operation: 1.4mA (max) @ 3 V Guaranteed Monotonic By Design over All Codes Power-Down to 120 nA @ 3 V, 400 nA @ 5 V Double-Buffered Input Logic Buffered/Unbuffered Reference Input Options Output Range: 0-2 VREF Power-On-Reset Programmability Individual-channel Powerdown Simultaneous Update of Outputs (LDAC) Low Power, SPITM, QSPITM, MICROWIRETM and DSPCompatible 3-Wire Serial Interface On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range -40oC to +105 oC
The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit buffered voltage-output DACs, in a 16-lead TSSOP package, which operate from a single 2.5 V to 5.5 V supply consuming 1.4 mA at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/s. The AD5308/AD5318/AD5328 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. The references for the eight DACs are derived from two reference pins (one per DAC quad). These reference inputs can be configured as buffered or unbuffered inputs. The parts incorporate a power-on-reset circuit that ensures that the DAC outputs power-up to 0 V and remain there until a valid write to the device takes place. The outputs of all DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 400 nA @ 5 V (120 nA @ 3 V). The eight channels of the DAC may be powered-down individually.
APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources All three parts are offered in the same pinout, which allows Optical Networking users to select the amount of resolution appropriate for their Automatic Test Equipment application without redesigning their circuit board. Mobile Comms Programmable Attenuators FUNCTIONAL BLOCK DIAGRAM Industrial Process Control
VDD VREF ABCD
INPUT LDAC
REGISTER
GA IN-SELECT LOGIC
DAC
REGISTER DAC REGISTER DAC REGISTER
STRING DAC A STRING DAC B STRING DAC C STRING DAC D STRING DA C E STRING DAC F STRING DAC G STRING DAC H
BUFFER
VOUTA VOUTB VOUTC VOUTD VOUTE VOUTF VOUTG VOUTH
INPUT
REGISTER
BUFFER
INPUT
REGISTER
BUFFER
SCLK INTERFACE LOGIC
INPUT
REGISTER
DAC
REGISTER
BUFFER
SYNC
INPUT
REGISTER
DAC
REGISTER
BUFFER
DIN
INPUT
REGISTER
DAC
REGISTER
BUFFER
INPUT
REGISTER
DAC
REGISTER
BUFFER
INPUT
REGISTER
DAC
REGISTER
BUFFER
POWER-ON RESET
GA IN-SEL EC T LO GIC
POWER-DOWN L OG IC
LDAC
VREF EFGH
GND
*Protected by U.S. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. PrH 07/01
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
PRELIMINARY TECHNICAL DATA
(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
Parameter1 DC PERFORMANCE AD5308 Resolution Relative Accuracy Differential Nonlinearity AD5318 Resolution Relative Accuracy Differential Nonlinearity AD5328 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband5 Upper Deadband5 Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6 DAC REFERENCE INPUTS6 VREF Input Range VREF Input Impedance (RDAC) 18 Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage7 Maximum Output Voltage7 DC Output Impedance Short Circuit Current Power-Up Time LOGIC INPUTS6 Input Current VIL, Input Low Voltage 1 0.25 >10 22 -90 -75
3, 4
AD5308/AD5318/AD5328-SPECIFICATIONS
Min B Version2 Typ Max Unit
Conditions/Comments
8 0.15 0.02 10 0.5 0.05 12 2 0.2 5 0.3 10 10 -12 -5 -60 200
Bits 1 LSB 0.25 LSB Bits LSB LSB Bits LSB LSB mV % of FSR mV mV
Guaranteed Monotonic by Design Over All Codes
4 0.5
Guaranteed Monotonic by Design Over All Codes
16 1 60 1.25 60 60
Guaranteed Monotonic by Design Over All Codes VDD = 4.5 V, Gain = 2; See Figures 4 and 5 VDD = 4.5 V, Gain = 2; See Figures 4 and 5 See Figure 4. Lower Deadband Exists Only If Offset Error Is Negative See Figure 5. Upper Deadband Exists Only If VREF = VDD/2 and Offset Plus Gain Error is Positive
ppm of FSR/C ppm of FSR/C dB VDD = 10% V RL = 2 k to GND or VDD VDD/2 V VDD/2 V M k dB dB V V mA mA s s A V V V V pF V mA mA A A VIH = VDD and V IL = GND All DACs in Unbuffered Mode. In Buffered Mode, extra current is typically x A per DAC; x = (5 A + VREF/RDAC)*4. VIH = VDD and V IL = GND Buffered Reference Mode Unbuffered Reference Mode Buffered Reference Mode and Power-Down Mode Unbuffered Reference Mode. 0-2 VREF Output Range Frequency = 10 kHz Frequency = 10 kHz This is a measure of the minimum and maximum drive capability of the output amplifier. VDD = 5 V VDD = 3 V Coming Out of Power-Down Mode. VDD = 5 V Coming Out of Power-Down Mode. VDD = 3 V
0.001 VDD - 0.001 0.5 25 16 2.5 5 3 0.8 0.6 0.5 1.7 9 2.5 1.0 0.8 0.4 0.12 5.5 1.8 1.5 1 1
VIH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode)8 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode)9 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V
VDD VDD VDD VDD
= 5 V 10% = 3 V 10% = 2.5 V = 2.5 V to 5.5 V; TTL and 1.8 V CMOS-Compatible
NOTES
See Terminology. Temperature range: B Version: -40C to +105C; typical at 25C. DC specifications tested with the outputs unloaded unless stated otherwise. 4 Linearity is tested using a reduced code range: AD5308 (Code 8 to 255); AD5318 (Code 28 to 1023); AD5328 (Code 115 to 4095). 5 This corresponds to x codes. x = Deadband Voltage/LSB size. 6 Guaranteed by design and characterization; not production tested. 7 For the amplifier output to reach its minimum voltage, Offset Error must be negative; for the amplifier output to reach its maximum voltage, VREF = VDD/2 and Offset plus Gain Error must be positive. 8 Interface Inactive. All DACs active. DAC outputs unloaded. 9 All 8 DACS powered down. Specifications subject to change without notice.
2 3 1
-2-
REV. PrH
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328 V to 5.5 AC CHARACTERISTICS1 (V = 2.5 noted.) V; R = 2 k to GND; C = 200 pF to GND; all specifications T to T unless otherwise
DD L L MIN MAX
Parameter
2
B Version3 Min Typ Max
Unit
Conditions/Comments
Output Voltage Settling Time AD5308 AD5318 AD5328 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion
6 7 8 0.7 12 0.5 0.5 1 3 200 -70
8 9 10
s s s V/s nV sec nV sec nV sec nV sec nV sec kHz dB
VREF = 2.5 V 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex) 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex) 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex) 1 LSB Change Around Major Carry
VREF = 2 V 0.1 V p-p. Unbuffered Mode VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz
NOTES 1 Guaranteed by design and characterization; not production tested. 2 See Terminology. 3 Temperature range: B Version: -40C to +105C; typical at 25C. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 B Version Limit at TMIN, TMAX 33 13 13 13 5 4.5 0 50 20 20 0
(VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX unless otherwise noted.)
Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time LDAC Pulsewidth SCLK Falling Edge to LDAC Rising Edge SCLK Falling Edge to LDAC Falling Edge
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
NOTES 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figures 2 and 3. Specifications subject to change without notice.
REV. PrH
-3-
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
t1 SCLK t8 SYNC t6 t5 DIN DB15 DB0 t9 t11 LDAC1 t10 LDAC2 t4 t3 t2 t7
NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE. 2. SYNCHRONOUS LDAC UPDATE MODE.
Figure 1. Serial Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Input Voltage to GND . . . . . . . -0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . -0.3 V to VDD + 0.3 V VOUT A-VOUT D to GND . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . . . -65C to +150C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . 150C 16-Lead TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . (TJ max - TA)/JA JA Thermal Impedance . . . . . . . . . . . . . . . . . . 150.4C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . 220 +5/-0C Time at Peak Temperature . . . . . . . . . . 10 sec to 40 sec
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model AD5308BRU AD5318BRU AD5328BRU
Temperature Range -40C to +105C -40C to +105C -40C to +105C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP)
Package Option RU-16 RU-16 RU-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5308/AD5318/AD5328 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. PrH
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic LDAC SYNC
Function Active low control input that transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively this pin can be tied permanently low. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Reference Input Pin for DACs A, B, C and D. It may be configured as a buffered or unbuffered input to the four DACs, depending on the state of the BUF control bits. It has an input range from 0.25 V to VDD/2 in unbuffered mode and from 1 V to VDD/2 in buffered mode. Reference Input Pin for DACs E, F, G and H. It may be configured as a buffered or unbuffered input to the four DACs, depending on the state of the BUF control bits. It has an input range from 0.25 V to VDD/2 in unbuffered mode and from 1 V to VDD/2 in buffered mode. Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. Ground reference point for all circuitry on the part. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
2
3 4 5 6 7 8
VDD VOUTA VOUTB VOUTC VOUTD VREFABCD
9
VREFEFGH
10 11 12 13 14 15 16
VOUTE VOUTF VOUTG VOUTH GND DIN SCLK
PIN CONFIGURATION
LDAC SYNC VDD VOUT A VOUT B VOUTC VOUTD VREFABCD
1 2 3 4 5 6 7 8
16
SCLK DIN GND VOUTH VOUTG VOUTF VOUT E VREFEFGH
AD5308/ AD5318/ AD5328
TOP VIEW (Not to Scale)
15 14 13 12 11 10 9
REV. PrH
-5-
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
TERMINOLOGY RELATIVE ACCURACY MAJOR-CODE TRANSITION GLITCH ENERGY
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus Code plots can be seen in TPCs 1, 2, and 3.
DIFFERENTIAL NONLINEARITY
Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plots can be seen in TPCs 4, 5, and 6.
OFFSET ERROR
Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to the (SYNC held high). It is specified in nV secs and is measured with a fullscale change on the digital input pins, i.e., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is a measure of the offset error of the DAC and the output amplifier. (See Figures 4 and 5.) It can be negative or positive. It is expressed in mV.
GAIN ERROR
This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV secs.
ANALOG CROSSTALK
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
GAIN ERROR DRIFT
This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV secs.
DAC-TO-DAC CROSSTALK
This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at 2 V and VDD is varied 10%.
DC CROSSTALK
This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV secs.
MULTIPLYING BANDWIDTH
This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in V.
REFERENCE FEEDTHROUGH
The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs.
CHANNEL-TO-CHANNEL ISOLATION
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs.
This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dBs.
-6-
REV. PrH
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
G AIN E RROR + O FFS E T E RRO R G AIN E RROR + O FFS E T ERRO R UP P E R DE A DBA ND CO DE S
O UTP UT V OLTA GE
O UTP UT V OLTA GE
A CTUA L IDEA L NE G A TIV E O FFS E T E RROR P OS ITIV E O FFS E T E RROR A CTUA L IDE A L DA C CO DE
DA C CO DE
FULL S CA LE
Figure 5. Transfer Function with Positive Offset (VREF = VDD/2)
LOW E R DE A DBA ND CO DE S A M PLIFIE R FOO TROO M
NE G A TIV E O FFS E T E RROR
Figure4. Transfer Function with Negative Offset (VREF = VDD/2)
REV. PrH
-7-
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
FUNCTIONAL DESCRIPTION
The AD5308/AD5318 /AD5328 are octal resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits respectively. Each contains eight output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/s. DACs A, B, C and D share a common reference input, namely VREFABCD. DACs E, F, G and H share a common reference input, namely VREFEFGH. Each reference input may be buffered to draw virtually no current from the reference source or may be unbuffered to give a reference input range from 0.25 V to VDD/2. The devices have a power-down mode in which all DACs may be turned off individually with a high-impedance output.
Digital-to-Analog Section
as low as 0.25 V and as high as VDD/2 since there is no restriction due to headroom and footroom of the reference amplifier.
R R R TO O UTP UT A M PLIFIE R
R R
Figure 7. Resistor String
The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corresponding DAC. Figure 6 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by:
VREF x D 2N
If there is a buffered reference in the circuit (e.g., REF192), there is no need to use the on-chip buffers of the AD5308/ AD5318/AD5328. In unbuffered mode the input impedance is still large at typically 22 k.
Output Amplifier
VOUT =
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, the gain of the output amplifier, offset error, and gain error. With a gain of 2 (Gain bit = 1), the output range is 0.001 V to 2 VREF. Because of clamping, however, the maximum output is limited to VDD - 0.001 V. The output amplifier is capable of driving a load of 2 k to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11. The slew rate is 0.7 V/s with a half-scale settling time to 0.5 LSB (at 8 bits) of 6 s.
POWER-ON RESET
where
D = decimal equivalent of the binary code that is loaded to the DAC register; 0-255 for AD5308 (8 Bits) 0-1023 for AD5318 (10 Bits) 0-4095 for AD5328 (12 Bits) N = DAC resolution
VREF ABCD
BUF
REFERENCE BUFFER (Gain = 2)
The AD5308/AD5318/AD5328 are provided with a poweron reset function, so that they power up in a defined state. The power-on state is:
VOUTA
INPUT REGISTER
DAC REGISTER
RESISTOR STRING OUTPUT BUFFER AMPLIFIER
* Normal Operation * Reference Inputs Unbuffered * GAIN bits not set-up * Output Voltage Set to 0 V * LDAC bits set to "LDAC High" Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.
Figure 6. Single DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 7. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
DAC Reference Inputs
There is a reference pin for each quad of DACs. The reference inputs are buffered, but can also be configured as unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage -8- REV. PrH
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
SERIAL INTERFACE Table I. Address Bits for the AD53x8
The AD5308/AD5318/AD5328 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE and DSP interface standards.
Input Shift Register
A2 (Bit 14) A1 (Bit 13) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
A0 (Bit 12) 0 1 0 1 0 1 0 1
DAC Addressed DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H
The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2. The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data will be shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. To end the transfer, SYNC must be taken high after the falling edge of the sixteenth SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the 16th falling edge of SCLK, the data transfer will be aborted and the DAC input registers will not be updated. Data is loaded MSB first (Bit 15). The first bit determines whether it is a DAC Write or a Control Function.
DAC Write
Control Functions
In the case of a Control Function the MSB (Bit 15) will be a `1'. This is followed by two control bits, which determine the mode. There are four different control modes, each of which is described below. The write sequences for these modes are shown in Table 2. (1)Reference Mode: This mode determines whether the reference for each group of DACs is buffered or unbuffered. The gain of the output amplifier must be set to 2VREF. To setup the reference of both groups, set the control bits to (00), set the GAIN bits, set the BUF bits and clear the RESERVED bits. BUF: Controls whether the reference of a group of DACs is buffered or unbuffered. The reference of the first group of DACs (A, B, C, D) is controlled by setting bit 2, and the second group of DACs (E, F, G, H) is controlled by setting bit 3. 0: Unbuffered Reference 1: Buffered Reference GAIN: The 2 GAIN bits (bit 4 and bit 5) must be set to `1' to give an output range of 0-2 VREF. RESERVED: These bits (bit 0 and bit 1) are reserved for possible future use, and must be cleared to `0'.
Here, the 16-bit word consists of 1 control bit and 3 address bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. In the case of a DAC Write, the MSB will be a `0'. The next three address bits determine whether the data is for DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G or DAC H. The AD5328 uses all 12 bits of DAC data. The AD5318 uses ten bits and ignores the two LSBs. The AD5308 uses eight bits and ignores the last four bits. As good programming practice, these ignored LSB's should be set to `0'. The data format is straight binary, with all zeros corresponding to 0 V output and all ones corresponding to full-scale output.
BIT 15 (MSB) D/C A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0
BIT 0 (LSB) 0
DATA BITS
Figure 8. AD5308 Input Shift Register Contents
BIT 15 (MSB) D/C A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 BIT 0 (LSB) 0
DATA BITS
Figure 9. AD5318 Input Shift Register Contents
B IT 15 (M S B ) D /C A2 A1 A0 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 B IT 0 (L S B ) D0
D A T A B IT S
Figure 10. AD5328 Input Shift Register Contents
REV. PrH
-9-
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
(2) LDAC Mode: LDAC Mode controls LDAC, which deterimnes when data is transfered from the input registers to the DAC registers. There are three options when updating the DAC registers, as shown in table 3 below.
Table IV. Reset Mode
Bit 15 1 1
Bit 14 1 1
Bit 13 1 1
Bit 12 0 1
Bit 11 .... 0 x .... x x .... x
Description DAC Data Reset Data and Control Reset
Table III. LDAC Mode
Bit 15 1 1 1 1
Bit 14 0 0 0 0
Bit Bits Bit Bit 13 12 .... 2 1 0 1 1 1 1 x ..... x x ..... x x ..... x x ..... x 0 0 1 1 0 1 0 1
Description LDAC Low LDAC High LDAC Single Update Reserved
DAC Data Reset: On completion of this write sequence, all DAC Registers and Input Registers are filled with zeros. Data and Control Reset: This function carries out a DAC Data Reset and also resets all the Control Bits (GAIN; BUF; RESERVED; LDAC; Powerdown Channels) to their power-on conditions. Note that the Reference Mode must be re-setup after this mode prior to another DAC write.
Low Power Serial Interface
LDAC Low: (00) This sets LDAC permanently low, thus allowing the DAC registers to be updated continuously. LDAC High: (01) This sets LDAC permanantly high. The DAC registers are latched, and the input registers may change without affecting the contents of the DAC registers. This is the default option for this mode. LDAC Single Update: (10) This causes a single pulse on LDAC, thus updating the DAC registers once. Reserved: (11) Reserved. (3) Power-Down Mode: The individual channels of the AD5308/AD5318/AD5328 can be powered down seperately. The control mode for this is (10). On completion of this write sequence, the channels that have been set to `1' are powered down. (4) Reset Mode: This mode consists of two possible reset functions, as outlined in Table 4.
To minimize the power consumption of the device, the interface only powers up fully when the device is being written to, i.e., on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC.
LOAD DAC INPUT (LDAC) FUNCTION
Access to the DAC registers is controlled by both the LDAC pin and the LDAC mode bits. The operation of the LDAC Function can be likened to the configuration shown in Fig. 11.
EXTERNAL LDAC PIN LDAC FUNCTION INTERNAL LDAC MODE
Figure 11. LDAC Function
If the user wishes to update the DAC through software, then the LDAC pin should be tied high and the LDAC mode bits set as required. Alternatively, if the user wishes to control the DAC through hardware, i.e. the LDAC pin, then the LDAC mode bits should be set to `LDAC High'.
Table II. Control Words for the AD53x8
D/C Control Bits 15 14 13 1 1 1 1 0 0 1 0 1
Mode 12 x x 11 x x x x 10 x x x x 9 x x x x 8 x x x x 7 6 5 4 3 2 1 0 (GAIN Bits) x x 1 1 (LDAC Bits) x x x x (Channels) HG F E x x x x (BUF Bits) (RESERVED) Reference Selection E..H A..D 0 0 x D x x C x 1/0 B x 1/0 A x LDAC Powerdown Reset
0 x (RESET) 1 1 1/0
-10-
REV. PrH
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
Use of the LDAC Function enables double-buffering of the DAC data, and GAIN, BUF and RESERVED bits. There are two ways in which the LDAC Function can operate: Synchronous LDAC: The DAC registers are updated after new data is read in on the falling edge of the 16th SCLK pulse. LDAC can be permanently low or pulsed as in Figure 2. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register.
DOUBLE-BUFFERED INTERFACE
registers are unaffected when in power-down. In fact it is possible to load new data to the input registers and DAC registers during power-down. The DAC outputs will update as soon as the device comes out of Powerdown Mode. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s when VDD = 3 V.
A M PLIFIE R RE S IS TO R S TRING DA C VOUT
P OW E R-DO W N CIRCUITRY
The AD5308/AD5318/AD5328 DACs all have double-buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. When the LDAC pin is high, or when the LDAC bits are set to (01), the DAC registers are latched and the input registers may change state without affecting the contents of the DAC registers. However, when the LDAC bits are set to (00) or when the LDAC pin is brought low, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user may write to seven of the input registers individually and then, by bringing LDAC low when writing to the remaining DAC input register, all outputs will update simultaneously. These parts contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5308/AD5318/AD5328, the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk.
Figure 12. Output Stage During Power-Down
POWER-DOWN MODE
The AD5308/AD5318/AD5328 have low power consumption, typically dissipating 2.4 mW with a 3 V supply and 5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is described previously. When in default mode, all DACs work normally with a typical power consumption of 1 mA at 5 V (800 A at 3 V). However, when all DACs are powered down, i.e. in Power-Down mode, the supply current falls to 400 nA at 5 V (120 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier making it open-circuit. This has the advantage that the output is threestate while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 12. The bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the REV. PrH -11-
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
MICROPROCESSOR INTERFACING ADSP-2101/ADSP-2103 to AD5308/AD5318/ad5328 Interface 80C51/80L51 to AD5308/AD5318/AD5328 Interface
Figure 13 shows a serial interface between the AD5308/AD5318/ AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active-Low Framing, 16-Bit Word Length. Transmission is initiated by writing a word to the TX register after the SPORT has been enabled. The data is clocked out on each rising edge of the DSP's serial clock and clocked into the AD5308/AD5318/ AD5328 on the falling edge of the DAC's SCLK.
ADSP-2101/ ADSP-2103*
AD5308/ AD5318/ AD5328* SYNC DIN SCLK
Figure 15 shows a serial interface between the AD5308/AD5318/ AD5328 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5308/AD5318/AD5328, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case port line P3.3 is used. When data is to be transmitted to the AD5308/AD5318/ AD5328, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format which has the LSB first. The AD5308/AD5318/AD5328 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
80C51/80L51* AD5308/ AD5318/ AD5328* SYNC SCLK DIN
TFS DT SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3 TXD
Figure 13. ADSP-2101/ADSP-2103 to AD5308/AD5318/ AD5328 Interface
68HC11/68L11 to AD5308/AD5318/AD5328 Interface
RXD
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14 shows a serial interface between the AD5308/AD5318/ AD5328 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5308/AD5318/ AD5328, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5308/AD5318/AD5328, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC and PC7 is taken high at the end of this procedure.
68HC11/68L11* AD5308/ AD5318/ AD5328* SYNC SCLK DIN
Figure 15. 80C51/80L51 to AD5308/AD5318/AD5328 Interface
MICROWIRE to AD5308/AD5318/AD5328 Interface
Figure 16 shows an interface between the AD5308/AD5318/ AD5328 and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock, SK and is clocked into the AD5308/AD5318/AD5328 on the rising edge of SK, which corresponds to the falling edge of the DAC's SCLK.
MICROWIRE* AD5308/ AD5318/ AD5328*
SYNC SCLK DIN
CS SK SO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. 80C51/80L51 to AD5308/AD5318/AD5328 Interface
PC7 SCK MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. 68HC11/68L11 to AD5308/AD5318/AD5328 Interface
-12-
REV. PrH
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
APPLICATIONS Typical Application Circuit
The AD5308/AD5318/AD5328 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD/2. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780, ADR381 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference would be the AD589 and AD1580 (1.2 V bandgap references). Figure 17 shows a typical setup for the AD5308/ AD5318/AD5328 when using an external reference.
VDD = 2.5V TO 5.5V 0.1F
POWER
5V REGULATOR
10F
0.1F
VDD 10k SCLK SCLK VDD VREFABCD VREFEFGH VDD 10k SYNC AD5308/AD5318/ AD5328 VOUTA SYNC VOUTB VOUTC VOUTD
VIN VOUT EXT REF AD780/ADR381/REF192 WITH VDD = 5V OR AD589/AD1580 WITH VDD = 2.5V
10F VOUTA VREFABCD VOUTB DIN
VDD 10k DIN GND
VOUTE VOUTF VOUTG VOUTH
1F
VREFEFGH AD5308/AD5318/ AD5328 SCLK DIN SYNC GND Serial Interface VOUTG VOUTH
Figure 19. AD5308/AD5318/AD5328 in an Opto-Isolated Interface
Decoding Multiple AD5308/AD5318/AD5328s
Figure 17. AD5308/AD5318/AD5328 Using a 2.5 V External Reference
Opto-Isolated Interface for Process Control Applications
The AD5308/AD5318/AD5328 have a versatile 3-wire serial interface making them ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it may be necessary to isolate the AD5308/AD5318/AD5328 from the controller. This can easily be achieved by using opto-isolators that will provide isolation in excess of 3 kV. The actual data rate achieved may be limited by the type of optocouplers chosen. The serial loading structure of the AD5308/AD5318/AD5328 makes them ideally suited for use in opto-isolated applications. Figure 19 shows an opto-isolated interface to the AD5308/AD5318/AD5328 where DIN, SCLK, and SYNC are driven from optocouplers. The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5308/AD5318/ AD5328.
The SYNC pin on the AD5308/AD5318/AD5328 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but only the SYNC to one of the devices will be active at any one time allowing access to four channels in this sixteen-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 20 shows a diagram of a typical setup for decoding multiple AD5308 devices in a system.
REV. PrH
-13-
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
AD5308 VOUTA VOUTB SYNC DIN VOUTG SCLK VOUTH AD5308 VOUTA VOUTB SYNC DIN SCLK VOUTG VOUTH AD5308 VOUTA VOUTB SYNC DIN SCLK
SCLK DIN VDD VCC ENABLE CODED ADDRESS 1G 1A 1B DGND 74HC139 1Y0 1Y1 1Y2 1Y3
in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 10F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5308/AD5318/AD5328 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
VOUTG VOUTH AD5308 VOUTA VOUTB
SYNC DIN SCLK
VOUTG VOUTH
Figure 20. Decoding Mutiple AD5308 Devices in a system
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5308/AD5318/AD5328 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5308/ AD5318/AD5328 is in a system where multiple devices require an AGND to DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5308/ AD5318/AD5328 should have ample supply bypassing of 10 F
-14-
REV. PrH
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
Table V. Overview of AD53xx Serial Devices
Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328
Resolution 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12
DNL 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0
VREF Pins 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 2 2 2 2 2 2 1 1 1 1 1 1 4 4 4 2 2 2 2 2 2
Settling Time 4 s 6 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s
Interface SPI SPI SPI 2-Wire 2-Wire 2-Wire SPI SPI SPI SPI SPI SPI SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI SPI SPI SPI
Package SOT-23, microSOIC SOT-23, microSOIC SOT-23, microSOIC SOT-23, microSOIC SOT-23, microSOIC SOT-23, microSOIC microSOIC microSOIC microSOIC TSSOP TSSOP TSSOP microSOIC microSOIC microSOIC microSOIC microSOIC microSOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Pins 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 8 8 8 16 16 16 10 10 10 10 10 10 16 16 16 16 16 16 16 16 16
Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html
Table VI. Overview of AD53xx Parallel Devices
Part No. SINGLES AD5330 AD5331 AD5340 AD5341 DUALS AD5332 AD5333 AD5342 AD5343 QUADS AD5334 AD5335 AD5336 AD5344
Resolution DNL 8 10 12 12 8 10 12 12 8 10 10 12 0.25 0.5 1.0 1.0 0.25 0.5 1.0 1.0 0.25 0.5 0.5 1.0
VREF Pins 1 1 1 1 2 2 2 1 2 2 4 4
Settling Time 6 s 7 s 8 s 8 s 6 s 7 s 8 s 8 s 6 s 7 s 7 s 8 s
Additional Pin Functions BUF GAIN HBEN CLR
Package TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Pins 20 20 24 20 20 24 28 20 24 24 28 28

REV. PrH
-15-
PRELIMINARY TECHNICAL DATA AD5308/AD5318/AD5328
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Small Outline Package (TSSOP) (RU-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
1
8
P IN 1 0.006 (0.15) 0.002 (0.05) 0.043 3 (1.10) MAX 0.025 6 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50)
0.246 (6.25)
S E A TING P LANE
8 0
0.028 (0.70) 0.020 (0.50)
-16-
REV. PrH

▲Up To Search▲

Price & Availability of AD5318

	To Download AD5318 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .