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ZR38650
DATA SHEET
PROGRAMMABLE DIGITAL AUDIO PROCESSOR
FEATURES
Full-Function Digital Audio Processor Hardware - 50 MIPS performance with multi-operation instructions - Large internal RAMs/ROM plus low-cost external memory - Wide selection of on-chip digital audio peripherals - Flexible interface for host or no-host operation Standard Software Functions in ROM - Dolby Digital AC-3, 5.1 channel and 2 channel decoding up to 640 Kbits per second - Dolby Pro Logic encoding and decoding - MPEG1 and MPEG2 two channel decoding with MPEG2 PES stream parsing, PTS decoding and SCR handling Downloadable SiliconSoftwareTM Functions - Tomorrow's ever-changing standards plus today's: - Aureal A3D, Dolby Virtual Surround, Harman VMAx - QSound QSurroundTM, Spatializer N-2-2TM, Home THX - SRS TruSurround, Music Modes, Bass Management Flexible Input/Output - Serial and/or parallel data stream I/O - Serial SPI, serial Z2C or 8-bit parallel host interface - 3 serial input data ports and 4 serial data output ports - Formatted S/PDIF receiver with up to 96 kHz sample rate - Sample rates: 32 kHz, 44.1 kHz, 48 kHz or 96 kHz - Formatted S/PDIF AC-3 and MPEG transmitter output Low System Cost - Host-less operation with no glue chips - Separate internal PLLs for DSP core and audio I/O - No external RAM required for 5.1 Dolby AC-3/MPEG2 - Wait-state generation for low-cost external memory - 144-pin Plastic Thin Quad Flat Pack (TQFP) package - 3.3 V supply with 5 V compatible I/O for low power
DESCRIPTION
The Zoran ZR38650 is a full-function, high performance programmable digital audio signal processor. It is today capable of real-time single-chip decoding of Dolby Digital AC-3 and MPEG2 digital surround algorithms with its standard ROM and SiliconSoftware functions. It is also today's best digital audio platform for meeting tomorrow's constantly evolving digital audio algorithm requirements. Using the proven ZR38000 architecture, it is the fourth generation audio processor made by Zoran. Because of its programmable high performance and high level of integration, the ZR38650 is unusually flexible in meeting a wide range of system requirements at the lowest possible system cost. At the low end it can provide standard fixed decoding functions with only a DAC and an optical interface for the S/PDIF input in addition to the oscillator crystal. At the high end it can
Encoded Data Input
XTAL SPI or Z2C Serial Interface
provide eight channels of output, analog input, long-delay memories, custom operating features and the ability to be upgraded with downloaded SiliconSoftware product enhancements. Yet all of this flexibility comes without design complexity. Highly configurable standard functions with a simple command structure minimize software development, while a full set of development tools are available for the highly-custom product developer. The ZR38650 is suitable for primarily audio applications such as Audio/Visual home theater receivers, Digital Audio Broadcast (DAB), 3-D audio, six-channel speaker systems and Karaoke processors; primarily video applications like SDTV and HDTV stereo television receivers, digital cable and satellite TV set-top boxes; and multimedia applications with both audio and video like Multimedia PCs and the Digital Video Disk (DVD) players.
Decoded Audio Outputs
Host Processor (Optional)
DAC S/PDIF Optical Interface DAC ZR38650 DAC DAC (Optional)
Left Right Left Surround Right Surround Center Subwoofer Left Center Right Center
S/PDIF Input
General Purpose Control I/O
Figure 1. A Typical Low-Parts-Count ZR38650 System
ZORAN Corporation
3112 Scott Blvd.
Santa Clara, CA 95054
+1 (408) 919-4111
FAX +1 (408) 919-4122
www.zoran.com
15 February 1999
ZR38650
GENERAL DESCRIPTION
The Zoran ZR38650 is the latest full-function digital audio processing member of the ZR38000 digital signal processor product line. It is especially configured with peripherals, I/O capability and software for digital audio. Today, quality digital audio starts with a primary decoding function and adds appropriate data stream protocols and interfaces with I/O configurations to match the application. The ZR38650 has these primary decode and protocol software functions and yet has program/data memory and processing cycles left for additional product-distinguishing features. The ZR38650 also has the necessary flexibility in system I/O and hardware configuration. The ZR38650 is instruction-set compatible with the earlier ZR38600, but has a higher 50-MIPS processing rate. This gives the new faster 96-kHz sample rate S/PDIF decoding and increased processing cycles for additional functions. Larger internal program and data RAMs and ROM along with wide external memories accommodate today's rapidly changing needs for large complex algorithms. Other new hardware features are a programmable timer, a Z2C serial host interface and more support for the 24-bit I/O data formats.
PCM + Pro Logic
With two-channel PCM inputs the choice of functions is fourchannel Pro Logic decoding or two-channel stereo mixing, including upmixing from only one input channel to two.
Left Two-Channel PCM Input Pro Logic Decoder Right Center Surround S/PDIF One- or TwoChannel PCM Left Right S/PDIF
PCM Mixer
MPEG
The MPEG1 decoder accepts either MPEG1 or MPEG2 input streams and produces either Pro Logic DAC outputs or twochannel stereo in DAC form.
Left Right Center Surround S/PDIF Left Right S/PDIF
Two-Channel MPEG1/MPEG2 Stream
Two-Channel MPEG1 Decoder
Pro Logic Decoder
Functions
AC-3 and MPEG with variations are the primary decoding functions in use today. The ZR38650 has these and their associated test function with the required set-up, operation and system functions to make them usable in an end-user product. In addition, an ever increasing number of SiliconSoftware functions can add special enhancing and differentiating features to products.
Two-Channel MPEG1/MPEG2 Stream MPEG1 Decoder
Pink Noise
A six-channel pink pseudo-random noise generator function is included for user testing of speaker balance in their listening space. Individual speakers can be enabled in any combination.
Left Pink Noise Generator Right Left Surround Right Surround Center Subwoofer
Primary Decoding and Test Functions AC-3
The figure shows the simultaneous S/PDIF input and 5.1 channel DAC (Digital-to-Analog Converter) outputs of this primary digital audio function, the six-channel AC-3 decoder.
Left Right Six-Channel AC-3 Stream Six-Channel AC-3 Decoder Left Surround Right Surround Center Subwoofer S/PDIF
SiliconSoftwareTM Functions
SiliconSoftware is a group of additional functions for the ZR38650 provided by Zoran or third-party suppliers that can add special features now or provide new functions in the future.
Or with four channels of Pro Logic output in either of two DAC forms: four channels directly or to an analog Pro Logic decoder.
Left Six- or TwoChannel AC-3 Stream Two-Channel AC-3 Decoder Pro Logic Decoder Right Center Surround S/PDIF Lt (Pro Logic) Rt (Pro Logic) S/PDIF
3-D Audio
Currently there are six providers of 3-D audio which gives the effect of a three-dimensional sound field with only two speakers. These functions are Aureal A3D, Dolby Virtual Surround, Harman VMAx, QSound QSurroundTM, Spatializer N-2-2TM and
Six- or TwoChannel AC-3 Stream
AC-3 Decoder
2
ZR38650
SRS TruSurround. They work with either two- or six-channel inputs and the AC-3 or MPEG decoders.
Custom Functions, Etc.
Product designers can always add custom functions and variations, often with very simple software additions.
Six-Channel AC-3 Stream
Six-Channel AC-3 Decoder
3-D Audio
Left Right
Operation and Set-Up Functions
These control the simple start and stop operation of the decoding functions and determine the initial hardware operation and configuration.
3-D Audio
Two-Channel AC-3/MPEG1/ MPEG2 Stream
Two-Channel AC-3/MPEG1 Decoder
Pro Logic Decoder
Left Right
System Functions
These functions control the real-time operation including interface transactions, program loading and in-circuit testing.
Bass Management
Selected low-frequencies can be redirected to different speakers with Bass Management. Useful with all types of decoding to compensate for the types of speakers used.
System Configurations
The ZR38650 is highly self-contained and can work with few external parts as shown in Figure 1. However it is very flexible in accommodating the needs of larger, higher performance systems. Figure 2 shows all of the possible options that are supported to make a complete system.
DVD - Linear PCM
Special provisions are included for data formats and synchronization for AC-3/MPEG decoding with 3-D audio and bass management for Digital Video Disk (DVD) applications.
Hosts
The ZR38650 does not require a host microprocessor but if there is one in the system it may be used to advantage. Either the bit-serial SPI (Small Peripheral Interface) or Z2C interface, or a byte-wide parallel interface may be used.
Hall Effects/Music Modes
Adds the natural acoustical effects of a performance environment to the original recording environment.
Home THX5.1
Theater THX for use in consumer home entertainment systems.
Data Input/Output
The encoded digital input data stream can use a bit-serial or byte-parallel interface or S/PDIF receiver with the ZR38650 either a master or slave. Up to six-channels of analog signals can be input in bit-serial ADC (Analog-to-Digital Converter) formats in a master or slave mode.
Karaoke Processing
Voice cancellation, pitch-shifting and echo and reverberation.
Host Processor (Optional)
XTAL Z2C or SPI Serial Interface
Analog Input Bit-Serial Input S/PDIF Input Encoded Data Input
ADC (Optional)
DAC DAC ZR38650 DAC
Left Right Left Surround Right Surround Center Subwoofer Left Center Right Center Decoded Audio Outputs
S/PDIF Input
S/PDIF Optical Interface (Optional)
Parallel Interface
DAC (Optional)
Parallel Input
8 8 32 8
General Purpose I/O
S/PDIF Optical Interface (Optional)
Lt/Rt
Host Processor (Optional)
Program/Data RAM or ROM (Optional)
Byte-Wide Program ROM (Optional)
Figure 2. ZR38650 Composite System Block Diagram
3
ZR38650
Decoded audio outputs can be up to eight channels in bit-serial DAC formats or six encoded channels from the S/PDIF transmitter. storage gives different or additional functions when a host is not used and allows a choice of ROM technologies to be employed for future upgradability at minimum cost and parts count. Wider 32-bit program storage allows directly executing large functions without downloading. External data memory may be required for functions with long acoustical delays, input buffering or large data tables.
Memory
External memory is not normally needed but can be added for program and/or digital audio data. Additional byte-wide program
FUNCTIONAL DESCRIPTION
A more complete description of the ZR38650 software's operation and configurations and its hardware configurations follows. with responses to control the ZR38650's operation. The utilities issue API calls to the functions. All of the software development can be limited to the host microprocessor even when feature types of variations in operation are based on getting information back from the ZR38650's operation. Alternatively, the control information in the commands can be entered in a sequence of API calls issued from a custom program running internally on the ZR38650 processor. Now no host is required. With either a host command/response stream or API calls, custom functions in native ZR38001 code can be added without losing the benefits of the ease of use in the common structure. Table 1 is a summary of the commands and responses for the standard primary, operation and set-up functions. Note there are read and write commands to the ZR38650 and responses back from the ZR38650 to the host. Responses are due to commands during normal operations that are in progress or from certain specific commands with read commands following.
Software - Operation
One of the major benefits of the ZR38650 is its ease of use for the system developer under a broad range of system requirements. Standard functions are easy to use, yet custom features can be added without falling back to custom software development with complicated real-time operating system considerations or detailed I/O protocols. This follows from the fact that all software functions are supplied with a common command and response sequence for use with a host or an API (Application Programming Interface) for calling from an internal program. And each provides for adding custom functions in not just one but a series of ways which depend upon the complexity of the custom function. This is shown schematically in Figure 3 where the operation, set-up, primary, and SiliconSoftware functions are shown in the middle. Using the system utilities to maintain the communications with the host, the host can issue a sequence of commands
ZR38650 Resident Control Program
Host Resident Control Program Host Processor With Control Program
Operation and Set-Up Functions PLAY Operation STOP Operation Custom ZR38650 Control Program Set-up A Operate A Set-up B Operate B, Etc. SETIO Set-up CFG Set-up, Etc. Primary Decoding, Test and SiliconSoftware Functions Function A Function B Function C, Etc. System Functions Monitor APIs Command Stream Set-up A APIs
Response Stream Response A
System Functions Utilities
Figure 3. ZR38650 Operation Control: Commands from a Host or Calls from a ZR38650 Resident Program
4
ZR38650
Table 1: Standard Function Command and Response Summary
Class Write Command Primary Decoding And Test Functions AC3 PCMPROL MPEG PNG USER Operation Functions PLAY MUTE UNMUTE STOP STOPF STAT SPDIFSTAT GETPTC NOP Set-Up Functions PLLTAB PLLCFG CFG SETSTC VER BOOT SPDIFCS PARAM INTRP SETIO POKE PEEK Read Command READ Reply Response AC3STATR PCMPROLR MPEGSTATR PNGSTATR VERR SETIOR PLLR PEEKR SPDIFSTATR GETPTCR Progress Response EXPECT ISTATUS Name Description Commands to ZR38650 to perform a specific function Select AC-3 or AC-3 + Pro Logic decoder function Select PCM or Pro Logic decoder functions with PCM input and mixer function Select MPEG or MPEG + Pro Logic decoder function Select pink noise generator function Select user defined function Resume selected function operation and unmute audio output Mute audio output without stopping the selected operation Restore muted audio output while continuing the selected operation Stop operation, retain data in input buffer and mute audio output Stop operation, flush the data in the input buffer and mute audio output Return decoder status information using the READ command Return the S/PDIF input channel status Return the PTC and STC values for timing synchronization Not a command, does not affect operation. Will return a Progress response. Set the PLL programmable registers Define the PLL configuration Configure the ZR38650 I/O to the specific system hardware Set the system time clock and video delay Return 32-bit ROM version number using the READ command Load and execute the N parameter words of bootstrap program Write the S/PDIF output channel status Define parameters for special functions Interpret: load and execute four parameter words as a ZR38001 instruction Set, test and return general purpose single-bit I/O registers Load N 32-bit words to the core processor RAM at the given start address Read N 32-bit words from core processor RAM at the given start address Commands to ZR38650 to return Reply words to the host Command to ZR38650 to return a Reply word after specific commands Data words returned to the host as the result of sending specific commands followed by READ commands Status and information about the AC-3 stream Status and information about the PCM or Pro Logic stream Status and information about the MPEG stream Status and information about the PNG stream Four byte version number of ROM read by VER command Two words of GPIOC and GPIO registers Two bits which indicate the PLL lock status N 32-bit words from core processor RAM specified by PEEK command S/PDIF input channel status PTC and STC values of 32 bits each Data words returned to host in the normal process of sending any command Expected number of parameter words still to be received from host Interpreter status
5
ZR38650
Software - Functions
Primary Decoding and Test Functions AC-3
The major modes of operation of the Dolby Digital AC-3 decoder function are summarized in Table 2. Choices are for input and output ports and their formats including operation with audio/video synchronization (AVS), constant or request driven PES packetized inputs and the linear PCM of DVD. AC-3 input decoding rates are up to 640 kbits per second. Full selection can be made for speaker configuration, dynamic range compression, downmixing, delays, filtering and error concealment strategy. The Karaoke downmixing is also supported including with downloaded Karaoke coefficients. individual speakers can be enabled in any combination at a single adjustable level, with or without a band-limiting filter.
SiliconSoftwareTM Functions 3-D Audio
There are six third-party providers of 3-D audio using the ZR38650. This function gives the effect of a three-dimensional sound field with only two speakers. These certified functions are Aureal A3D, Dolby Virtual Surround, Harman VMAx, QSound QSurroundTM, Spatializer N-2-2TM and SRS TruSurround. They work with either two- or six-channel inputs and the AC-3, MPEG and Pro Logic decoders as shown in Table 3.
Bass Management
Depending upon the speakers used in a listening area, it can be desirable to alter the distribution of the bass frequencies between speakers. A choice of speaker configurations is provided and of low-pass cut-off frequencies for 80, 100 or 120 Hertz in the simplest form. The full function allows the low-pass and high-pass filter coefficients to be downloaded along with individual speaker sound levels. Bass management works with either two- or six-channel inputs and the AC-3, MPEG and Pro Logic decoders. It does not work with 3-D audio although some 3-D audio functions include certain bass management features.
PCM + Pro Logic
With two-channel PCM inputs, the choice of functions is fourchannel Pro Logic decoding or two-channel stereo mixing. Selection can be made for speaker configuration, downmixing, delays and surround filtering.
MPEG
The MPEG1 decoder function accepts either MPEG1 or MPEG2 input streams and produces either Pro Logic or two-channel stereo outputs in DAC form. Selection can be made for speaker configuration, dynamic range compression, downmixing, delays and surround filtering.
DVD - Linear PCM
In addition to the audio/video synchronization (AVS) and request driven PES packetized input features of the standard decode functions, this DVD function has 3-D audio capability and bass management. It works with two-, six- or eight-channel PCM inputs and the AC-3, MPEG and Pro Logic decoders.
Pink Noise
This is a six-channel pink (equal energy per constant proportional bandwidth) pseudo-random noise generator test function. It is for user testing of speaker balance in a listening space. The six
Table 2: Primary Decoding and Test Function Options Summary
Input Primary Decoding Or Test Function AC3 Data Stream 6-Channel AC-3 Serial Port A, S/PDIF, Parallel SA, S/P, P MPEG2 PES Packetized Yes DVD PES Packetized Yes Output Serial DAC Ports B,C,D B B,C,D B B,C,D B B,C,D B B,C,D B B,C,D Input Stream Input Stream
AVS Yes
Function 6-Channel AC-3 2-Channel Pro Logic encoded
S/PDIF Port G Input Stream
2-Channel AC-3 PCM + Pro Logic 2-Channel PCM MPEG1
SA, S/P, P
Yes
Yes
Yes
4-Channel Pro Logic 2-Channel AC-3
SA, S/P, P
No
No
No
4-Channel Pro Logic 2-Channel PCM Mixed
MPEG
SA, S/P, P
Yes
Yes
Yes
4-Channel Pro Logic 2-Channel MPEG1
MPEG2
SA, S/P, P
Yes
Yes
Yes
4-Channel Pro Logic 2-Channel MPEG1
PNG
-
-
-
-
-
6-Channel Pink Noise
6
ZR38650
Hall Effects/Music Modes
Short and long term delays and reverberation are added to multichannel PCM inputs with this function. Delay coefficients are downloaded to simulate various acoustical environments (concert halls, churches, stadiums, etc.)
Custom Functions, Etc.
The User function allows developers to easily add custom functions using their own native ZR38001 code, yet retain the ease of control of the command and response structure of the ZR38650.
Home THX5.1
This function, when used in a two-chip set connected in cascade, provides the sound of the Lucasfilm theater THX in the home listening environment. The input chips runs all of the standard decoding functions and passes its PCM outputs to the second chip for the THX5.1 processing which included full bass management, decorrelation, timbre matching and re-equalization and individually programmable channel delays.
Operation and Set-Up Functions
The operation functions, summarized in Table 1, are the realtime start and stop commands needed for system control once the primary decoding function has been selected. Also included are commands to get the input channel and decoding status to monitor on-going operation. The PTC and STC time clocks can also be monitored to insure audio and video synchronization. The set-up functions configure both the hardware and software before operation starts or as major operational changes are made. Hardware configuration and initialization includes the phase-locked loops (PLLs), system clocks and the input/output (I/O). Software can be put in place through the host processor from its I/O or memory system. It may be in the form of custom commands and their parameters or directly executable native code for the core DSP processor.
Karaoke Processing
In addition to the Karaoke input mixing features of the standard decode functions, this is true Karaoke processing with voice cancellation, pitch shifting, voice echo and reverberation and bass management. External data memory may be required for this function.
Table 3: SiliconSoftware Function Options Summary
Input Serial Port A, E or F, S/PDIF, Parallel SA, S/P, P Standard Function Source AC-3, AC-3 + Pro Logic, PCM + Pro Logic, MPEG, MPEG + Pro Logic Output Serial DAC Ports B
SiliconSoftware Function
3-D Audio: Aureal A3D Dolby Virtual Surround Harman VMAx QSound QSurroundTM Spatializer N-2-2TM SRS TruSurround Bass Management DVD
Function 2-Channel 3-D Audio
S/PDIF Port G Input Stream
SA, S/P, P SA, P
All of the above All of the above + 8Channel PCM PCM AC-3, AC-3+Pro Logic, PCM+Pro Logic, MPEG, MPEG + Pro Logic AC-3, PCM, MPEG
Redirect low frequencies to different speakers Decoding, 3-D and bass management Add room effects Two chip set decodes and produces THX outputs Voice cancellation, pitch shifting, echo and reverberation and bass management.
B, C, D B, C, D, G
Input Stream Input Stream Unless 8-Ch. PCM Input Stream Input Stream Input Stream
Hall Effects/Music Modes Home THX5.1 Decoding Chip THX Processing Chip
SA, S/P, P SA, S/P, P SA, SE, SF S/P & SF or SA & SF
B, C, D B, C, D B, C, D B, C, D
Karaoke Processing
7
ZR38650
System Functions
The remaining portion of the standard ZR38650 functions that reside in every program ROM are the system functions, shown schematically in Figure 4. ration. Important considerations are if a host is used, if only standard commands are to be used and what provisions are to be made for current and future upgrades. Table 4 summarizes the most common configurations and their relative benefits. Figure 4 illustrates possible sources and residences of the software for different hardware configurations. Starting with the on-chip program ROM, it can be either the standard version or with custom functions as shown. Custom and SiliconSoftware functions can be available for downloading into the on-chip or external program/data RAM from three sources as indicated by the dashed arrows. If there is no host they must be loaded from the external byte-wide program ROM or executed directly from an external 32-bit ROM. With a host custom and SiliconSoftware functions may be loaded from the host's own non-volatile memory (ROM or flash EPROM typically) or through its I/O peripherals such as on-line links or movable memory media like floppy disks.
Monitor
This is the simple real-time operating system mini-kernel used by all ZR38650 functions in normal operation.
Utilities
System utilities maintain operation of the various I/O interfaces that are shared between functions. These include the serial audio data ports, the serial SPI or Z2C host interface and the parallel host interface for commands and responses. The utilities also include the initial and reset bootstrap routine that determines the start-up ROM and executes its initialization process.
ICE Debug
For In-Circuit Emulation debugging using the ZR38000 Family Simulator, the monitor is used in a mode for single-step and breakpoint execution of programs.
Hardware - System Configurations
All of the hardware shown in Figure 2, the composite system block diagram on page 3, is supported in the ZR38650. The choices for host, data input and output, and external memory are summarized in Table 5. Those that are supported by the standard functions with the standard commands are noted. Individual SiliconSoftware functions support additional configurations. For example, the Karaoke Processing supports the bit-serial ADC data input and the external data RAM required for pitch correction and voice reverberation.
Software - System Configurations
As a result of the ZR38650's ability to be configured from a lowcost, fixed-function device to a very flexible, full capability audio processor, there are many choices as to how the software is configured. These are related to the system hardware configu-
Table 4: Software Configurations
Configuration Host Operation Using Standard Commands Host Operation Using Standard and Custom Commands and APIs Internal Standard ROM with or without External RAM Internal Standard ROM with or without External RAM Internal Standard ROM with External Custom ROM Internal Custom ROM Description Download internal/external program RAMs with SiliconSoftware from host for additional current and future functions. Download internal/external program RAMs with SiliconSoftware from host for additional current, future and custom functions. Download internal program RAM with SiliconSoftware from external ROM for current and custom functions or from host for future functions. Download program RAM with SiliconSoftware from host for future functions. Standard and custom functions with control through GPIO port. Standard and custom functions with control through GPIO port. No future flexibility without internal ROM non-recurring engineering (NRE) cost. Benefits Moderate flexibility for current and future functions with only host S/W development. Maximum customization and flexibility for current and future functions. Maximum customization with moderate flexibility for current and future functions. Lower external memory size and costs. Moderate customization with moderate flexibility for future functions. Minimum cost. Low cost, maximum customization. Broad choice of ROM technologies for flexibility for future. Lowest recurring cost with moderate customization.
Stand Alone (No Host) Operation Using Standard and Custom Functions with APIs
Internal Standard ROM with External Custom ROM Internal Custom ROM
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ZR38650
Hosts
A host microprocessor is not required for the ZR38650's operation. A custom program, in either the internal ROM or an external ROM with the standard internal ROM, is sufficient. Control of the operation is then through the GPIO (General Purpose Input/Output) ports. However, the greatest flexibility is available if a host is used. The least costly in external hardware is a serial host interface. The four-wire SPI (Small Peripheral Interface) or two-wire Z2C signals (see Table 6) connect directly to most low-cost microcontrollers. There is no speed penalty with a host serial interface and it leaves the parallel interface free for use with external memories. The ZR38650's parallel interface can be used for a byte-wide connection to a microprocessor host along with byte-wide I/O with the standard command support. The full 32-bits of the parallel interface can be used for an I/O connection if called in the developer's software. Note that the parallel interface can not be used concurrently for the host and I/O while it is being used for external data or program memory. Up to six channels of bit-serial ADC data can be input as master or slave in a wide variety of industry formats when required by SiliconSoftware functions. Up to eight channels of bit-serial DAC data can be output as master or slave in the same variety of industry formats including I2S and EIAJ with word, frame and frameless synchronization. Ports B,C and D are used by standard 6-channel functions with Port G in addition for 8-channel SiliconSoftware functions. Otherwise Port G serves as a S/PDIF master transmitter.
External Memory
The 20 address and 32 data lines of the parallel port allow a wide choice of external memory for program and data storage if needed for SiliconSoftware functions or for future flexibility. Variable wait-states are supported for slower, lower cost memories. Not used concurrently with parallel host or I/O interfaces.
Hardware - Digital Audio Processor
The ZR38650 is composed of the interfaces, memories and system clocks that surround the ZR38001 DSP core shown in Figure 5. The individual signals of each of the interfaces and power supply connection are summarized in Table 6. The figure illustrates the sharing of the serial output port G with the S/PDIF transmitter and the multiple functions of the parallel port for the external host, I/O and memories. Note from Table 6 how some of the otherwise unused 32-bit memory data lines are utilized for additional control when the parallel byte-wide interface is employed for the external host and I/O. Using standard functions, three of the six GPIO signals are dedicated as a MUTE input, an I/O data request output, DREQ, and an I/O error output, ERROR.
Data Input/Output
The primary data input is the single-wire digital audio interface receiver. This conforms fully to S/PDIF, IEC-958, AES/EBU and EIAJ CP-340 consumer standards. All standard sampling rates are supported for raw or packetized bitstreams as well as the data driven master operation using the DREQ signal on the GPIO0 port. Serial port A or the byte-wide parallel interface may alternately be used for the channel bitstream as master or slave. The parallel interface also provides data driven master operation, but it can not be used concurrently with external memory in the system.
RAM Image SiliconSoftwareTM 3-D Audio Bass Management DVD Home THX Music Modes Custom, Etc.
I/O
Host Processor
Program ROM or Flash EPROM
RAM Image SiliconSoftwareTM 3-D Audio Bass Management DVD Home THX Music Modes Custom, Etc.
Standard ROM Program/ Data RAM Standard Functions ZR38650 Program/ Data ROM Pri. Decode & Test Operation Set-Up System
32 8
Custom ROM Standard and Custom Functions
OR
Decode & Test Operation Set-Up System
RAM Image SiliconSoftwareTM 3-D Audio Bass Management DVD Home THX Music Modes Custom, Etc.
Program/Data RAM or ROM
Byte-Wide Program ROM
Figure 4. Software Memory Configurations
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ZR38650
Table 5: System Hardware Configurations and Standard Command Support
Hardware Configuration Host None Bit-serial Interface Parallel Interface Data Input S/PDIF Channel Bit-serial Channel Parallel Channel ADC bit-serial Data Output DAC bit-serial S/PDIF Channel External Memory Program/Data ROM Program/Data RAM Hardware Configuration Description Custom program using parallel and/or GPIO interface for control. Industry standard four-wire SPI duplex or two-wire Z2C halfduplex. Byte-wide selectable for I/O and Commands. Not possible concurrent with external memory. Standard single-wire receiver. Serial Port A is a flexible slave or data driven master with DREQ. Byte-wide master, slave or data-driven master with DREQ. Not possible concurrent with external memory. Up to six channels as a flexible master or slave. Up to eight channels on Ports B, C, D and G as flexible master or slave. Standard single-wire transmitter on Port G. Master only. 8-, 16- or 32-bit for loading or 32-bit for execution. 32-bit memory for executing large functions or 16 or 32 bits for large delay or table memory. Standard Command Support None. Requires custom internal or external program ROM. Yes. Yes. Yes. Yes. Yes. No. Yes for 6-channel ports B, C and D. Yes, Port G. Yes for execution or 8-bit only loading. Not required for standard functions.
Internal memories are large: the 20-kwords of 32-bit program/data ROM is augmented with an addition 2-kwords of down-loadable RAM. The data only memory is a 10-kword RAM in the 20-bit data word precision. The two programmable phase-locked-loops (PLLs), one for the DSP core (fDSP) and one for the audio serial ports (fAUDIO) allow independent selection of these two critical internal clock rates. This is particularly important when the ZR38650 system oscillator is not determined by its own external crystal, but rather from
Host
4
a predetermined system clock frequency. Having two PLLs lets the DSP core synchronously operate at its maximum 50 MIPS rate (f DSP = 100 MHz) for processing while the serial I/O operates at the standard sample rates of 32, 44.1, 48 or 96 kHz, regardless of whether the predetermined system clock frequency is a common sub-multiple. The power supply is 3.3 Volts for lower power consumption, yet all I/O signals are 5.0 Volt tolerant for use in 5.0-Volt systems.
Serial Input Ports
A E F S/PDIF Input
Serial Audio Inputs
fAUDIO
Serial Host SPI or Z2C Interface
Internal Data RAM 10k x 20
Internal Program/ Data RAM 2k x 32
Internal Program/ Data ROM 20k x 32
S/PDIF Receiver ZR38001 DSP Core S/PDIF Transmitter G S/PDIF or Left/Right Center Serial Output Ports
Control
4
Parallel Host Interface Input Data FIFO 8x9 ICE Interface
Parallel Port
Data/ Control
32
Serial Audio Outputs
fDSP fAUDIO
B C D
Left/Right Left/Right Surround Center/Subwoofer
Address
20
Memory Interface
GPIO
System Oscillator & DSP PLL
Audio PLL Timer
4
6
Test
General Purpose I/O Ports
Xtal
Figure 5. ZR38650 Simplified Block Diagram
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ZR38650
Table 6: ZR38650 Signal Description Summary
Name A[19:0] D[31:15] D14/RDY D13/ C/D D12/ERR D[11:4]/PP[7:0] D[3:0] CS RD WR P/M SPFRX SDA, SDE, SDF WSA/FSA SCKA SDB SDC SDD SDG/SPFTX WSB/FSB SCKB SCKIN MUTE/GPIO5 GPIO[4:2] ERROR/GPIO1 DREQ/GPIO0 SI SO/SDA SCK/SCL SS TDI, TCK, TMS TDO INT RESET MMAP XTI XTO CLKOUT BYPASS FLTCAP VDD VDDA GND GNDA Number 20 17 1 1 1 8 4 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 16 1 25 1 Type [1] O I/O I/O or O I/O or I I/O or I I/O I/O I/O I/O I/O I I I I/O I/O O O O O I/O I/O I/O I or I/O I/O O or I/O O or I/O I I/O/T I I I O/T I I I I O O I I Power Power Power Power Parallel Port (56) Address bus of parallel port Data bus of parallel port when selected for external memory (P/M = 0) Data bus (P/M = 0) or Ready output signal of parallel port when selected for parallel I/O (P/M = 1) Data bus (P/M = 0) or Command/Data select input of parallel port when selected for parallel I/O (P/M = 1) Data bus (P/M = 0) or Error input signal of parallel port when selected for parallel I/O (P/M = 1) Data bus of parallel port when selected for external memory (P/M = 0) or Parallel Port I/O (P/M = 1) Data bus of parallel port when selected for external memory (P/M = 0) Chip Select output for external memory or Chip Select input for parallel I/O Read enable output for external memory or Read enable input for parallel I/O Write enable output for external memory or Write enable input for parallel I/O Parallel I/O or Memory select for parallel port. Determined at time of RESET. Serial Ports (13) S/PDIF Receiver input port Serial Data inputs. Ports A, E and F. Word Select or Frame Synchronization for input ports. An output when a master, an input when a slave. Serial Clock for input ports. An output when a master, an input when a slave. Serial left and right Data output. Port B. Also, at RESET defines SPI/Z2C for host serial interface. Serial left and right surround Data output. Port C. Also, at RESET defines Z2CADR[0] of Z2C address. Serial center and sub-woofer Data output. Port D. Also, at RESET defines Z2CADR[1] of Z2C address. Serial Data output. Port G or S/PDIF Transmitter port. Also, at RESET defines the SCKP value. Word Select or Frame Synchronization for output ports. An output when a master, an input when a slave. Serial Clock for output ports. An output when a master, an input when a slave. Serial master Clock output or master clock Input for output ports General Purpose Ports (6) Mute input signal or can be programmed as General Purpose Input/Output 5 Can be programmed as General Purpose Input/Output 4, 3 and 2 Error output signal or can be programmed as General Purpose Input/Output 1 Data Request output signal or can be programmed as General Purpose Input/Output 0 Serial Host Interface (4) Host Serial interface data Input. Also, at RESET defines Z2CADR[5] of Z2C address. SPI host Serial interface data Output or Serial Data for Z2C SPI host Serial interface Clock input or Slave Clock input for Z2C SPI host serial interface Slave Select input. Also, at RESET defines Z2CADR[4] of Z2C address. ICE Interface (4) ICE Test interface Data Input, Clock input and Mode Select ICE Test interface Data Output System Interface (8) External Interrupt request input Reset input to start operation in known state Determines location on Memory Map of reset and interrupt block External system clock Input or connection to external crystal, at frequency f XTI Output connection to external crystal Clock Output from the ZR38650 at frequency f DSP/2 Bypass internal DSP core PLL to use external system clock input on XTI External Filter Capacitor connection for PLL. A value of 47nF is recommended. Power (43) +3.3 volt power supply +3.3 volt power supply, Analog for PLL Power supply Ground Power supply Ground, Analog for PLL Total (144) = Active (134) + No Connection (10) Description
1. O = Output, I = Input, T = Tri-state in normal use. May be different at Reset time as shown in Table 23 on page 42.
11
ZR38650
STANDARD FUNCTIONS DESCRIPTION
The ZR38650 standard functions are selected and controlled by the commands and responses shown in Tables 7 and 8. These are the commands, parameters and responses sent and received by a microprocessor over the serial host interface or the parallel host interface when a parallel host is used. The Applications Program Interfaces (APIs) for the AC-3, Pro Logic, Pink Noise, etc. functions are similar. These APIs are used by a developers program executing on the core processor. Transfers between a host and the ZR38650 with the SPI are fullduplex with the host being the master. For every command sent a word is received back from the ZR38650. Transfers with the parallel host interface or the serial Z2C interface are half-duplex with the host master. Then the host must initiate the read for the response after each command is sent. The commands are sent only from the host and are in the general form shown.
7 6 5 4 3 2 1 0
Operation Code Parameter Word 1 Parameter Word 2
Parameter Word N
There are two classes of commands: those that Write to the decoder and those that Read back from the decoder. The Write commands may have parameter words in addition to the basic operation code. The Write commands are of three types as shown in Table 7: those that choose primary decoding and test functions (e.g., AC3), those that govern operation (e.g., STOP or PLAY) and those that set-up operation (e.g., CFG).
Table 7: Standard Function Command Summary (Host to ZR38650 Transfers)
Class Write Command Primary Decoding And Test Functions AC3 PCMPROL MPEG PNG USER Operation Functions PLAY MUTE UNMUTE STOP STOPF STAT SPDIFSTAT GETPTC NOP Set-Up Functions PLLTAB PLLCFG CFG SETSTC VER BOOT SPDIFCS PARAM INTRP SETIO POKE PEEK Read Command READ 00 0 85 86 87 83 88 8A 8B 89 8C 8D 8E 8F 9A 80 98 99 82 97 81 90 95 96 91 92 93 94 8 8 8 8 8 0 0 0 0 0 0 0 0 0 6 1 8 7 0 N 4 N 4 4 7+4N 7 Name Operation code (Hex) Number of parameter words Description Commands to ZR38650 to perform a specific function or operation Select AC-3 and Pro Logic decoder function, either six- or two-channel output Select PCM or Pro Logic decoder functions with PCM input and mixer function Select MPEG or MPEG + Pro Logic decoder function Select pink noise generator function Select user defined function Resume selected function operation and unmute audio output Mute audio output without stopping the selected operation Restore muted audio output while continuing the selected operation Stop operation, retain data in input buffer and mute audio output Stop operation, flush the data in the input buffer and mute audio output Return decoder status information using the READ command Return the S/PDIF input channel status Return the PTC and STC values Not a command, does not affect operation. Will return a Progress response. Set the PLL programmable registers Define the PLL configuration Configure the ZR38650 I/O to the specific system hardware Set the system time clock and video delay Return 32-bit ROM version number using the READ command Load and execute the N parameter words of bootstrap program Write the S/PDIF output channel status Define parameters for special functions Interpret: load and execute four parameter words as a ZR38001 instruction Set, test and return general purpose single-bit I/O registers Load N 32-bit words to the core processor RAM at the given start address Read N 32-bit words from core processor RAM at the given start address Commands to ZR38650 to return Reply words to the host Command to ZR38650 to return a Reply word after specific commands
12
ZR38650
The words received back from the ZR38650 when the host initiates a transfer will be of the form: The second example below shows the response to the VER command. The EXPECT value tells the host how many bytes of information are returned by the command.
Words sent from Host Data Word 0 Data Word 1 1
VER
7
6
5
4
3
2
1
0 Time 3
READ
2
READ
4
READ
5
READ
6
READ
7
READ
8
READ
Data Word N-1
Words sent from ZR38650 1
ISTATUS ISTATUS EXPECT=4
2
A1
3
20
4
10
5
02
6
ISTATUS
The responses are of two types, a Reply to READ commands following specific Write commands or the Progress responses to each Write command. The Progress response is always the number of still expected parameters (EXPECT) and/or READs, followed by the response and interpreter status (ISTATUS). All responses to commands sent on the SPI are delayed by two words as shown in the example of the SETIO command which has both parameter words (Para 1-4) and two Reply data words (SETIOR). Note that the initial ISTATUSes returned are a response to previous READs sent by the host. There are no delays on the parallel host interface or the serial Z2C interface in the normal alternating single-byte transmit/receive protocol.
Words sent from Host 1
SETIO
See Table 9 on page 23 for a summary of the sequence of commands, parameters, reads, responses and status. The following descriptions explain the ZR38650's standard functions as well as the specifics of the commands used and their responses. They are in the same order as Tables 7 and 8.
Note that the descriptions on the following pages are meant to be inclusive of all functions that are currently available on the ZR38650. Some functions require that additional code be downloaded into program RAM. Likewise, note that command parameter tables are all inclusive. Individual program and ROM release documents should be consulted to determine the exact functionality for the ROM version and program release that is being used.
Time 4
Para3
2
Para1
3
Para2
5
Para4
6
READ
7
READ
8
READ
9
READ
10
READ
Words sent from ZR38650 1
ISTATUS ISTATUS Exp1=5
2
Exp2=4
3
Exp3=3
4
Exp4=2
5
Exp5=1
6
7
8
SETIOR1 SETIOR2 ISTATUS
Table 8: Standard Function Response Summary (ZR38650 to Host Transfers)
Response operation code (Hex) Number of data words
Class Reply Response Primary Decoding And Test Functions Set-Up Functions
Name
Description Data words returned to the host as the result of sending specific commands followed by READ commands
AC3STATR PCMPROLR MPEGSTATR PNGSTATR VERR SETIOR PLLR PEEKR
05 04/06 07 03 -
16 8 12 8 4 2 1 4N 4 8
Status and information about the AC-3 stream Status and information about the PCM or Pro Logic stream Status and information about the MPEG stream Status and information about the PNG stream Four byte version number of ROM read by VER command Two words of GPIOC and GPIO registers Two bits which indicate the PLL lock status after a PLLCFG command N 32-bit words from core processor RAM specified by PEEK command S/PDIF input channel status PTC and STC values of 32 bits each Data words returned to host in the normal process of sending any command
Operation Functions
SPDIFSTATR GETPTCR
Progress Response EXPECT ISTATUS 1 1
Expected number of parameter words still to be received from host Interpreter status
13
ZR38650
Function Commands
AC-3 Decoder + Pro Logic Function
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 DSN 1 PRLG SF AB CDLY HDYNRNG LDYNRNG 0 KAR RPC 6 0 5 0 SIF BCFG 4 0 0 3 0 COMP SW SRDLY 2 1 1 0 DMM OCFG 0 1
HDYNRNG
AC3
LDYNRNG
High Dynamic Range scale factor controlling the depth of high-level compression. A two's complement fraction between 0.00 and 0.FE where 00 is no high-level compression and 7F is full compression. Low Dynamic Range scale factor controlling the depth of low-level compression. A two's complement fraction between 0.00 and 0.FE where 00 is no low-level compression and 7F is full compression. Data Stream Number for S/PDIF input. Selects which stream to decode. Range 0 -7. Normally zero. Karaoke mode: 0 = Disabled, 1 = Enabled. Repeat Count before muting. Maximum number of consecutive block repeats before muting output. PCM Scale Factor High. Output scale factor, 16-bit two's complement fraction between 0.0000 and 0. FFFE. The high byte. 0000 equals zero, 7FFF equals gain of one. PCM Scale Factor Low. Output scale factor low byte.
DSN KAR RPC PCMSFH
PCMSFH PCMSFL
The AC-3 Decoder function includes normal six-channel AC-3 and the two-channel AC-3 with Pro Logic output. Selection is made in the command for speaker configuration, dynamic range compression, downmixing, delays and error concealment strategy.
PRLG SIF COMP Pro Logic output: 0 = Off, 1 = On, 2 = Selected automatically based on input stream information. Serial Input Format: 0 = Non-formatted, 1 = AC-3 S/PDIF protocol. Compression and Dialog Normalization: 0 = Custom mode 0, 1 = Custom mode 1, 2 = Line mode (dialog normalization plus high level compression), 3 = RF modulation mode (peak level compression). Dual Mono Mode output selection when the two input channels are unrelated: 0 = Stereo, 1 = Mono channel 0 to both, 2 = Mono channel 1 to both, 3 = Mono channels 0 and 1 summed and scaled to both. Surround Filter for Pro Logic: 0 = Filter enabled, 1 = Filter (LP+NR) disabled. Auto-Balance for Pro Logic output: 0 = On, 1 = Off. Bass Redirection Configuration: 0 = No redirection, 1 = Redirect left, center, right to subwoofer for Pro-logic. All channels to subwoofer for AC-3, 2 = Redirect center to subwoofer for Pro-logic. Center, left surround and right surround to subwoofer for AC-3, 3 = Reserved. Subwoofer output channel: 0 = Off, 1 = On. Output Speaker Configuration of Front/Surround number of speakers (for Pro Logic only OCFG 3-7 can be used): 0 = 2/0 Surround Compatible, 1 = 1/0, 2 = 2/0 Normal, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2. In 2/0 configurations, a mono input is directed to both output channels. Center Delay in one millisecond steps from zero to five. Surround Delay: 0-15 = 0-15 ms for AC-3,15-30 ms for Pro Logic in one millisecond steps beyond 15 ms. 16 = zero delay for 3-D Sound.
PCMSFL
PCM + Pro Logic Decoder Function
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 SF AB CDLY 0 0 0 PCMSFH PCMSFL 1 6 0 0 BCFG SW SRDLY 5 0 4 0 3 0 DE 2 1 1 1
PCMPROL
0 0 DMM OCFG
DMM
SF AB BCFG
The PCM or Pro Logic Decoder function decodes two-channel PCM into four-channel Pro Logic output or transfers to twochannel PCM output. Selection is made in the command for speaker configuration, scale factor, mixing and delay. The parameter descriptions are the same as for the AC3 command except for OCFG and with the addition of DE.
DE De-Emphasis filter: 0 = Filter is disabled, 1 = Filter is enabled, 2 = Filter is enabled if pre-emphasis is defined in the channel status of the S/PDIF input stream. Output Speaker Configuration of Front/Surround number of speakers (for Pro Logic only OCFG 3-7 can be used): 0-2 = PCM, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2.
SW OCFG
OCFG
CDLY SRDLY
14
ZR38650
MPEG Decoder Function
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 DSN 0 1 PRLG SF AB CDLY 0 0 0 0 6 0 5 0 SIF BCFG 4 0 0 SW SRDLY 3 0 DE 2 1 1 1 DMM OCFG
MPEG
0 1
Pink Noise Generator Function
7 Command Parameter 1 Parameter 2 Parameters 3-6 Parameter 7 Parameter 8 0 BF L C 0 PCMSFH PCMSFL 1 6 0 5 0 4 0 0 R LS RS SW 3 0 2 0 1 1 0 1
PNG
PCMSFH PCMSFL
The MPEG function decodes MPEG1 or MPEG2 data streams into two-channel PCM output. The selection of MPEG1 or 2 is made automatically from the input stream. All parameters are the same as for the AC3 command except the following.
BCFG PRLG DE Bass Redirection Configuration: 0 = No redirection, 1 = Redirect left and right to subwoofer, 2 & 3 = Reserved. Pro Logic output: 0 = Off, 1 = On, 2 & 3 = Reserved. De-Emphasis filter: 0 =Filter is disabled, 1 =Filter is enabled, 2 = Filter is enabled if pre-emphasis is defined in the MPEG stream. Output Speaker Configuration. Number of Front/Surround speakers. Valid configurations for MPEG only is 2/0 and MPEG + Pro Logic are OCFG = 3-7. 0 & 1 = Reserved, 2 = 2/0 Normal, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2. In 2/0 configurations, a mono input is directed to both output channels.
The Pink Noise Generator function produces pseudo-random noise sequence outputs. Selection is made for output channel and scale factor. The parameter descriptions are the same as for AC-3 with the addition of the filter and output channels.
BF L C R LS RS SW Bandpass Filter. 0 = On, 1 = Off. Left channel output. 0 = Off, 1 = On. Center channel output. 0 = Off, 1 = On. Right channel output. 0 = Off, 1 = On. Left Surround channel output. 0 = Off, 1 = On. Right Surround channel output. 0 = Off, 1 = On. Subwoofer channel output. 0 = Off, 1 = On.
OCFG
User Function
7 Command Parameter 1 1 6 0 5 0 4 0 3 1 2 0 1 0
USER
0 0
Parameter Word 1
Parameter 8
Parameter Word 8
The USER function passes eight bytes of parameters to a user programmed function that has been downloaded.
15
ZR38650
Operation Commands
Resume Operation
7 Command 1 6 0 5 0 4 0 3 1 2 0 1 1 0 0
Return S/PDIF Status Information PLAY
Command 7 1 6 0 5 0 4 0 3 1 2 1
SPDIFSTAT
1 1 0 1
The PLAY command resumes operation of the selected function and unmutes the output after a STOP or STOPF command.
The SPDIFSTAT command allows the S/PDIF receiver channel status information and SPRXSTT register value to be returned to the Host by sending four READ commands.
Return PTC Information Mute Operation
7 Command 1 6 0 5 0 4 0 3 1 2 0 1 1
GETPTC
4 1 3 0 2 0 1 1 0 0
MUTE
0 1 Command
7 1
6 0
5 0
The MUTE command mutes the output without stopping the operation of the selected function.
The GETPTC command allows the PTC and STC (Presentation and System Time Clock) values be returned to the Host by sending eight READ commands.
Unmute Operation
7 Command 1 6 0 5 0 4 0 3 1 2 0 1 0
UNMUTE
0 1
No Operation
7 Command 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0
NOP
The UNMUTE command restores the muted output while continuing the operation of the selected function.
A NOP is not a command and does not affect operation except to cause the ZR38650 to return a response word to the host.
Stop Operation
7 Command 1 6 0 5 0 4 0 3 1 2 1 1 0 0 0
STOP
Set-Up Commands
PLL Table
7 6 0 0 AUDD [7:0] 0 AUDM [7:0] 0 DSPM DSPD AUDM [12:8] 5 0 4 1 3 1 2 0 AUDD [12:8] 1 0
PLLTAB
0 0
The STOP command stops operation of the selected function if the input is request driven and it mutes the output. Data in the input buffer is preserved but new data is ignored.
Command Parameter 1 Parameter 2 Parameter 3
1
Stop Operation and Flush
7 Command 1 6 0 5 0 4 0 3 1 2 1 1 0
STOPF
0 1
Parameter 4 Parameter 5 Parameter 6
The STOPF command stops operation of the selected function if the input is request driven and it mutes the output. Data in the input buffer is flushed out and new data is ignored.
The PLLTAB command sets the PLL programmable registers. The audio clock frequency is:
AUDM f AUDIO = f XTI x -----------------AUDD
where
f XTI AUDD < ------------------
10kHz
Return Status Information
7 Command 1 6 0 5 0 4 0 3 1 2 1 1 1 0 0
STAT
In master mode, the audio clock generates the serial port clocks, including the S/PDIF transmitter clock. The DSP clock is:
DSPM f DSP = f XTI x ----------------DSPD
where
f XTI DSPD < ---------------1MHz
During operation, the STAT command allows the N words of decoder status information to be returned to the host by sending N READ commands.
16
ZR38650
AUDM AUDD DSPM DSPD Audio PLL Multiplier: 13-bit number Audio PLL Divider: 13-bit number DSP PLL Multiplier: 8-bit number DSP PLL Divider: 6-bit number WFB
The CFG setup command determines the input, output and external memory configurations for the ZR38650.
WFA Word/Frame synchronization for inputs: 0 = Frame, 1 = Word. Word/Frame synchronization for outputs: 0 = Frame, 1 = Word. Wait-state cycles for external memory: 0 = None, 1 = One, 2 = Three, 3 = Seven. PES packetized input: 0 = Disabled, 1 = Enabled. DVD mode: 0 = Disabled, 1 = Enabled. Clock source for outputs: 0 = SCKIN input pin, 1 = Internal, using the SPBS scaler with the Audio PLL or system clock. Master mode for output clocking: 0 = Slave, 1 = Master. Master mode for input clocking: 0 = Slave, 1 = Master. Serial Clock B Polarity: 0 = Negative, 1 = Positive. Serial Clock A Polarity: 0 = Negative, 1 = Positive. Frame size (bits) for outputs: 0 = 16, 1 = 32, 2 = 64, 3 = 128, 4 = 192, 5 = 256, 6 = 193, 7 = 24. Normal value = 1. Frame size (bits) for input: 0 = 16, 1 = 32, 2 = 64, 3 = 128, 4 = 192, 5 = 256, 6 = 193, 7 = 24. Normal value = 1. Data Request output pin DREQ (GPIO0): 0 = Disabled, 1 = Enabled. Mute Pin Enable: 0 = Mute determined by host command, 1 = Mute determined by MUTE (GPIO5) input pin. Error Pin Enable for ERROR output pin (GPIO1): 0 = Disabled, 1 = Enabled. Input Word Select Polarity: 0 = Left is WS low, 1 = Left is WS high. Output Word Select Polarity: 0 = Left is WS low, 1 = Left is WS high. S/PDIF input selection: 0 = Input from SRA register, 1 = Input from S/PDIF receiver SPRXDAT register. Audio/Video Synchronization: 0 = Disabled, 1 = Enabled. S/PDIF Output: 0 = Disabled, 1 = Enabled. Input Word: 0 = 20 bits, 1 = 18 bits, 2 = 16 bits, 3 = 24 bits. Output Word: 0 = 20 bits, 1 = 18 bits, 2 = 16 bits, 3 = 24 bits. Parallel Data Interface for data input stream: 0 = Serial, 1 = Parallel. Group A internal clock divider. Group B internal clock divider. Format of serial ports group B: 0-5 = Delay bits, 6 = TDM mode, 7 = Right justified mode (maximum delay is 64). Format of serial ports group A: 0-5 = Delay bits, 6 = TDM mode, 7 = Right justified mode (maximum delay is 64).
For example, if fXTI = 24.576 MHz and fAUDIO is 256x a sample rate of 48 kHz, then AUDM = 1 and AUDD = 2. For the fastest processor operation if fXTI = 24.576 MHz, then fDSP = 99.84 MHz if DSPM = 65 and DSPD = 16. See the section OPERATION WITH COMMANDS on page 24 for a more complete description of these settings.
WAIT PES DVD CB MB MA
PLL Configuration
7 Command Parameter 1 1 6 0 SR 5 0 4 1 F3 3 1 F1 2 0 F2 1 0 AS
PLLCFG
0 1 DS
CPB CPA FRB
The PLLCFG command defines the PLL programmable configuration. It returns the current status of the PLL lock (PLLR). PLLCFG must be given before a CFG command. The next serial host command must be delayed by at least 2000 DSP instruction cycles (40 microseconds at 50 MHz) following a change of F1F3, AS, or DS fields.
SR F1 F2 F3 Sampling Rate of output: 0 = 48 kHz, 1 = 44.1 kHz, 2 = 32 kHz, 3 = 96 kHz. Determines input clock source for audio PLL: 0 = Internal oscillator or XTI input, 1 = S/PDIF mode using SPFRX. Determines audio clock fAUDIO source: 0 = Audio PLL, 1 = Internal oscillator or XTI input at fXTI. Determines master clock output frequency f SCKIN: 0 = Audio clock frequency fAUDIO, 1 = One-half audio clock frequency (fAUDIO/2). Audio PLL Set: 0 = No action, 1 = Resets Audio PLL. DSP PLL Set: 0 = No action, 1 = Resets DSP core PLL
FRA DRQ MPE EPE ISP OSP SEN AVS SPO INW
AS DS
Set Configuration
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 0 1 WFA PES CPB DRQ SEN 6 0 WFB 0 CPA 0 AVS MPE SPO 5 0 0 DVD 4 0 0 CB FRB EPE INW SPAS SPBS FMB FMA 0 0 3 0 0 MB 2 0 0 MA 0 FRA ISP OUTW OSP PDI 1 1 WAIT 0 0 0
CFG
OUTW PDI SPAS SPBS FMB FMA
17
ZR38650
Set STC
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 1 0 6 0 AVS 5 0 SCU STC [31:24] STC [23:16] STC [15:8] STC [7:0] VDY [15:8] VDY [7:0] 4 1 3 0 2 1 0 1 1
SETSTC
0 1
S/PDIF Channel Status
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 0 0 1 6 0 0 CC [7:0] PE C P 5 0 4 1 3 0 2 1 SR 1 0
SPDIFCS
0 1
0
The SETSTC command sets the system time clock and video delay for A/V synchronization.
AVS SCU STC VDY Audio/Video Synchronization: 0 = Passive synchronization, 1 = Active synchronization. System Clock Update: 0 = When SU flag is set, 1 = Immediately. System Time Clock: A 32-bit number in units of 90 kHz. Video Delay: A 16-bit two's-complement number in units of 90 kHz.
This command defines the output status information for the S/PDIF transmitter. It must be sent before the function command is sent. The SPO bit in the CFG command enables the S/PDIF transmitter.
SR CC Sample Rate of output: 0 = 44.1 kHz, 2 = 48 kHz, 3 = 32 kHz. All other values reserved. Category Code. The bit order in this parameter is reversed, i.e. bit 0 of IEC-958 Category Code is the rightmost bit. Pre-Emphasis when P = 0: 0 = None, 1 = 50/15 s. Copyright indication. PCM: 0 = PCM encoded audio, 1 = Non-PCM encoded audio.
PE C P
Return Version Number
7 Command 1 6 0 5 0 4 0 3 0 2 0 1 0 0
VER
Special Function Parameter
7 6 0 5 0 4 1 EXT PAR12 PAR11 PAR10 PAR22 PAR21 3 0 2 1 1 1
PARAM
0 0
1 Command Parameter 0 1
The VER command allows the four words of the ROM version number (VERR) to be returned to the host by sending four READ commands.
Parameter 1 Parameter 2 Parameter 3
Load Program
7 Command Parameter 1 1 6 0 5 0 4 1 3 0 2 0 1 0
BOOT
0 0
Parameter 4 Parameter 5
....
....
Program Word 0
Parameter N
Program Word N-1
The BOOT command allows serial loading and running of a program from the host. (The format is given in Appendix A of the PROCESSOR FUNCTIONAL DESCRIPTION and includes the start address, number of words and instructions). Execution transfers to the start address with no further action by the ROM resident executive.
This command defines parameters for special functions that require more then 8 bytes of information. The specific meaning and value of the command parameters are determined by the function that is using it. Any number of parameters can be specified depending on the function. Each parameter contains three bytes which are stored as a single 24-bit word to memory (PAR12 is the most significant byte). If the destination memory is 20 bits the four most significant bits of PARi2 are ignored.
EXT PARij Opcode Extension: 0-255 identification number. Parameter number: i = 1 through N parameter number, j = 2 through 0 byte index.
18
ZR38650
Interpret Instruction
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 1 6 0 5 0 4 1 3 0 2 0 1 0
INTRP
0 1
Load Memory Data
7 Command Parameters 1-3 Parameters 4-7 Parameter 8 1 6 0 5 0 4 1 3 0 2 0 1 1
POKE
0 1
Instruction [31:24] Instruction [23:16] Instruction [15:8] Instruction [7:0]
Start Address [23:0] Number of Words (N) [31:0] Data Word 0 [31:24]
Parameter 7+4N
Data Word N-1 [7:0]
The INTRP set-up command allows loading and running of a single ZR38650 core processor instruction from the host. After the single execution, control transfers to the ROM resident executive with further commands possible from the host.
Set and Return I/O Registers
7 Command Parameter 1 Parameter 2 Parameter 3 Parameter 4 1 0 0 0 0 6 0 5 0 4 1 3 0 2 0 1 1
SETIO
0 0
The POKE set-up command allows serial loading of data and program from the host to the ZR38650 memory. N 32-bit words are loaded at a 20-bit start address where bits [23:20] are ignored. After the loading, control transfers to the ROM resident executive with further commands possible from the host.
Return Memory Data
7 Command Parameter 1 Parameter 2 Parameter 3 1 6 0 5 0 4 1 3 0 2 1 1 0 0 0
PEEK
GPIOC MASK GPIOC GPIO MASK GPIO
Start Address [23:16] Start Address [15:8] Start Address [7:0] Number of Words (N) [31:24] Number of Words (N) [23:16] Number of Words (N) [15:8] Number of Words (N) [7:0]
The SETIO set-up command allows changing and reading the six single-bits of the general purpose I/O registers GPIO and GPIOC. For the bits set in the GPIO MASK field, the corresponding bits in the GPIO register will be updated to the values set in the GPIO field. The same is true for the GPIOC MASK field and GPIOC register and field. The SETIOR response returns the state of the two registers after the SETIO command.
GPIOC MASK GPIOC A set bit i of this GPIOC MASK field enables updating the bit i of the GPIOC register. The value of bit i in the GPIOC register is updated to the value of bit i in this GPIOC field if bit i in the GPIOC MASK field is set. GPIOC[ i ] = 0 for an input, GPIOC[ i ] = 1 for an output. A set bit i of this GPIO MASK field enables updating the bit i of the GPIO register. The value of bit i in the GPIO register is updated to the value of bit i in this GPIO field if bit i in the GPIO MASK field is set.
Parameter 4 Parameter 5 Parameter 6 Parameter 7
The PEEK command allows serial reading of data and program from the ZR38650 memory to the host. N 32-bit words are read from a 20-bit start address where bits [23:20] are ignored and where N is a 20-bit number. 4N READ commands must be sent from the host to transfer all PEEKR reply data. After reading, control transfers to the ROM resident executive with other commands possible from the host.
GPIO MASK GPIO
Read Command
Read
7 Command 0 6 0 5 0 4 0 3 0 2 0 1 0
READ
0 0
The READ command returns a single Reply word to the host after the STAT, VER, SETIO, PLLCFG, PEEK, GETPTC, NOP or SPDIFSTAT commands have been issued. One or more READ commands must be issued after the above commands.
19
ZR38650
Reply Responses
The first word returned is always EXPECT, the number of expected status words, followed by the status words followed by the interpreter status ISTATUS.
EW EF CCFG BSID BSM Extra Word packed: 0 = No, 1 = Yes for 44.1 kHz sample rate only. Effects channel for low frequency: 0 = No, 1 = Yes. Coding Configuration: 0 = Dual mono mode, 1 = 1/0, 2 = 2/0, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2. Bit-Stream Identification number of five bits. Bit-Stream Mode: 0 = Main audio service, 1 = Main audio service minus dialog, 2 = Associated service; visually impaired, 3 = Associated service; hearing impaired, 4 = Associated service; dialog, 5 = Associated service; commentary, 6 = Associated service; emergency flash. Center Mix level: 0 = -3 dB, 1 = -4.5 dB, 2 = -6 dB. Surround Mix level: 0 = -3 dB, 1 = -6 dB, 2 = None. Dolby Surround mode: 0 = No indication, 1 = Not Dolby Surround encoded, 2 = Dolby Surround encoded. Copyright: 0 = Not copyright protected, 1 = Copyright protected. Original: 0 = Copy of an original bit-stream, 1 = Original bit-stream. Dialog Normalization for Channel 2 in dual mono. Dialog Normalization value for normal operation. Language Code for Channel 2 in dual mono. Language Code for normal operation. Production information for Channel 2 in dual mono operation. 0 = Does not exist, 1 = Does exist. Room Type for Channel 2 in dual mono operation. 0 = Not indicated, 1 = Large, 2 = Small. Mix Level for Channel 2 in dual mono operation. Production information in normal operation: 0 = Does not exist, 1 = Does exist. Room Type in normal operation: 0 = Not indicated, 1 = Large, 2 = Small. Mix Level value in normal operation.
AC3 Status Reply
AC3STATR
This reply is a response to the STAT command during the AC3 function operation.
7 Status Word 1 Status Word 2 Status Word 3 Status Word 4 Status Word 5 Status Word 6 Status Word 7 Status Word 8 Status Word 9 Status Word 10 Status Word 11 Status Word 12 Status Word 13 Status Word 14 Status Word 15 Status Word 16 P2 P RT2 RT CM 0 0 LC2 SR 0 BSID SM DS DN2 DN 6 STATUS RST AC3DST 0 0 DIFT [15:8] DIFT [7:0] IDR EF CCFG BSM C OR EW 5 4 3 2 05 AC3IST 1 0
CM SM DS C OR DN2 DN LC2 LC P2
LC ML2 ML
RT2 ML2 P
STATUS
Global Status of operation in progress: 0 = No errors, 1 = Updated status information is not yet available (a new command has been received and is being processed), 2 = Operation error (see Status word 2 for details). Run Status: 0 = Running, 1 = Stopped, 2 & 3 = Reserved. AC-3 Decode Status returned by routine: 0 = No errors, 1 = Input status nonzero, last output block was repeated, 2 = Input status nonzero, outputs were muted, 3 = Unsupported bitstream identification revision, 4 = Unsupported number of channels in input stream, 5 = Unsupported number of input streams. AC-3 Frame Information Status returned by routine: 0 = No errors, 1 = Invalid frame sync, 2 = Invalid sample rate, 3 = Invalid data rate, 4-6 = Reserved, 7 = Input underflow. Difference Time. Signed difference between PTC and STC in units of the 90-kHz clock. For packetized inputs. Sample Rate: 0 = 48 kHz, 1 = 44.1 kHz, 2 = 32 kHz. Input Data Rate in Kbits per second: 0 = 32, 1 = 40, 2 = 48, 3 = 56, 4 = 64, 5 = 80, 6 = 96, 7 = 112, 8 = 128, 9 = 160, 10 = 192, 11 = 224, 12 = 256, 13 = 320, 14 = 384, 15 = 448, 16 = 512, 17 = 576, 18 = 640.
RT ML
RST AC3DST
PCMPROL Status Reply
7 Status Word 1 Status Word 2 Status Words 3-6 Status Word 7 Status Word 8 6 STATUS RST 0 VERSION 0 0 5 4 3 2 04/06
PCMPROLR
1 0
AC3IST
DIFT[15:0] SR IDR
This reply is a response to the STAT command during the PCM or Pro Logic function operation. The status fields are the same as for AC3STATR except:
VERSION Version number of the PCMPROL function.
20
ZR38650
MPEG Status Reply
7 Status Word 1 Status Word 2 Status Word 3 Status Word 4 Status Word 5 Status Word 6 Status Word 7 Status Word 8 Status Word 9 Status Words 10-12 MODE 0 BR MEXT 0 7 6 0 0 5 4 3 2 1 0 6 STATUS RST 0 0 0 DIFT [15:8] DIFT [7:0] ID SFR CRP ORG LAY PAD PRT PVR 5 4 3 2 07 MPGST
MPEGSTATR
1 0
Version Number Reply
7 Data Word 0 Data Word 1 Data Word 2 Data Word 3 6 5 4 3 2 1
VERR
0
ROM Version Number [31:24] ROM Version Number [23:16] ROM Version Number [15:8] ROM Version Number [7:0]
The VERR reply is a response to the VER command. It is four data words of the version number of the ROM resident executive transferred by using four READ commands.
EMPH
Set I/O Register Reply
SETIOR
This reply is a response to the STAT command during the MPEG function operation.
MPGST MPEG-1 Decode Status returned by routine: 0 = No errors, 1 = Invalid frame sync, 2 = CRC error, 3 = Invalid sample rate, 4 = Invalid data rate, 5 = Input underflow. Algorithm ID: 0 = Reserved, 1 = MPEG. Layer type: 0 = Reserved, 1 = Layer III, 2 = Layer II, 3 = Layer I. Protection bit: 0 = CRC word present, 1 = No CRC word. Bit-Rate index (see ISO-MPEG document CD 11172-3, part 3). Sampling Frequency: 0 = 44.1 kHz, 1 = 48 kHz, 2 = 32 kHz. Padding bit. Private bit. Encoding Mode: 0 = Stereo, 1 = Joint-stereo, 2 = Dual channel, 3 = Single channel. Mode Extension (see ISO-MPEG document). Copyright: 0 = None, 1 = Copyrighted. Original/home: 0 = Copy, 1 = Original.
Status Word 1 Status Word 2
GPIOC Register GPIO Register
ID LAY PRT BR SFR PAD PRV MODE MEXT CPR ORG EMPH
The SETIOR reply is a response to the SETIO command. It is two data words with the most recent contents of the GPIO and GPIOC registers.
PLLCFG Reply
7 Status Word 1 6 5 0 4 3 2 1 PA 0
PLLR
PD
The PLLR reply is a response to a READ following the PLLCFG command. Returns one byte indicating the status of PLL locking.
PA PD PLL for Audio: 0 = Not locked, 1 = Locked. PLL for DSP core: 0 = Not locked, 1 = Locked.
Data Memory Reply
7 6 5 4 3 2 1
PEEKR
0
Emphasis: 0 = None, 1 = 50/15 s, 2 = Reserved, 3 = CCITT J.17.
Data Word 0
Memory Data Word 0 [31:24]
PNG Status Reply
7 Status Word 1 Status Word 2 Status Words 3-6 Status Word 7 Status Word 8 6 STATUS RST 0 VERSION 0 0 5 4 3 2 03
PNGSTATR
1 0
Data Word N-1
Memory Data Word N-1 [7:0]
The PEEKR reply is a response to the PEEK command. It is N data words with the contents of the specified ZR38650 memory locations that is transferred by 4N READ commands.
This reply is a response to the STAT command during operation of the PNG function.
VERSION Version number of the Pink Noise functions.
21
ZR38650
S/PDIF Status Reply
7 Status Word 1 Status Word 2 Status Word 3 Status Word 4 0 6 0 CC [7:0] PE SPRXSTT [7:0] C P 0 Status Word 1 5 4 3 2 SR 7 6 5 4 3 2 1 0
SPDIFSTATR
1 0
Progress Responses
Expected Parameters Response EXPECT
Number of Expected Parameter Words
The SPDIFSTATR reply provides the following S/PDIF receiver status information in response to the SPDIFSTAT command:
SR CC Sample Rate of input: 0 = 44.1 kHz, 2 = 48 kHz or 96 kHz, 3 = 32 kHz. All other values reserved. Category Code. The bit order in this parameter is bitreversed from the standard IEC-958 Category Code where bit 0 is the left-most. Here bit 0 is the right-most bit. Pre-Emphasis when P = 0: 0 = None, 1 = 50/15 s.
EXPECT is a progress response to any command sent from the host. It is one data word returned to the host with the number of parameter words still expected by the ZR38650 at the time it was sent, or the number of words still to be returned by a reply response. It is not sent when the expected number is zero.
Interpreter Status Response
7 6 5 4 3 2 1
ISTATUS
0
PE C P SPRXSTT
Copyright indication.
Status Word 1 ISTATUS
PCM: 0 = PCM encoded audio, 1 = Non-PCM encoded. S/PDIF Receiver Status. Seven bits indicating L/R channel, loss of synchronization, beginning of a new block and errors for preamble, parity, biphase and invalid input.
The last word returned by the device after receiving a Host command is a status word. The ISTATUS field flags any errors detected during decoding and interpretation of the host command.
ISTATUS Interpreter Status (Hex): 80 = No errors, 81 = Invalid opcode, 82 = Invalid parameters, 83 = Not ready to accept new commands, 84 = Command overflow, 85 = Ready to accept new commands.
GETPTC Reply
7 Status Words 1-4 Status Words 5-8 6 5 4 3 2 1
GETPTCR
0
PTC [31:0] STC [31:0]
The GETPTCR reply is a response to eight READ commands following the GETPTC command.
PTC STC Presentation Time Clock. Least significant 32 bits in units of 90 kHz. Most significant byte first. System Time Clock. Least significant 32 bits in units of 90 kHz. Most significant byte first.
Note that the Host commands are executed only after all parameters have been received and correctly decoded. Therefore the status word does not show the outcome of the command execution, but only the result of command interpretation. If the Host issues a new command before the previous one has been executed the device ignores the new command and returns ISTATUS = 83. The Host command STAT can be used to get information on the current execution status of a function.
22
ZR38650
Table 9: Sequence Of Commands And Responses Summary
Command A Single Word AC3 Number of Parameter Words P 8 Number of Read Words R Response To Command + P+ R 8 EXPECT + ISTATUS Response To STAT Command + (S + 1) READs EXPECT + AC3STATR + ISTATUS EXPECT + PCMPROLR + ISTATUS EXPECT + MPEGSTATR + ISTATUS EXPECT + PNGSTATR + ISTATUS User Defined + ISTATUS Number of Status Words S 16
Class Function
Command Description AC-3 and Pro Logic decoder PCM or Pro Logic decoder
PCMPROL
8
-
8 EXPECT + ISTATUS
8
MPEG
8
-
8 EXPECT + ISTATUS
12
MPEG or MPEG + Pro Logic decoder Pink Noise Generator
PNG
8
-
8 EXPECT + ISTATUS
8
USER Operation PLAY MUTE UNMUTE STOP STOPF STAT SPDIFSTAT GETPTC NOP Set-Up PLLTAB PLLCFG CFG SETSTC VER BOOT SPDIFCS PARAM INTRP SETIO POKE PEEK
8 0 0 0 0 0 0 0 0 0 6 1 8 7 0 4N 4 1 + 3N 4 4 7 + 4N 7
-
8 EXPECT + ISTATUS ISTATUS ISTATUS ISTATUS ISTATUS ISTATUS
User Defined -
User defined function Resume operation Mute audio output Restore muted output Stop operation Stop operation, flush data Return decoder status
See under functions 4+1 8+1 EXPECT + SPDIFSTATR + ISTATUS EXPECT + GETPTCR + ISTATUS ISTATUS 1 4+1 4N 6 EXPECT + ISTATUS EXPECT + PLLR + ISTATUS 8 EXPECT + ISTATUS 7 EXPECT + ISTATUS EXPECT + VERR + ISTATUS 4N EXPECT + ISTATUS 4 EXPECT + ISTATUS 1 + 3N EXPECT + ISTATUS 4 EXPECT + ISTATUS 2 EXPECT + SETIOR + ISTATUS 7 + 4N EXPECT + ISTATUS 7 EXPECT + PEEKR + ISTATUS 4 8 1 4 2 4N
Return the S/PDIF input channel status Return the PTC value No operation Set the PLL tables Define the PLL configuration Configure the I/O Set System Time Clock Return ROM version number Load and execute N-word bootstrap program Write the S/PDIF output channel status Define N parameter data words for special functions Interpret parameters as ZR38001 instruction Set, test and return GPIO registers Load N core processor RAM locations Read N core processor RAM locations
23
ZR38650
OPERATION WITH COMMANDS
This section describes operation principles when using the command structure and its configuration choices.
Crystal or External System Clock Input (4-40 MHz) XTI fXTI System Crystal Oscillator XTO fXTI
X
Start-Up
After being reset by the system RESET signal, the ZR38650 will check for an external program ROM to load. Not finding this it will start execution from the internal ROM and await commands from the host. Normal host operation would confirm the ROM version number and then configure the ZR38650 to match the system and desired operation. The command configuration sequence PLLTAB, PLLCFG, CFG is mandatory and must precede any decoding function selection.
System Clock Oscillator
DSPM DSP PLL
/ DSPD BYPASS System Clock Output (30-50 MHz) CLKOUT SPFRX S/PDIF Receiver
0 1
MUX
fDSP
DSP Core Clock (60-100 MHz)
/2 fCLKOUT fSPFRX
1 0
The PLL Configuration
Two phase-locked-loops (PLLs) allow independent selection of the core processor clock rate (fDSP) and the serial digital audio clock rate (fAUDIO) for a variety of system clock frequencies (fXTI) and sources. Figure 6 shows the system oscillator, the two PLLs, the serial I/O divider chains and the interconnection selections. These are configured with the PLLTAB, PLLCFG and the CFG commands. The DSPM and DSPD fields in the PLLTAB command (see page 16) determine the core processor clock rate to allow a choice between processing performance and lower power at lower clock rates. Table 10 shows some representative values for common system clock frequencies. The AUDM and AUDD fields in the PLLTAB command determine the serial digital audio master clock rate for the I/O dividers. Table 11 shows some representative and recommended values for common sample rates and master clock multiples.
F1
X
MUX AUDM Audio PLL / AUDD
0 1
MUX /2
1 0
F2
fAUDIO Audio Clock
Master Clock SCKIN (fSCKIN)
F3
MUX
0
1
CB fPSB
MUX fPSA = fAUDIO / SPAS /2
1 0 1
/ SPBS /2
0
Serial I/O Dividers
Serial Clocks SCKB (fB)
SPBS=1
MUX fB
0 1
MUX
SPAS=1
MB
MUX fA
0 1
SCKA (fA) SCKB Output Clock Word/Frame Selects WSB/FSB
0 1
MA
MUX SCKA Input Clock / FRA Frame Size Dividers
/ FRB
MB WSA/FSA
MUX
0
1
MA Output Word/Frame Sync. B Group
MUX Input Word/ Frame Sync. A Group
Figure 6. The System Clock Oscillator, The DSP PLL And The Audio PLL With Serial I/O Divider Chains
24
ZR38650
Table 10: Representative Values For DSPM And DSPD In The PLLTAB Command
Nominal Processor Core Clock Frequency fDSP 66 MHz System Clock Frequency fXTI 12.288 MHz 16.9344 MHz 18.432 MHz 24.576 MHz 27.0 MHz 32.0 MHz DSPM/ DSPD 27/5 27/7 18/5 35/13 22/9 33/16 Actual fDSP 66.35 MHz 65.3 MHz 66.35 MHz 66.17 MHz 66.0 MHz 66.0 MHz DSPM/ DSPD 41/7 17/4 27/7 47/16 8/3 9/4 72 MHz Actual fDSP 72 MHz 72 MHz 71 MHz 72.2 MHz 72.0 MHz 72.0 MHz DSPM/ DSPD 13/2 14/3 13/3 39/12 80/27 5/2 80 MHz Actual fDSP 79.9 MHz 79 MHz 79.9 MHz 79.9 MHz 80.0 MHz 80.0 MHz DSPM/ DSPD 65/8 35/6 65/12 65/16 100/27 25/8 100 MHz Actual fDSP 99.8 MHz 98.8 MHz 99.8 MHz 99.8 MHz 100.0 MHz 100.0 MHz
Table 11: Representative And Recommended* Values For AUDM/AUDD In The PLLTAB Command
Serial Audio Master Clock Frequency fAUDIO 8.192 MHz (256 x 32 kHz) 3/2* 1280/2646 1/3* 1024/3375 32/125 11.2896 MHz (256 x 44.1 kHz) 147/160 2/3* 294/640 784/1875 441/1250 12.288 MHz (256 x 48 kHz) (384 x 32 kHz) 1/1* 640/882 1/2* 512/1125 48/125* 16.9344 MHz (384 x 44.1 kHz) 441/320 1/1* 882/128 392/625 1323/2500 18.432 MHz (384 x 48 kHz) 3/2* 960/882 3/4* 256/375 72/125
System Clock Frequency fXTI 12.288 MHz 16.9344 MHz 24.576 MHz 27.0 MHz 32.0 MHz
Input/Output Configuration
The CFG configuration command (see page 17) and the SETIO command (see page 19) determine the digital input and output configuration. Connections to the data stream input, the output DACs and the single-bit general purpose registers are made through the input/output ports. There are seven digital audio input and output ports (Port A, E and F are inputs and Ports B, C, D and G are outputs). There are six single-bit general purpose user defined I/O ports: GPIO[5:0].
can be activated with the clocking systems of Port Group B). The system clock (fXTI), the audio PLL locked to the system clock or the S/PDIF receiver can generate a master audio clock fAUDIO. This can be used to generate the two internal input and output bit-rate clocks when they are masters. See Figure 6. If input port group A is a master, SCKA is at a frequency fA = fPSA/(2*SPAS) where fPSA is the audio clock fAUDIO. In the case where SPAS equals one, fA is equal to fPSA. The divider SPAS is a field in the CFG command. Likewise, when output port group B is master, SCKB is at a frequency fB = fPSB/(2*SPBS) where fPSB is the internal audio clock fAUDIO or an external clock fSCKIN received through the SCKIN pin. In the case where SPBS equals one, fB is equal to f PSB .The outputs are unique in that when operating as a master their clock outputs can also be derived from an externally supplied master clock input (SCKIN) with the programmable divider rate SPBS. This selection is made with the CB field in the CFG command. Some of these choices are summarized in Table 12.
Serial Ports
The bit-serial ports serve a variety of peripheral device conventions. Their operation is determined solely by the CFG configuration command. The input Port Group A (serial inputs A, E, F) and output Port Group B (serial outputs B, C, D and G) have separate clocking systems and may be individually selected with the ZR38650 acting as a master or a slave (Port F
25
ZR38650
Table 12: Serial Ports A & B Clocking Summary In The CFG And PLLCFG Commands
Function Audio PLL source from S/PDIF or System Clock Audio Clock source from Audio PLL or System Clock External master clock input SCKIN pin (f SCKIN) Internal master clock (fPSB = fAUDIO) and Master external clock output pin Master or slave clocking mode Internal 12-bit master clock scalers for SCKA and SCKB. LS 8-bit fields. Bypass of clock scalers Data latched/sent out on rising/falling edge of clock Data latched/sent out on falling/rising edge of clock None None MA field SPAS field (f A = fPS A/ [2*SPAS]) fA = fPSAif SPAS=1 CPA = 0 CPA = 1 Input Port Group A F1 F2 CB field = 0 CB field = 1 MB field SPBS field (fB = fPSB / [2*SPBS]) fB = fPSB if SPBS=1 CPB = 0 CPB = 1 Output Port Group B
Table 13 shows some representative values for both SPBS and AUDM/AUDD for different output sample frequencies (fS) and
master clock multiples of the sample frequency. They are for the common choice of a system clock frequency of 24.576 MHz.
Table 13: Example SPBS And AUDM/AUDD Settings With A 24.576 MHz System Clock fXTI
fs 48 kHz 48 kHz 48 kHz 96 kHz fAUDIO 256 fs 384 fs 512 fs 256 fs fAUDIO (SCKIN Output) 12.288 MHz 18.432 MHz 24.576 MHz 24.576 MHz AUDM/AUDD 1/2 3/4 1/1 1/1 SPBS 2 3 4 2 6.144 MHz SCKB Output (64 fs) 3.07 MHz
Serial Port Formats
Many choices are possible for the bit-serial port formats and word sizes. The five most commonly used formats are summarized in Table 15 along with the selectable word sizes. Waveforms for each are illustrated in Figures 7-11. Note the various frame durations indicated. Clocking for both master and slave operation is shown. The transitions marked are the edges where data changes when the ZR38650 is a master or where the data is sampled when it is a slave. Settings for the appropriate fields in the CFG command are also summarized.
Word select (WS) or frame synchronization (FS) is chosen with the WFA and WFB fields. The polarity of the WS signal is chosen with the ISP and OSP fields. Either polarity is acceptable on any of the word select formats. Through the FMA field the frameless input operation of Format 3 can be chosen. The input then is sampled every SCKA and an interrupt generated after 16 bits has been received. Note that when a master the FS signal shown is, in fact, generated and if FS is asserted when a slave it will re-synchronize the data as shown. This format may not be accepted by some function operating modes.
26
ZR38650
Digital Audio Receiver
The digital audio receiver function of the ZR38650 is fully compliant with the IEC-958, S/PDIF, AES/EBU and EIAJ CP-340 consumer mode interface standards. It will lock on to the incoming bitstream and extract the clock and data information. The data is supplied to the processor for decoding and the clock is multiplied to yield a 256x or 384x sample rate, as required by the DACs. This master clock signal is available on the SCKIN pin as an output. For correct operation of the S/PDIF receiver the following initialization steps are required: * The AUDD variable in the PLLTAB command should be set to approximately 128 x fXTI, where fXTI is the clock input frequency expressed in MHz (i.e. if fXTI = 12.288 MHz, then AUDD equals the integer portion of 12.288 x 128 = 1572). AUDM should be set to 4 or 6, for 256x or 384x sample rate audio clock output, respectively. * The F1 field in the PLLCFG command should be set to 1. * The SEN field in the CFG command should be set to 1. Other representative values for AUDM/AUDD, F3 and SPBS when using the S/PDIF receiver are given in Table 14 for various sample rates and master clock rates. They are for the common choice of a system clock frequency (fXTI) of 24.576 MHz.
Table 14: Example SPBS, AUDM/AUDD and F3 Settings using the S/PDIF Receiver and a 24.576 MHz System Clock fXTI
fs 48 kHz 44.1 kHz 32 kHz 96 kHz Master Clock 256 fs 384 fs 256 fs 128 fs Master Clock fSCKIN 12.288 MHz 16.9344 MHz 8.192 MHz 12.288 MHz F3 0 0 0 1 Audio Clock (fAUDIO) 12.288 MHz 16.9344 MHz 8.192 MHz 24.576 MHz AUDM/AUDD 4/3416 6/3416 4/3416 4/3416 SPBS 2 3 2 2 SCKB Output (64 fs) 3.072 MHz 2.8224 MHz 2.048 MHz 6.144 Mhz
Digital Audio Transmitter
The digital audio transmitter of the ZR38650 is fully compatible with IEC-958, S/PDIF, AES/EBU and EAIJ CP-340 consumer mode standards. This function enables the transmission of digital audio bitstreams to an external decoder for processing in all modes of operation, i.e. AC-3, MPEG or PCM. The transmitter is enabled by setting the SPO bit in the CFG command. The Channel Status information required by IEC-958 should be supplied to the ZR38650 through the SPDIFCS command See the section S/PDIF Channel Status SPDIFCS on page 18. It is important to set the Channel Status bits for an external decoder to operate correctly. When the S/PDIF output is enabled, the fourth serial port SDG is disabled. Note that the output frame size must be 32 bits (FRB = 1) when using the S/PDIF output.
normally the ERROR output signal. GPIO[5:0] may be configured as user defined outputs by setting the GPIOC field in the SETIO command. Inputs pins, the ones that are defined as inputs from GPIO[5:0], are sampled and read from the GPIO register by the host with the SETIO command. At the same time it can set the state of the pins that are configured as output pins.
Decoder Operation
A typical decoder function selection command sequence would be: AC3, UNMUTE...MUTE...PROL, UNMUTE... where AC-3 is selected first, then followed by a switch to ProLogic at a later time. If the DRQ bit in command CFG is set, the command sequence must include a PLAY: AC3, PLAY, UNMUTE...MUTE, STOP...MPEG, PLAY, UNMUTE....
General Purpose Ports
There are six single-bit general purpose ports GPIO[5:0] normally configured as inputs at reset. GPIO5 is normally used as the MUTE input and GPIO0 as the DREQ output. GPIO1 is
27
ZR38650
Table 15: Input and Output Format Selections In The CFG Command
CFG Configuration Command Fields Format 0 1 2 3 4 I2S EIAJ Non-Delayed Frameless Frame Sync Figure 7 8 9 10 11 WFA or WFB Frame/Word 1 1 1 0 0 ISP or OSP Word Polarity 0 1 0 0 0 FMA or FMB Format 1 7 0 6 1 CPA or CPB Clock Polarity 0 0 0 1 1 INW or OUTW Input or Output Word Size 16, 18, 20, 24 bits 16, 18, 20, 24 bits 16, 18, 20, 24 bits 16 bits 16, 18, 20, 24 bits
SCKA (input)
SCKB (output)
Frame WS Left Channel Right Channel
MS 18 17 16
3
2
1 LS
MS 18 17 16
3
2
1 LS
SDA, SDB
MS 16 15 14
3
2
1 LS
MS 16 15 14
3
2
1 LS
MS 14 13 12
3
2
1 LS
MS 14 13 12
3
2
1 LS
Figure 7. I2S Input/Output - Format 0
SCKA (input)
SCKB (output)
Frame WS Left Channel Right Channel
MS
MS 18 17 16
2
1 LS
MS
MS 18 17 16
2
1 LS
SD
MS
MS 16 15 14
2
1 LS
MS
MS 16 15 14
2
1 LS
MS
MS 14 13 12
2
1 LS
MS
MS 14 13 12
2
1 LS
Figure 8. EIAJ Input/Output - Format 1
28
ZR38650
SCKA (input)
SCKB (output)
Frame WS Left Channel Right Channel
MS 18 17
1 LS
MS 18 17
1 LS
SD
MS 16 15
1 LS
MS 16 15
1 LS
MS 14 13
1 LS
MS 14 13
1 LS
Figure 9. Non-Delayed Input/Output - Format 2
SCKA (input)
SCKB (output)
FS
SD
MS 14 13
1 LS MS 14 13
1 LS MS 14 13
1 LS MS 14 13
Figure 10. Frameless Input - Format 3
SCKA (input)
SCKB (output) Frame FS
MS 18 17
1 LS
MS 18 17
1 LS
SD
MS 14 13 1 LS MS 14 13 1 LS
Figure 11. Frame Sync Input/Output - Format 4
29
ZR38650
PROCESSOR GENERAL DESCRIPTION
With its versatile internal architecture, general purpose instruction set and high speed, the ZR38650's core processor is also capable of executing many other types of algorithms for a wide variety of DSP applications. These algorithms can add differentiating product features to the basic audio decoding functions. With the ZR38650's state-of-the-art performance these additional features take little processing time or program memory. A high level of performance is made possible by the 32-bit wide instruction set which allows the device to perform a large number of concurrent operations. For example, in a single instruction cycle the following operations can be performed: * Fetch two source operands from registers, execute an arithmetic operation and store the result in a register. * Update two data address pointers * Perform two parallel data move operations * Generate the next program address * Fetch the next program instruction. Individual bit and immediate data instructions along with the ZR38650's four-level zero-overhead loop and repeat instructions, produce very compact code. Most instructions execute in a single cycle. The ZR38650 uses an internal clock rate of up to 100 MHz to achieve 50-million instructions per second (50-MIPS) performance. This allows accessing internal data memory twice per instruction cycle. An internal programmable phase-locked loop (PLL) multiplier/divider circuit permits any external crystal or input clock to be used (in the range of 12-50 MHz). The ZR38650's optimized 20-bit (120 dB) data precision make it particularly well suited for compact disk-quality audio applications including audio equalization, special effects and audio mixing where the 16-bit data precision of conventional fixedpoint DSPs is insufficient. Furthermore, by providing high performance support for block floating-point operations to extend dynamic range (including one cycle exponent detection and two cycle normalization), ZR38650-based systems are inherently more cost effective to implement than 24-bit precision fixedpoint DSPs which expand dynamic range solely via extended data precision. High performance block floating-point is due to the ZR38650's bi-directional barrel shifter, a feature unavailable on most conventional 16- and 24-bit fixed-point DSPs. To ease programming and increase speed, the ZR38650 architecture provides a general purpose data register file which can provide up to four source registers and two destination registers per instruction. A total of eight 20-bit data registers are provided, with two registers extended to 48-bits for use as accumulator registers with 8-bit overflow protection. The ZR38650 also provides a dual address generator and register file capable of generating two independent addresses per instruction cycle. The address generator supports modulo and bit-reversed addressing, in addition to a complete set of preand post-modify addressing modes. The ZR38650 has many built-in memory resources. A large 2k x 32-bit program/data RAM is available on-chip in additional to the mask programmable 20k x 32-bit ROM. The already large internal 10k x 20-bit data RAM along with program/data memory can be extended on the 32-bit external data bus and 20-bit memory address bus, with up to 1M words in a unified address space. Programmable wait-states accommodate lower-cost slow external memories and byte-wide configurations can be used for lower chip count if desired.
PROCESSOR FUNCTIONAL DESCRIPTION
Architectural Overview
Figure 12 shows the detailed functional units of the ZR38650 processor. The data path consists of the Arithmetic Unit, the portions of Memory used for data, and its associated Address Generation Unit. The control path is the Instruction Unit, the portions of Memory used for program, and its associated Program Sequence Unit. The remainder are the Input/Output Ports and the System Interface. Data flow between data path units is over the single 20-bit Data Bus with a corresponding 20-bit Data Address Bus. Control flow is over the single 32-bit Program Data Bus with a corresponding 20-bit Program Address Bus. These dual data and address buses are multiplexed to single external buses for external memories. This simple space-efficient bus structure maintains high performance as each internal bus makes two transfers per instruction cycle and each unit is self-contained with its own local memory. The high performance of the ZR38650 is apparent from the power of the data functional units with their attendant instructions and their being matched by the power of the control functional units and their instructions. Both are described in turn. Data and control paths are assured of working together in parallel because of the fast interconnecting bus structure and the wide-word instruction set controlling both. This view of the operation by function and instruction can confirm basic benchmark performance. In actual designs, the powerful assembler and simulator show the details of the pipelined operations and intermeshing of functions and transfers to assure balanced operation.
Arithmetic Unit
The arithmetic unit performs all data path operations in the processor, using a full-function ALU, a bi-directional barrel shifter and a 20 x 20-bit multiplier, all operating out of the multiport register file. The seven ports allow two transfers in or out of the
30
Instruction Unit 20 Program Address Bus 20 Addr Mux A0-7, I0-7, M0-7, SP 14 AALU 10 Data RAM 20 10k x 20 2k x 32 20k x 32 Program/Data RAM Program/Data ROM Data FIFO 8x9 9 Parallel Port 14 I Address Register File M 20 Program Counter 3 x 8 x 20 1 x 20 Increment 2 Mux 20 A Control 20 Memory Interface Control 4 Mux 20 Data Address Bus
Program Sequence Unit
Address Generation Unit
Memory
Repeat Count
Loop Count Stack
Compare
Instruction Register
Loop End Stack
32 Demux 20 32 32 Program Data Bus 32
20 Loop Start Stack
20
Reset & Intr. Intr. Mask
Parallel Port Host Control
12 Mux DBX 20 Data Bus 8 2 DS 48 20 20 Data Register File 2 x 48 6 x 20 D0-D1 D2-D7 48 20 Mux SPMODE 20 Status Adder MS Data Shifter 1 20 20 12 20 2 3 Inputs Outputs 18
32 Data
Shifter
Mux
ALU 48 Barrel Shifter 2 x 48 SD 48
Mux
31
42 48 Multiplier 20 x 20 CRCC PACKREG Arithmetic Unit
1
General Registers Aux. Registers
48
Control
Host
4
Serial Host I/F
48
SDA SDB SDC SDD SDE SDF SDG S/PDIF Transmitter
A Input B Output
Test
4
ICE I/F
Timer
48
INT RESET
External Interrupt Reset
SRA SRB SRC SRD SRE SRF SRG
C Output D Output Data E Input Serial Ports F Input G Output/ S/PDIF Output
Xtal
2
Oscillator, PLLs & Clocks
Clocks & Control
4
S/PDIF Receiver GPIOC[5:0] GPIO[5:0] Input/Output Ports
S/PDIF Input GPIO[5:0] General Purpose Ports
System Interface
ZR38650
Figure 12. ZR38650 Detailed Block Diagram
ZR38650
register file from memory in parallel with a three operand multiplier and ALU operation, including storing the result, every instruction cycle. In addition to the basic two's-complement arithmetic and logical operations, the 48-bit ALU also can find minimums and maximums, normalize, determine exponents for block floating-point, support multiple precisions and perform division primitives. A further refinement is a butterfly primitive that computes both a product sum and difference using an auxiliary adder. This fetching of four operands, doing a multiply, addition and subtraction and storing two results facilitates a very fast 4-cycle radix-2 FFT butterfly. ALU results set appropriate Status register bits in the System Interface, which has sticky bits for multiple precision and array computations. A large class of immediate data logical and arithmetic instructions free register space and reduce instruction count in the bit operations so common in communications coding applications. The multiplier provides both signed and unsigned operations with an optional one-bit left shift on the output determined by the MS bit in the Mode register. This shift for fractional number alignment preserves the maximum 42 bits of shifted products. The 48-bit barrel shifter does both logical and arithmetic shifts; the SD bit in the Mode register allows a positive shift operator to be interpreted as either a left or a right direction shift. A third Data Shifter provides arithmetic shifts, rounding and limiting when transferring data from the register file onto the Data Bus. The shifting range of 1 bit to the right through to 2 bits to the left is determined by the DS bits in the Mode register. Two of the eight registers of the register file (D0 & D1) are 48 bits, the remaining six are 20 bits and align as shown in Figure 13. In general all arithmetic unit operations are for implicit 20-bit operands with data being overflowed, limited, rounded or truncated accordingly for registers D2-D7. However when D0 or D1 are the source or destination, then the operations are such as to preserve the full 48-bit precision results in these registers. Likewise, transfers in and out of D0 & D1 with the data buses are extended or reduced based on their being 48-bit operands. These two registers usually serve as the high precision accumulators which are central to most signal processing algorithms. Any of the three fields can be explicitly addressed if the implicit operands are not the desired ones.
19 19 19 19 19 19 D1 47 D1H 40 39 D0 47 D0H 40 39 High D7 D6 D5 D4 D3 D2 D1M D0M Middle 0 0 0 0 0 0 20 19 20 19 D1L D0L Low 0 0
Address Generation Unit
Data operated on by the Arithmetic Unit is read from and restored to the Data Register File. Register file locations are directly addressed by register fields within the operate field of the instructions. For data transfers with the larger internal and external memories and registers, direct addressing can also be used, but indirect addressing by the Address Generation Unit is often faster and more program memory efficient. The Address Generator can sequentially produce two 20-bit addresses for the two bus transfers possible per cycle and post-modify the same two addresses in the same instruction cycle. The indirect addresses generated can be linearly incremented or decremented, indexed, bit-reverse indexed or circular with an arbitrary modulus M. This is done in the Address Generation Unit by the Address ALU (AALU) and the Address Register File which is organized as in Figure 14. The next address is produced in a postmodify operation using the appropriate sum of the address register Ax with index register Ix and a compare with modulus register Mx. The five addressing modes in their assembler notation are:
(ax) (ax)+ (ax)(ax)+i (ax)-i At the address in address register Ax with no postmodify operation With a postincrement by one With a postdecrement by one With a postincrement by the value in index register Ix With a postdecrement by the value in index register Ix
Note there is no indexing or circular addressing for the stack pointer SP. For M = Hex FFFFF the corresponding A register is incremented in a bit-reverse manner for doing the radix-2 FFT. For an N-point FFT the incrementing index register must be loaded with N/2. The Address Register File is accessible on the Data Bus and can be used for general purpose registers. Further, they can be loaded with immediate data from the Program Data Bus.
Program Counter 19 19 19 19 19 19 19 19 Stack Pointer A7 A6 A5 A4 A3 A2 A1 A0 Address 0 19 0 19 0 19 0 19 0 19 0 19 0 19 0 19 I7 I6 I5 I4 I3 I2 I1 I0 Index 0 19 0 19 0 19 0 19 0 19 0 19 0 19 0 19 M7 M6 M5 M4 M3 M2 M1 M0 Modulus 0 0 0 0 0 0 0 0
Figure 14. Data Register File
Memory
Internal
There are three internal on-chip memories, a 10k x 20-bit RAM, a 2k x 32-bit Program RAM and a 20k x 32-bit mask-program-
Figure 13. Data Register File
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ZR38650
mable ROM. The 20-bit wide RAM is used exclusively as data memory, it transfers on the Data Bus and is addressed only from the Data Address Bus. It is always located in lowest memory address space starting at Hex 00000 up to 027FF. The other RAM and the ROM are 32-bits wide and can be used for both data and program memory. They are addressable by both the Program and Data Address Buses and are sources, and the RAM a destination, for transfers on both Data and Program Data Buses. When the Program RAM is written to the most significant 12 bits are loaded at the same time from the Data Bus Extension (DBX) register. When the Program RAM is read as data the DBX register is loaded with the most significant 12 bits of data. The DBX register can also be loaded or read as a general register with data in the least significant 12 bits. The ROM is always at locations Hex E0000 to E4FFF in memory space on both Address Buses. The standard ZR38650 product has the ROM coded with the digital audio decoder functions and a bootstrap program for accepting commands from a host or loading an operating program into RAM from a byte-wide external ROM. Note that the external ROM data is on D[11-4]. The Program/Data RAM is always at locations Hex D0000 to D07FF in memory space on both Address Buses. It provides fast internal memory without the cost of a mask programmed internal ROM when the ZR38650 is used with an external byte-wide bootstrap ROM or host microcontroller. All internal memories have a single port, but consistent with the buses, all can perform two complete operations per instruction cycle. The memories can operate in parallel provided buses are available. Each internal address bus has its own address space, but since the internal memories do not overlap and external memories share a common address bus, all memories can be considered to be in one address space as shown in Figure 15.
D19 00000 10k x 20 Internal Data RAM 02800 40000 D11 D4 Bootstrap ROM 64k x 8 D11 D4 D0
External
Program/data memory is extended externally on the Parallel Port in the address spaces shown in Figure 15. Internal data buses are multiplexed into a single bus for external memory. Thus only one external data or instruction transfer can take place at a time. Also, only a single transfer can be made in each instruction cycle due to the slower external memories. This memory cycle-time can be lengthened by inserting wait-states to allow the use of lower-cost slow memories. The number of waitstates is determined by the CFG command so that external memory operations take one, three or seven instruction-cycletimes. The addresses shown are the internal 20-bit ones. The optional external bootstrap ROM is 8-bits wide and connected to D[11-4]. Various widths of memory can be used for external RAM or ROM as required. The choices are 8, 16 or 32 bits. Data must be left justified on the data bus.
Reset and Interrupt Memory Locations
The reset and interrupt vectors occupy a reserved block of memory of 64 (Hex 40) locations. As shown in Figure 15 these can be located at the lowest portion of the on-chip 20k x 32-bit ROM or 2k x 32-bit RAM, or in external memory. This is selected by the MMAP pin and the MM and PM bits in the Mode Register as follows:
Table 16: Reset and Interrupt Start Locations
MMAP Pin 0 0 1 X MM Bit 0 1 X X PM Bit 0 0 0 1 Reset & Interrupts Location A - Internal ROM B - External Memory B - External Memory C - Internal RAM Start Address (Hex) E0000 80000 80000 D0000
Program Sequence Unit
All processor operation is governed by the decoded instruction in the Instruction Register (IR). The control flow of the processor is the sequence of instructions that are presented to the IR. The Program Sequence Unit determines this flow by generating the program address to fetch instructions from program memory. This unit in the ZR38650 is a powerful address generator also, often producing a long sequence of operations with a minimum of program memory transfers. Examples of this are the RePeaT and LOOP instructions which allow repeated single and multiple instructions respectively with no instruction overhead. In addition to these instructions, major changes in the control flow are determined by the reset operation, interrupts, branches and subroutines to which the Program Sequence Unit responds.
4FFFF Memory Address (Hex) 80000
External Data Memory
Reset & Interrupts Location B 80040 D0000 Reset & Interrupts Location C D0040 2k x 32 Internal Program/Data RAM
D0800 E0000 Reset & Interrupts Location A E0040 Reserved for Decoder Functions E5000 20k x 32 Internal Program/Data ROM
Reset and Interrupt Operation
Operation of the processor starts with the system asserting the RESET pin. When RESET is asserted, the Mode Register is set to Hex 00038 and the Status register is set to Hex 00000. The serial port data registers are all cleared, as are the shift registers
Figure 15. Program/Data Memory Map
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ZR38650
Table 17: Reset and Interrupt Block Memory Map
Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 7 4 11 9 8 Priority 1 (highest) 2 3 10 5 6 Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C Interrupt Type Reset Service Routine ICE Interrupt Service Routine Breakpoint Interrupt Service Routine HREG Interrupt Service Routine INT External Interrupt Service Routine Serial Port Group A Service Routine Reserved Serial Port Group B Service Routine Reserved Serial Host Interrupt Service Routine Reserved Audio Receiver Error Interrupt Service Routine Data FIFO Interrupt Service Routine Timer Service Routine Reserved Jump to Software Interrupt Service Routine no yes yes yes yes yes Mask no no no yes yes yes
single RePeaT instruction. The Repeat Count (RC) register in the Program Sequence Unit allows up to 220 repeated operations. Likewise, the LOOP instruction allows zero overhead for repeating multiple instruction sequences. The Loop Count (LC), the Loop Start (LS) and the Loop End (LE) registers implement this instruction. Loops may be nested up to four deep with these registers automatically being pushed on their individual stacks. The RC, LC, LS and LE can be a source or destination for general register data transfers, with each transfer in or out of the LE register being the appropriate push or pop operation respectively for their stacks.
Subroutines and Stack Operations
An operational stack is maintained in data memory to service context switches caused by changes in control flow. Interrupts as well as the PUSH, POP and Jump SubRoutine instruction macros use the stack. The Stack Pointer (SP) in the Address Generation Unit determines the stack location, usually in the internal Data or Program/Data RAM for highest speed.
Instruction Unit
for the output serial ports, and the serial port shift register pointers are reset. The modulus registers and the loop end registers are cleared. The program counter is set to Hex E0000 before unconditionally jumping to the beginning of the Reset and Interrupt block (shown in Table 17) to start executing the reset service routine. The complete service routine may be read from an external bootstrap device and in turn, executed. Assertion of RESET does not affect the stack pointer, loop start register, loop and repeat count registers, address and index registers, internal RAM and the data registers. The 15 hardware interrupts and the software Interrupt, have their corresponding vector addresses and the priority shown in Table 17. The priority reflects only the order of servicing when more than one request is pending, and does not determine whether or not a currently executing interrupt service routine will itself be interrupted. All interrupts are collectively disabled with the IE bit and individually enabled with their own mask bits in the auxiliary Interrupt Mask Register (IMR). Before an interrupt service routine is executed, the processor clears the IE bit to disable further interrupts and then pushes the return address and Status register contents on to the stack.
Pipeline
Each instruction is fetched from program memory (either internal RAM or ROM), decoded in the Instruction register and finally executed. This three stage instruction pipeline takes a minimum of three instruction cycles, but is generally transparent to the user. The delayed branch instructions, however clearly exhibit this pipeline's delay. The pipeline is extended, in effect, whenever there is a requirement for multiple simultaneous accesses to a particular memory resource that cannot be resolved in a single cycle. This occurs, for example, when an instruction fetch and a dual data move all require access to the internal Program/Data RAM or ROM.
Instruction Set
Each of the instructions of the ZR38650 is a single word in length and except for program flow control instructions, all generally execute in a single cycle unless multiple external memory accesses are required. Much of the power of the processor lies in the parallel operations that go on within one instruction. Instructions are named for the dominant operation that executes, usually an Arithmetic Unit operation or a Program Sequence Unit operation. The instruction set names are summarized in Table 18 by the functional unit. Also listed are the instruction macros which the assembler generates from the basic instructions.
RePeaT and LOOP Instructions
The RePeaT instruction allows the single instruction that follows it to be repeated with no instruction overhead beyond the initial
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ZR38650
Table 18: Instruction Set Summary
Instructions
Arithmetic Unit Address Generati on Unit Program Sequence Unit
Table 19: Instruction Class Summary Table
I. Single operand ALU operations with parallel transfer operations
Class Code Opcode Operand Parallel Opcode Parallel Operands
Arithmetic
Logic
Multiplier
ABS ADD, ADDI ASHift, ASHI CMP, CMPI CMPA CMPZ DIVS DIVU MOVEMAX MOVEMIN NEG NORM NORMMAX SUB
AND, ANDI DEC INC LSHift, LSHI OR, ORI XOR, XORI NOP CLRBit SETBit TSTBit
BFY MADD MNEG MSUB MUL, MULI MULSU MULUU
MOVE
Delayed Branch Conditional DB Jump to SW Interrupt LOOP RePeaT
II. Two operand ALU operations with parallel transfer operations
Class Opcode Operands Parallel Opcode Parallel Operands
III. Three operand ALU operations with parallel transfer operations
Opcode Operands Parallel Opcode Parallel Operands
IV. Load/Store direct
Class Code Register Address
V. Load Immediate
Class Code Register Data
VI. Conditional delayed branch
Class Code Condition Code Address
VII. Repeat immediate
Class Code Data
MACROS
VIII. Software jump to interrupt immediate POP PUSH DO Jump Conditional JuMP
unconditional
Class Code Interrupt #
CLeaR
For parallel transfer operations there are the following six subclasses:
i ii iii iv v vi Register-to-register transfers, single Load register immediate (6-bits), single Register-to-memory transfers, single Memory-to-register transfers, single Address modify, single and dual Single and dual transfers including memory-to-memory (through a register) and with optional address modify.
Jump SubRoutine ReTurn Interrupt ReTurn Subroutine
The instructions divide into eight classes or bit-pattern formats summarized in Table 19. It is here that the full power of the ZR38650 is most evident. The first three classes provide the full function of the Arithmetic Unit with its operate fields (Opcode and Operand), but also simultaneous parallel operations. The parallel operate fields (Parallel Opcode and Parallel Operand) specify single and double, direct and indirect transfers with the sources and destinations along with address generation modify operations. The Bit instructions are also parallel operations. The last five classes of instructions are for the large-field direct data transfers and program control. For classes IV and V the possible source or destination register is a General Register. For parallel operations, the possible source and destination registers include the Auxiliary Registers as well as the General Registers.
with the most powerful being the last which can do the following four types of sequential dual transfers:
First transfer Data register to memory Data register to memory Memory to data register Memory to data register Second transfer Data register to memory Memory to data register Data register to memory Memory to data register
All memory references in this subclass are indirect and with possible address modification.
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ZR38650
Input/Output Ports
Connections to external memory and peripherals are made through the input/output ports. There is a single 32-bit parallel data port, eight serial data ports and six single-bit general purpose I/O ports (GPIO). These last can be configured by the user as outputs or inputs.
Serial DAC and ADC Ports
The serial ports are flexible on the ZR38650 to serve a wide variety of applications and peripheral devices. The three ADC inputs and four DAC outputs may be variously grouped to share two sets of common control signals, each being a master or a slave. Other selections are word or frame synchronization, frame size and either 16, 18, 20 or 24-bit word transfers. A master clock output which can be generated internally and two group programmable rate clocks. The I2S format, the frame-less time-division-multiplex (TDM) format and the LSB justified frame of the EIAJ format are all supported. Ports A, E, F are always ADC data inputs, while B, C, D are always DAC data outputs. Port G can be a DAC data output or the S/PDIF transmitter output. The ports may be configured in two groups with shared clocking: all inputs and all outputs, or as two groups with one of the inputs in the outputs group. This selection is made by the AB bit in the Mode register. The B group is unique in that when operating as a source to DACs, its clock outputs can also be derived from an externally supplied master clock input (SCKIN). Transfers are on the positive- or negative-going edge of the bitrate clocks (SCKA and SCKB) with the most significant bit being shifted first into or out of the double buffered shift registers. Word boundaries are signaled by a single-bit-duration frame signal (FSA and FSB) for each word or an alternating word signal (WSA and WSB) indicating left or right channel, even or odd word. The signal type is selected independently for each group as is the word length of 16, 18, 20 or 24 bits and the frame size of 16 to 256 bits per frame. The Word Select bits in the Status register reflect when the left or right channel is being transferred for each group. The WS/FS signals maybe advanced by one or more bit intervals for the non-I2S format. Completed frame transfers for each group are indicated to the processor by a vectored interrupt when individually enabled. An exception is for TDM where there is an interrupt for each word within a frame. Each group can be a source or a slave as selected in the auxiliary Serial Port Mode register. When a source, the clock rates are independently programmable sub-multiples of the internally generated master clock. The B group clocks can come from the external master clock input (SCKIN) as well. If this input is not used the pin may be selected as an output for the internally generated master clock.
Parallel Port
The ZR38650 parallel port works in two separate modes which are selected by the pin P/M at RESET. It can work as a data parallel port which is used to load data, instructions and programs to the chip and read status and other information from the chip, or it may work as an external memory interface. The external memory interface consists of the 20-bit address bus A[19:0], the 32-bit bi-directional data bus D[31:0], and the control signals CS, RD and WR. The data parallel port interface consists of the 8-bit bi-directional data bus PP[7:0], and the control signals CS, RD, WR, ERR, C/D, RDY. The RDY, C/D, and ERR signals are D[14:12] and PP[7:0] are D[11:4] also. When controlling the external memory interface (P/M = 0), CS is asserted low whenever there is an access to external memory. RD is asserted during an external read cycle, and can be used as an output enable for memory. WR is asserted during an external write cycle and can be used as a write enable for memory. The ZR38650 can generate wait-states for use with slow external memory using the WAIT field of the CFG command. In access cycles with wait-states, the timing relationship of the transitions of the memory interface signals remain the same as in a zero-wait cycle, but all are stretched by the specified number of instruction clock periods (1, 3 or 7). During an instruction cycle in which there is no external data access, the RD and WR signals are not active. However, the address bus continues to be driven with the internal instruction fetch address. When the parallel I/O interface is selected (P/M = 1), an internal FIFO is used to enable the host to write data in long bursts. The RDY output signal indicate when the FIFO is ready to receive more data (RDY = 1) or when the FIFO is almost full and not ready to accept data (RDY = 0). The ERR signal is an input to indicate for each data byte received if there is an error in the data. The C/D input signal distinguishes between input data and instructions or status which use the HREGIN/HREGOUT registers. When C/D = 1 transfers are a host command or reply status and therefore are written to the HREGIN register or read from the HREGOUT register. When C/D = 0 then all data from the host is written to the internal FIFO. CS, RD and WR are always inputs when P/M = 1. When RESET is asserted, the address and data buses and control signals CS, RD and WR are all set to a high-impedance state.
S/PDIF Serial Ports
The SPFRX signal is the single-wire input to the S/PDIF digital audio receiver. In use, the Audio PLL locks on the incoming SPFRX bitstream to determine the audio master clock SCKIN and to recover the digital input data. The serial output Port G is the single-wire S/PDIF digital audio transmitter output when not used as a DAC data output. Its SDG/SPFTX signal is used to output S/PDIF encoded data for decoding in other peripheral devices.
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ZR38650
Table 20: ADC and DAC Serial Ports Function Summary
Function Grouping: AB = 0 Grouping: AB = 1 Word size Frame size (bits/frame) Synchronization Source and slave clocking modes Latching on rising or falling edge of clock Transmitting data on rising or falling edge of clock External master clock input Internal master clock output Internal clock scaler I2S format TDM format Left/Right justified formats A Group 3 Inputs (A, E, F) 2 Inputs (A, E) 16, 18, 20, 24 bits 16, 24, 32, 64, 128, 192, 193, 256 Word or Frame Yes Yes Yes No Yes 12-bit Counter Yes Yes Yes B Group 4 Outputs (B, C, D, G) 1 Input (F), 4 Outputs (B, C, D, G) 16, 18, 20, 24 bits 16, 24, 32, 64, 128, 192, 193, 256 Word or Frame Yes Yes (when port F belongs to Port group B) Yes Yes Yes 12-bit Counter Yes Yes Yes
General Purpose Ports
Six single-bit general purpose ports may be individually selected as an input or output in the GPIOC auxiliary register. If config-
ured as an input, its sampled state may be read in the GPIO general register, or if an output, its state may be set by writing to the GPIO register.
System Interface
The system interface consists of all external signal functions other than Input/Output Ports plus the general and auxiliary registers which are associated with functional units and I/O operation.
Table 21: The General Registers (Continued)
Name RC LC LS LE STATUS MODE PC SP Z SRA SRB SRC SRD PACKREG DBX DS IE SRE SRF GPIO WAIT Bits 20 20 20 20 20 20 20 20 20 20 20 20 20 20 12 2 1 20 20 6 2 Description Repeat Count Register Loop Count Register. Stack of four. Loop Start Register. Stack of four. Loop End Register. Stack of four. Status Register Mode Register Program Counter Stack Pointer Z Register for JSR and JSRQ Serial Port A Data Register Serial Port B Data Register Serial Port C Data Register Serial Port D Data Register Pack Register Data Bus Extension Register Data Shifter Interrupt Enable Serial Port E Data Register Serial Port F Data Register General Purpose I/O Data Register External Memory Wait-states
General Registers
In addition to the primary data flow and control flow of instructions between functional units on the two data buses, there is the secondary control flow between the general and auxiliary registers for initialization and maintenance of operation. The following general registers are all directly addressable on the Data Bus for register-to-register, memory-to-register or register-to-memory parallel transfers.
Table 21: The General Registers
Name D0-7 A0-1 M0-7 I0-7 D0L D0M D0H SRG_SPF D1L D1M D1H Bits 48 20 20 20 20 20 8 20 20 20 8 Description Data Registers 0-7 Address Registers 0-7 Modulus Registers 0-7 Index Registers 0-7 Data Register 0 Low Data Register 0 Middle Data Register 0 High S/PDIF Transmitter Data Register Data Register 1 Low Data Register 1 Middle Data Register 1 High
Some of the more important General Registers are described next in detail.
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ZR38650
Mode Register
The Mode register is a source or destination register containing 18 fields that define the basic processor configuration. They tend to be set once at initialization and not change. The interrupt enable (IE), the wait-state selection (WAIT), and the register file data shifter (DS) bits that may change during processing are also individually addressable as registers. The IE, IM, AM and BM bits are also accessible in the Interrupt Mask Register (IMR). The Mode register is defined as shown below.
19
18 IM
17 AM
16 BM
15 0
14 0
13 PM
12 CRCR
11 WFA
10 WBA
9 AB
8 AW
7 BW
6 MM
5 WAIT
4
3 MS
2 DS
1
0 SD
MODE
IE
IE IM AM BM PM CRCR WFA WFB AB AW BW MM WAIT MS DS SD
Interrupt Enable when set enables all unmasked interrupts. When cleared, disables all interrupts. INT Mask when set enables the external interrupt input. A Mask when set enables the A Group serial ports interrupt. B Mask when set enables the B Group serial ports interrupt. Program Memory selection. When set the Reset and Interrupt Block is located in internal RAM. CRC Reset register flag. A transition from `0' to `1' of this flag resets the CRCC register to zero in the next cycle. Cleared at RESET. Word/Frame A group serial port synchronization mode bit. Word synchronization when set, Frame synchronization when cleared. Word/Frame B group serial port synchronization mode bit. Word synchronization when set, Frame synchronization when cleared. A/B groupings of serial ports. When set, A Group is ports A, E and B Group is ports B, C, D, F, G. When cleared, A group is port A, E, F and B Group is ports B, C, D & G. A Word precision. Together with the AW1 bit in the SPMODE register defines the precision of group A data words. For [AW,AW1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. B Word precision. Together with the BW1 bit in the SPMODE register defines the precision of group B data words. For [BW,BW1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. Memory Map. Together with the MMAP pin and PM bit determine the Reset and Interrupt Block start location. Cleared at RESET. Wait-state selection for external memory. 0 = No wait-states, 1 = One wait-state, 2 = Three wait-states, 3 = Seven wait-states (a total of eight instruction cycles for an external memory operation). Multiplier Shifter. When set specifies 1-bit left arithmetic shift on multiplier output, when cleared there is no shifting. Data Shifter on transfers from the Data Register File to memory. 00 = No shift, 01 = Left shift by one, 10 = Left shift by two, 11 = Right shift by one. Shift Direction on the barrel shifter. When cleared a positive shift code corresponds to a left shift, when set a positive shift code corresponds to a right shift.
Status Register
The Status register is a source or destination register containing fields that reflect the state of the processor following each instruction cycle. They affect the conditional program control of the processor. The least significant 8 bits reflect arithmetic and
19 18 0 17 0
logical operation results from the ALU, multiplier, barrel shifter or on transfers that involve scaling or limiting. The other eight involve word identification on the serial and host ports, status of the PLLs and configuration of the chip. The Status Register is defined below.
16
0
15
PLOCKA
14
P/M
13 SIE
12 PLOCKD
11 0
10 HWR
9 WSA
8 WSB
7 Q
6 SS
5 SL
4 SV
3 V
2 C
1 N
0 Z
STATUS
0
PLOCKA P/M SIE PLOCKD HWR
Audio PLL Lock Status. Setting RSTAUD resets the audio PLL. This clears PLOCKA indicating that the audio PLL is not locked. When the audio PLL is locked on the acquired frequency it sets PLOCKA again. Read only. Parallel port/Memory status. The P/M status flag reflects this pin's state at RESET indicating whether the parallel port is configured for parallel I/O or memory. Read only. Store Interrupt Enable status Flag. This flag stores the IE value in the mode register upon entering an interrupt processing sequence, simultaneously with resetting IE flag. Read only. DSP PLL Lock Status. Setting RSTDSP resets the DSP PLL This clears PLOCKD indicating that the PLL is not locked. When the DSP PLL is locked on the acquired frequency it sets PLOCKD again. Read only. Host Write indicated the host interrupt is due to a write operation to the Host register. Read only.
38
ZR38650
WSA WSB Q SS SL SV V C N Z Word Select A bit indicates Left channel data is being input if cleared or Right channel data if set, on the A Group serial ports. Word Select B bit indicates Left channel data is being output if cleared or Right channel data if set, on the B Group serial ports. Quotient bit is used with the divide iteration instructions. Sticky Scaling bit is set if any data transferred through the Data Shifter has a magnitude of greater than 0.25. A typical use is to indicate the potential for overflow in the next pass of an FFT. It is cleared by a RESET or by an explicit instruction to clear it. Sticky Limiting bit is set whenever limiting takes place in the Arithmetic Unit or during a data transfer through the Data Shifter. It is cleared by a RESET or by an explicit instruction to clear it. Sticky Overflow bit is set whenever the Overflow bit is set except for the compare instructions. It is cleared by a RESET or by an explicit instruction to clear it. Overflow bit is set if an overflow results from any operation in the Arithmetic Unit. Overflow is determined if any number can not be properly represented in its destination register. Carry bit is set if a carry results from an addition or a borrow results from a subtraction in the ALU, or results from shifts in the barrel shifter of the Arithmetic Unit. Negative bit is set if the most significant bit of the destination register is set, otherwise it is cleared. Zero bit is set if the entire result of an Arithmetic Unit operation in its destination register is zero.
DBX Register
The data bus extension register (DBX) is a 12-bit register that permits full use of the 32-bit internal memories for data. When reading data from 32-bit wide internal memory to a 20-bit register, the least significant 20 bits are loaded into the destination register. The most significant 12 bits are loaded into the DBX
register. When writing data from a 20-bit register to the 32-bit internal RAM, the least significant 20 bits are driven by the specified source register, while the most significant 12 bits are driven by the DBX register. When the DBX is specified as the destination or source in a transfer, the least significant 12 bits are read into or loaded from the DBX.
Auxiliary Registers
In addition to the primary data flow and control flow of instructions between functional units on the two data buses, there is the secondary control flow with the general and auxiliary registers for initialization and maintenance operations. The auxiliary registers are accessed by register-to-register parallel transfers only.
Table 22: The Auxiliary Registers (Continued)
Name SPIRX/SCRX SPIMODE/SCMODE SPISTAT/SC STAT SPDEL SPFAUD SPFSTT SPFCHS DSPDM AUDD ICR IDR TESTMODE SPRXDAT SPRXAUX SPRXCHS SPRXSTT SPRXMODE CRCC CLKMODE DFIFO DFFCNT TIMER Z2CADR Bits 8 2 7 12 7 1 20 14 13 13 20 12 20 6 20 8 4 16 7 20 20 18 7 Description Serial host Interface Receive register, SPI/Z2C (RO) Serial host Interface Mode register, SPI/Z2C Serial host Interface Status register, SPI or Z2C (RO) Serial port bit Delay A and B S/PDIF transmitter auxiliary Audio register S/PDIF Transmitter Status register (RO) S/PDIF transmitter Channel Status register DSP PLL Divide/Multiply register Audio PLL Divide register ICE Command Register (RO) ICE Data Register (RO) Test Mode data register S/PDIF Receiver Data register (RO) S/PDIF Receiver Auxiliary register (RO) S/PDIF Receiver Channel Status (RO) S/PDIF Receiver Status register (RO) S/PDIF Receiver Mode register Cyclic Redundancy Check Code register Clock Mode register. Parallel port Data FIFO register (RO) Parallel port Data FIFO counter (RO) Timer register Z2C Address
Table 22: The Auxiliary Registers
Name HREGOUT HREGIN ISR IRR BKP1 BKP2 BKP3 BCT1 BCT2 BCR BSR IMR GPIOC SPMODE AUDM SPAS SPBS SPITX/SCTX Bits 8 8 1 20 20 20 20 20 20 4 3 20 6 20 13 12 12 8 Description Host Register Output Host Register Input (RO) ICE host Status Register ICE host Response Register Instruction address Breakpoint register 1 Instruction address Breakpoint register 2 Data address Breakpoint register 3 Breakpoint 1 Counter Breakpoint 2 Counter Breakpoint Control Register Breakpoint Status Register Interrupt Mask Register General Purpose I/O Control register Serial Ports Mode register Audio PLL Multiply register Serial Ports A group Scaler register Serial Ports B group Scaler register Serial host Interface Transmit register, SPI/Z2C
39
ZR38650
One of the more generally important Auxiliary Registers is described next in detail.
Serial Ports Mode Register
The Serial Ports Mode register is an auxiliary source or destination register containing fields that determine the serial ports operation and configuration. The fields are defined below.
SPMODE
19
SPFEN
18 0
17 0
16 0
15 0
14 BW1
13 AW1
12 CB
11 MB
10 MA
9 TB
8 TA
7 CPB
6 CPA
5
4 FRB
3
2
1 FRA
0
SPFEN BW1 AW1 CB MB MA TB TA CPB CPA FRB FRA
S/PDIF Output Enable. Setting SPFEN enables Port G as the S/PDIF output. Clearing it makes Port G serial I/O. B Word precision. Together with the BW bit in the MODE register defines the precision of group B data words. For [BW,BW1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. A Word precision. Together with the AW bit in the MODE register defines the precision of group A data words. For [AW,AW1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. Clock B source. Selects the group B clock source. Setting CB selects the Audio PLL and SCKIN is an output. Clearing CB selects SCKIN as the group B clock. Master B. Setting MB makes group B outputs masters with SCKB an output. Clearing MB makes group B slaves with SCKB an input. Master A. Setting MA makes group A inputs masters with SCKA an output. Clearing MA makes group A slaves with SCKA an input. TDM B. Setting TB selects TDM (Time Division Multiplexing) mode for group B outputs with a frame size determined by the FRB field. Clearing TB disables the TDM mode. TDM A. Setting TA selects TDM (Time Division Multiplexing) mode for group A inputs with a frame size determined by the FRA field. Clearing TA disables the TDM mode. Clock Polarity B determines the group B serial outputs clock polarity. When CPB is set, data is output with the rising edge of the clock. When CPB is cleared, data is output with the falling edge of the clock. Clock Polarity A determines the group A serial inputs clock polarity. When CPA is set, data is input on the falling edge of the clock. When CPA is cleared, data is input on the rising edge of the clock. Frame B size. Determines the frame size of the group B serial output ports in master mode: 0 = 16 bits, 1 = 32 bits, 2 = 64 bits, 3 = 128 bits, 4 = 192 bits, 5 = 256 bits, 6 = 193 bits, 7 = 24 bits. Frame A size. Determines the frame size of the group A serial input ports in master mode: 0 = 16 bits, 1 = 32 bits, 2 = 64 bits, 3 = 128 bits, 4 = 192 bits, 5 = 256 bits, 6 = 193 bits, 7 = 24 bits.
Timer
The ZR38650 timer is an 18-bit programmable counter auxiliary register. Once loaded, it counts down at the instruction cycle rate of fCLKOUT or fDSP/2. At a count of one it issues an interrupt and reloads to continue counting the next interval. interface signals are data input (SI), data output or slave data (SO/SDA), serial clock input (SCK/SCL) and slave select (SS), where SDA and SCL are for the two-wire Z2C interface. Four auxiliary registers receive data (SPIRX/SCRX), transmit data (SPITX/SCTX), govern operation (SPIMODE/SCMODE) and provide control flags (SPISTAT/SCSTAT) for the interrupt driven operation with the two protocols. An additional auxiliary register Z2CADR holds the seven-bit Z2C address determined at Reset from the SI, SS, SDD and SDC pins for Z2CADR[5,4,1,0] respectively. Z2CADR[6,3,2] are always zero. In SPI operation, transfers are full-duplex with a single byte transmitted to the host for every byte received. The polarity of the SCK clock is defined by the SCKP bit in the SPIMODE register which is determined by the state of SDG/SPFTX pin at Reset. When SCKP = 1 the output data on the SO signal changes after the falling edge of SCK and the input data on the SI line is sampled on the rising edge of SCK. When SCKP = 0 the output data on SO line changes after the rising edge of SCK and input data on the SI line is sampled on the falling edge of SCK. When SS is not asserted, the SCK line should be at the high level if SCKP = 1 and at the low level if SCKP = 0. The
Serial Host Interface
The serial host interface provides a low-cost, low-bandwidth interface to a host processor for down-loading RAM programs and basic operating commands. The ZR38650 always operates as a slave and transfers are internal program interrupt driven. There are the two industry standard signals and protocols supported, SPI (Serial Peripheral Interface) and Z2C (Zoran Two Conductor interface). Transfers are bit-serial with parallel eightbit data registers. The standard function ROM can accept commands or down-load RAM program through the serial host interface if it does not find an external byte-wide EPROM at Reset time. The serial host signals and protocol are determined by SPI/Z2C, the state of the SDB pin at Reset. SPI/Z2C = 0 for Z2C if SDB is tied to a pull-down resistor. SPI/Z2C = 1 for SPI if SDB relies on the internal pull-up resistor or uses an external one. The shared
40
ZR38650
SCKP bit in the SPIMODE register is set at Reset if the SDG/SPFTX pin is tied to a pull-up resistor, or cleared if the pin is pulled down. In Z2C operation, byte transfers are half-duplex with the ZR38650 either a slave-receiver or slave-transmitter. Figure 16 shows a normal read operation by the host master. Normal operation is in the alternating single-byte transmit/receive protocol, but the transmit-only protocol can be used to speed program downloading. The 400 kbit/second fast mode transfer rate is supported as well as standard mode of 100 kbit/second.
SDA
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
R
ACK
MSB
LSB
ACK
SCL
Start
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Stop ZR38650 is Slave Receiver (SR) ST ZR38650 is Slave Transmitter (ST) SR SR
Figure 16. A Z2C Host Interface Read Operation by a Master Host
In Circuit Emulation Interface
The ZR38650's In Circuit Emulation (ICE) capability for both hardware and software debugging is provided through four test pins (TDI, TDO, TCK, TMS) using a standard JTAG interface. This interface is serviced by routines in the on-chip Program/Data ROM and the highest priority interrupt. This provides register and memory read and set commands for hardware debugging. Three breakpoint address-detection registers and two count registers with interrupt additionally provide for realtime program debugging capability in the ICE.
be supplied: PLLTAB, PLLCFG, CFG, AC-3 (if AC-3 mode is required) UNMUTE. The states of pins after reset that are tri-state or can be either input or output are given in Table 23.
External Interrupts
The external interrupt input signal INT is edge-sensitive and must remain asserted for two clock cycles to set the internal INT flag. This flag is cleared as the interrupt service routine starts so that any new interrupt condition must allow INT to go high and then low again for another interrupt to be generated.
Reset and Initialization
The processor can be reset only by asserting the RESET signal input pin externally. On the initial power-up it must be asserted for a minimum of 160 clock cycles with proper supply voltage operating conditions. Operation starts 16 cycles after the rising edge. After power-up, any reset must be asserted for at least 16 clock cycles but less than 128 clock cycles if there is no need to reset the PLLs. If the user wishes to reset the PLLs the reset signal must be active for at least 160 clock cycles. Operation starts 16 cycles after the rising edge at the selected reset service routine location in memory. The processor will not, however, accept a serial host command and return a response until 200 instruction cycles have elapsed. In order for the decoder to operate correctly, the following sequence of commands should
Oscillator and Clock Inputs
The XTI and XTO signals jointly supply the oscillator clock fXTI either as an input from a TTL system clock or as the crystal connection to enable the internal oscillator. The maximum frequency fXTI is 40 MHz and the minimum is 4 MHz. An internal phase-locked-loop (PLL) generates from this a DSP core clock fDSP. This internal DSP clock can be in the range of 4-100 MHz. (For low fDSP frequencies, care should be taken because the SPI data rate is slowed down proportionally). After RESET but before PLL lock, fDSP = fXTI. The external clock is applied to XTI, while the external crystal connection is as shown in Figure 17. A parallel-resonant fundamental-mode crystal should be used with two 20-pF capacitors.
41
ZR38650
Signal Description Summary
Table 23 summarizes information about all pins on the ZR38650. During reset all T type pins are tri-state and I/O pins are inputs. Pin states immediately after reset are shown in the Reset State column. All unused input pins should be connected to VDD if active low, or GND if active high unless internally pulled low. Unused tri-state pins should be resistively pulled-up to VDD. Unused outputs should be left unconnected. Internal pull-downs are 50 A maximum current sinks and pullups are 50 A maximum current sources, both are connected only when configured as an input. The pull-downs on D[31:15] and D[3:0] are connected only when P/M = 1.
Table 23: ZR38650 Signal Description Summary
Signal Name Number of Pins Type [1] Reset State [1] Internally Pulled Parallel Port (56) A[19:0] D[31:15] D14/RDY D13/ C/D D12/ERR D[11:4]/PP[7:0] D[3:0] CS RD WR P/M 20 17 1 1 1 8 4 1 1 1 1 O/T I/O/T I/O/T or O I/O/T or I I/O/T or I I/O/T I/O/T I/O/T I/O/T I/O/T I O I I or O I I I I O or I O or I O or I I Down [2]
-
Description
Address bus of parallel port Data bus of parallel port when selected for external memory (P/M = 0) Data bus (P/M = 0) or Ready output signal of parallel port when selected for parallel I/O (P/M = 1) Data bus (P/M = 0) or Command/Data select input of parallel port when selected for parallel I/O (P/M = 1) Data bus (P/M = 0) or Error input signal of parallel port when selected for parallel I/O (P/M = 1) Data bus of parallel port when selected for external memory (P/M = 0) or Parallel Port I/O (P/M = 1) Data bus of parallel port when selected for external memory (P/M = 0) Chip Select output for external memory or Chip Select input for parallel I/O Read enable output for external memory or Read enable input for parallel I/O Write enable output for external memory or Write enable input for parallel I/O Parallel I/O or Memory select for parallel port. Determined at time of RESET. Serial Ports (13)
-
-
Down [2] Up Up Up -
SPFRX SDA SDE SDF WSA/FSA SCKA SDB SDC SDD SDG/SPFTX WSB/FSB SCKB SCKIN
1 1 1 1 1 1 1 1 1 1 1 1 1
I I I I I/O I/O O O O O I/O I/O I/O
I I I I I I O O O O I I I
Down Down Up Up Up Down Down -
S/PDIF Receiver input port Serial Data input. Port A. Serial Data input. Port E. Serial Data input. Port F. Word Select or Frame Synchronization for input ports. An output when a master, an input when a slave. Serial Clock for input ports. An output when a master, an input when a slave. Serial left and right Data output. Port B. Also, at RESET defines SPI/Z2C for host serial interface. Serial left and right surround Data output. Port C. Also, at RESET defines Z2CADR[0] of Z2C address. Serial center and sub-woofer Data output. Port D. Also, at RESET defines Z2CADR[1] of Z2C address. Serial Data output. Port G or S/PDIF Transmitter port. Also, at RESET defines the SCKP value. Word Select or Frame Synchronization for output ports. An output when a master, an input when a slave. Serial Clock for output ports. An output when a master, an input when a slave. Serial master Clock output or master clock Input for output ports
42
ZR38650
Table 23: ZR38650 Signal Description Summary (Continued)
Signal Name Number of Pins Type [1] Reset State [1] Internally Pulled General Purpose Ports (6) MUTE/GPIO5 GPIO4 GPIO3 GPIO2 ERROR/GPIO1 DREQ/GPIO0 1 1 1 1 1 1 I or I/O I/O I/O I/O I/O I/O I I I I I I Mute input signal or can be programmed as General Purpose Input/Output 5 Can be programmed as General Purpose Input/Output 4 Can be programmed as General Purpose Input/Output 3 Can be programmed as General Purpose Input/Output 2 Error output signal or can be programmed as General Purpose Input/Output 1 Data Request output signal or can be programmed as General Purpose Input/Output 0 Description
Serial Host Interface (4) SI SO/SDA SCK/SCL SS 1 1 1 1 I I/O/T I I I T I I Host Serial interface data Input. Also, at RESET defines Z2CADR[5] of Z2C address. SPI host Serial interface data Output or Serial Data for Z2C SPI host Serial interface Clock input or Slave Clock input for Z2C SPI host serial interface Slave Select input. Also, at RESET defines Z2CADR[4] of Z2C address. ICE Interface (4) TDI TDO TCK TMS 1 1 1 1 I O/T I I I T I I ICE Test interface Data Input ICE Test interface Data Output ICE Test interface Clock input ICE Test interface Mode Select System Interface (8) INT RESET MMAP XTI XTO CLKOUT BYPASS FLTCAP 1 1 1 1 1 1 1 1 I I I I O O I I I I I I O I Down External Interrupt request input Reset input to start operation in known state Determines location on Memory Map of reset and interrupt block External system clock Input or connection to external crystal, at frequency f XTI Output connection to external crystal Clock Output from the ZR38650 at frequency f DSP/2 Bypass internal DSP core PLL to use external system clock input on XTI External Filter Capacitor connection for PLL. A value of 47nF is recommended. Power (53) VDD VDDA GND GNDA nc 16 1 25 1 10 Power Power Power Power NC +3.3 volt power supply +3.3 volt power supply, Analog for PLL Power supply Ground Power supply Ground, Analog for PLL No connection Total (144)
1. O = Output, I = Input, T = Tri-state. 2. When P/M = 1.
43
ZR38650
TYPICAL CONFIGURATIONS
Stand Alone (No Host)
Figure 17 shows a ZR38650 in a typical stand-alone configuration without a host microprocessor but with various optional external memories. For the lowest cost, only a byte-wide ROM need be used for loading a developer-written program that governs the decoder operation. The standard ZR38650 has a Reset bootstrap loading routine in its internal ROM that reads the program/data from the external byte-wide ROM at the address location Hex 40000. The boot-strap recognizes the external ROM rather than waiting for commands from a host that does not exist in this configuration. An alternative is to use the optional 32-bit wide program/data ROM shown. With the MMAP pin pulled-up, reset execution will start directly from this external ROM at the address location Hex 8000 and can continue there with the developer-written program. The optional program/data RAM can be used in any configuration, including with hosts, for additional 32-bit directly executable program (with data) memory space. If needed only for data then this RAM may be only 16 or 24 bits wide. The compressed data stream is input through the internal S/PDIF receiver which also acts as a clock master for the output DACs. This master clock can be selected to be 256 x SR or 384 x SR. The internal clock divider on the ZR38650 generates the clocking for the three slave DACs that provide the sixchannel audio output. Note that the PLL capacitor connected to FLTCAP, and the bypass capacitors on VDDA, should all be mounted close to the ZR38650 package with short leads over the GNDA analog ground plane, using normal good design practice for high frequency mixed-signal circuits.
Byte-Wide Bootstrap ROM (Optional) D OE CS A
Program/Data RAM (Optional) D OE WR CS A
Program/Data ROM (Optional) D OE CS A
8
32
Address Decode
32
32 6 +3.3V GPIO VDD
27 47 F Tant. 0.1F
20
RD
WR CS
D[31:0] A[19:0] SDB Data L/R DCLK CLK Data L/R DCLK CLK Data L/R DCLK CLK DAC Left Right
VDDA GNDA
47 nF
SDC ZR38650
FLTCAP Optical To TTL S/PDIF Input SDD SPFRX WSB S 64 fS SCKB 256 fS SCKIN
f
DAC
Left Surround Right Surround
DAC
Center Subwoofer
GND
XTI
4-40 MHz
XTO
RESET
INT
XTAL
20 pF 20 pF
System Reset
System Interrupt
Figure 17. Typical ZR38650 Stand-Alone Configuration With External Memories
44
ZR38650
Serial Host And Serial Data
Figure 18 and Figure 19 show a ZR38650 in typical system configurations with a host controller. At Reset time the internal ROM bootstrap will check for the byte-wide external ROM. A resistive pull-up on any one data line D[11-4] assures that an external ROM will not be found. Not finding that, it will then expect to receive program commands from the host through the selected serial connection. Note the optional pull-up on SDB in Figure 18 to select the SPI and the pull-down for the Z2C in Figure 19. The resistive pull-ups/pull-downs on SI, SS, SDC and SDD in Figure 19 determine the ZR38650's Z2C address at Reset time.
+3.3V
VDD
MUTE
Host Microprocessor SO SI SCK SS VDD
VDD
27 47 F Tant. 0.1F
D11
GPIO5
SI
SO/ SCK/ SDA SCL
SS
SDB
Data L/R DCLK CLK Data L/R DCLK CLK
VDDA GNDA
47 nF
DAC
Left Right
SDC ZR38650
FLTCAP SDD SPFRX RS422 Receiver WSB
fS 64 fS
DAC
Left Surround Right Surround
GND
XTI
4-40 MHz
XTO
RESET
INT
SCKB 256 fS SCKIN
Data L/R DCLK CLK
DAC
Center Subwoofer
XTAL
20 pF 20 pF
System Reset
System Interrupt
Figure 18. ZR38650 Typical Configuration With The SPI Serial Interface To A Host Controller
Host Microprocessor SDA SCL +3.3V VDD MUTE
VDD
27 47 F Tant. 0.1F
D11
GPIO5
SI
SO/ SCK/ SDA SCL
SS
SDB
VDDA GNDA
47 nF
SDC ZR38650
FLTCAP SDD SPFRX RS422 Receiver WSB S 64 fS SCKB 256 fS SCKIN
f
GND
XTI
4-40 MHz
XTO
RESET
INT
Data L/R DCLK CLK Data L/R DCLK CLK Data L/R DCLK CLK
DAC
Left Right
DAC
Left Surround Right Surround
DAC
Center Subwoofer
XTAL
20 pF 20 pF
System Reset
System Interrupt
Figure 19. ZR38650 Typical Configuration With The Z2C Serial Interface To A Host Controller
45
ZR38650
Parallel Host And Parallel Data
Figure 20 shown the connections for using the parallel port as the interface to a host controller for both control with commands and for the parallel data stream input. The ZR38650 appears in the controller's address space as three registers: an 8-bit read/write command/response register, a 9-bit data input write-only register and as a 3-bit read-only flag register. The flag register permits getting error messages from the ZR38650 (ERROR) and the DREQ and RDY bits are for programmed transfers when the ZR38650 is respectively a master or slave on the input data stream. Or the RDY signal may be used directly for a hardware I/O transfer as shown when the ZR38650 is a slave.
Host Processor A D C
CS Address
VDD P/M
Address Decode
Command/Data Register
CS D13/ C/D RD WR
RD WR CS OE Data 3
ERROR DREQ RDY
ZR38650 ERROR/GPIO1 DREQ/GPIO0
Tri-State Buffer Flag Register
RDY Data Data 8
D14/RDY D12/ERR D[11:4]/PP[7:0]
Host Bus
Figure 20. ZR38650 Connections With Parallel Port Interface To Host For Commands And Data Input
46
ZR38650
PRODUCT SUPPORT
Documentation
This Data Sheet is a summary description of the ZR38650's functional operation and command and response operation as well as electrical, timing and physical specifications. The complete source of information on its physical function and programmed operation including instruction set is the "ZR38650 Users Hardware Manual". Also available are the "ZR38000 Family Simulator User's Manual" and the "ZR38000 Family Assembler/Linker User's Manual." The following Application Notes are currently available that contain additional design related information: * "Designing with the ZR38600 Audio Processor" * "Bass Redirection for the ZR38600 Audio Processor" * "Audio Source Type Detection for the ZR38600 Audio Processor". New Application Notes are added on a regular basis and are available from sales representatives. stream is fed to the board in S/PDIF format. Both optical and coaxial interfaces are supported. Decoding and operation functions are selected via push buttons and a large LCD display is provided for status information. The demonstration board is equipped with a PC interface for controlling operation with the standard function commands and responses and for loading of custom programs. An ICE interface is also available on the board.
Software Development Kit
Two software development tools provide all that is necessary to write, assemble, link, simulate, and debug programs in native ZR38001 code for the ZR38650. They run on a Pentium PC under Microsoft WindowsTM 95. The ZR38000 Family Assembler/Linker translates the assembly language code, including macros, to object code which can be linked with data files and other object code to generate a complete executable program file. The ZR38000 Family Simulator accurately executes the program file while permitting full displays of registers and memory along with single-step operation and breakpoints for debugging. Both are of modern design being highly interactive and with macro and symbolic naming support throughout. The ZR38650 is software compatible with Zoran's previous generation ZR38000 family devices.
Demonstration Board
The ZR38600 Demonstration Board is a stand-alone Dolby AC3 and MPEG audio decoder. The demonstration board is equipped with three high-quality, stereo 20-bit DACs and one stereo 20-bit ADC for microphone or line input. The input bit-
47
ZR38650
SPECIFICATIONS - ABSOLUTE MAXIMUM RATINGS
Storage Temperature...................................... -65 C to +150 C Supply Voltage to Ground Potential Continuous .......................................... -0.5 V to +4.5 V DC Voltage Applied to Outputs for High Impedance Output State............................ -0.5 V to +5.5 V DC Input Voltage .................................................. -0.5 V to 5.5 V DC Output Current, into Outputs (not to exceed 200mA total) .................................. 20 mA/output DC Input Current ...........................................-10 mA to +3.0 mA
NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
SPECIFICATIONS - OPERATING RANGE
Temperature ................................................... 0C TA +70 C Supply Voltage ......................................... 3.15 V VCC 3.45 V
SPECIFICATIONS - DC CHARACTERISTICS
Symbol VIL VIH VOL VOH ICC ILI IPUI IPDI ILO CIN CIO Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current Input Leakage Current Input Internal Pull-up Current Source Input Internal Pull-down Current Sink Output Leakage Current Input Capacitance I/O and Output Capacitance -- - -- - Min -0.5 2.0 - 2.4 - -Typ - - - - 300 -Max 0.8 5.5 0.4 - 350 +10 50 50 +10 10 10 Units V V V V mA A A A A pF pF IOL = 2 mA IOH = 0.4 mA fCLKOUT = 50 MHz, VCC = 3.45 V Test Conditions
2.4V
INPUT
0.45V
2.0V 1.5V 0.8V
DEVICE UNDER TEST
2.0V 1.5V 0.8V
OUTPUT
From Output Under Test
50 pF
Test Point
During AC testing, inputs are driven at 0.4 V and 2.4 V levels. Unless otherwise specified, switching times are measured from the 1.5 V level of DCLK to the 0.8 V or 2.0 V levels at the input/output.
Figure 21. AC Testing Input, Output
Figure 22. Normal AC Test Load
48
ZR38650
SPECIFICATIONS - AC CHARACTERISTICS
Memory Read (fCLKOUT = 50 MHz)
Parameter Output Timing 1 2 3 4 5 6 Input Timing 7 8 9 Read cycle duration Address hold from RD rising edge Address setup to RD falling edge RD pulse duration RD after RD recovery time WR after RD recovery time Data in hold from RD rising edge RD low to data valid Address stable, CS low to data valid Min 25 1 2 11 6 6 0 - - - 4 7 Max - - - - - Units ns ns ns ns ns ns ns ns ns
[1] [1] [1]
Notes
1. These specifications are for zero wait-state operation. For operation with wait states, add 1 or 7 external clock periods, as appropriate.
1 A 2 3 RD 8 9 D 7 4 5
6 WR
CS
Figure 23. Memory Read
49
ZR38650
Memory Write (fCLKOUT = 50 MHz)
Parameter (Output Timing) 10 11 12 13 14 15 16 17 18 19 20 21 Write cycle duration Address setup to WR falling edge WR pulse duration Address hold from WR rising edge Data out setup to WR rising edge Data out hold from WR rising edge WR low to data out enabled WR after WR recovery time RD after WR recovery time Data disable to RD after WR WR falling edge to data valid Address valid to WR rising edge 13 Min 25 2 11 1 6 1 3 6 6 4 Max - - - - - - - - - - 5 Units ns ns ns ns ns ns ns ns ns ns ns ns
[1] [1] [1]
Notes
1. These specifications are for zero wait-state operation. For operation with wait states, add 1 or 7 internal clock periods, as appropriate.
10 A 13 11 WR 12 17
21 20 16 D 19 18 RD 14 15
Figure 24. Memory Write
50
ZR38650
A-Group Serial Ports (Frame Sync Mode)
Parameter Input Timing 22 23 24 25 26 27 Output Timing 29 30 SCKA high duration SCKA low duration FSA setup time to SCKA falling edge FSA hold time from SCKA falling edge SDA, SDE, SDF setup time to SCKA falling edge SDA, SDE, SDF hold time from SCKA falling edge FSA output delay from SCKA rising edge SCKA period Min tCLKOUT tCLKOUT 15 15 15 15 - 8 tCLKOUT Max - - - - - - 25 4096 tCLKOUT Units ns ns ns ns ns ns ns ns Master Mode (MA = 1) Master Mode (MA = 1) Notes Slave Mode (MA = 0) Slave Mode (MA = 0) Slave Mode (MA = 0) Slave Mode (MA = 0)
30 22 SCKA 23
24 FSA Slave Mode
25
24
25
29 FSA Master Mode 26 SDA,SDE,SDF [1] 1. Mode AB = 0 27
29
Figure 25. A-Group Serial Ports (Frame Sync Mode)
51
ZR38650
A-Group Serial Ports (Word Select Mode)
Parameter Input Timing 22 23 31 32 33 36 Output Timing 30 73 SCKA high duration SCKA low duration WSA setup time to SCKA rising edge WSA hold time from SCKA rising edge SDA, SDE, SDF setup time to SCKA rising edge SDA, SDE, SDF hold time from SCKA rising edge SCKA period WSA output delay from SCKA falling edge Min tCLKOUT tCLKOUT 15 15 15 15 8 tCLKOUT - Max - - - - - - 4096 tCLKOUT 25 Units ns ns ns ns ns ns ns ns Master Mode (MA = 1) Master Mode (MA = 1) Notes Slave Mode (MA = 0) Slave Mode (MA = 0) Slave Mode (MA = 0) Slave Mode (MA = 0)
30 22 SCKA 23
31 WSA Slave Mode 73 WSA Master Mode 33 SDA, SDE, SDF (note 1) 1. Mode AB = 0 36
32
Figure 26. A-Group Serial Ports (Word Select Mode)
52
ZR38650
B-Group Serial Ports (Frame Sync Mode)
Parameter Input Timing 41 42 75 76 48 49 78 79 Output Timing 40 43 SCKIN low duration SCKIN high duration SCKB high duration SCKB low duration SDF setup time to SCKB falling edge SDF hold time from SCKB falling edge FSB setup time to SCKB falling edge FSB hold time from SCKB falling edge SCKIN period (tSCKIN) SCKB period Min tCLKOUT tCLKOUT tCLKOUT tCLKOUT 15 15 15 15 tCLKOUT tSCKIN tAUDIO 44 45 FSB delay from SCKB rising edge SDB, SDC delay from SCKB rising edge - - 8192 tSCKIN 8192 tAUDIO 25 25 Max - - - - - - - - Units ns ns ns ns ns ns ns ns ns ns ns ns ns CB = 0 CB = 0 Slave Mode (MB = 0) Slave Mode (MB = 0) Mode AB = 1, CPB = 1 Mode AB = 1, CPB = 1 Slave Mode (MB = 0), CPB = 1 Slave Mode (MB = 0), CPB = 1 CB = 1 Master Mode (MB = 1), CB = 0 Master Mode (MB = 1), CB = 1 Master Mode (MB = 1) Notes
40 42 SCKIN 43 75 SCKB 76 41
79 FSB Slave Mode 44 FSB Master Mode 45, 47 SDB,SDC,SDD,SDG (Note 1)
78 78
79
48 SDF (Note 2) 1. Mode AB = 0 2. Mode AB = 1
49
Figure 27. B-Group Serial Ports (Frame Sync Mode)
53
ZR38650
B-Group Serial Ports (Word Select Mode)
Parameter Input Timing 50 51 52 53 Output Timing 80 81 SDF setup time to SCKB rising edge SDF hold time from SCKB rising edge WSB setup to SCKB rising edge WSB hold from SCKB rising edge WSB delay from SCKB falling edge SDB, SDC, SDD delay from SCKB falling edge Min 15 15 15 15 - - Max - - - - 25 25 Units ns ns ns ns ns ns Notes Mode AB = 1 Mode AB= 1 Slave Mode (MB = 0) Slave Mode (MB = 0) Master Mode (MB = 1)
SCKB
52 WSB Slave Mode 80 WSB Master Mode 81 SDB, SDC, SDD, SDG (Note 1) 50 SDF (Note 2) 1. Mode AB = 0 2. Mode AB = 1 51
53
Figure 28. B-Group Serial Ports (Word Select Mode)
54
ZR38650
Parallel Host Interface Timing
Characteristics 99 100 101 102 103 104 105 106 107 108 109 110 RD, WR high time RD, WR low time RD, WR cycle time Data hold time from WR high Data setup time to WR high Data out delay from RD low CS setup to falling edge of RD, WR CS hold from rising edge of RD, WR CS low to CS low WR to RD, RD to WR timing Data hold time from rising edge of RD RDY delay time Min 2 tCLKOUT 2 tCLKOUT 3 tCLKOUT 3 11 - 0 1 30 60 16 2 tCLKOUT ns ns - - 30 Max Units ns ns ns ns ns ns ns ns ns Write cycle Read cycle Notes
105 CS
107
106
101 100 WR 101 99 RD 100 108 99
103 D[7:0], ERR, C/D (Write Cycle) 104 D[7:0] (Read Cycle) 109
102
110 RDY
Figure 29. Parallel Host Interface Timing
55
ZR38650
Z2C Serial Host Interface Timing
Parameter 201 202 203 204 205 206 207 208 209 210 211 SCL/SCK clock period SCL/SCK clock high duration SCL/SCK clock low duration START condition setup time START condition hold time Data setup time to SCL/SCK active edge Data hold time from SCL/SCK active edge Rise time of SCL/SCK and SDA/SO Fall time of SCL/SCK and SDA/SO STOP condition setup time Free time between STOP and START condition Min 2.5 0.6 1.3 0.6 0.6 100 0.0 - - 0.5 1.3 Max - - - - - - - 300 300 - - Units s s s s s ns ns ns ns s s Notes
SDA/SO 204 SCL/SCK 202 208 START 203 209 201 STOP START 205 206 207 210 211
Figure 30. Z2C Serial Host Interface Timing
56
ZR38650
SPI Serial Host Interface Timing
Parameter 111 112 113 114 115 116 117 118 119 SCK/SCL clock period SCK/SCL clock high duration SCK/SCL clock low duration SS setup time to first SCK/SCL edge SS hold time from last edge of SCK/SCL SI setup time to SCK/SCL active edge SI hold time from SCK/SCL active edge SS negation to data Hi-Z SO/SDA delay from SCK/SCL active edge Min 6 tCLKOUT 3 tCLKOUT 3 tCLKOUT 10 10 10 10 - - Max - - - - - - - 10 20 Units ns ns ns ns ns ns ns ns ns
[1]
Notes
1. SCK polarity is controlled by field SCKP of register SPIMODE. The polarity shown in Figure 31 corresponds to SCKP=0.
SS 111 114 SCK/SCL (SCKP=0) 119 SO/SDA 118 113 112 115
116 SI
117
Figure 31. SPI Serial Host Interface Timing
57
ZR38650
External Clocks
Parameter 56 57 58 55 XTI period (tXTI) XTI high duration XTI low duration CLKOUT period (tCLKOUT) Min 25 10 10 20 250 Max 250 Units ns ns ns ns Notes
56 57 XTI 58
55 CLKOUT
Figure 32. External Clocks
External Interrupt
Parameter 63 64 65 INT setup time INT hold time INT duration Min 6 5 2 tCLKOUT Max Units ns ns ns
[1] [1]
Notes
1. For testing only. Synchronous operation is not required.
CLKOUT 63 65 INT 64
Figure 33. External Interrupt
58
ZR38650
Reset Timing
Parameter 59 60 61 62 RESET duration, warm reset RESET duration, cold reset Memory bus enable after RESET rising edge, warm reset Memory bus disable after RESET falling edge Min 16 tXTI 200 tXTI tXTI +10 tXTI +10 2 tXTI +15 2 tXTI +15 Max 127 tXTI Units ns ns ns ns
[1]
Notes
1. Applies to the power-up sequence. The rising edge of RESET must occur after the crystal oscillator or external clock frequency and amplitude have stabilized. After the rising edge of a cold RESET, 4096 clock cycles are required for initialization of the internal phase locked loop, during which the processor is inactive. Any subsequent reset pulse of 128 clocks or longer is interpreted as a cold reset and will start a new initialization of the phase locked loop.
XTI
59, 60 RESET
62 CS
61
Figure 34. Warm/Cold Reset
59
ZR38650
ICE Interface Timing
Parameter 121 122 123 124 125 126 127 128 129 TCK clock period TCK clock high duration TCK clock low duration TDO negation to data Hi-Z TDO delay from falling edge of TCK TDI hold time from rising edge of TCK TDI setup time to rising edge of TCK TMS hold time from rising edge of TCK TMS setup time to rising edge of TCK Min 4 tCLKOUT 2 tCLKOUT 2 tCLKOUT - - 10 10 10 10 Max - - - 15 15 - - - - Units ns ns ns ns ns ns ns ns ns Notes
121 123 TCK 122
125 TDO
124
127 TDI
126
129 TMS
128
Figure 35. ICE Interface Timing
60
ZR38650
PINOUT INFORMATION
Table 24: 144-Pin TQFP Package Pin Assignment By Pin Number
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name GND nc GND SS TMS INT D26 D25 VDD D14/RDY GND A1 A2 A3 VDD D13/ C/D GPIO5 D12/ERR D24 A4 VDD GPIO4 GND A5 A6 D11/PP7 GPIO3 VDD A7 A8 D10/PP6 A9 A10 nc nc GND Pin # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name GND nc GND D23 D22 VDD A11 D9/PP5 D8/PP4 SO/SDA D21 VDD GND D20 GND A12 TDO A13 D7/PP3 D6/PP2 A14 GND VDD A15 D5/PP1 D4/PP0 VDD A16 RD WR CS D3 D2 GND nc GND Pin # 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name GND nc GND SDD VDD GPIO2 D1 GPIO1 D0 GPIO0 VDD GND BYPASS SPFRX P/M XTO XTI MMAP GND GND SCKIN VDD VDD GND GNDA FLTCAP VDDA GND CLKOUT D19 D18 A17 A18 A19 nc GND Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name GND nc nc SDC D31 D30 SDB D29 D28 VDD RESET SDA VDD SDE TCK SCK TDI SI GND SCKA WSA/FSA VDD SDF GND D27 WSB/FSB D17 SCKB D16 SDG/SPFTX D15 VDD A0 GND nc GND
61
ZR38650
Table 25: 144-Pin TQFP Package Pin Assignment By Alphabetical Signal Name
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 BYPASS CLKOUT CS D0 D1 D2 D3 D4/PP0 D5/PP1 D6/PP2 D7/PP3 D8/PP4 D9/PP5 D10/PP6 D11/PP7 D12/ERR Pin # 141 12 13 14 20 24 25 29 30 32 33 43 52 54 57 60 64 104 105 106 85 101 67 81 79 69 68 62 61 56 55 45 44 31 26 18 Pin Name D13/ C/D D14/RDY D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DREQ/GPIO0 ERROR/GPIO1 FLTCAP GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin # 16 10 139 137 135 103 102 50 47 41 40 19 8 7 133 117 116 114 113 82 80 98 1 3 11 23 36 37 39 49 51 58 70 72 73 75 Pin Name GND GND GND GND GND GND GND GND GND GND GND GNDA GPIO2 GPIO3 GPIO4 INT MMAP MUTE/GPIO5 nc nc nc nc nc nc nc nc nc nc P/M RD RESET SCK/SCL SCKA SCKB SCKIN SDA Pin # 84 91 92 96 100 108 109 127 132 142 144 97 78 27 22 6 90 17 2 34 35 38 71 74 107 110 111 143 87 65 119 124 128 136 93 120 Pin Name SDB SDC SDD SDE SDF SDG/SPFTX SI SO/SDA SPFRX SS TCK TDI TDO TMS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDA WR WSA/FSA WSB/FSB XTI XTO Pin # 115 112 76 122 131 138 126 46 86 4 123 125 53 5 9 15 21 28 42 48 59 63 77 83 94 95 118 121 130 140 99 66 129 134 89 88
62
ZR38650
Table 26: 144-Pin TQFP Package Pin Assignment By Functional Signal Name
Pin Name A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 SPFRX SDA SDE SDF MUTE/GPIO5 GPIO4 SI TDI INT RESET VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD nc nc nc Pin # 106 105 104 64 60 57 54 52 43 33 32 30 29 25 86 120 122 131 17 22 126 125 6 119 9 15 21 28 42 48 59 63 77 83 94 2 34 35 Pin Name A5 A4 A3 A2 A1 A0 D31 D30 D29 D28 D27 D26 D25 D24 WSA/FSA SCKA SDB SDC GPIO3 GPIO2 SO/SDA TDO MMAP XTI VDD VDD VDD VDD VDD VDDA GND GND GND GND GND nc nc nc Pin # Pin Name Parallel Port (56) 24 D23 20 14 13 12 141 113 114 116 117 133 7 8 19 D22 D21 D20 D19 D18 D17 D16 D15 D14/RDY D13/ C/D D12/ERR D11/PP7 D10/PP6 Pin # 40 41 47 50 102 103 135 137 139 10 16 18 26 31 76 138 134 136 80 82 124 123 88 101 37 39 49 51 58 70 72 73 75 84 91 107 110 111 nc 143 SS TMS BYPASS FLTCAP GND GND GND GND GND GND GND GND GND GNDA 4 5 85 98 92 96 100 108 109 127 132 142 144 97 Pin Name D9/PP5 D8/PP4 D7/PP3 D6/PP2 D5/PP1 D4/PP0 D3 D2 D1 D0 CS RD WR P/M SCKIN Pin # 44 45 55 56 61 62 68 69 79 81 67 65 66 87 93
Serial Ports (13) 129 SDD 128 115 112 27 78 SDG/SPFTX WSB/FSB SCKB ERROR/GPIO1 DREQ/GPIO0
General Purpose Ports (6)
Serial Host Interface (4) 46 SCK/SCL ICE Interface (4) 53 TCK System Interface (8) 90 XTO 89 CLKOUT Power (43) 95 118 121 130 140 99 1 3 11 23 GND GND GND GND GND GND GND GND GND GND
36 GND No Connection (10) 38 nc 71 74 nc nc
63
ZR38650
Pin 1 index mark, notched corner, or both
GND nc GND A0 VDD D15 SDG/SPFTX D16 SCKB D17 WSB/FSB D27 GND SDF VDD WSA/FSA SCKA GND SI TDI SCK TCK SDE VDD SDA RESET VDD D28 D29 SDB D30 D31 SDC nc nc GND
144
GND nc GND SS TMS INT D26 D25 VDD D14/RDY GND A1 A2 A3 VDD D13/ C/D GPIO5 D12/ERR D24 A4 VDD GPIO4 GND A5 A6 D11/PP7 GPIO3 VDD A7 A8 D10/PP6 A9 A10 nc nc GND
109 108
GND nc A19 A18 A17 D18 D19 CLKOUT GND VDDA FLTCAP GNDA GND VDD VDD SCKIN GND GND MMAP XTI XTO P/M SPFRX BYPASS GND VDD GPIO0 D0 GPIO1 D1 GPIO2 VDD SDD GND nc GND
1
ZR38650
144 pin TQFP (TOP VIEW)
36
37
GND nc GND D23 D22 VDD A11 D9/PP5 D8/PP4 SO/SDA D21 VDD GND D20 GND A12 TDO A13 D7/PP3 D6/PP2 A14 GND VDD A15 D5/PP1 D4/PP0 VDD A16 RD WR CS D3 D4 GND nc GND
73
72
Figure 36. ZR38650 Pin Out Diagram
64
ZR38650
22.00 0.20 20.00 0.10
144
109
1
108
ZR38650
144 pin TQFP, 20 x 20 (TOP VIEW)
36
37 0.22 0.05 0.50 BSC
73
72
11o - 13o
1.40 0.05 0.15 0.05 0.10 0.05 Legend BSC REF BASIC, dimensions locating true position. A dimension which is obtained from other dimensions and their tolerances Angularity (degrees) Linear dimensions in millimeters 0.60 0.15 0o - 7o 1.00 REF 11o - 13o
Figure 37. ZR38650 144-Pin TQFP Package Dimensions
65
20.00 0.10
ZR38650
ORDERING INFORMATION
ZR 38650 TQ C
PACKAGE TQ - Plastic Thin Quad Flat Pack (EIAJ) SCREENING KEY PACKAGE PART NUMBER PREFIX SCREENING KEY C - 0C to +70C (VCC = 3.15V to 3.45V)
Note: Dolby Licensing:
AC-3 and Pro Logic usage is available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA 94111, USA, +1 (415) 558-0200, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation.
SALES OFFICES
U.S. Headquarters Zoran Corporation 3112 Scott Blvd. Santa Clara, CA 95054 USA Telephone: +1 (408) 919-4111 FAX: +1 (408) 919-4122 Israel Operations Zoran Microelectronics, Ltd. Advanced Technology Center P.O. Box 2495 Haifa, 31024 Israel Telephone: +972 4 8545-777 FAX: +972 4 8551-550 Canada Zoran Toronto Labs 2157 Queen Street East Suite 302 Toronto, Ontario, Canada M4E 1ES Telephone: +1 (416) 690-3356 FAX: +1 (416) 690-3363 Japan Zoran Sales Office 2-26-2 Sasazuka Shibuya-ku, Tokyo 151 Japan Telephone: +81 3 5352-0971 FAX: +81 3 5352-0972
P. R. China Zoran China Office (Shenzhen) Suite 1706, Grand Skylight Hotel 8 Central Shennan Road Shenzhen, Guangdong 518041 P. R. China Telephone: +86 755-3363225 Mobile Phone: +86 139-2704950 FAX: +86 755-3363256
The material in this product brief is for information only. Zoran Corporation assumes no responsibility for errors or omissions and reserves the right to change, without notice, product specifications, operating characteristics, packaging, etc.
Zoran Corporation assumes no liability for damage resulting from the use of information contained in this document. All brand, product, and company names are trademarks or registered trademarks of their respective companies.
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