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19-1927; Rev 0; 2/01
Quad LVDS Line Driver with Flow-Through Pinout
General Description
The MAX9123 quad low-voltage differential signaling (LVDS) differential line driver is ideal for applications requiring high data rates, low power, and low noise. The MAX9123 is guaranteed to transmit data at speeds up to 800Mbps (400MHz) over controlled impedance media of approximately 100. The transmission media may be printed circuit (PC) board traces, backplanes, or cables. The MAX9123 accepts four LVTTL/LVCMOS input levels and translates them to LVDS output signals. Moreover, the MAX9123 is capable of setting all four outputs to a high-impedance state through two enable inputs, EN and EN, thus dropping the device to an ultra-low-power state of 16mW (typ) during high impedance. The enables are common to all four transmitters. Outputs conform to the ANSI TIA/EIA-644 LVDS standard. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVTTL/LVCMOS inputs and LVDS outputs. The MAX9123 operates from a single +3.3V supply and is specified for operation from -40C to +85C. It is available in 16-pin TSSOP and SO packages. Refer to the MAX9121/ MAX9122* data sheet for quad LVDS line receivers with integrated termination and flow-through pinout. o Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk o Pin Compatible with DS90LV047A o Guaranteed 800Mbps Data Rate o 250ps Maximum Pulse Skew o Conforms to TIA/EIA-644 LVDS Standard o Single +3.3V Supply o 16-Pin TSSOP and SO Packages
Features
MAX9123
Ordering Information
PART MAX9123EUE MAX9123ESE TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 SO
Applications
Digital Copiers Laser Printers Cell Phone Base Stations Add Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
Typical Applications Circuit
LVDS SIGNALS MAX9122*
MAX9123
TX
107
RX
Pin Configuration
TOP VIEW
EN 1 IN1 2 IN2 3 VCC 4 GND 5 IN3 6 IN4 7 EN 8 16 OUT115 OUT1+ 14 OUT2+
LVTTL/CMOS DATA INPUT
TX
107
RX
LVTTL/CMOS DATA OUTPUT
TX
107
RX
MAX9123
13 OUT212 OUT311 OUT3+ 10 OUT4+ 9 OUT4100 SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES TX 107 RX
TSSOP/SO
* Future product--contact factory for availability. ________________________________________________________________ Maxim Integrated Products 1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad LVDS Line Driver with Flow-Through Pinout MAX9123
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-0.3V to (VCC + 0.3V) OUT_+, OUT_- to GND..........................................-0.3V to +3.9V Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin SO (derate 8.7mW/C above +70C)................696mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection Human Body Model, IN_, OUT_+, OUT_-.......................4kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER LVDS OUTPUT (OUT_+, OUT_-) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Voltage Change in Magnitude of VOS Between Complementary Output States Output High Voltage Output Low Voltage Differential Output Short-Circuit Current (Note 3) Output Short-Circuit Current Output High-Impedance Current Power-Off Output Current INPUTS (IN_, EN, EN) High-Level Input Voltage Low-Level Input Voltage Input Current SUPPLY CURRENT No-Load Supply Current Loaded Supply Current Disabled Supply Current ICC ICCL ICCZ RL = , IN_ = VCC or 0 for all channels RL = 100, IN_ = VCC or 0 for all channels Disabled, IN_ = VCC or 0 for all channels, EN = 0, EN = VCC 9.2 22.7 4.9 11 30 6 mA mA mA VIH VIL IIN IN_, EN, EN = 0 or VCC 2.0 GND -20 VCC 0.8 20 V V A VOD VOD VOS VOS VOH VOL IOSD IOS IOZ IOFF Enabled, VOD = 0 OUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_ = 0, enabled EN = low and EN = high, OUT_+ = 0 or VCC, OUT_- = 0 or VCC , RL = VCC = 0 or open, OUT_+ = 0 or 3.6V, OUT_= 0 or 3.6V, RL = -10 -20 -3.8 0.90 -9 -9 10 20 Figure 1 Figure 1 Figure 1 Figure 1 1.125 250 368 1 1.25 4 450 35 1.375 25 1.6 mV mV V mV V V mA mA A A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Quad LVDS Line Driver with Flow-Through Pinout
SWITCHING CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 15pF, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 4, 5, 6)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew (Note 7) Differential Channel-to-Channel Skew (Note 8) Differential Part-to-Part Skew (Note 9) Differential Part-to-Part Skew (Note 10) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 11) SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 4 and 5 Figures 4 and 5 Figures 4 and 5 Figures 4 and 5 400 0.2 0.2 MIN 0.7 0.7 0.04 0.07 0.13 0.43 0.39 0.39 2.7 2.7 2.3 2.3 TYP MAX 1.7 1.7 0.25 0.35 0.8 1.0 1.0 1.0 5 5 7 7 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MHz
MAX9123
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25C. Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD. Note 3: Guaranteed by correlation data. Note 4: AC parameters are guaranteed by design and characterization. Note 5: CL includes probe and jig capacitance. Note 6: Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 100MHz, 50% duty cycle, RO = 50, tR 1ns, tF 1ns (0% to 100%). Note 7: tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. Note 8: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 9: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5C of each other. Note 10: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 11: fMAX signal generator conditions: VOL = 0, VOH = 3V, f = 400MHz, 50% duty cycle, RO = 50, tR 1ns, tF 1ns (0% to 100%). Transmitter output criteria: duty cycle = 45% to 55%, VOD 250mV.
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3
Quad LVDS Line Driver with Flow-Through Pinout MAX9123
Typical Operating Characteristics
(VCC = +3.3V, RL = 100, CL = 15pF, TA = +25C, unless otherwise noted.)
OUTPUT HIGH VOLTAGE vs. POWER-SUPPLY VOLTAGE
MAX9123 toc01
OUTPUT LOW VOLTAGE vs. POWER-SUPPLY VOLTAGE
MAX9123 toc02
OUTPUT SHORT-CIRCUIT CURRENT vs. POWER-SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT (mA) -3.695 -3.690 -3.685 -3.680 -3.675 -3.670 -3.665 -3.660 -3.655 -3.650 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6 VIN = VCC or GND
MAX9123 toc03
1.100
1.100
-3.700
OUTPUT HIGH VOLTAGE (V)
1.096
OUTPUT LOW VOLTAGE (V)
1.098
1.098
1.096
1.094
1.094
1.092
1.092
1.090 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6
1.090 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6
OUTPUT HIGH-IMPEDANCE STATE CURRENT vs. POWER-SUPPLY VOLTAGE
OUTPUT HIGH-IMPEDANCE STATE CURRENT (pA)
MAX9123 toc04
DIFFERENTIAL OUTPUT VOLTAGE vs. POWER SUPPLY
MAX9123 toc05
DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTOR
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9123 toc06
0 VIN = VCC or GND -50
390 DIFFERENTIAL OUTPUT VOLTAGE (V) 385 380 375 370 365 360 355 350 3.0 3.3 POWER-SUPPLY VOLTAGE (V)
600 550 500 450 400 350 300
-100
-150
-200
-250 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6
3.6
90
100
110
120
130
140
150
LOAD RESISTOR ()
OFFSET VOLTAGE vs. POWER-SUPPLY VOLTAGE
MAX9123 toc07
POWER-SUPPLY CURRENT vs. FREQUENCY
MAX9123 toc08
POWER-SUPPLY CURRENT vs. POWER-SUPPLY VOLTAGE
FREQ = 1MHz VIN = 0 to 3V
MAX9123 toc09
1.260
40 38
POWER-SUPPLY CURRENT (mA)
25.0 POWER-SUPPLY CURRENT (mA)
VIN = 0 to 3V
1.256 OFFSET VOLTAGE (V)
35 33 30 28 ALL SWITCHING 25 23 ONE SWITCHING
24.0
1.252
23.0
1.248
22.0
1.244
21.0
1.240 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6
20 0.1 1 10 FREQUENCY (MHz) 100 1000
20.0 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6
4
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Quad LVDS Line Driver with Flow-Through Pinout
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100, CL = 15pF, TA = +25C, unless otherwise noted.)
POWER-SUPPLY CURRENT vs. AMBIENT TEMPERATURE
MAX9123 toc10
MAX9123
DIFFERENTIAL PROPAGATION DELAY vs. POWER SUPPLY
MAX9123 toc11
DIFFERENTIAL PROPAGATION DELAY vs. AMBIENT TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9123 toc12
25.0 POWER-SUPPLY CURRENT (mA) FREQ = 1MHz VIN = 0 to 3V
1.600 DIFFERENTIAL PROPAGATION DELAY (ns) 1.550 1.500 1.450 1.400 1.350 1.300 1.250 1.200 3.0 3.3 POWER-SUPPLY VOLTAGE (V) tPHLD tPLHD FREQ = 1MHz
1.600
24.0
1.500 tPLHD 1.400
23.0
22.0
1.300
tPHLD FREQ = 1MHz
21.0
1.200
20.0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (C)
1.100 3.6 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (C)
DIFFERENTIAL SKEW vs. POWER-SUPPLY VOLTAGE
MAX9123 toc13
DIFFERENTIAL SKEW vs. AMBIENT TEMPERATURE
175 DIFFERENTIAL SKEW (ps) 150 125 100 75 50 25 FREQ = 1MHz
MAX9123 toc14
100 FREQ = 1MHz 80 DIFFERENTIAL SKEW (ps)
200
60
40
20
0 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6
0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (C)
TRANSITION TIME vs. POWER-SUPPLY VOLTAGE
MAX9123 toc15
TRANSITION TIME vs. AMBIENT TEMPERATURE
FREQ = 1MHz 550 TRANSITION TIME (ps) 500 450 400 350 300 tTHL tTLH
MAX9123 toc16
400 FREQ = 1MHz 390 TRANSITION TIME (ps) 380 370 tTHL 360 350 340 3.0 3.3 POWER-SUPPLY VOLTAGE (V) tTLH
600
250 200 3.6 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (C)
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5
Quad LVDS Line Driver with Flow-Through Pinout MAX9123
Pin Description
PIN 1 2, 3, 6, 7 4 5 8 9, 12, 13, 16 10, 11, 14, 15 NAME EN IN_ VCC GND EN OUT_OUT_+ FUNCTION Driver Enable Input. The driver is disabled when EN is low. EN is internally pulled down. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and are high impedance. LVTTL/LVCMOS Driver Inputs Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. Ground Driver Enable Input. The transmitter is disabled when EN is high. EN is internally pulled down. Inverting LVDS Driver Outputs Noninverting LVDS Driver Outputs
Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9123 is an 800Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, and low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The MAX9123 generates a 2.5mA to 4.0mA output current using a current-steering configuration. This currentsteering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are shortcircuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the MAX9123 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver. Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the MAX9123 produces an output voltage of 370mV when driving a 100 load.
Termination
Because the MAX9123 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The MAX9123 is optimized for point-to-point interface with 100 termination resistors at the receiver inputs. Termination resistance values may range between 90 and132, depending on the characteristic impedance of the transmission medium.
Table 1. Input/Output Function Table
ENABLES EN H H EN L or open L or open INPUTS IN_ L H Don't care L H Z OUTPUTS OUT_+ OUT_ H L Z
All other combinations of ENABLE pins
Applications Information
Power-Supply Bypassing
Bypass V CC with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC.
Differential Traces
Output trace characteristics affect the performance of the MAX9123. Use controlled-impedance traces to match trace impedance to the transmission medium.
6
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Quad LVDS Line Driver with Flow-Through Pinout MAX9123
OUT_+ CL
RL/2 GND RL/2 VOS VOD
OUT_ +
VO
S
VCC
IN_ GENERATOR
IN_
RL OUT_ CL
50
OUT_-
Figure 1. Driver VOD and VOS Test Circuit
Figure 2. Driver Propagation Delay and Transition Time Test Circuit
3V IN_ 1.5V 1.5V 0 tPLHD OUT_ 0 DIFFERENTIAL OUT_+ 0 VOL 80% 0 VDIFF 20% tTLH tTHL 80% VDIFF = (VOUT_+) - (VOUT_-) 0 20% tPHLD VOH
Figure 3. Driver Propagation Delay and Transition Time Waveforms
Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver.
Board Layout
For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Isolate the LVTTL/LVCMOS and LVDS signals from each other to prevent coupling.
Cables and Connectors
Transmission media should have a nominal differential impedance of 100. To minimize impedance discontinuities, use cables and connectors that have matched differential impedance. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate TRANSISTOR COUNT: 1246 PROCESS: CMOS
Chip Information
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7
Quad LVDS Line Driver with Flow-Through Pinout MAX9123
CL
Functional Diagram
OUT1+ OUT_+
VCC GND GENERATOR 50 EN EN
IN1 OUT1-
IN_
RL/2
+1.2V RL/2 OUT_1/4 MAX9123 CL OUT2IN2 OUT2+
Figure 4. Driver High-Impedance Delay Test Circuit
IN3
OUT3+
OUT3-
OUT4+ IN4 OUT4-
EN EN
EN WHEN EN = 0 OR OPEN 1.5V 1.5V
3V
0
3V 1.5V EN WHEN EN = VCC tPHZ OUT_+ WHEN IN_ = VCC OUT_- WHEN IN_ = 0 50% 50% 1.2V 1.2V 50% OUT_+ WHEN IN_ = 0 OUT_- WHEN IN_ = VCC 50% VOL tPLZ tPZL tPZH VOH 1.5V 0
Figure 5. Driver High-Impedance Delay Waveform 8 _______________________________________________________________________________________
Quad LVDS Line Driver with Flow-Through Pinout
Package Information
TSSOP,NO PADS.EPS
MAX9123
_______________________________________________________________________________________
9
Quad LVDS Line Driver with Flow-Through Pinout MAX9123
Package Information (continued)
SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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