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CXP820P60
CMOS 8-bit Single Chip Microcomputer
Description The CXP820P60 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, capture timer/counter, fluorescent display panel controller/driver, remote control reception circuit, and PWM output circuit besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP820P60 also provides sleep/stop function that enables lower power consumption. CXP820P60 is the PROM-incorporated version of the CXP82052/82060 with bult-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation 122s at 32kHz operation * Incorporated PROM capacity 60K bytes * Incorporated RAM capacity 3984 bytes (including fluorescent display area) * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 3.25s/16MHz) -- Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel 8-bit clock synchronized type, (MSB/LSB first selectable), 1 channel Start-stop synchronization (UART), 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer 16-bit capture timer/counter, 32kHz timer/counter -- Fluorescent display panel Supports the universal grid fluorescent display panel controller/driver High voltage drive output port of 56 pins (40V) Maximum of 640 segments display possible Display timing number of 1 to 20 Dimmer function Incorporated pull-down resistor (mask option) Hardware key scan function (Maximum of 16 x 8 key matrix supportable) -- Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO -- PWM output 14 bits, 1 channel * Interruption 17 factors, 15 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin plastic QFP * Piggy/Evaluation chip CXP82000 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97638-PS
Block Diagram
INT0 INT1 INT2 INT3/NMI TEX TX EXTAL XTAL RST VDD VSS Vpp
2
G0/A0 to G15/A15 16 RAM
SPC 700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL
A16 to A23
8
PORT A
AN0 to AN7 8
8
A/D CONVERTER
PA0 to PA7
A24 to A56 VFDP KR0 to KR7 RAM PROM 60K BYTES RAM 3984 BYTES
8
KEY SCAN
PORT B
32
FDP CONTROLLER/ DRIVER
8
PB0 to PB7
8
PC0 to PC7
TxD
PORT C
RxD
RMC FIFO
REMOCON
PORT E
CS0 SI0 SO0 SCK0 BUFFER RAM
SERIAL INTERFACE (CH0)
PORT F
SI1 SO1 SCK1 2
SERIAL INTERFACE (CH1)
PRESCALER/ TIME-BASE TIMER
32kHz TIMER/COUNTER
PORT G
8-BIT TIMER 1 2
PORT H
TO CINT EC1 2
ADJ CXP820P60
PORT I
-2-
PWM
14-BIT PWM GENERATOR
INTERRUPT CONTROLLER
PORT D
UART RECEIVER UART TRANSMITTER UART BAUD RATE GENERATOR
8
PD0 to PD7
6 2
PE0 to PE5 PE6 to PE7
8
PF0 to PF7
8
PG0 to PG7
EC0
8-BIT TIMER/COUNTER 0
8
PH0 to PH7
16-BIT CAPTURE TIMER/COUNTER 2
4
PI0 to PI4
CXP820P60
Pin Assignment (Top View)
G2/A2 G3/A3 G4/A4 G5/A5 G6/A6 G7/A7 G8/A8 G9/A9 G10/A10 G11/A11 G12/A12 G13/A13 G14/A14 G15/A15
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 G1/A1 G0/A0 Vpp PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CINT PE6/PWM PE7/TO/ADJ PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PB0/TxD PB1/CS0/RxD PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PI0 PA0/AN0 PA1/AN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A21 A22 A23 PH7/A24 PH6/A25 PH5/A26 PH4/A27 PH3/A28 PH2/A29 PH1/A30 PH0/A31 PG7/A32 PG6/A33 PG5/A34 PG4/A35 PG3/A36 PG2/A37 PG1/A38 PG0/A39 PF7/A40 PF6/A41 PF5/A42 PF4/A43 PF3/A44 PF2/A45 PF1/A46 PF0/A47 PD7/A48 PD6/A49 PD5/A50
VDD
PI3/TEX
A16
A17
A18
A19 PD3/A52
PA2/AN2
Note) 1. Vpp (Pin 3) is left open. 2. VDD (Pins 44 and 89) are both connected to VDD. -3-
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
PD0/A55
PD1/A54
PD2/A53
PD4/A51
PI2/TX
EXTAL
XTAL
VFDP
RST
VDD
Vss
PI1
A20
CXP820P60
Pin Description Symbol I/O Functions (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins)
PA0/AN0 to PA7/AN7
I/O/ Analog input
Analog inputs to A/D converter. (8 pins)
PB0/TxD PB1/CS0/RxD PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Output I/O/Input/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sink current. Incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins)
UART transmission data output. UART reception Chip select input for serial interface (CH0). data input. Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).
PC0/KR0 to PC7/KR7
I/O/Input
Serves as key return inputs when operating key scan with fluorescent display panel (FDP) segment signal. (8 pins)
PD0/A55 to PD7/A48 PE0/INT0/ EC0 PE1/INT1/ EC1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5/CINT PE6/PWM PE7/TO/ ADJ
I/O/Output
FDP segment signal (anode connection) outputs.
Input/Input/Input Input/Input/Input Input/Input Input/Input/Input Input/Input Input/Input Output/Output Output/Output/ Output (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) Inputs for external interruption request. (4 pins)
External event inputs for timer/counter. (2 pins)
Non-maskable interruption request input. Remote control reception circuit input. External capture input for 16-bit timer/counter. 14-bit PWM output. Output for the 16-bit timer/counter rectangular waves, and 32kHz oscillation frequency division.
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CXP820P60
Symbol PF0/A47 to PF7/A40 PG0/A39 to PG7/A32 PH0/A31 to PH7/A24 PI0 PI1 PI2/TX PI3/TEX A16 to A23 G0/A0 to G15/A15 VFDP EXTAL XTAL RST Vpp VDD VSS Input Input
I/O (Port F) 8-bit output port. I/O can be set in a unit of single bits. (8 pins) (Port G) 8-bit output port. (8 pins) (Port H) 8-bit output port. (8 pins)
Functions FDP segment signal (anode connection) outputs. (8 pins) FDP segment signal (anode connection) outputs. (8 pins) FDP segment signal (anode connection) outputs. (8 pins)
I/O/Output
Output/Output
Output/Output Input Input Input Input/Input Output
(Port I) 4-bit input port. (4 pins)
Crystal connectors for 32kHz timer/counter clock oscillation. For usage as event counter, input to TEX, and leave TX open.
FDP segment signal (anode connection) outputs. (8 pins) Outputs for FDP timing signals (grid connection)/segment signals (anode connection). (16 pins) FDP voltage supply for incorporated pull-down (PD) resistor. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active, system reset. Vcc supply for incorporated PROM writing. Leave this pin open during normal operation. Positive power supply. GND.
Output/Output
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CXP820P60
I/O Circuit Format for Pins Pin Port A
Pull-up registor "0" after a reset Port A data
Circuit format
After a reset
PA0/AN0 to PA7/AN7
Internal data bus
Port A direction "0" after a reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A input selecton "0" after a reset A/D converter Input multiplexer
8 pins Port B
Pull-up registor "0" after a reset TxD UART output selection
Pull-up transistor approx. 100k
PB0/TxD
"0" after a reset Port B data Port B direction "0" after a reset Internal data bus IP
Hi-Z
1 pin Port B
RD (Port B) Pull-up transistor approx. 100k
Pull-up registor "0" after a reset Port B data
PB1/CS0/RxD PB3/SI0 PB6/SI1
Internal data bus
Port B direction "0" after a reset
IP Schmitt input
Hi-Z
RD (Port B) CS0 SI0 SI1 RxD
3 pins
Pull-up transistor approx. 100k
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CXP820P60
Pin Port B
Pull-up registor "0" after a reset SCK OUT Serial clock output enable
Circuit format
After a reset
PB2/SCK0 PB5/SCK1
Port B output selecton "0" after a reset Port B data Port B direction "0" after a reset Internal data bus RD (Port B) Schmitt input IP
Hi-Z
2 pins Port B
Pull-up registor "0" after a reset
SCK IN
Pull-up transistor approx. 100k
SO Serial data output enable
PB4/SO0 PB7/SO1
Port B outputput selecton "0" after a reset Port B data Port B direction "0" after a reset Internal data bus IP
Hi-Z
2 pins Port C
RD (Port B) Pull-up transistor approx. 100k
Pull-up registor "0" after a reset
2
PC0/KR0 to PC7/KR7
Internal data bus
Port C data
Port C direction "0" after a reset
1 IP
Hi-Z
8 pins
RD (Port C) Key input signal
1 Large current 12mA 2 Pull-up transistor approx. 100k
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CXP820P60
Pin PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CINT 6 pins Port E
PWM Port E output selecton "0" after a reset
Circuit format Port E
Schmitt input IP EC0/INT0 EC1/INT1 INT2 INT3/NMI RMC CINT Internal data bus RD (Port E)
After a reset
Hi-Z
PE6/PWM
Port E data "1" after a reset Internal data bus Output enable
High level
1 pin Port E
RD (Port E)
Internal reset signal Port E data "1" after a reset TO ADJ16K1 ADJ2K2 00 01 10 11 MPX 2
PE7/TO/ADJ
Port E output selecton (upper) Port E output selecton (lower) "00" after a reset TO output enable 1 ADJ signal is a frequency dividing output for 32kHz oscillation frequency adjustment. ADJ2K can be used for buzzer output. 2 Pull-up transistor approx. 150k
High level (High level at ON resistance of pull-up transistor during a reset)
1 pin Port D Port F PD0/A55 to PD7/A48 PF0/A47 to PF7/A40
Segment output data
Output selection control signal ("0" after a reset)
Port D and F data Port D and F direction "1" after a reset Internal data bus RD (Port D and F) IP
Hi-Z
16 pins -8-
High voltage drive transistor
CXP820P60
Pin Port G Port H PG0/A39 to PG7/A32 PH0/A31 to PH7/A24
Segment output data
Circuit format
After a reset
Output selection control signal ("0" after a reset)
Port G and H data "0" after a reset Internal data bus High voltage drive transistor RD (Port G and H)
Hi-Z
16 pins
Segment output data
A16 to A23
Output selection control signal ("0" after a reset) Pull-down registor
VFDP
Hi-Z or Low level (when PD resistor is connected)
8 pins
High voltage drive transistor
G0/A0 to G15/A15
Segment output data Timing output data Output selection control signal ("0" after a reset) Pull-down registor
VFDP
Hi-Z or Low level (when PD resistor is connected)
16 pins
High voltage drive transistor
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit composition during oscillation. * Feedback resistor is removed and XTAL becomes High level during stop.
Oscillation
2 pins
XTAL
PI0 PI1 2 pins
IP RD (Port I)
Internal data bus
Hi-Z
-9-
CXP820P60
Pin
Circuit format
TEX oscillation circuit control "1" after a reset Internal data bus RD Internal data bus RD PI3/TEX IP IP Clock input
After a reset
PI2/TX PI3/TEX
Oscillation stop port input
2 pins
PI2/TX
Pull-up registor
RST Low level
IP
1 pin
Schmitt input
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CXP820P60
Absolute Maximum Ratings Item Supply voltage Symbol VDD Vpp FDP display supply voltage VFDP Input voltage Output voltage Display output voltage VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current IOH IODH IOL IOLC Low level total output current IOL Operating temperature Storage temperature 1 2 3 4 Topr Tstg Rating -0.3 to +7.0 -0.3 to +13.0 -402 to +7.01 -0.3 to +7.01 -0.3 to +7.01 -402 to +7.01 -5 -15 -50 -30 -120 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V V V mA mA mA mA mA mA mA mA C C mW Incorporated PROM
(Vss = 0V reference) Remarks
All pins excluding display outputs3 (value per pin) Display outputs A20 to A55 (value per pin) Display outputs G0/A0 to G15/A15, and A16 to A19 (value per pin) Total for all pins excluding display outputs Total for all display outputs Pins excluding large current output (value per pin) Large current output pins4 (value per pin) Total for all output pins
Low level output current
Allowable power dissipation PD
VIN, VOUT and VOD must not exceed VDD + 0.3V. VFDP and VOD must not exceed VDD - 40V. Specifies output current of general-purpose I/O ports. The large current drive transistor is the N-CH transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
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CXP820P60
Recommended Operating Conditions Item Symbol Min. 4.5 Max. 5.5 Unit V
(Vss = 0V reference) Remarks Guaranteed operation range during 1/2, 1/4 frequency dividing clock modes Guaranteed operation range during 1/16 frequency dividing clock or sleep modes Guaranteed operation range with TEX clock Guaranteed data hold range during stop 1 2 3 EXTAL4 1 2 3 EXTAL4
Supply voltage
VDD
3.5
5.5
V
2.7 2.5 VIH High level input voltage VIHS VIHH VIHEX VIL Low level input voltage VILS VILH VILEX Operating temperature Topr 0.7VDD 0.8VDD 0.7VDD
5.5 5.5 VDD VDD VDD
V V V V V V V V V V C
VDD - 0.4 VDD + 0.3 0 0 0 -0.3 -20 0.3VDD 0.2VDD 0.7 0.4 +75
1 Value for each pin of normal input port (PA, PB0, PB4, PB7, PC). 2 Value of the following pins: RST, CINT, CS0/RxD, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC. 3 Value for each pin (PD, PF). 4 Specifies only during external clock input.
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CXP820P60
Electrical Characteristics DC Characteristics Item High level output current Low level output current Symbol VOH Pins PA to PD, PE6, PE7, PF to PH PA to PC, PE6, PE7 PC IIHE IILE IIHT Input current IILT IILR IIL EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V TEX RST PA to PC1 A20 to A55 Display output IOH current Open drain output leakage current (P-CH Tr off state) Pull-down resistance G0/A0 to G15/A15, A16 to A19 G0/A0 to G15/A15, A16 to A55 G0/A0 to G15/A15, A16 to A23 PA to PC1, PD2, PE0 to PE5, PF2, PI VDD = 4.5V VOH = VDD - 2.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, VSS = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 -50 -3.3 -8 -30 Typ. Max. Unit V V V V V A A A A A A A mA mA
VOL
ILOL
VDD = 5.5V VOL = VDD - 35V VFDP = VDD - 35V VDD = 5V VOD - VFDP = 30V
-20
A
RL
30
70
220
k
I/O leakage current
IIZ
VDD = 5.5V VI = 0, 5.5V
10
A
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CXP820P60
Item
Symbol IDD1
Pins
Conditions 1/2 frequency dividing clock mode operation VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF)
Min.
Typ.
Max.
Unit
27
55
mA
IDD2 Supply current3 VDD
VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Sleep mode VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode VDD = 5.5V, termination of 16MHz and 32kHz oscillation PA to PC, PD2, Clock 1MHz PE0 to PE5, 0V for all pins excluding PF2, PI, measured pins EXTAL, RST
35
110
A
IDDS1
1.5
8
mA
IDDS2
15
30
A
IDDS3
10
A
Input capacity
CIN
10
20
pF
1 PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. 2 PD and PF pins specify when they are used as input pins by program. 3 When all pins are open.
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CXP820P60
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC0, EC1 EC0, EC1 TEX TX TEX TEX
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 20 Min. 1 28 Typ. Max. 16 Unit MHz ns 200 ns ns ms
tXL tXH tCR tCF tEH tEL tER tEF
fC
tsys + 501
32.768
kHz
Event count input pulse width Event count input rise time, fall time 1
tTL tTH tTR tTF
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL C1
XTAL
EXTAL
XTAL
TEX
TX
C2
74HC04
C1
C2
Fig. 2. Clock applied conditions
0.8VDD 0.2VDD
TEX EC0 EC1 tEH tTH tEF tTF tEL tTL tER tTR
Fig. 3. Event count clock timing - 15 -
CXP820P60
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0
SCK0 High, Low level width SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1)
SCK0
tsys + 100
8000/fc - 50 100 200
SI0
SI0
tsys + 200
100
SO0
tsys + 200
100
ns ns
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
- 16 -
CXP820P60
tWHCS
CS0 0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
Fig. 4. Serial transfer CH0 timing
- 17 -
CXP820P60
Serial transfer (CH1) Item SCK1 cycle time SCK1 High, Low level width SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Ouput mode SCK1 Input mode Ouput mode SI1 SCK1 input mode SCK1 ouput mode SI1 SCK1 input mode SCK1 ouput mode SO1 SCK1 input mode SCK1 ouput mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY tKL tKH
0.8VDD SCK1 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output dat
Fig. 5. Serial transfer CH1 timing
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CXP820P60
(3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Symbol Pin
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Min. Typ. Max. 8 3 Ta = 25C VDD = 5.0V VSS = 0V -10 4910 26/fADC3 6/fADC3 10 4970 70 5030 Unit Bits LSB mV mV s s VDD V
tCONV tSAMP
VIAN AN0 to AN7
0
FFh FEh
Linearity error 01h 00h VZT Analog input VFT
1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. 2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. 3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9h) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEh). However, the selection for fADC = fC (CKS = "0") is limited in the clock range of fC = 1 to 14MHz (VDD = 4.5 to 5.5V).
Digital conversion value
Fig. 6. Definition of A/D converter terms
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CXP820P60
(4) Interruption, reset input Item External interruption High, Low level width Reset input Low level width
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 NMI/INT3 RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
32/fc
s
tIH
tIL
0.8VDD INT0 INT1 INT2 NMI/INT3 (NMI specifies only for the falling edge.) 0.2VDD tIL tIH
Fig. 7. Interruption input timing
tRSL
RST 0.2VDD
Fig. 8. RST input timing
- 20 -
CXP820P60
Appendix
(i) Main clock (ii) Main clock (iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL TEX
XTAL TX Rd
C1
C2 C1 C2
C1
C2
Fig. 9. Recommended oscillation circuit
Manufacturer
Model CSA10.0MTZ CSA12.0MTZ
fc (MHz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0
C1 (pF) 30 5 30 5 18 12 10 10 5 Open 18
C2 (pF) 30 5 30 5 18 12 10 10 5 Open 18
Rd ()
Circuit example
Remarks
(i) 0 (ii)
MURATA MFG CO., LTD.
CSA16.00MXZ040 CST10.0MTW CST12.0MTW CST16.00MXW0C1
RIVER ELETEC CO., LTD
HC-49/U03
12.0 16.0 8.0
330 (i) 0
KINSEKI LTD. Seiko Instruments Inc.
HC-49/U (-S)
12.0 16.0
VTC-200 SP-T
32.768kHz
330k
(iii)
CL = 12.5pF
Models marked with an asterisk () have the built-in ground capacitance (C1, C2).
Mask Option Table Item Package ROM capacitance Reset pin pull-up resistor High voltage drive pin pull-down resistor Mask ROM 100-pin plastic QFP 52K/60K byte Existent/Non-existent Existent/Non-existent CXP820P60Q-1100-pin plastic QFP PROM 60K byte Existent Non-existent (PH7/A24 to PD0/A55) Existent (G0/A0 to A23)
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CXP820P60
Characteristics Curve
IDD vs. VDD
100 25
IDD vs. fc
1/2 dividing mode 1/4 dividing mode 10 20
1/2 dividing mode
IDD - Supply current [mA]
1/16 dividing mode
IDD - Supply current [mA]
15
Sleep mode 1
1/4 dividing mode 10
0.1
32kHz mode 5 32kHz Sleep mode 1/16 dividing mode
Sleep mode 0.01 0 1 2 3 4 5 6 7 VDD - Supply voltage [V] 0 0 5 10 fc - System clock [MHz] 15 20
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CXP820P60
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
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