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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
D D D D D D D D D D D D
3.3-V Core Logic With Universal PCI Interface Compatible With 3.3-V or 5-V PCI Signaling Environments Supports PCI Local Bus Specification 2.1 Mix-and-Match 3.3-V/5-V PC Card16 Cards and 3.3-V CardBus Cards Supports Two PC Card TM or CardBus Slots With Hot Insertion and Removal 1995 PC Card-Standard Compliant Low-Power Advanced Submicron CMOS Technology Uses Serial Interface to Texas Instruments (TITM) TPS2206 Dual Power Switch System Interrupts Can Be Programmed as PCI-Style or ISA IRQ-Style Interrupts ISA IRQ Interrupts Can Be Serialized Onto a Single IRQSER Pin Programmable Output Select for CLKRUN Supports Burst Transfers to Maximize Data Throughput on the PCI and CardBus Bus Multifunction PCI Device With Separate Configuration Spaces for Each Socket
D D D D D D D D D D D
Five PCI Memory Windows and Two I/O Windows Available to Each PC Card16 Socket Two I/O Windows and Two Memory Windows Available to Each CardBus Socket CardBus Memory Windows Can Be Individually Selected Prefetchable or Nonprefetchable Exchangeable Card Architecture (ExCA)-Compatible Registers Mapped in Memory or I/O Space TI Extension Registers Mapped in the PCI Configuration Space Intel TM 82365SL-DF Register Compatible Supports 16-Bit Distributed Direct Memory Access (DMA) on Both PC Card Sockets Supports PC/PCI DMA on Both PC Card Sockets Supports Zoom Video Mode Supports Ring Indicate Packaged in 208-Pin Thin Plastic Quad Flatpack
Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Terminal Assignments - PCI-to-PC Card (16 Bit) . . . . . . . . . . . . 4 Terminal Assignments - PCI-to-CardBus Card . . . . . . . . . . . . . . 5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . 15 Recommended Operating Conditions for PCI Interface . . . . . 15 Recommended Operating Conditions for PC Cards A and B . 16 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . PCI Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Parameter Measurement Information . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 19 20 21 22 23 23 25
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel and MPIIX are trademarks of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
description
The TI PCI1131 is a high-performance PCI-to-PC Card controller that supports two independent PC Card sockets compliant with the 1995 PC Card standard. The PCI1131 provides a set of features that makes it ideal for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card standard retains the 16-bit PC Card specification defined in PCMCIA release 2.1 and defines the new 32-bit PC Card, called CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1131 supports any combination of 16-bit and CardBus PC Cards in its two sockets, powered at 3.3 V or 5 V, as required. The PCI1131 is compliant with the PCI local bus specification revision 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bus-mastering cycles. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1131 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1131 internal datapath logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent 32-bit write buffers allow fast-posted writes to improve system-bus utilization. An advanced CMOS process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes allow the host power-management system to further reduce power consumption. All unused PCI1131 inputs should be pulled high through a 43-k resistor.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
system block diagram
A simplified system block diagram using the PCI1131 is provided below. The PCI950 IRQ deseralizer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability. The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1131 that include:
D D D
Multifunction IRQ terminals SUSPEND, RI_OUT (power management control signals) SPKROUT.
PCI Bus
INTA INTB Interrupt Controller
TPS22xx Power Switch
3
PCI1131
IRQSER
PCI950 IRQSER Deserializer
IRQ2-15
3 PC Card Socket A
68
68 23 PCI930 ZV Switch
Zoom Video 19
VGA Controller
PC Card Socket B External ZV Port
23
Zoom Video 4
Audio Sub-System
NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals too the VGA controller.
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3
PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
terminal assignments - PCI-to-PC Card (16 bit)
IRQ5 IRQ4/INTB IRQ3/INTA GND DATA CLOCK LATCH SPKROUT/SUPEND VCCP A_D10 A_D2 A_D9 A_D1 V CC A_D8 A_D0 A_CD2 A_WP(IOIS16) A_BVD1(STSCHG/RI) A_BVD2(SPKR) A_WAIT A_READY(IREQ) A_VS1 A_A0 A_A1 A_A2 A_REG GND A_A3 A_INPACK A_A4 A_A5 A_RESET A_A6 A_VS2 A_A25 VCCA A_A7 A_A24 A_A12 A_A23 A_A15 A_A22 VCC A_A16 A_A21 A_WE A_A20 A_A14 A_A19 A_A13 A_A18 IRQ7/PCDMAREQ IRQ9/IRQSER IRQ10/CLKRUN IRQ11/PCDMAGNT IRQ12/CLKRUN IRQ14 IRQ15/RI_OUT VCC PCLK RSTIN GND GNT REQ AD31 AD30 VCCP AD29 AD28 VCC AD27 AD26 AD25 AD24 C/BE3 GND IDSEL AD23 AD22 AD21 AD20 VCC AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR V CC PAR C/BE1 AD15 AD14 AD13 GND AD12 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
PDV PACKAGE (TOP VIEW)
Card A
PCI
PCI1131 Core
Card B
4
AD11 AD10 AD9 AD8 C/BE0 AD7 V CC AD6 AD5 AD4 AD3 AD2 GND AD1 AD0 B_CD1 B_D3 B_D11 B_D4 B_D12 B_D5 GND B_D13 B_D6 B_D14 B_D7 B_D15 B_CE1 B_A10 B_CE2 V CC B_OE B_IORD B_A11 B_IOWR B_A9 B_A17 V CCB B_A8 B_A18 B_A13 B_A19 B_A14 GND B_A20 B_WE B_A21 B_A16 B_A22 B_A15 B_A23 B_A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
A_A8 A_A17 A_A9 A_IOWR A_A11 A_IORD A_OE A_CE2 GND A_A10 A_CE1 A_D15 A_D7 A_D14 A_D6 A_D13 A_D5 A_D12 VCC A_D4 A_D11 A_D3 A_CD1 B_D10 B_D2 B_D9 B_D1 B_D8 B_D0 GND B_CD2 B_WP(IOIS16) B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A0 B_A1 B_A2 V CC B_REG B_A3 B_INPACK B_A4 B_A5 B_RESET B_A6 B_VS2 B_A25 B_A7 B_A24
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
terminal assignments - PCI-to-CardBus Card
IRQ5 IRQ4/INTB IRQ3/INTA GND DATA CLOCK LATCH SPKROUT/SUSPEND VCCP A_CAD31 A_RSVD A_CAD30 A_CAD29 V CC A_CAD28 A_CAD27 A_CCD2 A_CCLKRUN A_CSTSCHG A_CAUDIO A_CSERR A_CINT A_CVS1 A_CAD26 A_CAD25 A_CAD24 A_CC/BE3 GND A_CAD23 A_CREQ A_CAD22 A_CAD21 A_CRST A_CAD20 A_CVS2 A_CAD19 VCCA A_CAD18 A_CAD17 A_CC/BE2 A_CFRAME A_CIRDY A_CTRDY VCC A_CCLK A_CDEVSEL A_CGNT A_CSTOP A_CPERR A_CBLOCK A_CPAR A_RSVD IRQ7/PCDMAREQ IRQ9/IRQSER IRQ10/CLKRUN IRQ11/PCDMAGNT IRQ12/CLKRUN IRQ14 IRQ15/RI_OUT VCC PCLK RSTIN GND GNT REQ AD31 AD30 VCCP AD29 AD28 VCC AD27 AD26 AD25 AD24 C/BE3 GND IDSEL AD23 AD22 AD21 AD20 VCC AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR V CC PAR C/BE1 AD15 AD14 AD13 GND AD12 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
PDV PACKAGE (TOP VIEW)
Card A
PCI
PCI1131 Core
Card B
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B_CC/BE1 B_RSVD B_CPAR B_CBLOCK B_CPERR GND B_CSTOP B_CGNT B_CDEVSEL B_CCLK B_CTRDY B_CIRDY B_CFRAME B_CC/BE2
AD11 AD10 AD9 AD8 C/BE0 AD7 V CC AD6 AD5 AD4 AD3 AD2 GND AD1 AD0 B_CCD1 B_CAD0 B_CAD2 B_CAD1 B_CAD4 B_CAD3 GND B_CAD6 B_CAD5 B_RSVD B_CAD7 B_CAD8 B_CC/BE0 B_CAD9 B_CAD10 VCC B_CAD11 B_CAD13 B_CAD12 B_CAD15 B_CAD14 B_CAD16 VCCB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
A_CC/BE1 A_CAD16 A_CAD14 A_CAD15 A_CAD12 A_CAD13 A_CAD11 A_CAD10 GND A_CAD9 A_CC/BE0 A_CAD8 A_CAD7 A_RSVD A_CAD5 A_CAD6 A_CAD3 A_CAD4 V CC A_CAD1 A_CAD2 A_CAD0 A_CCD1 B_CAD31 B_RSVD B_CAD30 B_CAD29 B_CAD28 B_CAD27 GND B_CCD2 B_CCLKRUN B_CSTSCHG B_CAUDIO B_CSERR B_CINT B_CVS1 B_CAD26 B_CAD25 B_CAD24 V CC B_CC/BE3 B_CAD23 B_CREQ B_CAD22 B_CAD21 B_CRST B_CAD20 B_CVS2 B_CAD19 B_CAD18 B_CAD17
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
Terminal Functions PCI system
TERMINAL NAME PCLK NO. 165 I/O TYPE I FUNCTION PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. PCI reset. When the RSTIN signal is asserted low, the PCI1131 forces all output buffers to the high-impedance state and resets all internal registers. When asserted, the PCI1131 is nonfunctional. After RSTIN is deasserted, the PCI1131 returns to the default state. When the PCI1131 SUSPEND mode is enabled, the device is protected from any RSTIN reset (i.e., the PCI1131 internal register contents are preserved).
RSTIN
166
I
PCI address and data
TERMINAL NAME AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE3 C/BE2 C/BE1 C/BE0 PAR NO. 170 171 173 174 176 177 178 179 183 184 185 186 188 189 190 191 204 205 206 208 1 2 3 4 6 8 9 10 11 12 14 15 180 192 203 5 202 I/O TYPE FUNCTION
I/O
Address/data bus. AD31-AD0 are the multiplexed PCI address and data bus. During the address phase of a PCI cycle, AD31-AD0 contain a 32-bit address or other destination information. During the data phase, AD31-AD0 contain data.
I/O
Bus commands and byte enables. C/BE3-C/BE0 are multiplexed on the same PCI terminals. During the address phase, C/BE3-C/BE0 define the bus command. During the data phase, C/BE3-C/BE0 are used as byte enables. The byte enables determine which byte lanes carry meaningful data. C/BE0 applies to byte 0 (AD7-AD0), C/BE1 applies to byte 1 (AD15-AD8), C/BE2 applies to byte 2 (AD23-AD16), and C/BE3 applies to byte 3 (AD31-AD24). Parity. As a PCI target during PCI read cycles, or as PCI bus master during PCI write cycles, the PCI1131 calculates even parity across the AD and C/BE buses and outputs the results on PAR, delayed by one clock.
I/O
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Terminal Functions (Continued) PCI interface control
TERMINAL NAME DEVSEL NO. 197 I/O TYPE I/O FUNCTION Device select. As a PCI target, the PCI1131 asserts DEVSEL to claim the current cycle. As a PCI master, the PCI1131 monitors DEVSEL until a target responds or a time-out occurs. Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an access, FRAME is low (asserted) to indicate that a bus transaction is beginning. While FRAME is asserted, data transfers continue. When FRAME is sampled high (deasserted), the transaction is in the final data phase. Grant. GNT is driven by the PCI arbiter to grant the PCI1131 access to the PCI bus after the current data transaction is complete. Initialization device select. IDSEL selects the PCI1131 during configuration accesses. IDSEL can be connected to one of the upper 24 PCI address lines. Initiator ready. IRDY indicates the bus master's ability to complete the current data phase of the transaction. IRDY is used with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled low (asserted). During a write, IRDY indicates that valid data is present on AD31-AD0. During a read, IRDY indicates that the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are low (asserted) at the same time. This signal is an output when the PCI1131 is the PCI bus master and an input when the PCI bus is the target. Interrupt request 10 and 12. IRQ10/CLKRUN and IRQ12/CLKRUN are software configurable and used by the PCI1131 to support the PCI clock run protocol. When configured as CLKRUN by setting bit 0 in the system control register offset 80h, this terminal is an open-drain output. To select between IRQ10 and IRQ12 as the output, use bit 7 of register 80h. Parity error. PERR is driven by the PCI target during a write to indicate that a data parity error has been detected. Request. REQ is asserted by the PCI1131 to request access to the PCI bus as a master. System error. SERR pulsed from the PCI1131 indicates an address parity error has occurred. Stop. STOP is driven by the current PCI target to request the master to stop the current transaction. Target ready. TRDY indicates the ability of the PCI1131 to complete the current data phase of the transaction. TRDY is used with IRDY. A data phase is completed on any clock where both TRDY and IRDY are sampled asserted. During a read, TRDY indicates that valid data is present on AD31-AD0. During a write, TRDY indicates that the PCI1131 is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted together. This signal is an output when the PCI1131 is the PCI target and an input when the PCI1131 is the PCI bus master.
FRAME
193
I/O
GNT IDSEL
168 182
I I
IRDY
195
I/O
IRQ10/CLKRUN IRQ12/CLKRUN
159 161
I/O
PERR REQ SERR STOP
199 169 200 198
I/O O O I/O
TRDY
196
I/O
power supply
TERMINAL NAME GND VCC VCCA VCCB VCCP NO. 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207 7, 31, 64, 86, 113, 143, 164, 175, 187, 201 120 38 148, 172 Device ground terminals Power supply terminal for core logic (3.3 V) Power supply terminal for PC Card A (5 V or 3.3 V) Power supply terminal for PC Card B (5 V or 3.3 V) Power supply terminal for PCI interface (5 V or 3.3 V) FUNCTION
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
Terminal Functions (Continued) PC Card power switch
TERMINAL NAME CLOCK DATA LATCH NO. 151 152 150 I/O TYPE O O O FUNCTION Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. The frequency of the clock is derived from dividing PCICLK by 36. The maximum frequency of CLOCK is 2 MHz. Power switch data. DATA is used by the PCI1131 to serially communicate socket power control information. Power switch latch. LATCH is asserted by the PCI1131 to indicate to the PC Card power switch that the data on the DATA line is valid.
interrupt
TERMINAL NAME NO. I/O TYPE FUNCTION Interrupt request 3 and interrupt request 4. IRQ3/INTA-IRQ4/INTB can be connected to either PCI or ISA interrupts. IRQ3/INTA-IRQ4/INTB are software configurable as IRQ3 or INTA and as IRQ4 or INTB. When configured for IRQ3 and IRQ4, IRQ3/INTA-IRQ4/INTB must be connected to the ISA IRQ programmable interrupt controller. When IRQ3/INTA-IRQ4/INTB are configured for INTA and INTB, IRQ3/INTA-IRQ4/INTB must be connected to interrupts on the PCI bus. Interrupt request 7. IRQ7/PCDMAREQ is software configurable and is used by the PCI1131 to request PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When IRQ7/PCDMAREQ is configured for PC/PCI DMA request (IRQ7), it must be connected to the appropriate request (REQ) pin on the Intel Mobile Triton PCI I/O accelerator (MPIIXTM). Interrupt request 9/serial IRQ. IRQ9/IRQSER is software configurable and indicates an interrupt request from a PC Card to the PCI1131. When IRQ9/IRQSER is configured for IRQ9, it must be connected to the system programmable interrupt controller. IRQSER allows all IRQ signals to be serialized onto one pin. IRQ9/IRQSER is configured via bits 2-1 in the device control register of the TI extension registers. Interrupt request 10 and 12. IRQ10/CLKRUN and IRQ12/CLKRUN are software configurable and used by the PCI1131 to support the PCI clock run protocol. When configured as CLKRUN by setting bit 0 in the system control register offset 80h, this terminal is an open-drain output. To select between IRQ10 and IRQ12 as the output, use bit 7 of register 80h. Interrupt request 11. IRQ11/PCDMAGNT is software configurable and is used by the PCI1131 to accept a grant for PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When IRQ11/PCDMAGNT is configured for PC/PCI DMA grant (IRQ11), it must be connected to the appropriate grant (GNT) pin on the Intel MPIIX controller. Interrupt request 5 and 14. These signals are ISA interrupts. These terminals indicate an interrupt request from one of the PC Cards. The interrupt mode is selected in the device control register of the TI extension registers. Interrupt request 15. IRQ15/RI_OUT indicates an interrupt request from one of the PC Cards. RI_OUT allows the RI input from the 16-bit PC Card to be output to the system. IRQ15/RI_OUT is configured in the card control register of the TI extension registers.
IRQ3/INTA IRQ4/INTB
154 155
O
IRQ7/PCDMAREQ
157
O
IRQ9/IRQSER
158
O I/O
IRQ10/CLKRUN IRQ12/CLKRUN
159 161
I/O
IRQ11/PCDMAGNT
160
I/O
IRQ5 IRQ14
156 162
O
IRQ15/RI_OUT
163
I/O
speaker control
TERMINAL NAME SPKROUT/ SUSPEND NO. 149 I/O TYPE O FUNCTION Speaker. SPKROUT carries the digital audio signal from the PC Card. SUSPEND places the PCI1131 in suspend mode. SPKROUT/SUSPEND is configured in the card control register of the TI extension registers.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
Terminal Functions (Continued) 16-bit PC Card address and data (slots A and B)
TERMINAL NUMBER NAME A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SLOT A 121 118 116 114 111 109 107 105 103 112 115 108 106 117 100 95 102 104 119 123 125 126 128 131 132 133 93 91 89 87 84 147 145 142 92 90 88 85 83 146 144 141 SLOT B 55 53 51 49 47 45 42 40 37 48 50 43 41 52 34 29 36 39 54 57 59 60 62 65 66 67 27 25 23 20 18 81 79 77 26 24 21 19 17 80 78 76 I/O TYPE FUNCTION
O
PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.
I/O
PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.
Terminal name is preceded with A_. For example, the full name for terminal 121 is A_A25. Terminal name is preceded with B_. For example, the full name for terminal 55 is B_A25.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
Terminal Functions (Continued) 16-bit PC Card interface control signals (slots A and B)
TERMINAL NUMBER NAME SLOT A SLOT B I/O TYPE FUNCTION
BVD1 (STSCHG/RI)
138
72
I
Battery voltage detect 1. Generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate ring detection. Battery voltage detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B can be combined by the PCI1131 and output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts BVD2 to request a DMA operation. PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts INPACK to indicate a request for a DMA operation. I/O read. IORD is asserted by the PCI1131 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1131 asserts IORD during DMA transfers from the PC Card to host memory. I/O write. IOWR is driven low by the PCI1131 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA read strobe during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts IOWR during DMA transfers from host memory to the PC Card. Output enable. OE is driven low by the PCI1131 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts OE to indicate TC for a DMA write operation.
BVD2(SPKR)
137
71
I
CD1 CD2 CE1 CE2
82 140 94 97
16 74 28 30
I
O
INPACK
127
61
I
IORD
99
33
O
IOWR
101
35
O
OE
98
32
O
Terminal name is preceded with A_. For example, the full name for terminal 138 is A_BVD1. Terminal name is preceded with B_. For example, the full name for terminal 72 is B_BVD1.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
Terminal Functions (Continued) 16-bit PC Card interface control signals (slots A and B) (continued)
TERMINAL NUMBER NAME SLOT A SLOT B I/O TYPE FUNCTION
READY(IREQ)
135
69
I
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts REG to indicate a DMA operation. REG is used with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. PC Card reset. RESET forces a hard reset to a 16-bit PC Card. Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE also is used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts WE to indicate TC for a DMA read operation. Write protect. This signal applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. The status of WP can be read from the ExCA interface status register. I/O is 16 bits. WP applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to request a DMA operation. Voltage sense 1 and voltage sense 2. VS1 and VS2, when used together, determine the operating voltage of the 16-bit PC Card.
REG
130
63
O
RESET WAIT
124 136
58 70
O I
WE
110
46
O
WP(IOIS16)
139
73
I
VS1 VS2
134 122
68 56
I/O
Terminal name is preceded with A_. For example, the full name for terminal 98 is A_OE. Terminal name is preceded with B_. For example, the full name for terminal 32 is B_OE.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
Terminal Functions (Continued) CardBus PC Card address and data signals (slots A and B)
TERMINAL NUMBER NAME CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 CC/BE0 CC/BE1 CC/BE2 CC/BE3 SLOT A 147 145 144 142 141 133 132 131 128 126 125 123 121 119 118 103 101 102 99 100 98 97 95 93 92 89 90 87 88 84 85 83 94 104 117 130 SLOT B 81 79 78 77 76 67 66 65 62 60 59 57 55 54 53 37 35 36 33 34 32 30 29 27 26 23 24 20 21 18 19 17 28 39 52 63 I/O TYPE FUNCTION
I/O
CardBus PC Card address and data. CAD31-CAD0 are multiplexed address and data signals. A bus transaction consists of an address phase followed by one or more data phases. The PCI1131 supports both read and write bursts. The address phase is the clock cycle in which CFRAME is asserted. During the address phase, CAD31-CAD0 contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a DWORD address. During data phases, CAD7-CAD0 contain the least-significant byte and CAD31-CAD24 contain the most-significant byte. Write data is stable and valid when CIRDY is asserted. Read data is stable and valid when CTRDY is asserted. Data is transferred during those clocks when CIRDY and CTRDY are asserted.
I/O
CardBus PC Card command and byte enables. CC/BE0-CC/BE3 are multiplexed on the same pin. During the address phase of the transaction, CC/BE3-CC/BE0 define the bus command. During the data phase transaction, CC/BE3-CC/BE0 are used as byte enables. Byte enables are valid during the entire data phase and determine the byte lanes that carry the data. CC/BE0 applies to byte 0, CC/BE1 applies to byte 1, CC/BE2 applies to byte 2, and CC/BE3 applies to byte 3. CardBus PC Card parity. Even parity across CAD31-CAD0 and CC/BE3-CC/BE0 is calculated and driven by this signal. CPAR is stable and valid for one clock after the address phase. For data phases, CPAR is stable and valid one clock after either CIRDY is asserted on a write transaction or CTRDY is asserted on a read transaction. Once CPAR is valid, it remains valid for one clock after the completion of the current data phase. NOTE: CPAR has the same timing as CAD31-CAD0 but delays by one clock. When the PCI1131 is acting as an initiator, it drives CPAR for address and write data phases; and when acting as a target, the PCI1131 drives CPAR for read data phases.
CPAR
106
41
I/O
Terminal name is preceded with A_. For example, the full name for terminal 147 is A_CAD31. Terminal name is preceded with B_. For example, the full name for terminal 81 is B_CAD31.
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Terminal Functions (Continued) CardBus PC Card interface system signals (slots A and B)
TERMINAL NUMBER NAME SLOT A SLOT B I/O TYPE FUNCTION
CCLK
112
48
O
CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus PC Card interface. All signals except CRST (upon assertion) CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2-CCD1, and CVS2-CVS1 are sampled on the rising edge of the clock, and all timing parameters are defined with the rising edge of CCLK. The CardBus clock operates at 33 MHz but can be stopped in the low state. CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency. It is used by the PCI1131 to indicate that the CCLK frequency is decreased. CardBus PC Card reset. CRST is used to bring CardBus PC Card specific registers, sequencers, and signals to a consistent state. When CRST is asserted, all CardBus PC Card signals must be driven to the high-impedance state. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.
CCLKRUN
139
73
I/O
CRST
124
58
O
CardBus PC Card interface control signals (slots A and B)
TERMINAL NUMBER NAME SLOT A SLOT B I/O TYPE FUNCTION
CAUDIO
137
71
I
CardBus audio. CAUDIO is an optional digital output signal from a PC Card to the system speaker. CardBus cards support two types of audio: single amplitude, binary waveform and/or pulsewidth modulation (PWM) encoded signal. The PCI1131 supports the binary audio mode and can output a binary audio signal from the PC Card to SPKROUT. CardBus lock. CBLOCK is an optional signal used to lock a particular address, ensuring a bus initiator exclusive access. This signal is not supported on the PCI1131. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used with CVS1 and CVS2 to determine the type and voltage of the CardBus PC Card. CardBus device select. When actively driven, CDEVSEL indicates that the PCI1131 has decoded its address as the target of the current access. As an input, CDEVSEL indicates whether any device on the bus has been selected. CardBus cycle frame. CFRAME is driven by the PCI1131 or a CardBus card when it is acting as an initiator to indicate the beginning and duration of a transaction. CFRAME is asserted to indicate a bus transaction is beginning, and while it is asserted, data transfer is continuous. When CFRAME is high (deasserted), the transaction is in its final data phase. CardBus grant. CGNT is driven by the PCI1131 to grant a CardBus PC Card access to the CardBus bus after the current data transaction is complete. CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.
CBLOCK CCD1 CCD2 CDEVSEL
107 82 140 111
42 16 74 47
I/O I
I/O
CFRAME
116
51
I/O
CGNT CINT
110 135
46 69
O I
Terminal name is preceded with A_. For example, the full name for terminal 112 is A_CCLK. Terminal name is preceded with B_. For example, the full name for terminal 48 is B_CCLK.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
Terminal Functions (Continued) CardBus PC Card interface control signals (slots A and B) (continued)
TERMINAL NUMBER NAME SLOT A SLOT B I/O TYPE FUNCTION
CIRDY
115
50
I/O
CardBus initiator ready. CIRDY indicates that the PCI1131 is initiating the ability of the bus initiator to complete a current data phase of the transaction. It is used with CTRDY. When both CIRDY and CTRDY are sampled asserted, a data phase is completed on any clock. During a write, CIRDY indicates that valid data is present on CAD31-CAD0. During a read, CIRDY indicates the PCI1131, as an initiator, is prepared to accept the data. Wait cycles are inserted until CIRDY and CTRDY are both low (asserted). CardBus parity error. CPERR reports errors during all CardBus PC Card transactions except during special cycles. CPERR is sustained in the high-impedance state and must be driven active by the agent receiving data, two clocks following the data, when a data parity error is detected. CPERR must be driven active for a minimum duration of one clock for each data phase. CPERR must be driven high for one clock before it is returned to the high-impedance state. An agent cannot report a CPERR until it claims the access by asserting CDEVSEL and completes a data phase. CardBus request. CREQ indicates to the arbiter that the CardBus PC Card requires use of the CardBus bus. CardBus system error. CSERR reports address parity error, data errors on the special cycle command, or any other system error such that the CardBus card can no longer operate correctly. CSERR is open drain and is actively driven for a single CardBus PC Card clock by the agent reporting the error. The assertion of CSERR is synchronous to the clock and meets the setup and hold times of all bused signals. Restoring CSERR to the deasserted state is accomplished by a weak pullup provided by the system designer. This pullup can take two to three clock periods to fully restore CSERR. The PCI1131 reports CSERR to the operating system any time it is sampled low (asserted). CardBus stop. CSTOP indicates the current target is requesting the initiator to stop the current transaction. CardBus status change. CSTSCHG is used to alert the system to a change in the READY, WP, or BVD condition of the I/O CardBus PC Card. CardBus target ready. CTRDY indicates that the PCI1131, as a selected target, can complete a current data phase of the transaction. CTRDY is used with CIRDY. When both of these signals are sampled asserted, a data phase is completed on any clock. During a read, CTRDY indicates that valid data is present on CAD31-CAD0. During a write, CIRDY indicates the PCI1131, as a target, is prepared to accept the data. Wait cycles are inserted until CIRDY and CTRDY are both low (asserted). CardBus voltage sense 1 and voltage sense 2. CVS1 and CVS2, together with CCD1 and CCD2, g g ,g , determine the operating voltage of the CardBus PC Card.
CPERR
108
43
I/O
CREQ
127
61
I
CSERR
136
70
I
CSTOP CSTSCHG
109 138
45 72
I/O I
CTRDY
114
49
I/O
CVS1 CVS2
134 122
68 56
I/O
Terminal name is preceded with A_. For example, the full name for terminal 115 is A_CIRDY. Terminal name is preceded with B_. For example, the full name for terminal 50 is B_CIRDY.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
absolute maximum ratings over operating temperature ranges (unless otherwise noted)
Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Input voltage range, VI: Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCB + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO: Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCB + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies to external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. 2. Applies to external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals.
recommended operating conditions
MIN tt TA TJ Input transition (rise and fall) time Operating ambient temperature CMOS compatible Commercial 0 0 25 NOM MAX 25 70 115 UNIT ns C C
Commercial 0 25 Virtual junction temperature These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
recommended operating conditions for PCI interface
OPERATION VCC VCCP VI VO Core voltage PCI supply voltage Input voltage Commercial Commercial 3.3 V 3.3 V 5V 3.3 V 5V 3.3 V Output voltage CMOS compatible High-level input voltage g g Fail safe# VIL CMOS compatible Fail safe# Applies to external output buffers Applies to external input and bidirectional buffers without hysteresis # Fail-safe pins are 16, 56, 68, 72, 74, 82, 122, 134, 138, 140, 149, and 152. 5V 3.3 V 5V 3.3 V 3.3 V Low-level input voltage 5V 3.3 V MIN 3 3 4.75 0 0 0 0 0.5 VCCP 2 0.5 VCC 0.3 VCCP 0.8 0.3 VCC V V NOM 3.3 3.3 5 MAX 3.6 3.6 5.25 VCCP VCCP VCCP VCCP UNIT V V V V
VIH
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
recommended operating conditions for PC Cards A and B and miscellaneous inputs and outputs
OPERATION VCC(A/B) VI VO PC Card supply voltage Commercial 3.3 V 5V 3.3 V 5V Out ut Output voltage 3.3 V 5V CMOS compatible VIH High-level input voltage Fail safe 3.3 V 5V 3.3 V 3.3 V 5V Fail safe Applies to external output buffers Applies to external input and bidirectional buffers without hysteresis Fail-safe pins are 16, 56, 68, 72, 74, 82, 122, 134, 138, 140, 149, and 152. Meets TTL levels, VIH MIN =1.65 V and VIL MAX = 0.99 V 3.3 V MIN 3 4.75 0 0 0 0 0.475 VCC(A/B) 2.4 0.475 VCC(A/B) 0.325 VCC(A/B) 0.8 0.325 VCC(A/B) V V NOM 3.3 5 MAX 3.6 5.25 VCC(A/B) VCC(A/B) VCC(A/B) VCC(A/B) V V UNIT V
In ut Input voltage
CMOS compatible VIL Low-level input voltage
16
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER PCI VOH High-level output voltage PC Card Miscellaneous PCI SIDE TEST CONDITIONS IOH = -0.5 mA IOH = -2 mA IOH = -0.15 mA IOH = -0.15 mA IOH = -4 mA IOL = 1.5 mA IOL = 6 mA IOL = 0.7 mA IOL = 0.7 mA IOL = 4 mA IOL = 12 mA VI = VCC VI = VCC VI = VCC VI = VCC VI = VCC VI = VCCP VI = GND VI = GND 3.6 V 5.25 V 3.6 V 5.25 V 3.6 V 3.3 V 5V 3.3 V 5V OPERATION 3.3 V 5V 3.3 V 5V MIN 0.9 VCC 2.4 0.9 VCC 2.4 2.1 0.1 VCC 0.55 0.1 VCC 0.55 0.5 0.5 10 20 10 25 10 290 -1 -10 A A V V MAX UNIT
VOL
Low level output voltage Low-level
PC Card Miscellaneous SERR Input pins
IIH
High le el input current High-level inp t c rrent
I/O pins# Fail safe DATA Input pins I/O pins
IIL
Low-level Low level input current
VOH is not tested on SERR (pin 200) due to open-drain output. Miscellaneous pins are 150, 151, 156, 157, 159, 160, 161, 162, 163. IIL is not tested on DATA (pin 152) due to internal pulldown resistor, and IIH is not tested on SPKROUT (pin 149) due to internal pullup resistor. For PCI and miscellaneous pins, VCC = VCCP. For card A/B, VCC = VCCA/VCCB, respectively. # For I/O pins, the input leakage current includes the off-state output current IOZ.
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 2 and Figure 3)
ALTERNATE SYMBOL tc twH twL v/t tw tsu Cycle time, PCLK Pulse duration, PCLK high Pulse duration, PCLK low Slew rate, PCLK Pulse duration, RSTIN Setup time, PCLK active at end of RSTIN tcyc thigh tlow tr, tf trst trst-clk MIN 30 11 11 1 1 100 4 MAX UNIT ns ns ns V/ns ms
ms
PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 3, Figure 1, and Figure 4)
TEST CONDITIONS PCLK to shared signal valid delay time PCLK to shared signal invalid delay time CL = 50 pF, See Note 4 CL = 50 pF, See Note 4 ALTERNATE SYMBOL tval tinv ton toff tsu th 7 0 2 2 28 ns ns ns ns MIN MAX 11 ns UNIT
tpd d
Propagation delay time
ten tdis tsu th
Enable time, high-impedance-to-active delay time from PCLK Disable time, active-to-high-impedance delay time from PCLK Setup time before PCLK valid Hold time after PCLK high
NOTES: 3. This data sheet uses the following conventions to describe time (t) intervals. The format is: tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 4. PCI shared signals are AD31-AD0, C/BE3-C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
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PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD (pF) 50 50 50 IOL (mA) 8 8 8 IOH (mA) -8 -8 -8 VLOAD (V) 0 3 1.5 From Output Under Test Test Point VLOAD CLOAD IOH IOL
CLOAD includes the typical load-circuit distributed capacitance. VLOAD - VOL = 50 , where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT Timing Input (see Note A) tsu Data Input 90% VCC 10% VCC tr 50% VCC VCC 50% VCC 0V th VCC 50% VCC tf 0V Low-Level Input tw 50% VCC High-Level Input 50% VCC
VCC 50% VCC 0V
VCC 50% VCC 0V
VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES Output Control (low-level enabling) tPZL 0V tpd In-Phase Output tpd Out-of-Phase Output 50% VCC 50% VCC tpd VOH 50% VCC VOL tpd VOH 50% VCC VOL Waveform 1 (see Note B) tPZH Waveform 2 (see Note B)
VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC 50% VCC 0V tPLZ VCC 50% VCC VOL + 0.3 V VOL VOH VOH - 0.3 V 50% VCC 0V
Input (see Note A)
VCC 50% VCC 50% VCC
50% VCC tPHZ
50% VCC
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 , tr 6 ns, tf 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values.
Figure 1. Load Circuit and Voltage Waveforms
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
PCI BUS PARAMETER MEASUREMENT INFORMATION
twH 2V 0.8 V tr tc tf twL 2 V MIN Peak to Peak
Figure 2. PCLK Timing Waveform
PCLK
tw RSTIN tsu
Figure 3. RSTIN Timing Waveforms
PCLK
1.5 V tpd tpd Valid toff Valid tsu th
PCI Output
1.5 V ton
PCI Input
Figure 4. Shared-Signals Timing Waveforms
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
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PC Card cycle timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. The PC Card address setup and hold times are a function of the wait-state bits. Table 1 shows address setup time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 2 and Table 3 show command active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 4 shows address hold time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 1. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles
WAIT-STATE BITS I/O Memory Memory WS1 WS1 0 1 TS1 - 0 = 01 (PCLK/ns) 3/90 2/60 4/120
Table 2. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles
WAIT-STATE BITS WS 0 I/O 1 0 00 01 Memory 10 11 00 ZWS 0 X 1 0 X X X 1 TS1 - 0 = 01 (PCLK/ns) 19/570 23/690 7/210 19/570 23/690 23/690 23/690 7/210
Table 3. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles
WAIT-STATE BITS WS 0 I/O 1 0 00 01 Memory 10 11 00 ZWS 0 X 1 0 X X X 1 TS1 - 0 = 01 (PCLK/ns) 7/210 11/330 N/A 9/270 13/390 17/510 23/630 5/150
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
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Table 4. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles
WAIT-STATE BITS I/O Memory Memory WS1 WS1 0 1 TS1 - 0 = 01 (PCLK/ns) 2/60 2/60 3/90
timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see Note 5 and Figure 5)
ALTERNATE SYMBOL tsu tsu tsu tpd tw th th tsu th th tsu th Setup time, CE1 and CE2 before WE/OE low Setup time, CA25-CA0 before WE/OE low Setup time, REG before WE/OE low Propagation delay time, WE/OE low to WAIT low Pulse duration, WE/OE low Hold time, WE/OE low after WAIT high Hold time, CE1 and CE2 after WE/OE high Setup time (read), CDATA15-CDATA0 valid before OE high Hold time (read), CDATA15-CDATA0 valid after OE high Hold time, CA25-CA0 and REG after WE/OE high Setup time (write), CDATA15-CDATA0 valid before WE low Hold time (write), CDATA15-CDATA0 valid after WE low T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 0 th(A)+1PCLK 60 240 120 200 MIN 60 tsu(A)+2PCLK 90 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns
NOTE 5: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.
timing requirements over recommended ranges of supply voltage and operating free-air temperature, I/O cycles (see Figure 6)
ALTERNATE SYMBOL tsu tsu tsu tpd tpd tw th th th th tsu th tsu th Setup time, REG before IORD/IOWR low Setup time, CE1 and CE2 before IORD/IOWR low Setup time, CA25-CA0 valid before IORD/IOWR low Propagation delay time, IOIS16 low after CA25-CA0 valid Propagation delay time, IORD low to WAIT low Pulse duration, IORD/IOWR low Hold time, IORD low after WAIT high Hold time, REG low after IORD high Hold time, CE1 and CE2 after IORD/IOWR high Hold time, CA25-CA0 after IORD/IOWR high Setup time (read), CDATA15-CDATA0 valid before IORD high Hold time (read), CDATA15-CDATA0 valid after IORD high Setup time (write), CDATA15-CDATA0 valid before IOWR low Hold time (write), CDATA15-CDATA0 valid after IOWR high T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 0 120 th(A)+1PCLK 10 0 90 90 35 TcA MIN 60 60 tsu(A)+2PCLK 35 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see Figure 7)
PARAMETER BVD2 low to SPKROUT low tpd d Propagation delay time BVD2 high to SPKROUT high IREQ to IRQ15-IRQ3 STSCHG to IRQ15-IRQ3 ALTERNATE SYMBOL T27 T28 MIN MAX 30 30 30 30 ns UNIT
PC Card PARAMETER MEASUREMENT INFORMATION
CA25-CA0 T10 REG
CE1, CE2 T1 WE, OE T2 WAIT T11 CDATA15-CDATA0 (write) T8 T9 CDATA15-CDATA0 (read) With no wait state With wait state T12 T3 T4 T6 T5 T7
Figure 5. PC Card Memory Cycle
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23
PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
PC Card PARAMETER MEASUREMENT INFORMATION
CA25-CA0 T16 IOIS16 T22
REG T20 CE1, CE2 T14 IORD, IOWR T13 T15 T18 T21
T17
T19
WAIT T25 CDATA15-CDATA0 (write) T23 T24 CDATA15-CDATA0 (read) With no wait state With wait state T26
Figure 6. PC Card I/O Cycle
BVD2 T27 SPKROUT
IREQ T28 IRQ15-IRQ3
Figure 7. Miscellaneous PC Card Delay Times
24
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
PCI1131 PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 - DECEMBER 1997
MECHANICAL DATA
PDV (S-PQFP-G208)
156 105
PLASTIC QUAD FLATPACK
157
104
0,27 0,17
0,08 M
0,50
0,13 NOM 208 53
1 25,50 TYP 28,05 SQ 27,95 30,10 SQ 29,90 1,45 1,35
52
Gage Plane 0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 0,08 1,60 MAX 4087729/B 06/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136
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25
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Copyright (c) 1998, Texas Instruments Incorporated

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