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Video Camera LSIs
MN6732741
Signal-processing IC for surveillance cameras and cameras for PC input
I Overview
The MN6732741 is camera signal-processing IC appropriate for a wide variety of applications, including surveillance cameras and cameras used for input to personal computers. In addition to the basic functions of luminance and chrominance signal processing, it also integrates the ALC, AWB, and AGC functions that were previously implemented using microcontroller signal processing. Furthermore, it also integrates on a single chip, including SSG, CG, and I2C-bus functions.
I Features
* Input: * Outputs: Analog signal (A/D converter input) Digital output 8-bit YUV signal Analog outputs Luminance signal Chrominance signal Composite video signal output RGB output * Operating supply voltage: 3.3 V 0.3 V * Operating clock frequency: 9.5 MHz to 28.7 MHz * Main functions * 10-bit A/D converter * Single-channel 10-bit D/A converter * Two-channel 8-bit D/A converter * Supports analog AGC (NN2038 or NN2039) * CG and SSG circuits * Supports 510 and 768 horizontal lines (NTSC and PAL) * Supports VGA progressive scan readout CCDs (complementary color filters) * Also supports black-and-white CCD signal processing * CCD white defect/black defect correction circuit * Digital AGC gain: up to 24 dB * Left/right reversing function * Variable gamma correction ( = 0.3 to 1) * ZV port standard mode, BT656 standard mode * Modes: LL, SYNC, VD2, and HD/VD external synchronization support * Built-in I2C-bus circuit * ALC and AGC (Also supports external AGC) * Two white balance modes (manual and ATW) with ATW lock function * Automatic OB correction function
I Applications
* Surveillance cameras, PC input cameras, multimedia cameras
Publication date: August 2001
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I Block Diagram
YUVOE
Y VIN 10-bit A/D AGC Luminance processing Y/C MPX 10-bit D/A C Chrominance processing ENC 8-bit D/A
YUV0 to YUV7
Y COMP output G
RGB CNV WB gain Horizontal drive pulse output
(2-ch) R C output, B
Register R/W for each block CG Carrier signal YLPF Digital AGC control ALC ATN SSG SUB control FCK 2FCK BLK CSYNC DATA I2C-bus WE RE control PWM PWM PWM PWM YUVOE SCL SDA PWM0 PWM1 PWM2 PWM3
Vertical system drive Sync system pulse output FCK 2FCK
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I Function Descriptions (by circuit block)
1. ADC Converts the post-CDS CCD signal to a 10-bit digital signal. 2. PATGEN Generates test pattern signals. This circuit generates horizontal and vertical patterns with a color bar (3 colors) format. Since it simulates the output of the CCD 4-color complementary color filters, it conveniently allows problems in the analog block, from the CCD to the A/D converter, and IC internal problems, to be isolated. It can also be used to temporarily halt CCD image output and generate a blue background signal. 3. AGC (AGC, pixel mixing, mirror reversal, and OB clamping functions) Performs AGC control (up to +24 dB) digitally by linking with the ALC. Since the IC also provides an interface output to an external analog AGC (NN2038 or NN2039), over 24 dB of gain can be provided. When a VGA CCD is used, since progressive scan is used, the photodiode mixing operation used with earlier interlaced CCDs is not required. The AGC circuit includes an internal pixel mixing circuit, and is designed for both progressive and interlaced scan at the circuit level. In the mirror mode provided by 510 H and 768 H CCDs, it is possible to generate a reversed video signal by controlling RAM. OB correction is also performed in this block, and this function has both a digital mode, in which processing is performed internally to the IC, and an analog mode that controls the external CDS and AGC IC clamp voltage.
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I Function Descriptions (by circuit block) (continued)
4. ALC The ALC block controls the exposure electronically by inputting the luminance signal, taking an averaged but center weighted exposure reading over the whole image, and comparing that to the target value. That result is used to control the CCD's electronic shutter. In ELC mode, since the step size of the electronic shutter accumulation time is discrete, the AGC system is used in conjunction with the ALC function to create a smoothly operating control system. This block also performs a 3field averaging flicker correction operation as well. 5. Luminance system After generating the luminance signal from the complementary color filter CCD output using a low-pass filter, this block generates the horizontal and vertical aperture signals and performs coring/low-luminance suppression, gamma correction, and blanking processing. This block includes a defect correction circuit that corrects for defective pixels in the CCD. One of two outline correction levels can be selected with the APGAIN pin. The IC also includes a defect correction circuit that corrects for missing pixels in the CCD. The gamma correction is continuously variable from = 0.3 to 1. The luminance signal low-pass filter can be bypassed to allow this device to handle black-and-white CCDs. 6. Chrominance system This block performs white balance processing, carrier balance, color temperature correction, and low-luminance/ high-luminance chrominance suppression processing. 7. AWB This block generates the auto white balance control signal. This white balance function operates so that the state of the immediately prior and proper illumination level will be held in case of low illumination levels. 8. ENC This block converts between NTSC and PAL. A digital technique in which 4fSC is created from FSC is adopted, and the clock system is unified into a single system. To create the composite video signal, clock rate conversion is also applied to the Y signal and the signals are mixed digitally. The sync signal can also be mixed digitally. 9. RGBCNV The YUV signal generated from the luminance and chrominance signals is converted to RGB using a matrix. However, since the band of the UV signal is dropped to around 800 kHz at a relatively early stage relative to the chrominance signal, this is not a signal in which all three channels have the same wide band as the Y signal, such as the signals used in 3-CCD video cameras. 10. YCMPX This block takes the FCK rate luminance and UV signals and outputs them as an 8-bit time-division multiplexed signal with a 2FCK rate. In BT656 standard mode, SAV and EAV are embedded in the signal. 11. D/A converters One D/A converter block converts the digital input to analog output. There are three channels, and one channel with a 10-bit resolution is provided for each of the composite, Y, and G signals. The circuit is designed so that the sync can be mixed digitally. The remaining D/A converter is a two-channel 8-bit device used for the chrominance, R, and B signals. 12. PWM Provides an independently controllable 4-channel PWM output circuit that can be used to control analog circuits peripheral to the IC. These outputs can be used, for example, for VREF adjustment of D/A converter. 13. CG This circuit generates the high-speed pulse signals (H1, H2, DS1, and DS2) used by the CCD. This block's logic system power supply is isolated from the other IC internal logic circuits to minimize noise.
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I Function Descriptions (by circuit block) (continued)
14. SSG This block generates both low-speed pulse signals used by the CCD and various kinds of pulse signals used for signal processing. (However, note that VBSGEN locking is not supported.) 15. I2C-bus When power is first applied, the contents of an external EEPROM are read out and used to set the IC internal registers. Since this circuit does not support multi-master operation, no external devices will have become bus master when power is first applied. This I2C-bus also can be used by external devices to read or write the IC internal registers. (Note that certain limitations apply.)
I Pin Arrangement
FCK2O FCKO VSS3 VDD3 YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 PWM3 PWM2 PWM1 PWM0 VSS2 VDD2 A2 A1 A0 SCL SDA RESET CCDSEL2 CCDSEL1 CCDSEL0 TEST0 TEST1 TEST2 TEST3 TEST4
COIN OBCTL EXTAGC IRIS ALCELC ATWLOCK APGAIN BLCSW DIN8 DIN7 DIN6 DIN5 DIN4 VDD4 VSS4 DIN3 DIN2 DIN1 DIN0 DS2 DS1 TESTDC2 TESTSW5 R N.C. TGVDD TGVSS N.C. H2 N.C. H1 N.C. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VIN VREFL VREFML ADVDD ADVSS VREFM VREFHM VREFH VREF23 IREF23 COMP23 BSIG DAVSS1 DAVDD1 RSIG VREF1 IREF1 COMP1 GSIG DAVSS2 DAVDD2 VCXO LPFI FVR MINTEST SCANT HREFCBLK VCSYNCVD YUVOE NTPL PCO EXTMOD
4
N.C. V4 V3 VSS5 VDD5 V2 N.C. V1 N.C. SUB N.C. CH2 N.C. CH1 OSCCNT CXIN CXOUT OSCVDD OSCVSS TESTDC1 WHD FVD FWHD CPOB PBLK HCLR LLDET FLC VDD1 VSS1 EXTIN0 EXTIN1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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I Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin N.C. V4 V3 VSS5 VDD5 V2 N.C. V1 N.C. SUB N.C. CH2 N.C. CH1 OSCCNT CXIN CXOUT OSCVDD OSCVSS TESTDC1 WHD FVD FWHD CPOB PBLK HCLR LLDET I/O O O VSS VDD O O O O O O I O VDD VSS I O O O O O O I V1 charge pulse Oscillator control test Synchronization oscillator (crystal oscillator) Synchronization oscillator (crystal oscillator) Oscillator cell power supply Oscillator cell ground Test input (Normally connect to low.) WHD signal that is in proper phase relative to the sync signal VD signal that is in proper phase relative to the sync signal WHD for TG drive A/D converter input signal clamp pulse, or D/A converter output clamp pulse Pre-blanking pulse Horizontal reference signal Power supply synchronization switching signal Low: internal synchronization, High: LL synchronization 28 29 30 31 32 33 34 35 FLC VDD1 VSS1 EXTIN0 EXTIN1 EXTMOD PCO NTPL I VDD VSS I I I O I Flicker correction (pulled up). High: Flicker correction on Digital system power supply (3.3 V) Digital system ground External sync signal input 1 External sync signal input 2 Monitor/automotive mode switch (pulled up) High: Automotive mode (HDVD/SYNC synchronization mode) Phase comparator output NTSC/PAL switching. Low: NTSC, High: PAL (pulled down) V3 charge pulse Vertical removal pulse V1 charge pulse V4 charge pulse V3 charge pulse Digital system ground Digital system power supply (3.3 V) V2 charge pulse Description
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I Pin Descriptions (continued)
Pin No. 36 37 38 39 40 41 42 43 44 45 46 Pin YUVOE VCSYNCVD HREFCBLK SCANT MINTEST FVR LPFI VCXO DAVDD2 DAVSS2 GSIG I/O I O O I I I I O VDD VSS O Description Digital output system output enable VCSYNC output/VD output (VGA mode CSYNC/IT mode register switching) HREF output/CBLK output (VGA mode HREF/IT mode register switching) Test input (Normally connect to low.) Test input (Normally connect to low.) Frequency control DC input Low-pass filter analog switch input Analog switch output. LC oscillator D/A converter power supply D/A converter ground Video signal output (composite/luminance signal/G signal) (Connect RL between this pin and DAVSS2.) 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 6 COMP1 IREF1 VREF1 RSIG DAVDD1 DAVSS1 BSIG COMP23 IREF23 VREF23 VREFH VREFHM VREFM ADVSS ADVDD VREFML VREFL VIN TEST4 TEST3 TEST2 TEST1 TEST0 CCDSEL0 CCDSEL1 I I I O VDD VSS O I I I I I I VSS VDD I I I I I I I I I I Phase compensation (Connect a 1 F capacitor between this pin and DAVSS2.) Bias current setting resistor connection (Connect RIREF between this pin and DAVSS2.) Reference voltage input Video signal output (R signal) D/A converter power supply D/A converter ground Video signal output (Chrominance signal/B signal) Phase compensation (Connect a 1 F capacitor between this pin and DAVSS1.) Bias current setting resistor connection (Connect RIREF between this pin and DAVSS1.) Reference voltage input High-level reference voltage input Mid-level reference voltage (Connect this pin to ADVSS through a capacitor.) Mid-level reference voltage (Connect this pin to ADVSS through a capacitor.) A/D converter ground A/D converter power supply Mid-level reference voltage (Connect this pin to ADVSS through a capacitor.) Low-level reference voltage input Analog signal input Test input (Normally connect to low.) Test input (Normally connect to low.) Test input (Normally connect to low.) Test input (Normally connect to low.) Test input (Normally connect to low.) CCD switching CCD switching
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I Pin Descriptions (continued)
Pin No. 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin CCDSEL2 RESET SDA SCL A0 A1 A2 VDD2 VSS2 PWM0 PWM1 PWM2 PWM3 YUV0 YUV1 YUV2 YUV3 YUV4 YUV5 YUV6 YUV7 VDD3 VSS3 FCKO FCK2O COIN OBCTL EXTAGC IRIS ALCELC ATWLOCK APGAIN BLCSW DIN8 DIN7 DIN6 DIN5 I/O I I I/O I/O I I I VDD VSS O O O O O O O O O O O O VDD VSS O O I O O O I I I I I I I I CCD switching Logic system initial reset I2C-bus (data) I2C-bus (clock) EEPROM address setting (pulled down) EEPROM address setting (pulled down) EEPROM address setting (pulled down) Digital system power supply (3.3 V) Digital system ground PWM signal output PWM signal output PWM signal output PWM signal output Digital Y/UV output (LSB) Digital Y/UV output Digital Y/UV output Digital Y/UV output Digital Y/UV output Digital Y/UV output Digital Y/UV output Digital Y/UV output (MSB) Digital system power supply (3.3 V) Digital system ground FCK output 2FCK output Synchronization oscillator cell (LC oscillator) OB automatic correction output External AGC control Mechanical iris fixation (PWM output) Fixed/ELC switching. Low: ELC, High: Fixed ATW/Stop. Low: Normal, High: ATWLOCK Aperture gain switching. Low: Register value High: One half of the register value Backlighting correction. Low: Normal, High: ATWLOCK Digital signal input (MSB) Digital signal input Digital signal input Digital signal input
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I Pin Descriptions (continued)
Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin DIN4 VDD4 VSS4 DIN3 DIN2 DIN1 DIN0 DS2 DS1 TESTDC2 TESTSW5 R N.C. TGVDD TGVSS N.C. H2 N.C. H1 N.C. I/O I VDD VSS I I I I O O I I O VDD VSS O O H2 transfer pulse H1 transfer pulse TG power supply TG ground Digital signal input Digital system power supply (3.3 V) Digital system ground Digital signal input Digital signal input Digital signal input Digital signal input (LSB) CDS pulse 1 CDS pulse 2 Test input (Normally connect to low.) Test input (Normally connect to low.) R pulse Description
I Electrical Characteristics
1. Absolute Maximum Ratings Parameter Supply voltage (digital) Supply voltage (analog) Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Symbol VDD AVDD VI VO IO PD Topr Tstg Rating - 0.3 to +4.6 - 0.3 to +4.6 - 0.3 to VDD+0.3 - 0.3 to VDD+0.3 48 750 -20 to +70 -55 to +150 Unit V V V V mA mW C C
Note) 1. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Operation is not guaranteed within these ranges. 2. Always apply the identical potential to the following pins: VDD1, VDD2, VDD3, VDD4, VDD5, VDDTG, ADVDD, DAVDD1, and DAVDD2. Always apply the identical potential to the following pins: VSS1, VSS2, VSS3, VSS4, VSS5, VSSTG, ADVSS, DAVSS1, and DAVSS2.
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I Electrical Characteristics (continued)
2. Recommended Operating Conditions at VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V Parameter Supply voltage (digital) Symbol VDD Condition Digital system power supply Min 3.0 3.0 3.0 9.5 Typ 3.3 3.3 3.3 3.3 3.3 Max 3.6 3.6 3.6 28.7 MHz V Unit V
TGVDD TG power supply OSCVDD Oscillator power supply Supply voltage (analog) ADVDD A/D converter power supply DAVDD D/A converter power supply Operating frequency fosc duty 50%
3. DC Characteristics at VDD = TGVDD = OSCVDD = 3.0 V to 3.6 V, ADVDD = DAVDD = 3.0 V to 3.6 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = -20C to +70C Parameter Operating supply current Symbol IDD Condition VDD = TGVDD = OSCVDD = 3.6 V, Min Typ 80 23 20 Max 120 33 40 Unit mA
DAIDD ADVDD = DAVDD = 3.6 V, ADIDD fCLK = 28.7 MHz, Ta = 25C
1) Input pins 1-1: Standard input pins LLDET, EXTIN0, EXTIN1, YUVOE, CCDSEL0 to CCDSEL2, RESET, COIN, ALCELC, ATWLOCK, APGAIN, BLCSW, DIN8 to DIN0, TESTDC2, TESTSW5 Input voltage High level Low level Input leakage current VIH VIL ILIPD VIH VIL ILIPD RPU1 VI = VDD VDD = 3.3 V, VI = VSS VI = VDD or VSS FLC, EXTMOD VDD x 0.8 0 -10 10 VDD x 0.8 0 VI = VSS VI = VDD -10 10 30 30 VDD VDD x 0.2 10 90 A k V VDD x 0.8 0 -5 VDD VDD x 0.2 5 A V
2) Input pins 1-2: Pulled-up input pins Input voltage High level Low level Input leakage current Pull-up resistance
3) Input pins 1-3: Pulled-down input pins Input voltage High level Low level Input leakage current Pull-down resistance VIH VIL ILIPD RPD1
TESTDC1, NTPL, SCANT, A0 to A2, MINTEST, TEST4 to TEST0 VDD VDD x 0.2 10 90 A k V
4) Output pins 1-1 V4 to V1, SUB, CH2, CH1, OSCCNT, WHD, CPOB, PBLK, HCLR, PCO, PWM0 to PWM3, OBCTL, EXTAGC, IRIS Output voltage High level Low level 5) Output pins 1-2 Output voltage VOH VOL IO = -1 mA IO = 1 mA IO = -2 mA IO = 2 mA VDD - 0.6 VDD - 0.6 0.4 0.4 V
YUV0 to YUV7 VOH VOL V
High level Low level
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I Electrical Characteristics (continued)
3. DC Characteristics at VDD = TGVDD = OSCVDD = 3.0 V to 3.6 V, ADVDD = DAVDD = 3.0 V to 3.6 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = -20C to +70C (continued) Parameter 6) Output pins 1-3 Output voltage Symbol Condition IO = -4 mA IO = 4 mA IO = -8 mA IO = 8 mA IO = -16 mA IO = 16 mA VDD = 3.0 V to 3.6 V Vref5 = 4.75 V to 5.25 V (Vref5 is an external reference voltage.) IO = 4 mA VO = VDD or VSS VDD = 3.3 V, with an external crystal VDD = 3.3 V VI (XI) = VDD or VSS VDD = 3.3 V VI = VSS , VO = VSS VDD = 3.3 V VI = VDD , VO = VDD Min VDD - 0.6 VDD - 0.6 VDD - 0.6 0.6 -10 15 0.73 -57.5 9.6 Typ 1.6 1.2 2.2 -23 24 Max 0.4 0.4 0.4 Unit VCSYNCVD, HREFCBLK VOH VOL V
High level Low level
7) Output pins 1-4 Output voltage
FVD, FWHD, FCKO, FCK2O VOH VOL V
High level Low level
8) Output pins 1-5 Output voltage
DS2, DS1, R, H2, H1 VOH VOL VT+ VT- VOL ILO fOSC RFB IOH IOL V
High level Low level
9) I/O pins 1 TTL Schmitt trigger input voltage
SDA, SCL Input threshold voltage 2.2 0.4 10 V A MHz k mA V
Output voltage
Low level
Output leakage current 10) Oscillator pins 1
CXIN, CXOUT 30 6.6 -9.2 60
Standard oscillator frequency Internal feedback resistance Output current High level Low level
4. AC Characteristics Parameter Input pins 2-1 CXIN tcyc dclk See figure 1 See figure 1 dclk = thi /tcyc 34.8 50 105.3 ns % Symbol Condition Min Typ Max Unit
Clock waveform Period Clock duty
tcyc thi Clock CLK Vclk /2 Figure 1. Clock waveform Vclk
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I Electrical Characteristics (continued)
5. A/D converter at VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25C Pins: VIN, VREFH, VREFL, VREFM, VREFML, VREFHM Parameter Symbol Condition Min Typ 330 2.5 0.5 440 5.0 2.0 Max Unit 1) A/D converter recommended operating conditions Analog input voltage Analog input pin capacitance High-level reference voltage Low-level reference voltage Reference resistance (VREFL to VREFH) VAIN CAI VREFH VREFL RREF VIN VIN VREFH VREFL VREFL fADCK = 14.3 MHz VREFH = 2.5 V VREFL = 0.5 V VREFH V pF V V
2) A/D converter characteristics Resolution Nonlinearity error Differential nonlinearity error Analog input dynamic range RES INL DNL VAIN 10 7.5 6.5 VREFH - VREFL bit LSB LSB V[p-p]
6. D/A converter at VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25C 1) Pins: VREF23, IREF23, COMP23, BSIG, RSIG Parameter (1) Symbol Condition RL = 75 RIREF23 = 820 Connected between COMP23 and AVDD. Connect output resistors between each of the BSIG and RSIG pins and AVSS. Connect this resistor between IREF23 and AVSS. Min Typ Max Unit D/A converter recommended operating conditions VREF CCOMP RL 1.37 1.0 75 V F
Reference voltage External phase compensation capacitor External output resistors
External bias current setting resistor (2)
RIREF
820
D/A converter characteristics RES INL DNL VOFS VOZS RL = 75 VREF23 = 1.37 V RIREF23 = 820 1.0 0 8 2.5 2.5 bit LSB LSB V V
Resolution Nonlinearity error Differential nonlinearity error Full-scale voltage Zero-scale voltage
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I Electrical Characteristics (continued)
6. D/A converter at VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25C (continued) 2) Pins: VREF1, IREF1, COMP1, GSIG Parameter Symbol Condition RL = 75 RIREF1 = 1.13 k Connect between COMP1 and AVDD. Connect an output resistor between GSIG and AVSS. Connect this resistor between IREF1 and AVSS. Min Typ Max Unit (1) D/A converter recommended operating conditions Reference voltage External phase compensation capacitor External output resistor External bias current setting resistor VREF CCOMP RL RIREF 1.5 1.0 75 1.13 V F k
(2) D/A converter characteristics Resolution Nonlinearity error Differential nonlinearity error Full-scale voltage Zero-scale voltage RES INL DNL VOFS VOZS RL = 75 VREF1 = 1.5 V RIREF1 = 1.13 k 1.0 0 10 2.5 2.5 bit LSB LSB V V
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I Application System Examples
1. Example A (Minimum configuration) * Internal synchronization * Composite video output
EEPROM
Color CCD
Vertical driver
CDS
MN6732741
75 driver
2. Example B * Internal synchronization * RGB output
EEPROM 75 driver Color CCD
Vertical driver
R G B
CDS
MN6732741
75 driver 75 driver
3. Example C (Surveillance camera) * External synchronization * YC output
EEPROM LL pulse Color CCD
Vertical driver
CDS AGC
MN6732741
YC mixer
75 driver VD2 separation
Analog switch
VCXO VCO
4. Example D (PC camera) * Internal synchronization * Digital output
EEPROM
Color CCD
Vertical driver
CDS
YUV MN6732741 8-bit
5. Example E * Internal synchronization * Y output
EEPROM
Black-andwhite CCD
Vertical driver
CDS
MN6732741
75 driver
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I Package Dimensions (Units: mm)
* LQFP128-P-1818C
20.000.20 18.000.10 96 97 65 64
(1.25)
128 1 (1.25) 0.50 32 0.200.05 33 0.10 M
1.400.10
18.000.10 20.000.20
0.150.05
0.10
Seating plane
0.100.10 1.70 max.
0.25
(1.00)
0 to 10 0.500.20 (0.60)
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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