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MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
I2C BUS Control 5-Input 2-Output AV Switch
Monolithic IC MM1313
Outline
This IC is a 5-input 2-output AV switch with I2C control, developed for use in televisions. Two outputs enable it to support two screens or "picture-in-picture".
Features
1. Serial control by I2C bus. 2. 5-inputs, 2-outputs. 3. Video and audio system switches can be controlled independently. 4. 6dB amplifier built in to video system. 5. Built-in Y/C MIX circuit. 6. Slave address can be changed : 90H or 92H. 7. Audio muting possible by external pin. 8. Maintains high impedance even when I2C BUS line (SDA, SCL) power supply is off. 9. Built-in 3 value discrimination function. 10.On-chip power ON reset function. 11.Two types of audio input impedance : 60k and 30k. MM1313AD : 60k MM1313BD : 30k 12.Supports 2-screen or P-IN-P TV.
Package
SDIP-42A (MM1313AD, MM1313BD)
Applications
1. Televisions 2. Other video equipment
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Equivalent Block Diagram
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Pin Function
Pin No. 41 1 7 13 27 3 9 31 5 11 29 Name MTV-V V1-V V2-V V3-V STV-V V1-Y V2-Y YIN1 V1-C V2-C CIN1 36 BIAS Internal equivalent circuit diagram Pin No. 33 22 32 24 Name LOUT1 LOUT2 ROUT1 ROUT2 Internal equivalent circuit diagram
42 2 8 14 25 40 4 10 16 26 34 23
MTV-L V1-L V2-L V3-L STV-L MTV-R V1-R V2-R V3-R STV-R VOUT1 VOUT2
19
SCL
20
SDA
37 39
YOUT1 COUT1
6 12 21 28
S1 S2 ADR Mute
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Absolute Maximum Ratings (Ta=25C)
Item Storage temperature Operating temperature Power supply voltage Allowable power dissipation Symbol TSTG TOPR VCC Pd Ratings -40~+125 -20~+75 12 850 Units C C V mW
Electrical Characteristics
Item Operating power supply voltage Current consumption VOUT1 output Voltage gain Frequency characteristics
(Ta=25C, VCC=9V) Measure Conditions (unless otherwise indicated, Min. Typ. Max. Units Measurement Circuit Figure 1) ment pin 8 9 10 V 38 VCC=9V, no signal, no load 40 52 mA TP1 TP1 TP1 Sine wave 1.0VP-P, 100kHz 5.5 Sine wave 1.0VP-P, 10MHz/100kHz -1.0 Vn-V : Staircase 1VP-P APL=10~90% Vn-Y : Staircase (luminance signal) 1VP-P -3 Vn-C : Chroma signal 0.3VP-P APL=10~90% Vn-V : Staircase 1VP-P APL=10~90% Vn-Y : Staircase (luminance signal) 1VP-P -3 Vn-C : Chroma signal 0.3VP-P APL=10~90% Sine wave 100kHz Maximum input for total higher 1.6 harmonic distortion factor < 1.0% Sine wave 1.0VP-P, 100kHz 5.5 Sine wave 1.0VP-P -1.0 10MHz/100kHz Vn-V : Staircase 1VP-P APL=10~90% Vn-Y : Staircase (luminance signal) 1VP-P -3 Vn-C : Chroma signal 0.3VP-P APL=10~90% Vn-V : Staircase 1VP-P APL=10~90% Vn-Y : Staircase (luminance signal) 1VP-P -3 Vn-C : Chroma signal 0.3VP-P APL=10~90% Sine wave 100kHz Maximum input for total higher 1.6 harmonic distortion factor < 1.0% Vn-Y : Sine wave 1.0VP-P, 100kHz YIN1 : Sine wave 2.0VP-P, 100kHz Vn-Y : Sine wave 1.0VP-P 10MHz/100kHz YIN1 : Staircase 2.0VP-P 10MHz/100kHz Vn-Y : Staircase 1VP-P APL=10~90% YIN1: Staircase 2VP-P APL=10~90% Vn-Y : Staircase 1VP-P APL=10~90% YIN1 : Staircase 2VP-P APL=10~90% 5.5 -0.5 -1.0 -1.0 -3 6.0 0 0 6.5 1.0 3 dB dB %
Symbol VCC ICC GV1 FV1 DGV1
Differential gain
Differential phase
DPV1
TP1
0
3
deg
Input dynamic range VOUT2 output Voltage gain Frequency characteristics
DV1 GV2 FV2
SG1~3 TP6 TP6
1.9 6.0 0 6.5 1.0
VP-P dB dB
Differential gain
DGV2
TP6
0
3
%
Differential phase
DPV2
TP6
0
3
deg
Input dynamic range YOUT1 output Voltage gain
DV2 GY1 GY2 FY1
SG1~3 TP2 TP2 TP2 TP2 TP2
1.9 6.0 0 0 0 0 6.5 0.5 1.0
VP-P
dB dB
Frequency characteristics FY2 DGY
1.0 3 %
Differential gain
Differential phase
DPY
TP2
-3
0
3
deg
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Item
Symbol DY1
Input dynamic range DY2 Output impedance COUT1 output Voltage gain ZOYC1 GC1 GC2 FC1 Frequency characteristics FC2 Differential gain Differential phase DGC DPC DC1 Input dynamic range DC2 Input impedance Output impedance LOUT1 output Voltage gain Frequency characteristics Total higher harmonic distortion Input dynamic range Output offset voltage ZIC ZOC1 GL11 GL12 FL1 THDL1 DL1 VOFFL1
Measure Conditions (unless otherwise indicated, Min. Typ. Max. Units Measurement Circuit Figure 1) ment pin Vn-Y : Sine wave 100kHz SG2 Maximum input for total higher 1.6 1.9 harmonic distortion factor < 1.0% VP-P VIN1 : Sine wave 100kHz SG4 Maximum input for total higher 3.2 3.8 harmonic distortion factor < 1.0% 50 TP3 TP3 TP3 TP3 TP3 TP3 SG3 SG5 Vn-C : Sine wave 1.0VP-P, 100kHz CIN1 : Sine wave 2.0VP-P, 100kHz Vn-C : Sine wave 1.0VP-P 10MHz/100kHz CIN1 : Sine wave 2.0VP-P 10MHz/100kHz CIN1 : Staircase 2VP-P APL=10~90% CIN1 : Staircase 2VP-P APL=10~90% Vn-C : Sine wave 100kHz Maximum input for total higher harmonic distortion factor < 1.0% CIN1: Sine wave 100kHz Maximum input for total higher harmonic distortion factor < 1.0% Vn-C, CIN1 5.5 -0.5 -1.0 -1.0 -3 -3 2.75 5.5 10 6.0 0 0 0 0 0 3.25 VP-P 6.5 15 50 -6.0 0.0 0 0.03 2.8 0 60 120 0.0 0 0.03 2.8 0 120 TP5 TP5 TP5 TP5 SG7 32 b7=0, Sine wave 2.5VP-P, 1kHz -6.5 b7=1, Sine wave 2.5VP-P, 1kHz -0.5 Sine wave 2.5VP-P, 1MHz/1kHz -3.0 Sine wave 2.5VP-P, 1kHz Sine wave 1kHz Maximum input for total higher 2.6 harmonic distortion factor < 0.5% ROUT1 pin DC difference during SW switching 42 -6.0 0.0 0 0.03 2.8 0 60 120 15 78 -5.5 0.5 1.0 0.1 15 15 78 0.5 1.0 0.1 20 -5.5 0.5 1.0 0.1 k dB dB % Vrms mV k dB dB % Vrms mV dB dB % Vrms mV k 6.5 0.5 1.0 dB 1.0 3 3 % deg dB
TP4 TP4 TP4 TP4 SG6 33
Input impedance ZIL1 Output impedance ZOL1 LOUT2 output Voltage gain GL2 Frequency characteristics FL2 Total higher harmonic distortion THDL2 Input dynamic range Output offset voltage Output impedance ROUT1 output Voltage gain DL2 VOFFL2 ZOL2
b7=0, Sine wave 2.5VP-P, 1kHz -6.5 b7=1, Sine wave 2.5VP-P, 1kHz -0.5 Sine wave 2.5VP-P, 1MHz/1kHz -3.0 Sine wave 2.5VP-P, 1kHz Sine wave 1kHz Maximum input for total higher 2.6 harmonic distortion factor < 0.5% LOUT1 pin DC difference during SW switching 42 Sine wave 2.5VP-P, 1kHz -0.5 Sine wave 2.5VP-P, 1MHz/1kHz -3.0 Sine wave 2.5VP-P, 1kHz Sine wave 1kHz Maximum input for total higher 2.6 harmonic distortion factor < 0.5% LOUT2 pin DC difference during SW switching
TP7 TP7 TP7 SG6 22
GR11 GR12 Frequency characteristics FR1 Total higher harmonic distortion THDR1 Input dynamic range Output offset voltage Input impedance Output impedance DR1 VOFFR1 ZIR1 ZOR1
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Item
Symbol Measure Conditions (unless otherwise indicated, Min. Typ. Max. Units Measurement Circuit Figure 1) ment pin TP8 TP8 TP8 SG7 24 Sine wave 2.5VP-P, 1kHz -0.5 Sine wave 2.5VP-P, 1MHz/1kHz -3.0 Sine wave 2.5VP-P, 1kHz Sine wave 1kHz Maximum input for total higher 2.6 harmonic distortion factor < 0.5% ROUT2 pin DC difference during switching 0.0 0 0.03 2.8 0 120 TP1 TP2 TP3 TP6 TP4 TP5 TP7 TP8 Measurement Circuit Figure 2 for SG1 input : 4.43MHz, 1VP-P for SG2 input : 4.43MHz, 0.5VP-P Measurement Circuit Figure 2 1kHz, 2.5VP-P No signal, no load VOUT1 pin, VOUT2 pin No signal, no load YOUT1 pin, COUT1 pin No signal, no load No signal, no load No signal, no load I2C logic low level discrimination value I2Clogic high level discrimination value SDA for 3mA inflow when SDA, SCL=4.5V impressed when SDA, SCL=0.4V impressed 4.6 4.1 3.3 4.0 3.9 0.0 3.0 0.0 -10 -10 4.7 4.0 4.7 4.0 4.7 200 250 4.0 -60 -60 -60 -60 -90 -90 -90 -90 4.9 4.4 3.6 4.3 4.2 -53 -53 -53 -53 -80 -80 -80 -80 5.2 4.7 3.9 4.6 4.5 1.5 5.0 0.4 +10 +10 100 15 0.5 1.0 0.1 dB dB % Vrms mV dB dB dB dB dB dB dB dB V V V V V
ROUT2 output Voltage gain GR2 Frequency characteristics FR2 Total higher harmonic distortion THDR2 Input dynamic range Output offset voltage Output impedance Crosswalk VOUT 1 VOUT 2 YOUT 1 COUT 1 LOUT 1 LOUT 2 ROUT 1 ROUT 2 Video I/O Pin Voltage Input pin voltage Output pin voltage VSOP Audio I/O Pin Voltage Input pin voltage VAIP Output pin voltage VAOP Logic section (Refer to figure below) Input voltage L VIL Input voltage H VIH Low level output voltage (SDA) VOL High level input current IIH Low level input current IIL Clock frequency fSCL Data transmission waiting time tBUF SCL start hold time tHD;STA SCL low level hold time tLOW SCL high level hold time tHIGH SCL start set-up time tSU;STA SDA data hold time tHD;DAT SDA data set-up time tSD;DAT SCL rise time tR SCL fall time tF SCL stop set-up time tSU;STO DR2 VOFFR2 ZOR2 CTV1 CTV2 CTY1 CTC1 CTL1 CTL2 CTR1 CTR2 VVIP VVOP
V V V A A kHz S S S S S nS nS 1000 nS 300 nS S
I2C BUS BUS Control Signal
SDA tBUF SCL P S tHD:STA tLOW tHD:DAT tHIGH tSU:DAT tSU:STA Sr tSU:STD P
tR
tF
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Measurement Circuit
Measurement Circuit 1
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Measurement Circuit 2 (Crosstalk measurement)
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
I2C BUS
SDA
SCL S 1 2 3 45 6 78A 1 2 3 8 A P
S:Start Condition P:Stop Condition A:Acknowledge
The I2C BUS is a BUS system developed by Philips for internal use in equipment. Data transmission is carried out by the two SDA and SCL lines, in byte units, with the MSB first from start condition. [Control Register] The control register contains data sent from the master in order to determine the status of each switch. S Slave address 1 0 0 1 0 R/W 0 0/1 0 A Control register 1 b7 b6 b5 b4 b3 b2 b1 b0 A Control register 2 b7 b6 b5 b4 b3 b2 b1 b0 A P
Address byte
Control data
The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 0 when using as a control register. The MM1313 slave address can be selected as 90H/92H depending on the status of the ADR pin. When ADR pin is low it is 90H. The relationship between the control register bits and switch control is as shown below. b7 Gain b6 Select b5 b4 Video-Select b3 b2 b1 Audio-Select b0
Audio S/Comp
The control register bits are reset to 0 when power is applied. MM1313 control is carried out by the 3-byte structure of the 1 address byte and 2 control data bytes. The first byte in the control data is control data for output 1, and the remaining 1 byte is control data for output 2. All of the remaining data (fourth byte and after) are ignored. Refer to the separate tables for details on switch control.
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
[Status Register] The status register contains data for sending device status to the master. Slave address 1 0 0 1 0 0 0/1 R/W 1 Status register b7 b6 b5 b4 b3 b2 b1 b0
S
A
NA
P
Address byte
Status data
The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 1 when using as a status register. The MM1313 slave address can be selected as 91H/93H depending on the status of the ADR pin. When the ADR pin is low it is 91H. However, the confirmation response after completion of the status register should be non-acknowledge. The status register output data as shown below. b7 P-ON RESET b6 b5 S1 OPEN b4 S1 SEL b3 S2 OPEN b2 S2 SEL b1 b0
P-ON RESET : Returns 1 for power on reset. However once data read begins, 0 is returned next. S1/S2 OPEN : Returns 0 when the S1/S2 pin is not open, and returns 1 when the S1/S2 pin is open S1/S2 SEL : Returns 0 when the S1/S2 pin is not grounded, and returns 1 when the S1/S2 pin is grounded. S1/S2 OPEN, SEL have 3-value discrimination, and the combinations are as shown below. S1/S2 pin DC voltage 0.8V or less 1.3V or more, 3.5V or less 4.5V or more S1/S2 OPEN 0 0 1 S1/S2 SEL 1 0 0
[Power On Reset] Power on reset is built in to reset each control register to 0 when power is turned on. Power on reset threshold has hysteresis as shown in the figure below. The IC power on reset status can be discriminated by reading the status register P-ON RESET.
Reset released Undefined Reset status
0.6V
4.3V
5.4V
VCC
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Switch Control Table
1. Video Output 1
b6 0 0 0 0 0 0 0 1 1 1 1 1 1 1 b5 0 0 0 0 1 1 1 0 0 0 0 1 1 1 b4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT1 Mute MTV-V V1-V V2-V V3-V STV-V Mute Mute MTV-V V1-Y+C V2-Y+C V3-V STV-V Mute YOUT1 Mute YIN1 YIN1 YIN1 YIN1 YIN1 Mute Mute YIN1 V1-Y V2-Y YIN1 YIN1 Mute COUT1 Mute CIN1 CIN1 CIN1 CIN1 CIN1 Mute Mute CIN1 V1-C V2-C CIN1 CIN1 Mute
2. Video Output 2
b6 0 0 0 0 0 0 0 1 1 1 1 1 1 1 b5 0 0 0 0 1 1 1 0 0 0 0 1 1 1 b4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT2 Mute MTV-V V1-V V2-V V3-V STV-V Mute Mute MTV-V V1-Y+C V2-Y+C V3-V STV-V Mute
3. Audio Output 1
Mute pin b2 0 0 0 1.5V or less (OPEN) 0 1 1 1 3.0V or more b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 LOUT1 Mute MTV-L V1-L V2-L V3-L STV-L Mute Mute ROUT1 Mute MTV-R V1-R V2-R V3-R STV-R Mute Mute
4. Audio Output 1 Gain Switching
b7 0 1 Output gain -6dB output 0dB output
5. Audio Output 2
Mute pin b2 0 0 0 1.5V or less (OPEN) 0 1 1 1 3.0V or more b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 LOUT2 Mute MTV-L V1-L V2-L V3-L STV-L Mute Mute ROUT2 Mute MTV-R V1-R V2-R V3-R STV-R Mute Mute
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Application Circuit
Notes 1. VOUT is set at 4.4V and CIN at 4.9V Please note that capacitance polarity may vary depending on comb filter bias. 2. Each audio output can be muted by making pin 19 high. Mute is off when it is open or low.

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